Semiconductor structure and shallow trench isolation structure preparation method

Abstract

The present application provides a method for preparing a semiconductor structure and a shallow trench isolation structure. The method for preparing a shallow trench isolation structure includes: providing a substrate; forming a hard mask layer on the substrate, the hard mask layer including a first etch barrier layer, a sacrificial layer and a second etch barrier layer stacked in sequence; patterning the hard mask layer, and etching the substrate using the patterned hard mask layer as a mask to form a plurality of spaced trenches; removing the remaining sacrificial layer; depositing an isolation material and flattening it to form a shallow trench isolation structure in each of the trenches, and the step height difference between the plurality of shallow trench isolation structures is uniform. The above technical solution, by setting a sacrificial layer between the first etch barrier layer and the second etch barrier layer, avoids the first etch barrier layer from being consumed during the trench etching process, so that the step height difference between the plurality of shallow trench isolation structures formed is uniform, thereby improving the product yield.

Description

Technical Field

[0001] The present application relates to the field of semiconductor manufacturing, and in particular to a method for preparing a semiconductor structure and a shallow trench isolation structure. Background Art

[0002] With the increasing integration density of large-scale integrated circuits (ICs), shallow trench isolation (STI) technology is often used to fabricate isolation trenches between active areas of components with a thickness of 0.18µm or less. The trenches are typically etched using an anti-reflective (Darc) layer and a silicon nitride (SiN) layer as a hard mask. The SiN layer not only serves as a mask for trench etching but also as a stop layer for chemical mechanical polishing (CMP).

[0003] However, using only silicon nitride as a CMP stop layer may cause a portion of the silicon nitride to be consumed during the trench etching process. Figure 7 Schematic diagram of the shallow trench structure in the prior art. Figure 7 As shown in FIG, since a portion of the silicon nitride layer 71 is consumed during the trench etching process, the difference in wafer etching rate directly affects the uniformity of the silicon nitride layer 71, as shown in FIG. Figure 7 As shown in part (a); the poor uniformity of the silicon nitride layer 71 directly leads to poor uniformity of the step height of the CMP process, such as Figure 7 As shown in part (b); thus affecting the subsequent polysilicon (Poly) etching, resulting in a height difference between the multiple shallow trench structures 72 formed, such as Figure 7 As shown in part (c), it further affects the electrical properties of the product.

[0004] Therefore, providing a method for improving the uniformity of shallow trench isolation step height difference to avoid affecting subsequent polysilicon etching and product electrical properties is a technical problem that needs to be solved urgently. Summary of the Invention

[0005] The technical problem to be solved by the present application is to provide a semiconductor structure and a shallow trench isolation structure preparation method to improve the uniformity of the shallow trench isolation step height difference in the semiconductor structure, thereby avoiding affecting the subsequent polysilicon etching and product electrical properties.

[0006] In order to solve the above problems, the present application provides a method for preparing a shallow trench isolation structure, which includes: providing a substrate; forming a hard mask layer on the substrate, the hard mask layer including a first etch barrier layer, a sacrificial layer and a second etch barrier layer stacked in sequence; patterning the hard mask layer, and etching the substrate using the patterned hard mask layer as a mask to form a plurality of spaced trenches; removing the remaining sacrificial layer; depositing isolation material and planarizing it to form a shallow trench isolation structure in each of the trenches, and the step height difference between the plurality of shallow trench isolation structures is uniform.

[0007] In some embodiments, the substrate is a silicon substrate or a silicon substrate with an epitaxial layer; the material of the first etch stop layer is silicon nitride; the material of the sacrificial layer is silicon oxide or amorphous carbon; and the material of the second etch stop layer is an anti-reflective material.

[0008] In some embodiments, the step of patterning the hard mask layer further includes: patterning the second etch stop layer; patterning the sacrificial layer using the patterned second etch stop layer as a mask; and patterning the first etch stop layer using the patterned sacrificial layer as a mask.

[0009] In some embodiments, the step of patterning the hard mask layer further includes patterning the hard mask layer by self-aligned contact etching.

[0010] In some embodiments, the step of etching the substrate using the patterned hard mask layer as a mask to form a plurality of spaced trenches further includes: after the trench etching is completed, the remaining thickness of the sacrificial layer is greater than or equal to 30 nanometers.

[0011] In some embodiments, the material of the sacrificial layer is silicon oxide; and the step of removing the remaining sacrificial layer further includes: removing the remaining sacrificial layer by wet etching.

[0012] In some embodiments, the material of the sacrificial layer is amorphous carbon; and the step of removing the remaining sacrificial layer further includes: removing the remaining sacrificial layer using an ashing process.

[0013] In some embodiments, the step of depositing isolation material and planarizing to form a shallow trench isolation structure in each of the trenches further includes: depositing isolation material in the trench and on the surface of the first etch barrier layer using high-density plasma chemical vapor deposition; performing planarization using the first etch barrier layer as a stop layer for planarization; and removing the remaining first etch barrier layer to form the shallow trench isolation structure.

[0014] In some embodiments, the step of removing the remaining first etch stop layer further includes: removing the remaining first etch stop layer by chemical mechanical polishing.

[0015] In order to solve the above problems, the present application also provides a semiconductor structure including a plurality of shallow trench isolation structures, wherein the shallow trench isolation structures are prepared using the method described in the present invention, and the step height differences of the plurality of shallow trench isolation structures are uniform.

[0016] The above technical solution avoids the first etch barrier layer from being consumed during the trench etching process by setting the sacrificial layer between the first etch barrier layer and the second etch barrier layer, thereby avoiding the difference in wafer etching rate directly affecting the uniformity of the first etch barrier layer, making the step height difference between the multiple shallow trench isolation structures formed uniform, avoiding affecting the subsequent polysilicon etching and product electrical properties, and improving the product yield.

[0017] It should be understood that the above general description and the following detailed description are exemplary and explanatory only and do not limit the present application. Technologies, methods, and devices known to those skilled in the art may not be discussed in detail, but where appropriate, such technologies, methods, and devices should be considered part of the specification. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following is a brief introduction to the drawings required for use in the embodiments of the present application. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0019] Figure 1 Schematic diagram of the steps of a method for preparing a shallow trench isolation structure in one embodiment of the present application;

[0020] Figures 2 to 6 A schematic diagram of a device structure formed by the main steps in an embodiment of the present application;

[0021] Figure 7 It is a schematic diagram of a shallow trench structure in the prior art. DETAILED DESCRIPTION

[0022] The following will be combined with the accompanying drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are only part of the embodiments of this application, not all of the embodiments. Based on the embodiments of this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0023] The following first introduces a method for preparing a shallow trench isolation structure provided in an embodiment of the present application.

[0024] Please also refer to Figures 1 to 6 ,in, Figure 1 This is a schematic diagram of the steps of a method for preparing a shallow trench isolation structure in one embodiment of the present application. Figures 2 to 6 This is a schematic diagram of the device structure formed by the main steps in one embodiment of the present application.

[0025] like Figure 1 As shown, the method for preparing the shallow trench isolation structure described in this embodiment includes: step S101, providing a substrate; step S102, forming a hard mask layer on the substrate, the hard mask layer including a first etch barrier layer, a sacrificial layer and a second etch barrier layer stacked in sequence; step S103, patterning the hard mask layer, and etching the substrate using the patterned hard mask layer as a mask to form a plurality of spaced trenches; step S104, removing the remaining sacrificial layer; step S105, depositing isolation material and planarizing to form a shallow trench isolation structure in each of the trenches, and the step height difference between the plurality of shallow trench isolation structures is uniform.

[0026] In this embodiment, the substrate 1 can be a silicon substrate or a silicon substrate with an epitaxial layer (not shown). The epitaxial layer can be a single layer or a multilayer structure. Due to its high resistivity, the epitaxial layer can ensure that the semiconductor structure has a high breakdown voltage during the subsequent manufacturing process of the semiconductor structure. The low-resistance substrate reduces the resistance, thereby reducing the saturation voltage drop of the semiconductor structure. In some embodiments, the epitaxial layer can be made of gallium nitride (GaN).

[0027] Please refer to step S102 and Figure 2A hard mask layer 3 is formed on the substrate 1. The hard mask layer 3 includes a first etch stop layer 31, a sacrificial layer 32, and a second etch stop layer 33 stacked in sequence. In this embodiment, the first etch stop layer 31 is made of silicon nitride; the sacrificial layer 32 is made of silicon oxide or amorphous carbon; and the second etch stop layer 33 is made of an anti-reflective material. The second etch stop layer 33 can be an inorganic anti-reflective layer (e.g., silicon oxynitride) or an organic anti-reflective layer (Brac). The second etch stop layer 33 is used to reduce interference between incident and reflected light waves, thereby preventing it from affecting the resolution of photoresist imaging during photolithography. In this embodiment, the surface of the substrate 1 has an initial oxide layer 2. The initial oxide layer 2 serves as a buffer layer to prevent the first etch stop layer 31 from directly contacting the substrate 1 and generating stress that could damage the substrate 1. In this embodiment, a patterned photoresist layer 4 is also formed on the hard mask layer 3 to serve as an initial mask for subsequent patterning of the hard mask layer 3.

[0028] Please refer to step S103 and Figures 3 and 4 , patterning the hard mask layer 3, and etching the substrate using the patterned hard mask layer as a mask to form a plurality of trenches 5 arranged at intervals.

[0029] like Figure 3 As shown, in this embodiment, the step of patterning the hard mask layer 3 further includes: patterning the second etch stop layer 33, specifically, patterning the second etch stop layer 33 using the patterned photoresist layer 4 as a mask and the sacrificial layer 32 as an etch stop layer, and the device structure formed is as shown. Figure 3 As shown in part (a); the sacrificial layer 32 is patterned using the patterned second etch barrier layer 33 as a mask. Specifically, the sacrificial layer 32 is patterned using the patterned second etch barrier layer 33 as a mask and the first etch barrier layer 31 as an etch stop layer. The remaining second etch barrier layer 33 is etched away during etching. The device structure formed is as shown in FIG. Figure 3 As shown in part (b); the first etch stop layer 31 is patterned using the patterned sacrificial layer 32 as a mask, specifically using the patterned sacrificial layer 32 as a mask and the substrate 1 as an etch stop layer to pattern the first etch stop layer 31 (when an initial oxide layer 2 is formed on the substrate 1, this step also includes patterning the initial oxide layer 2). The device structure formed is as shown in FIG. Figure 3 As shown in part (c).

[0030] In some other embodiments, the step of patterning the hard mask layer 3 further includes patterning the hard mask layer 3 by self-aligned contact etching, specifically using the patterned upper film structure as a mask and sequentially self-aligned contact etching the corresponding lower film structure.

[0031] like Figure 4 As shown, in this embodiment, the step of etching the substrate 1 using the patterned hard mask layer 3 as a mask to form a plurality of spaced trenches 5 further includes: after the trenches 5 are etched, the remaining thickness X of the sacrificial layer 32 is greater than or equal to 30 nanometers. By ensuring that the remaining thickness X of the sacrificial layer 32 is greater than or equal to 30 nanometers after the trenches 5 are etched, an etching window is ensured, thereby preventing damage to the underlying substrate 1.

[0032] Please refer to step S104 and Figure 5 , remove the remaining sacrificial layer 32. Figure 5 As shown, in this embodiment, after the remaining sacrificial layer 32 is removed, the surface of the first etch stop layer 31 is smooth, which can improve the uniformity of the step height in the subsequent CMP process.

[0033] Specifically, when the material of the sacrificial layer 32 is silicon oxide, the step of removing the remaining sacrificial layer 32 further includes: removing the remaining sacrificial layer 32 by wet etching. When the material of the sacrificial layer 32 is amorphous carbon, the step of removing the remaining sacrificial layer 32 further includes: removing the remaining sacrificial layer 32 by an ashing process.

[0034] Please refer to step S105 and Figure 6 , depositing isolation material and planarizing to form a shallow trench isolation structure 6 in each of the trenches, and the step height difference between the plurality of shallow trench isolation structures 6 is uniform. Figure 6 As shown, in this embodiment, the deposited isolation material is specifically deposited in the trench 5 and on the surface of the first etch stop layer 31 by high density plasma chemical vapor deposition (HDP). The device structure formed is as shown in FIG. Figure 6 As shown in part (a); the planarization is specifically, planarization is performed using the first etch barrier layer 31 as a planarization stop layer, and the device structure formed is as shown Figure 6 As shown in part (b), at this time, the isolation material deposited in the groove 5 is at the same horizontal plane AA'; the remaining first etch stop layer 31 is removed to form the shallow trench isolation structure 6, and the device structure formed is as shown Figure 6As shown in part (c) of FIG. 1 , in this embodiment, the planarization step further includes: performing planarization by chemical mechanical polishing.

[0035] The above technical solution avoids the first etch barrier layer 31 from being consumed during the etching of the trench 5 by setting the sacrificial layer 32 between the first etch barrier layer 31 and the second etch barrier layer 33, thereby further avoiding the difference in wafer etching rate affecting the uniformity of the first etch barrier layer 31; since the first etch barrier layer 31 has good uniformity before planarization, the step height difference between the multiple shallow trench isolation structures 6 formed is uniform, avoiding affecting the subsequent polysilicon etching and product electrical properties, and improving the product yield.

[0036] Based on the same inventive concept, the present application also provides a semiconductor structure.

[0037] like Figure 6 As shown in (c), the semiconductor structure includes multiple shallow trench isolation structures 6, each fabricated using the aforementioned method of the present invention. The multiple shallow trench isolation structures 6 have uniform step height differences. Specifically, the surfaces of the multiple shallow trench isolation structures 6 facing away from the substrate are flush and located on the same horizontal plane AA'. The formation method of the shallow trench isolation structures 6 is described above and will not be repeated here.

[0038] The above technical solution avoids the first etch barrier layer 31 from being consumed during the etching of the trench 5 by setting the sacrificial layer 32 between the first etch barrier layer 31 and the second etch barrier layer 33, thereby further avoiding the difference in wafer etching rate affecting the uniformity of the first etch barrier layer 31; since the first etch barrier layer 31 has good uniformity before planarization, the step height difference between the multiple shallow trench isolation structures 6 formed is uniform, avoiding affecting the subsequent polysilicon etching and product electrical properties, and improving the product yield.

[0039] It should be noted that, in this document, relational terms such as second and second are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "comprises", "comprising" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article or device. In the absence of further limitations, the presence of an element defined by the phrase "also includes a..." does not exclude the presence of other identical elements in the process, method, article or device comprising the element.

[0040] Each embodiment in this specification is described in a related manner. Similar portions between the embodiments can be referenced to each other. Each embodiment focuses on the differences from other embodiments. In particular, the structural embodiments are generally similar to the method embodiments, so their description is relatively simple. For related portions, reference can be made to the description of the method embodiments.

[0041] The above description is only a preferred embodiment of the present application and is not intended to limit the scope of protection of the present application. It should be noted that those skilled in the art may make several improvements and modifications without departing from the principles of the present application, and such improvements and modifications shall also be considered within the scope of protection of the present application.

Claims

1. A method for preparing a shallow trench isolation structure, characterized in that: The method comprises: providing a substrate; forming a hard mask layer on the substrate, wherein the hard mask layer comprises a first etch stop layer, a sacrificial layer, and a second etch stop layer stacked in sequence; Patterning the hard mask layer, and etching the substrate using the patterned hard mask layer as a mask to form a plurality of trenches arranged at intervals; removing the remaining sacrificial layer; An isolation material is deposited and planarized to form a shallow trench isolation structure in each trench, and the step height differences between the plurality of shallow trench isolation structures are uniform.

2. The method according to claim 1, characterized in that The substrate is a silicon substrate or a silicon substrate with an epitaxial layer; The material of the first etch stop layer is silicon nitride; The material of the sacrificial layer is silicon oxide or amorphous carbon; The material of the second etch stop layer is an anti-reflective material.

3. The method according to claim 1, characterized in that The step of patterning the hard mask layer further includes: patterning the second etch stop layer; patterning the sacrificial layer using the patterned second etch stop layer as a mask; The first etching stop layer is patterned using the patterned sacrificial layer as a mask.

4. The method according to claim 1, wherein The step of patterning the hard mask layer further includes: patterning the hard mask layer by self-aligned contact etching.

5. The method according to claim 1, wherein The step of etching the substrate using the patterned hard mask layer as a mask to form a plurality of spaced trenches further includes: after the trench etching is completed, the remaining thickness of the sacrificial layer is greater than or equal to 30 nanometers.

6. The method according to claim 1, characterized in that The material of the sacrificial layer is silicon oxide; the step of removing the remaining sacrificial layer further includes: removing the remaining sacrificial layer by wet etching.

7. The method according to claim 1, characterized in that The material of the sacrificial layer is amorphous carbon; the step of removing the remaining sacrificial layer further includes: removing the remaining sacrificial layer by an ashing process.

8. The method according to claim 1, characterized in that Depositing isolation material and planarizing, The step of forming a shallow trench isolation structure in each of the trenches further includes: Depositing an isolation material in the trench and on the surface of the first etch stop layer by high-density plasma chemical vapor deposition; performing planarization using the first etch barrier layer as a planarization stop layer; The remaining first etch stop layer is removed to form the shallow trench isolation structure.

9. The method according to claim 8, characterized in that The planarization step further includes: performing planarization by chemical mechanical polishing.

10. A semiconductor structure, characterized in that The invention comprises a plurality of shallow trench isolation structures, wherein the shallow trench isolation structures are prepared by the method according to any one of claims 1 to 9, and the step height differences of the plurality of shallow trench isolation structures are uniform.

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