Ultrasonic signal acquisition processing system and method based on FPGA control

Abstract

This invention belongs to the field of nondestructive testing technology, and relates to an FPGA-controlled ultrasonic signal acquisition and processing system and method. The acquisition and processing system includes an FPGA chip and a host computer. The FPGA chip has an FPGA control module, which is electrically connected to a signal acquisition module, a data buffer module, and a transmission module. The signal acquisition module is electrically connected to a signal conditioning module and a data buffer module. The ultrasonic analog signal is input to the signal conditioning module for filtering and amplification. The transmission module interacts with the host computer, which includes a human-machine interface module and a signal processing module. The signal processing module reconstructs the denoised signal and obtains the final denoised signal through a VMD decomposition process. The signal is then displayed in both A-mode and C-mode modes. This invention realizes the acquisition, filtering, analog-to-digital conversion, automatic transmission, and denoising of ultrasonic analog signals, improving the signal-to-noise ratio and resolution of ultrasonic signals.

Description

Technical Field

[0001] This invention belongs to the field of nondestructive testing technology and relates to an ultrasonic signal acquisition and processing system and method based on FPGA control. It can transmit data to a host computer via USB serial communication, and the host computer performs noise reduction processing on the ultrasonic signal. Background Technology

[0002] Ultrasonic testing is widely used in the field of non-destructive testing. Conventional ultrasonic testing uses a coupling agent to reduce the attenuation of ultrasonic waves. However, for some materials (such as aerospace honeycomb composite materials and lithium batteries), conventional methods are difficult to achieve penetration testing. Air-coupled ultrasonic testing can overcome this shortcoming and truly achieve non-contact, non-destructive, and non-invasive testing.

[0003] The development of ultrasonic testing technology has been relatively slow due to various factors, including ultrasonic wave attenuation in the medium, significant reflections caused by the large impedance difference at the gas-solid interface, and low signal-to-noise ratio. While advancements in coupling theory and materials science have led to better solutions for the first two factors, the low signal-to-noise ratio problem remains largely unresolved. Digital signal processing technology is currently one of the most important methods for improving the signal-to-noise ratio and resolution in ultrasonic testing. Because FPGAs (Field-Programmable Gate Arrays) have high clock frequencies and parallel data transmission capabilities, controlling signal acquisition through FPGAs can improve speed and accuracy. Therefore, with the continuous development of digital signal processing technology, FPGA-based ultrasonic signal acquisition, control, and processing technology has become a worthy research direction. Summary of the Invention

[0004] To address the problems of slow acquisition speed and low signal accuracy in the ultrasonic testing signal sampling process, this invention provides a fast and accurate ultrasonic signal acquisition and processing system and method.

[0005] The technical solution adopted in this invention is as follows:

[0006] An FPGA-controlled ultrasonic signal acquisition and processing system includes an FPGA chip and a host computer. The FPGA chip has an FPGA control module and is electrically connected to a signal acquisition module, a data buffer module, and a transmission module. The signal acquisition module is electrically connected to a signal conditioning module and a data buffer module. The ultrasonic analog signal is input to the signal conditioning module for filtering and amplification. The transmission module interacts with the host computer. The host computer has a human-computer interaction module and a signal processing module.

[0007] Preferably, the signal conditioning module includes a voltage follower module, a primary amplification module, a secondary amplification module, and a bandpass filter module that are electrically connected in sequence within a metal fiber shield.

[0008] Preferably, the voltage follower module is constructed using an OPA192 voltage follower and resistors R1, R2, and R3, with resistor R1 = 20Ω; the primary amplification module consists of an instrumentation amplifier AD8429 and a front-end resistor R G It consists of the rear resistor R4, and the resistor R G Resistors with 0.1% precision are used; the post-amplification module uses an OPA1611 operational amplifier, which is composed of a cascaded two-stage and a three-stage amplifier circuit. The two-stage and three-stage amplifier circuits employ a voltage parallel negative feedback method. The two-stage amplifier circuit consists of an OPA1611 operational amplifier, capacitor C7, and resistors R5, R6, and R7. The three-stage amplifier circuit consists of an OPA1611 operational amplifier, capacitor C10, and resistors R8, R9, and R10. The feedback resistor R of the three-stage amplifier circuit... 10 A variable resistor is used; the bandpass filter module uses an operational amplifier OPA171, which consists of an operational amplifier OPA171, capacitors C13 and C14, and resistors R11, R12, R13, and R14.

[0009] Preferably, the FPGA chip is the Cyclone IV series EP4CE10F17C8N, the FPGA control module is based on the NIOS II soft-core processor included in the FPGA chip, configures the IP cores of the sub-modules required by the circuit, completes the construction of the software control environment, completes the construction of the system bus based on the AVALON-MM bus, and realizes data transmission between sub-modules through DMA; the signal acquisition module uses the AD9244 chip, the data buffer module uses the W9825G6KH-6 dynamic random access memory, and the transmission module uses the CH340 chip.

[0010] An FPGA-based ultrasonic signal acquisition and processing method, using the aforementioned FPGA-based ultrasonic signal acquisition and processing system, includes the following steps:

[0011] Step 1: Obtain the time-frequency information of the original signal using wavelet transform, process the wavelet coefficients using a threshold function, and finally perform inverse wavelet transform on the processed wavelet coefficients to reconstruct the denoised signal.

[0012] Step 2: The VMD decomposition process involves filtering the original signal and decomposing the frequency-dominant signal into a set of amplitude-modulated and frequency-modulated signals. The Intrinsic Mode Function (IMF) is defined as a bandwidth-limited amplitude-modulated and frequency-modulated function. The VMD algorithm constructs and solves a constrained variational problem to decompose the original signal into a specified number of IMF components. Selecting the IMF of the desired frequency band from the decomposed IMFs yields the final denoised signal.

[0013] Step 3: The ultrasonic signal after noise reduction is displayed in A-mode and C-mode on the host computer's display interface.

[0014] Preferably, in step 1, performing a continuous wavelet transform on the received signal f(t) yields the wavelet coefficients W. f (a,b):

[0015]

[0016] In the formula, a and b are the scaling and translation factors, respectively, and * represents complex conjugation. The scaling and translation of the mother wavelet are achieved through factors a and b, thereby obtaining a series of wavelet bases ψ. a,b (t), as shown in formula (2):

[0017]

[0018] In step 2, the k-th order IMF component is represented as:

[0019]

[0020] In the formula A k (t) is μ k The instantaneous amplitude of (t); For μ k The instantaneous frequency of (t); μ k (t) is a set of discrete sub-signals, each with a sparse bandwidth in the time spectrum;

[0021] The expression for the constrained variational model is:

[0022]

[0023]

[0024] In the formula μ k (t) represents the IMF components obtained from the decomposition; ω k The center frequency of the IMF component;

[0025] To obtain the optimal solution to the above constrained variational problem, a quadratic penalty term α and a Lagrange multiplier λ are introduced to transform the constrained variational problem into an unconstrained variational problem. The resulting augmented Lagrange expression is:

[0026]

[0027] The saddle point of the augmented Lagrangian function is obtained using the alternating direction multiplier algorithm, which is the optimal solution of the constrained variational model. This decomposes the original signal into k IMF components, yielding the following result:

[0028]

[0029]

[0030]

[0031] In the formula, n represents the number of iterations, and ω represents the frequency value. and They are respectively The Fourier transforms of f(t) and λ(t), where γ represents the noise tolerance. For the desired mode... The Intrinsic Mode Function (IMF) can be obtained by performing an inverse Fourier transform. The final denoised signal can be obtained by selecting the IMF of the desired frequency band from the k decomposed IMFs.

[0032] The beneficial effects of this invention are:

[0033] This invention realizes the acquisition, filtering and noise reduction, analog-to-digital conversion and automatic transmission of ultrasonic analog signals through an FPGA control module. It uses wavelet transform and VMD decomposition to perform in-depth processing on ultrasonic signals to obtain the final noise-reduced ultrasonic signal, which greatly improves the signal-to-noise ratio and resolution of ultrasonic signals. Furthermore, it enables A-mode and C-mode display on the host computer's display interface. Attached Figure Description

[0034] Picture 1 This is a schematic diagram of the architecture of the ultrasonic signal acquisition and processing system according to an embodiment of the present invention;

[0035] Picture 2 This is a schematic diagram of the input stage of the AD9244 chip according to an embodiment of the present invention;

[0036] Picture 3 This is a schematic diagram of the signal conditioning module according to an embodiment of the present invention;

[0037] Picture 4 This is a design diagram of the voltage follower module according to an embodiment of the present invention;

[0038] Picture 5 This is a schematic diagram of the primary amplification module according to an embodiment of the present invention;

[0039] Picture 6 This is a circuit diagram of the second-stage amplifier module of the present invention.

[0040] Picture 7 This is a three-stage amplifier circuit diagram of the post-amplification module in an embodiment of the present invention;

[0041] Picture 8 This is a circuit diagram of a bandpass filter module according to an embodiment of the present invention. Detailed Implementation

[0042] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the examples in the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0043] The following detailed description, in conjunction with the accompanying drawings, provides a technical solution for an FPGA-controlled ultrasonic signal acquisition and processing system and method proposed in this invention, so that those skilled in the art can better understand and implement this invention.

[0044] like Picture 1 The diagram shows the architecture of an ultrasonic signal acquisition and processing system according to an embodiment of the present invention. An ultrasonic signal acquisition and processing system based on FPGA control includes an FPGA chip and a host computer. The FPGA chip is the core of ultrasonic signal acquisition, controlling the acquisition, analog-to-digital conversion, storage, and transmission of ultrasonic analog signals. The host computer is the core of ultrasonic digital signal processing and display, controlling the improvement of the signal-to-noise ratio and resolution of the ultrasonic digital signals. The FPGA chip includes an FPGA control module, which is electrically connected to a signal acquisition module, a data buffer module, and a transmission module. The signal acquisition module is electrically connected to a signal conditioning module and a data buffer module. The ultrasonic analog signal is input to the signal conditioning module for filtering and amplification. The transmission module is electrically connected to the host computer for data interaction. The host computer includes a human-computer interaction module and a signal processing module. The host computer is preferably a PC.

[0045] The workflow of the FPGA-controlled ultrasound signal acquisition and processing system is as follows: First, the PC host computer encapsulates the main parameter settings for ultrasound signal acquisition into protocol data according to the communication protocol agreed upon with the FPGA control module. The FPGA control module receives and parses the protocol data, executes the corresponding operation settings, and controls the signal acquisition module to acquire ultrasound analog signal data from the signal conditioning module and complete analog-to-digital conversion. The converted ultrasound digital signal is saved to the data buffer module. At the same time, the FPGA control module controls the transmission module to send the digital signal to the PC host computer through the USB transmission port. After the signal processing module in the PC host computer performs filtering and noise reduction processing, ultrasound A-scan and C-scan images are generated on the display interface of the PC host computer through the human-computer interaction module.

[0046] The FPGA chip used is the EP4CE10F17C8N from Altera's Cyclone IV series. This chip boasts significant advantages in power consumption and cost-effectiveness, featuring 10,320 logic units, 414 Kbits of embedded memory, 23 18×18 embedded multipliers, 2 general-purpose phase-locked loops, 10 global clock networks, 8 user I / O banks, and a maximum of 179 user I / Os. Its abundant resources fully meet the requirements for controlling ultrasonic signal acquisition. The FPGA control module uses the NIOS II soft-core processor embedded in the FPGA chip as its core, configuring the IP cores of the required sub-modules to construct the software control environment. It establishes the system bus based on the AVALON-MM bus and achieves data transmission between sub-modules via DMA.

[0047] The signal acquisition module uses the AD9244 chip to perform analog-to-digital conversion of ultrasonic analog signals. Its advantages lie in the AD9244 chip's convenient interface, on-chip high-performance sample-and-hold amplifier and reference voltage source, signal overflow indicator, and direct output of data in binary form. Furthermore, the AD9244 chip employs a multi-stage differential pipelined structure with error correction logic, ensuring no code loss across the entire operating temperature range and obtaining accurate 14-bit data. Simultaneously, the AD9244 chip also features low power consumption and a high signal-to-noise ratio. Picture 2 The diagram shown is a schematic of the input stage of the AD9244 chip according to an embodiment of the present invention.

[0048] The data buffer module uses SDRAM, specifically the domestically produced W9825G6KH-6 dynamic random access memory (WINBOND). Since FPGA chips require data buffering during data reception and transmission, and SDRAM offers a high interface speed and large storage capacity, it has a significant advantage in data buffering. DDR3 SDRAM, for better power efficiency and faster transmission, uses an SSTL 15 I / O interface with an operating I / O voltage of 1.5V. It is packaged in CSP and FBGA packages. In addition to inheriting the ODT, OCD, Posted CAS, and AL control methods of DDR2 SDRAM, it adds more advanced CWD, Reset, ZQ, SRT, and PASR functions. It boasts a high storage speed of up to 166MHz and a storage capacity of up to 256MHz, meeting the data buffering requirements of a 65MHz sampling rate.

[0049] The transmission module uses the domestically produced CH340 chip manufactured by Nanjing Qinheng Microelectronics Co., Ltd. This chip is a USB bus adapter chip with a full-speed USB device interface, compatible with USB V2.0. The only external components required are a crystal and capacitors. It features a full-duplex serial port, built-in transmit / receive buffers, and supports communication baud rates from 50bps to 2Mbps. Furthermore, the chip boasts low power consumption, ensuring extended operation time.

[0050] The signal conditioning module includes a voltage follower module, a primary amplification module, a secondary amplification module, and a bandpass filter module, which are electrically connected in sequence within a metal fiber shield, such as... Picture 3 The diagram shows the structure of the signal conditioning module according to an embodiment of the present invention. The ultrasonic analog signal acquired by the ultrasonic probe is transmitted to the voltage follower module. After filtering and noise reduction processing by the signal conditioning module, a denoised ultrasonic analog signal is obtained. The ultrasonic analog signal undergoes multiple gas-solid interface couplings, resulting in a signal of only a few hundred microvolts reaching the receiving end. However, the subsequent acquisition circuit requires a signal amplitude of over 2V. Therefore, the total amplification factor of the signal conditioning module is designed to be over 10,000 times. The metal shield can cover the entire circuit, isolating it from electromagnetic noise in the surrounding space.

[0051] Voltage followers, with their high input impedance and low output impedance, are frequently used for impedance matching. Furthermore, they can isolate subsequent circuitry from the sensor to prevent damage to the ultrasonic probe due to signal reflection. The voltage follower used is the OPAx192, which is characterized by its high common-mode input impedance (up to 10). 13 Ω, nearly 10,000 times higher than the primary op-amp AD8429), with extremely low zero drift and noise (zero drift 0.2μV / ℃, noise at 1kHz is...). This is ideal for use as a voltage follower. The voltage follower module is built using the OPA192 voltage follower and resistors R1, R2, and R3. A voltage follower module built with the OPA192 is as follows: Picture 4 As shown, since the larger the resistance value, the greater the inherent thermal noise, in order to reduce the thermal noise introduced by the front-end resistor to weak signals, the resistor R1 should be selected with the smallest possible resistance value. Here, the resistor R1 = 20Ω.

[0052] The primary amplification module uses the ultra-low noise instrumentation amplifier AD8429 as the front-end amplification to reduce the interference of the chip's inherent noise on weak signals. The primary amplification module consists of the instrumentation amplifier AD8429 and the front-end resistor R. GThis consists of the voltage follower and the resistor R4 at the back end. The voltage follower has no gain, and the ultrasonic analog signal passing through this stage is further amplified by the inherent noise of the op-amp and the thermal noise of the resistor. Therefore, to prevent the useful signal from being overwhelmed by noise, the primary amplification module needs to be a low-noise, low-drift, and highly stable op-amp. The AD8429BRZ is an ultra-low noise op-amp. This instrumentation amplifier excels at measuring minute signals and boasts a common-mode rejection ratio (CMRR) of up to 90dB, preventing interference signals from disrupting data acquisition. With a maximum input offset voltage of only 50μV, its superior performance meets design requirements. The AD8429BRZ provides both high gain and high bandwidth: 4MHz at G=10 and 1.2MHz at G=100. Using the AD8429 ensures a high bandwidth for the entire circuit, allowing for amplification of ultrasonic signals at different center frequencies when using ultrasonic probes with varying center frequencies. Only the resistor R connected to pins 2 and 3 needs to be changed. G You can then set the magnification factor; the relationship between the two is as follows: To increase the stability of the primary amplifier module, resistor R G Low-temperature drift, high-precision (0.1% accuracy) resistors are used. In the primary amplification module, the amplification factor G is selected as 25, and the calculated R... G The impedance is 250Ω. The primary amplifier module, composed of the instrumentation operational amplifier AD8429, is as follows: Picture 5 As shown.

[0053] For high-gain amplifier circuits dealing with weak signals, the impact of the op-amp's DC offset voltage cannot be ignored. Since the amplitude of the offset voltage is similar to that of the desired signal, in the primary amplifier module, the offset voltage is amplified along with the desired signal, causing the desired signal to be boosted beyond the voltage input range of the next stage amplifier circuit, resulting in output voltage distortion. Therefore, the offset voltage generated by the primary amplifier module must be filtered out in the subsequent amplifier stage. To ensure a high bandwidth for the entire amplifier circuit, the subsequent amplifier stage uses ultra-low noise (at 1kHz) amplifiers. The high-bandwidth OPA1611 operational amplifier achieves a bandwidth of up to 40MHz with a gain G=1. The subsequent amplification module consists of... Picture 6 Secondary amplifier circuit and Picture 7 The circuit consists of three cascaded amplifier stages, employing a voltage parallel negative feedback method. The second-stage amplifier comprises an OPA1611 operational amplifier, capacitor C7, and resistors R5, R6, and R7. The third-stage amplifier comprises an OPA1611 operational amplifier, capacitor C10, and resistors R8, R9, and R10. To ensure lossless signal transmission from the primary amplifier module to the next stage, the input resistor R5 in the second-stage amplifier circuit cannot be too small. In this circuit, R5 = 1KΩ, R7 = 20KΩ, and C7 is a DC blocking capacitor. The amplification factor of the second-stage amplifier circuit is... The three-stage amplifier circuit is exactly the same as the two-stage amplifier circuit. To make the circuit gain adjustable and to amplify input signals of different amplitudes, the feedback resistor R in the three-stage amplifier circuit... 10 A variable resistor with a maximum resistance of 20KΩ is used to achieve a gain of 60dB to 80dB for the entire amplifier circuit. This circuit uses 0.1μF capacitors C7 and C10 for RC coupling to filter out the DC offset voltage, leaving only the effective AC signal.

[0054] In existing filtering topologies, the infinite-gain multiple-feedback bandpass filter possesses a steep transition band and good selectivity, making it suitable for retaining a fixed frequency signal while filtering out other frequencies. The bandpass filter module uses the OPA171 operational amplifier, consisting of the OPA171, capacitors C13 and C14, and resistors R11, R12, R13, and R14. The OPA171 is a low-noise... This low-offset rail-to-rail operational amplifier has a gain bandwidth of 10MHz. The amplified signal reaches over 2V, and after passing through the filtering circuit, there is little superimposed noise, making the OPA171 suitable for use as an active filter. A second-order infinite-gain multiple-feedback bandpass filter circuit is shown below. Picture 8 As shown, in addition, in order to increase the stopband attenuation rate and improve the signal-to-noise ratio, two second-order infinite-gain multiple-feedback bandpass filters are cascaded to form a fourth-order filter.

[0055] The specific implementation methods for each module are as follows:

[0056] The main control circuit is designed around the EP4CE10F17C8N core. This circuit uses a 5V input voltage and provides stable 3.3V, 1.2V, and 2.5V output voltages through power management chips MP1484, AMS1117-1.2, AMS1117-2.5, and AMS1117-3.3. A 50MHz clock source is provided to ensure optimal clock quality. The development board uses a mature USB Blaster implementation, enabling onboard USB Blaster functionality. In its most streamlined mode, only a single USB cable is needed for development and debugging. The board also includes a 256Mb SDRAM memory chip. This chip connects to the FPGA via a 16-bit data bus, operates on 3.3V, and can run at a maximum frequency of 166MHz, facilitating future development. To facilitate connection between the development board and a PC, a USB-to-serial converter is provided on the circuit board. This USB port can be used directly as a power supply port for the development board or as a serial port circuit. Through the serial port (UART), communication between the circuit board and the computer can be easily achieved.

[0057] The signal acquisition module uses the AD9244 chip to implement the analog-to-digital conversion circuit. The external clock input is on the CLK pin; the acquired signal input is on the VINA pin; the output pins BIT1 to BIT12 output the converted result; OTR is the overflow flag pin, a high level indicates that the input signal exceeds the AD9244's range. +5V is the analog voltage input. GND is digital ground, and AGND is analog ground. Digital ground and analog ground are essentially both ground; the distinction is made for two main reasons: first, digital and analog signals can interfere with each other; second, analog signals have much higher requirements for grounding than digital signals. When the SENSE pin is grounded, the chip uses an internal reference source. In this mode, the internal reference voltage is output from VREF and is 2V, which is provided to the attenuation circuit. The AD acquisition circuit consists of three parts: the input stage circuit, the AD9244 circuit, and the input stage circuit. The input stage circuit converts the received signal into a 0-5V range for input to the AD9244. The connection method between the AD9244 and the FPGA pins is shown in the table below.

[0058] SignialName FPGA pin No. SignialName FPGA pin No. ADCA_CLK PIN_L8 ADNABCLK PIN_J6 ADCA_IN0 PIN_L9 ADCB0 PIN_K5 ADCA_IN1 PIN_P8 ADCB_1 PIN_F5 ADCA_IN2 PIN_M8 ADCB_2 PIN_G5 ADCA_IN3 PIN_P6 ADNA_3 PIN_E5 ADCA_IN4 PIN_M7 ADCB_4 PIN_F3 ADCA_IN5 PIN_M6 ADCB_5 PIN_D4 ADCA_IN6 PIN_N6 ADCB6 PIN_D3 ADCA_IN7 PIN_P3 ADNA_7 PIN_F6 ADCA_IN8 PIN_N5 ADCB_8 PIN_C3 ADCA_IN9 PIN_N3 ADCB19 PIN_D6 ADCA_IN10 PIN_L7 ADCB_10 PIN_D5 ADCA_IN11 PIN_L4 ADCB_11 PIN_E6 ADCA_IN12 PIN_L6 ADCB_12 PIN_C6 ADCA_IN13 PIN_K6 ADCB_13 PIN_C8

[0059] Because the AD9244 circuit uses a single-ended input, a bandgap reference chip REF3125 is used for intermediate level shifting, and an OPA355 is used for input isolation, resulting in an equivalent input impedance ≥100kΩ. The circuit board employs a dual-channel design, with G1, G2, and G3 constituting the input and level shifting. Therefore, the relationship between the input terminal S and the output terminal Vout is defined, and Vout is fixed within the range of 1V to 3V to match the input requirements of the AD9244.

[0060]

[0061] in S is the input signal, V out This is the output signal.

[0062] The data buffer module adopts SDRAM mode and uses the domestic chip W9825G6KH-6. The connection method between W9825G6KH-6 and FPGA is shown in the table below.

[0063]

[0064]

[0065] To facilitate signal processing by the PC host computer, a host computer software module was designed and developed based on the QT cross-platform C++ graphical user interface application development framework: a human-computer interaction module and a signal processing module. The signal processing module and the human-computer interaction module are used to implement ultrasonic digital signal noise reduction, real-time A-mode display, and real-time C-mode display.

[0066] To address the issues of severe superimposed noise in ultrasonic signals and the high memory consumption of arithmetic mean noise reduction, this invention combines the advantages of wavelet analysis ("signal microscope") and variational mode decomposition (VMD) in narrowband harmonic signal extraction, proposing an ultrasonic signal noise reduction method based on wavelet analysis combined with VMD. First, wavelet analysis is used to preprocess the ultrasonic signal, achieving initial separation of signal and noise. Then, VMD is used to decompose the signal, extracting components of the desired frequency band. The wavelet processing results are then optimized to achieve the final noise reduction.

[0067] An FPGA-based ultrasonic signal acquisition and processing method, using the aforementioned FPGA-based ultrasonic signal acquisition and processing system, includes the following steps:

[0068] Before applying threshold denoising to process signal noise, wavelet transform is first used to obtain the time-frequency information of the original signal. In the wavelet coefficients obtained after wavelet transform, the useful signal energy is mainly concentrated in a few wavelet coefficients with larger values, while the noise energy is almost distributed across all wavelet coefficients. Typically, the amplitude of the useful signal wavelet transform coefficients is greater than that of the noise wavelet transform coefficients. Based on this difference, a suitable threshold is selected from existing thresholds (existing thresholds include fixed thresholds, minima thresholds, unbiased risk estimation thresholds, and heuristic thresholds). The threshold function is then used to process the wavelet coefficients. Finally, an inverse wavelet transform is performed on the processed wavelet coefficients to reconstruct the denoised signal.

[0069] The VMD decomposition process can be summarized as decomposing the frequency-dominant signal into a set of amplitude-modulated and frequency-modulated (AM-FM) signals by filtering the original signal. After wavelet denoising, the signal undergoes VMD to select the frequency-dominant useful signal, achieving the final denoising goal. Assuming each "mode" has a finite bandwidth and a center frequency, the goal is to minimize the sum of the estimated bandwidths of each mode, achieving adaptive signal decomposition. The constraint is that the sum of the bandwidths of all modes equals the input signal. In this algorithm, the intrinsic mode function (IMF) is defined as a bandwidth-constrained AM-FM function. The function of the VMD algorithm is to construct and solve a constrained variational problem to decompose the original signal into a specified number of IMF components.

[0070] Because VMD decomposition exhibits a certain degree of sparsity, the bandwidth of the IMF components can be treated as a constrained variational problem when performing k-order decomposition to obtain the bandwidth. When evaluating the bandwidth of the IMF components, the VMD method first performs a Hilbert transform on each IMF component to calculate the corresponding analytic signal, obtaining a one-sided spectrum. Then, an exponential term is added to adjust the estimated frequencies at each center, shifting the spectrum of the IMF components to the "baseband." Finally, Gaussian smoothing, such as the gradient of the squared norm, is used to estimate the bandwidth using the modulated signal.

[0071] After noise reduction, the ultrasonic signal is displayed on the host computer's interface in both A-mode and C-mode. A-mode display, also known as A-scan, uses the time of the ultrasonic pulse signal emission as the starting point and records the ultrasonic echo signal after that time point, using this signal as a direct basis for defect judgment. In terms of display, the horizontal axis represents time, and the vertical axis represents signal amplitude. Different inspected objects will have different echo signals, and the presence or absence of internal material defects is manually judged based on their amplitude and waveform characteristics. C-mode display, also known as C-scan, works by scanning a certain area of ​​the workpiece using reflection or transmission, and then forming a two-dimensional image based on a specific characteristic of the echo at the corresponding position. C-scan detection can very intuitively identify defects and determine their location within the inspected workpiece. Combining this with digital automatic control equipment makes ultrasonic C-scan results more accurate and efficient. Therefore, this technology is widely used in the field of non-destructive testing due to its advantages of high sensitivity, high automation, and high intuitiveness.

Claims

1. An FPGA-controlled ultrasonic signal acquisition and processing system, comprising an FPGA chip and a host computer, characterized in that, The FPGA chip includes an FPGA control module, which is electrically connected to a signal acquisition module, a data buffer module, and a transmission module. The signal acquisition module is electrically connected to a signal conditioning module and a data buffer module. The ultrasonic analog signal is input to the signal conditioning module for filtering and amplification. The transmission module is electrically connected to a host computer to achieve data interaction. The host computer includes a human-machine interaction module and a signal processing module. The signal conditioning module includes a voltage follower module, a primary amplification module, a secondary amplification module, and a bandpass filter module, which are electrically connected in sequence within a metal fiber shield. The voltage follower module is built using an OPA192 voltage follower and resistors R1, R2, and R3, with resistor R1 = 20Ω; the primary amplification module consists of an instrumentation amplifier AD8429 and a front-end resistor R. G It consists of the rear resistor R4, and the resistor R G Resistors with 0.1% precision are used; the post-amplification module uses an OPA1611 operational amplifier, which consists of a cascaded two-stage and a three-stage amplifier circuit. The two-stage and three-stage amplifier circuits employ a voltage parallel negative feedback method. The two-stage amplifier circuit consists of an OPA1611 operational amplifier, capacitor C7, and resistors R5, R6, and R7. The three-stage amplifier circuit consists of an OPA1611 operational amplifier, capacitor C10, and resistors R8, R9, and R10. The feedback resistor R of the three-stage amplifier circuit... 10 A variable resistor is used; the bandpass filter module uses an operational amplifier OPA171, which consists of an operational amplifier OPA171, capacitors C13 and C14, and resistors R11, R12, R13, and R14.

2. The FPGA-controlled ultrasonic signal acquisition and processing system according to claim 1, characterized in that, The FPGA chip used is the Cyclone IV series EP4CE10F17C8N. The FPGA control module uses the NIOS II soft-core processor included in the FPGA chip as its core, configures the IP cores of the sub-modules required by the circuit, completes the construction of the software control environment, builds the system bus based on the AVALON-MM bus, and realizes data transmission between sub-modules through DMA. The signal acquisition module uses the AD9244 chip, the data buffer module uses the W9825G6KH-6 dynamic random access memory, and the transmission module uses the CH340 chip.

3. An ultrasonic signal acquisition and processing method based on FPGA control, characterized in that, The application of the FPGA-controlled ultrasonic signal acquisition and processing system as described in claim 1 includes the following steps: Step 1: Obtain the time-frequency information of the original signal using wavelet transform, process the wavelet coefficients using a threshold function, and finally perform inverse wavelet transform on the processed wavelet coefficients to reconstruct the denoised signal. Step 2: The VMD decomposition process involves filtering the original signal and decomposing the frequency-dominant signal into a set of amplitude-modulated and frequency-modulated signals. The Intrinsic Mode Function (IMF) is defined as a bandwidth-limited amplitude-modulated and frequency-modulated function. The VMD algorithm constructs and solves a constrained variational problem to decompose the original signal into a specified number of IMF components. Selecting the IMF of the desired frequency band from the decomposed IMFs yields the final denoised signal. Step 3: The ultrasonic signal after noise reduction is displayed in A-mode and C-mode on the host computer's display interface.

4. The ultrasonic signal acquisition and processing method based on FPGA control according to claim 3, characterized in that, In step 1, the received signal Perform continuous wavelet transform to obtain wavelet coefficients. : (1) In the formula, a and b are the scaling and translation factors, respectively, and * represents complex conjugation. The scaling and translation of the mother wavelet are achieved through factors a and b, thereby obtaining a series of wavelet bases. As shown in formula (2): (2) In step 2, the k-th order IMF component is represented as: (3) In the formula for The instantaneous amplitude; for The instantaneous frequency; It is a set of discrete sub-signals, each with a sparse and different bandwidth in the time spectrum; The constrained variational model expression is: (4) In the formula These are the IMF components obtained from the decomposition; The center frequency of the IMF component; Introducing a secondary penalty term The constrained variational problem is transformed into an unconstrained variational problem by using the Lagrange multiplier λ, and the resulting augmented Lagrange expression is: (5) The saddle point of the augmented Lagrangian function is obtained using the alternating direction multiplier algorithm, which is the optimal solution of the constrained variational model. This decomposes the original signal into k IMF components, yielding the following result: (6) (7) (8) In the formula, n represents the number of iterations. Represents frequency value, , and They are respectively , and The Fourier transform of the desired mode, where γ represents the noise tolerance, is given by the desired mode. The Intrinsic Mode Function (IMF) can be obtained by performing an inverse Fourier transform. The final denoised signal can be obtained by selecting the IMF of the desired frequency band from the k decomposed IMFs.

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