High speed current steering DAC circuit

Abstract

The application discloses a high-speed current steering DAC circuit, which comprises a bias circuit module, a current source array, a decoder module, a latch control array and a current source control array; the current source array and the bias circuit module are implemented by high-voltage devices, and the decoder module, the latch control array and the current source control array are implemented by low-voltage devices; the current source array is used for generating N paths of currents based on a reference current; the bias circuit module is used for providing a bias voltage for the current source array, so that each path of current in the current source array is consistent with the reference current; the decoder module is used for decoding a digital signal and outputting a decoding signal; the latch control array is used for controlling the current source control array to work according to the decoding signal; and the current source control array is used for sequentially controlling each path of current in the current source array to flow through a resistor, so as to output an analog voltage signal. The application can effectively improve the DAC speed and the synchronism of a multi-path logic circuit.

Description

Technical Field

[0001] This invention relates to the field of circuit technology, specifically to a high-speed current-driven DAC circuit. Background Technology

[0002] A digital-to-analog converter (DAC) is a device that converts digital signals into analog signals. The input to a DAC is a codeword, composed of parallel binary signals generated by a digital signal processing system. Using a reference voltage or current, the parallel binary signal is converted into an equivalent analog signal. This analog signal, after filtering and amplification, is used in analog signal processing systems, playing a crucial role in signal transmission systems. With the development of communication technology, higher demands are placed on the speed and accuracy of DACs. Current-steering (CS) DACs effectively alleviate this contradiction. Unlike other DAC structures, current-steering DACs have a simple structure, consisting of a binary current source or a current source matrix, plus a current switch controlled by binary numbers.

[0003] Traditional current-driven DACs generally suffer from the following problems:

[0004] (1) High voltage devices are used, which are slower and have a higher crossover voltage (i.e., the voltage when the level changes). This will cause the current mirror array switches to turn off at the same time, resulting in a slower current source conversion speed. Additional circuits are needed to reduce the crossover voltage, which is complex in structure and has timing inconsistency issues.

[0005] (2) There is a current mirror mismatch problem, which leads to low DAC accuracy.

[0006] (3) The bias current of the current source has an overshoot problem, which may cause the switching device to break down. Summary of the Invention

[0007] This invention provides a high-speed current-steering DAC circuit to solve one or more problems existing in the above-mentioned existing current-steering DAC circuits.

[0008] Therefore, the embodiments of the present invention provide the following technical solutions:

[0009] A high-speed current-controlled DAC circuit includes: a bias circuit module, a current source array, a decoder module, a latch control array, and a current source control array; the current source array and the bias circuit module are implemented using high-voltage devices, while the decoder module, the latch control array, and the current source control array are all implemented using low-voltage devices.

[0010] The current source array is used to generate multiple current sources based on a reference current source;

[0011] The bias circuit module is configured to provide bias voltage for the current source array, so that each current source in the current source array mirrors the reference current according to a set ratio.

[0012] The decoder module is configured to decode the digital signal and output a decoded signal.

[0013] The latch control array is configured to latch the decoded signal and control the operation of the current source control array.

[0014] The current source control array is configured to control each current source in the current source array to flow through a resistor in sequence, so as to output an analog voltage signal.

[0015] Optionally, the bias circuit module comprises two bias circuits, i.e., a first bias circuit and a second bias circuit, the first bias circuit provides bias voltage for a high-N1 current source array in the current source array, the second bias circuit provides bias voltage for a low-N2 current source array in the current source array, and N1+N2=N, where N is the total number of current sources in the current source array.

[0016] Optionally, each bias circuit outputs two bias voltages to one current source.

[0017] Optionally, the decoder module decodes the low bits and high bits of the digital signal in different ways.

[0018] Optionally, the decoder module comprises a binary decoder and a thermometer decoder.

[0019] The binary decoder is configured to decode the low bits of the digital signal.

[0020] The thermometer decoder is configured to decode the high bits of the digital signal.

[0021] Optionally, the digital signal is N bits, the binary decoder decodes the low N1 bits of the digital signal, the thermometer decoder decodes the high N2 bits of the digital signal, N1+N2=N, and N2≥N1.

[0022] Optionally, the latch control array comprises a plurality of latches, each of which is connected to an output terminal of the decoder module.

[0023] Optionally, the current source control array comprises a plurality of control switches, each of which is connected to the output terminal of a latch and the output terminal of a current source in the current source array, and is configured to control the output or disconnection of the current source connected thereto according to the output signal of the latch connected thereto.

[0024] Optionally, each control switch is a differential switch composed of a first PMOS transistor and a second PMOS transistor.

[0025] Optionally, the circuit further comprises a bias current detection module for controlling the bias current output by the bias circuit module.

[0026] Optionally, the bias current detection module comprises:

[0027] a voltage collection unit for collecting the bias current output by the bias circuit module to generate a monitoring voltage;

[0028] a comparator for comparing the monitoring voltage and a reference voltage, and feeding back a high level to the bias circuit module in the case that the monitoring voltage is greater than the reference voltage.

[0029] Optionally, the circuit further comprises a bandgap reference module for providing the reference current source and the reference voltage.

[0030] A chip comprising the high-speed current steering DAC circuit described above.

[0031] The high-speed current steering DAC circuit provided by the embodiment of the present application adopts high-voltage devices for the bias circuit module and the current source array module, and adopts low-voltage devices for the rest of the modules. Since the low-voltage devices have a faster rising and falling time, the DAC speed can be effectively improved, and the problem that the current source conversion speed is slowed down due to the simultaneous shutdown of the current mirror array switch caused by the excessively high cross-point voltage can be solved. Moreover, compared with the scheme in which a high-voltage device DAC needs to be implemented by using a cross-point voltage reduction circuit, the scheme of the present application can simplify the circuit, improve the DAC conversion speed, and improve the synchronization of the multi-path logic circuit.

[0032] Further, the high and low bias voltages in the bias circuit module are matched separately, which can facilitate layout matching, reduce current mirror mismatch, and effectively improve the DAC precision.

[0033] Further, the bias current detection module can be used to limit the size of the current source bias current, prevent overshoot caused by excessively large current, avoid the breakdown of the low-voltage device switch, and improve the safety and reliability of the circuit. BRIEF DESCRIPTION OF DRAWINGS

[0034] Figure 1 is a schematic structural diagram of a current steering DAC circuit provided by the embodiment of the present application;

[0035] Figure 2 is a schematic structural diagram in which one bias circuit is used to provide bias voltage for the current source array in the embodiment of the present application;

[0036] Figure 3is a structural schematic diagram of a biasing circuit providing biasing voltage for a current source array in an embodiment of the present application;

[0037] Figure 4 is a specific application structural schematic diagram of a current steering DAC circuit provided by an embodiment of the present application;

[0038] Figure 5 is another principle structural schematic diagram of a current steering DAC circuit provided by an embodiment of the present application;

[0039] Figure 6 is a structural schematic diagram of a biasing current detection module in an embodiment of the present application;

[0040] Figure 7 is a DAC simulation result obtained by simulation test of the high-speed current steering DAC circuit provided by an embodiment of the present application;

[0041] Figure 8 is a simulation result of a current steering DAC circuit designed by using a high-voltage device and one biasing circuit in a traditional way. DETAILED DESCRIPTION

[0042] In order to make the above-mentioned purposes, features and advantages of the present application more obvious and easy to understand, the specific embodiments of the present application will be described in detail below with reference to the drawings.

[0043] The current steering DAC is used to control the output of the current generated by different bit weight current sources through input digital signal sequence, so as to convert the digital signal into corresponding analog voltage signal. The working process is to form a current source network by using active devices, and to control corresponding switches by using input signal sequence to gate corresponding current source branches to output different results.

[0044] In view of the problems of low current source conversion speed and complex circuit of the existing current steering DAC, an embodiment of the present application provides a high-speed current steering DAC circuit, in which high-voltage devices are used in the biasing circuit module and the current source array module, and low-voltage devices are used in the rest modules.

[0045] As shown in Figure 1 is a principle structural schematic diagram of a current steering DAC circuit provided by an embodiment of the present application.

[0046] The current steering DAC circuit of the embodiment comprises a biasing circuit module 11, a current source array 12, a decoder module 13, a latch control array 14 and a current source control array 15. Among them:

[0047] The current source array 12 is used to generate multiple current sources based on a reference current;

[0048] The bias circuit module 11 is used to provide a bias voltage to the current source array so that each current source in the current source array mirrors the reference current according to a set ratio.

[0049] The decoder module 13 is used to decode digital signals and output decoded signals;

[0050] The latch control array 14 is used to latch the decoded signal and control the current source control array to work.

[0051] The current source control array 15 is used to sequentially control the current in the current source array to flow through the resistors in order to output an analog voltage signal.

[0052] In a non-limiting embodiment of the present invention, the current source array 12 and the bias circuit module 11 are implemented by high-voltage devices, while the decoder module 13, the latch control array 14, and the current source control array 15 are all implemented by low-voltage devices.

[0053] Because low-voltage devices have faster rise and fall times, they can effectively improve DAC speed and solve the problem of excessively high crossover voltage in existing current-controlled DAC circuits causing the current mirror array switches to turn off simultaneously, resulting in slower current source switching speed.

[0054] In specific applications, the bias circuit module 11 can adopt a conventional bias circuit structure, that is, use one bias circuit to provide the same bias voltage to each current source in the current source array 12.

[0055] In order to better align each current in the current source array 12 with the reference current, in a non-limiting embodiment of the present invention, the bias circuit in the bias circuit module 11 may also output two bias voltages to each current source in the current source array 12.

[0056] like Figure 2 The diagram shown is a schematic of a current source array using a bias circuit in an embodiment of the present invention.

[0057] Among them, the function of NMOS transistors MN1 and MN2 is to convert the reference current I... REFThe PMOS tube MP1 is used to provide bias voltage for the PMOS tubes MP3 and MP5, the NMOS tube MN3 and the PMOS tubes MP2 and MP3 are used to provide bias voltage for the PMOS tube MP4, the PMOS tubes MP2 to MP5 form a Cascode (common source and common gate) current mirror, which can suppress the influence of channel length modulation, so that the current mirror can obtain more accurate current, thereby improving the dynamic performance of the DAC. The NMOS tubes MN4 to MN7 are used to convert the PMOS Cascode current mirror into an NMOS Cascode current mirror, the PMOS tube MP6 is used to provide a first bias voltage PBC for the current source array 12, and the PMOS tubes MP7 and MP8 are used to provide a second bias voltage PB for the current source array 12. Through the second bias voltage PB and the first bias voltage PBC, each branch current in the current source array 12 can be more accurately mirrored to the reference current.

[0058] Figure 2 In the embodiment, the current source array can include multiple current sources, which correspond to the number of bits of the decoding signal output by the decoder module 13. For example, if the decoding signal output by the decoder module 13 has 8 bits, the current source array has 8 current sources. In order to make the drawing clear, only two current sources are shown in the embodiment, i.e., a current source in which the PMOS tubes MP11 and MP12 are located, representing a low-bit current source, and a current source in which the PMOS tubes MP13 and MP14 are located, representing a high-bit current source. Each current source is composed of two PMOS tubes connected in common source and common gate. Figure 1 Figure 2 It should be noted that the PMOS tubes in the current array are all high-voltage devices.

[0059] It should be noted that the PMOS tubes in the current array are all high-voltage devices.

[0060] Figure 2 In the circuit structure shown in the embodiment, the bias circuit module includes the PMOS tubes MP1 to MP8 and the NMOS tubes MN1 to MN9, which are all high-voltage devices. The bias circuit module includes a bias circuit for each current source in the current source array, which outputs bias voltage for each current source. In the embodiment, the bias circuit outputs two bias voltages for each current source, such as the first bias voltage PBC input to the gate of MP12 of the low-bit current source and the gate of MP14 of the high-bit current source, and the second bias voltage PB input to the gate of MP11 of the low-bit current source and the gate of MP13 of the high-bit current source. Figure 2

[0061] It should be noted that the main function of the bias voltage is to make the matching of the current of each current source and the reference current more accurate.

[0062] ​​According to the MOS transistor current formula in the saturation region I = (1 / 2) U n C ox (W / L)(V gs -V th ) 2 , where U n is the electron mobility, Cox is the unit area gate oxide capacitance, W / L is the MOS transistor channel width-length ratio (referred to as MOS transistor width-length ratio or width-length ratio), Vgs is the gate-source voltage, and Vth is the threshold voltage, which is the gate-source voltage when a specified current appears between the source and the drain.

[0063] From the above formula, for two mirror current sources, the bias voltage is the same, V gs -V th of the two is equal, and the rest of the parameters are equal. In this case, the current relationship of the two is proportional to the corresponding MOS transistor width-length ratio. Therefore, the ratio of the current of each current source in the current source array 12 to the reference current depends on the ratio of the MOS transistor width-length ratio of the current source to the MOS transistor width-length ratio of the MOS transistor that provides the bias voltage for the reference current.

[0064] Figure 2 The bias circuit module structure shown is relatively simple, but the flexibility of device matching in this structure is small, because in this embodiment, MP11 and MP13 both need to be proportional to the W / L of MP7, and MP12 and MP14 both need to be proportional to the W / L of MP8, to ensure the ratio of each current source to the reference current. In addition, the W / L of MP11 and MP13 also needs to be proportional, and the W / L of MP12 and MP14 also needs to be proportional. The so-called width-length ratio is the ratio of the width to the length of the conductive channel of the MOS transistor. The larger the width-length ratio, the larger the Id (maximum drain-source current) of the MOS transistor, that is, the width-length ratio is proportional to the Id.

[0065] For example, in the ideal state (i.e., without mismatch) W MP11 / L MP11 = k1W MP7 / L MP7 , W MP12 / L MP12 = k1W MP8 / L MP8 , W MP13 / L MP13 = k2W MP7 / L MP7 , W MP14 / L MP14 = k2W MP8 / L MP8 , I 11 = k1I7, I 13 = k2I7.

[0066] in addition, Figure 2 The bias circuit module structure shown can require a large layout area. Typically, the layout area depends on the product of the W and L values ​​of the MOSFETs. For single-path bias, all W and L values ​​are the same, only the number of MOSFETs differs. Higher bit counts result in more MOSFETs and a larger area. Furthermore, since each MOSFET has the same shape, the overall current source array will have a relatively uniform shape, making it difficult to adjust to the shapes of other modules in the layout, ultimately leading to a large overall layout area. However, for dual-path bias, two types of MOSFETs with different W and L values ​​can be selected. Current sources with higher bit counts can choose MOSFETs with relatively smaller W and L values. The shape of the entire current source array composed of two sets of MOSFETs with different W and L values ​​is more flexible and can be adjusted to the shapes of other modules in the layout. This effectively reduces the overall layout area without affecting matching.

[0067] Therefore, in another non-limiting embodiment of the present invention, the bias circuit module can adopt a two-way bias circuit structure, such as... Figure 3 The diagram shown is a schematic of the structure in an embodiment of the present invention, which uses two bias circuits to provide bias voltage for the current source array.

[0068] Figure 3 Current source array in Figure 2 The same applies here, so I will not repeat it further.

[0069] and Figure 2 Compared to the bias circuit module in the middle, in Figure 3 In the illustrated embodiment, an additional bias circuit is added to the bias circuit module, namely, PMOS transistors MP9 and MP10, and NMOS transistors MN10 and MN11, all of which are high-voltage devices. The bias circuit containing MP9 and MP10 has the same structure as the bias circuit containing MP7 and MP8. For ease of description, these two bias circuits are referred to as the first bias circuit (the bias circuit containing MP7 and MP8) and the second bias circuit (the bias circuit containing MP9 and MP10), respectively. The bias voltage output by the first bias circuit and the bias voltage output by the second bias circuit can be the same or different.

[0070] exist Figure 3 In the illustrated embodiment, the first bias circuit provides a bias voltage for the low-level current source, and the second bias circuit provides a bias voltage for the high-level current source. Figure 2 Similar to the examples in, Figure 3 Each bias circuit in the circuit outputs two bias voltages to a current source, for example... Figure 3The first bias voltage PBC and the second bias voltage PB_LSB of MP12 and MP11, which are input to the low-level current sources respectively by the first bias circuit, and the first bias voltage PBC and the second bias voltage PB_MSB of MP14 and MP13, which are input to the high-level current sources respectively by the second bias circuit.

[0071] It should be noted that, in specific applications, the first bias circuit can provide bias voltage to the low N1 current source arrays in the current source array, and the second bias circuit can provide bias voltage to the high N2 current source arrays in the current source array; or the first bias circuit can provide bias voltage to the high N1 current source arrays in the current source array, and the second bias circuit can provide bias voltage to the low N2 current source arrays in the current source array. Wherein, N1 + N2 = N, and N is the total number of current sources in the current source array 12.

[0072] exist Figure 3 In the illustrated embodiment, the process parameters of some MOSFETs need to meet the following requirements: the W / L ratio of MP11 is proportional to that of MP7, the W / L ratio of MP12 is proportional to that of MP8, the W / L ratio of MP13 is proportional to that of MP9, and the W / L ratio of MP14 is proportional to that of MP10.

[0073] For example, W MP11 / L MP11 =k1W MP7 / L MP7 W MP12 / L MP12 =k1W MP8 / L MP8 W MP13 / L MP13 =k2W MP9 / L MP9 W MP14 / L MP14 =k2W MP10 / L MP10 .

[0074] Figure 3 The bias circuit module structure in the illustrated embodiment, although adding one bias circuit (i.e., adding a component), offers greater flexibility in component matching. For example, the two bias circuits can provide bias voltages to the low-order and high-order current sources of the current source array respectively. Therefore, the W / L ratios of MP7 and MP9 can be different, and the W / L ratios of MP11 and MP13 will not restrict each other. This allows for more flexible layout matching, enabling more reasonable layout design and reducing chip area. Furthermore, Figure 3 The structure of the bias circuit module shown can also reduce current mirror mismatch without increasing the layout area, thereby further improving DAC accuracy.

[0075] The reason of the current mirror mismatch is that the channel width W and length L of the PMOS transistor in the current source array and the PMOS transistor for providing the reference current are smaller than the ideal values due to the process manufacturing. In order to reduce the mismatch, the W / L of the reference current PMOS transistor and the current source PMOS are proportional, and the larger the W and L are, the smaller the mismatch is. However, the large W and L will result in the large area of the high bit current mirror. The W and L of the high bit current mirror are relatively small and the W and L of the low bit current mirror are relatively large by using two sizes of W and L to match, so that the current mirror mismatch is reduced and the current source current is more accurate without increasing the layout area.

[0076] With reference to the foregoing Figure 3 In the embodiment of the application, the current source control array 15 includes a plurality of control switches corresponding to the number of the current sources in the current source array 12. Each control switch is connected with the output of a latch and the output of a current source in the current source array 12, and is used to control the connection or disconnection of the current source according to the output signal of the latch.

[0077] The control switch is a differential switch composed of a first PMOS transistor and a second PMOS transistor. When one of the PMOS transistors is turned on, the other PMOS transistor is turned off, so as to output a differential voltage signal.

[0078] The PMOS transistors are turned on or turned off by the latch control array. In the normal working state, only one of the PMOS transistors is turned on and the other is turned off. The current of the current source array 12 flows through the resistor through the switch, so as to output an analog voltage signal.

[0079] If the latch control array is a high voltage device, the output low voltage is too high, which may cause the two PMOS switches to be turned off at the same time, so as to slow down the current source switching speed. Therefore, the switch tubes MP15- MP18 in the current source control array 15 are low voltage devices, and the circuit structure is the same as that of the high voltage device, only the working voltage domain is low voltage domain, such as 1.2V, and the working voltage domain of the high voltage device is high voltage domain, such as 3.3V. In the case that the switch tubes MP15- MP18 in the current source control array 15 are low voltage devices, as long as the current of each current source in the current source array 12 is controlled, that is, the reference current I REFThe size of the low-voltage device ensures that the voltage on the switch tubes MP15- MP18 is less than or equal to 1.2V. Since the decoder module and the latch control array adopt low-voltage devices, the rising and falling time of the low-voltage device is faster, so the speed of the DAC of the design is relatively faster than that of the high-voltage device. In addition, the cross-point voltage of the low-voltage device is lower than that of the high-voltage device, and the ideal cross-point voltage is 1 / 2 of the power supply voltage. Since the power supply voltage of the low-voltage device is low, the cross-point voltage is naturally low. Therefore, the use of low-voltage devices can effectively prevent the problem that the high cross-point voltage of the latch causes the switch tubes MP15- MP18 of the current source control array to be simultaneously turned off, thereby slowing down the switching speed of the current source. For example, the working voltage of the 1.2V low-voltage device is 1.2V at most and 0V at least, the low voltage output by the latch is about 0V, the switch tube is a PMOS, the source voltage is fixed, the lower the gate voltage, the greater the absolute value of V gs , and the easier the PMOS is turned on. The absolute value of V gs is difficult to be lower than the absolute value of V th . Since the V gs of the PMOS is negative, the absolute value of V gs is greater than the absolute value of V th , and the PMOS is turned on. Therefore, the two PMOS tubes will not be turned off at the same time. For the high-voltage device, the working voltage is 3.3V at most, and the low voltage output by the latch of the high-voltage device is higher than that of the low-voltage device, which will cause the V gs to be lower than V th , so that the two PMOS tubes are turned off at the same time, thereby slowing down the switching speed of the current source.

[0080] It should be noted that, in actual applications, the bias circuit module, the current source array and the current source control array provided in the embodiments of the present application are not limited to the structures shown in the above Figure 2 and Figure 3 , and other variant structures can also be used as long as the corresponding functions can be met, and the embodiments of the present application are not limited in this regard.

[0081] In a non-limiting embodiment of the present application, as shown in Figure 4 , the decoder module 13 adopts different decoding methods to decode the low bits and the high bits of the digital signal. As shown in Figure 4 , the decoder module 13 can include a binary decoder 131 and a thermometer decoder 132. The binary decoder 131 is configured to decode the low bit digital signal, and the thermometer decoder 132 is configured to decode the high bit digital signal.

[0082] Specifically, the digital signal is N bits; the binary decoder decodes low N1 bits of the digital signal, and the thermometer decoder decodes high N2 bits of the digital signal, N1+N2=N, and N2≥N1. Taking an 11-bit DAC as an example, low 5 bits can be decoded by the binary decoder 131, and high 6 bits can be decoded by the thermometer decoder 132. Of course, other allocation manners, such as low 6 bits and high 5 bits, can also be used, and the embodiments of the present application are not limited in this regard.

[0083] If binary decoders are used, when the DAC input signal changes from 01111111111 to 10000000000, all the switches in the current source control array 15 will be switched at the same time, which may cause the DAC to generate a pulse signal and make the linearity of the DAC poor. In the manner of decoding high and low bits respectively, for example, low 5 bits are decoded by the binary decoder 131, and high 6 bits are decoded by the thermometer decoder 132. Since the weight of low 5 bits is low, the binary decoder is used, the structure is relatively simple, and the speed is relatively fast; the high 6 bits are decoded by the thermometer decoder, which ensures that when the DAC input signal changes, only one switch in the high 6 bits is switched each time, and thus the linearity of the DAC can be effectively improved.

[0084] It should be noted that the specific structure of the binary decoder 131 and the thermometer decoder 132 is the same as that of the prior art, and will not be described here.

[0085] Continuing to refer to Figure 4 In the embodiments of the present application, a latch corresponding to each decoding output in the latch control array 14 is connected, and the main function of the latch is to cache the decoding signals output by the decoder. Since the input signal of the DAC is always changing, the signal output by the decoder will also always change, and through the latch, the signal output by the decoder in the previous state can be locked at 0 and 1, and the current source control array 15 is controlled to work. At this time, the output of the decoder has become the next state, and then the latch locks the signal output by the decoder in the next state at 0 and 1, and controls the current source control array 15 to work subsequently, so as to ensure that the DAC circuit can work at high speed.

[0086] It should be noted that the structure of each latch can be the same as that of the existing latch, but the difference is that, in the embodiments of the present application, two latches with the same voltage domain are needed for the decoding signals output by the two different decoders.

[0087] In the embodiments of the present application, the voltage domain of the latch needs to be consistent with the voltage domain of the decoder module and the current source control array, and is a low-voltage device.

[0088] The devices in the latch of the embodiment of the present application are all low-voltage devices, and no high-voltage device is used, which not only can effectively solve the problem that the current source conversion speed is slowed down due to the simultaneous turn-off of the multi-path control switches in the current source control array caused by the excessively high cross point voltage, but also can reduce the complexity of the circuit, improve the synchronization of the multi-path logic circuit, and improve the conversion speed of the DAC.

[0089] As shown in Figure 5 , Figure 5 is another schematic diagram of the principle structure of the current steering DAC circuit provided by the embodiment of the present application.

[0090] Compared with the embodiment shown in Figure 1 , in this embodiment, the current steering DAC circuit further comprises a bias current detection module 16 for controlling the bias current output by the bias circuit module 11.

[0091] As shown in Figure 6 , it is a schematic diagram of one structure of the bias current detection module.

[0092] The bias current detection module comprises a voltage acquisition unit 161 and a comparator 162. The voltage acquisition unit 161 is used to acquire the bias current I BIAS output by the bias circuit module 11, and generate a monitoring voltage V B ; the comparator 162 is used to compare the monitoring voltage V B and a reference voltage V REF . In the case that the monitoring voltage V B is greater than the reference voltage V REF , a high level is fed back to the bias circuit module 11, so that the bias voltage thereof is increased, thereby reducing the bias current generated thereby, and the reference current of each subsequent bias circuit is correspondingly reduced, forming a negative feedback loop. The output of the comparator 162 can only be 0 or a high level. The embodiment of the present application does not limit the specific way in which the feedback signal output by the comparator 162 is connected to the bias circuit module 11, as long as the effect of reducing the current in the MP4 and MP5 branches can be achieved.

[0093] It should be noted that the bias current I BIAS can be obtained by copying one current output in the current source array 12 and copying one bias circuit in the bias circuit 11. For the case shown in Figure 3 , there are two bias circuits, and any one of them can be copied, which is not limited by the embodiment of the present application.

[0094] In addition, it should be noted that the reference voltage V REFThe reference current I input in the bias circuit module 11 can be provided by a bandgap reference module (not shown) REF (as shown in Figure 2 and Figure 3 ) can also be provided by the bandgap reference module.

[0095] In actual applications, if there is a corresponding bandgap reference module in the device to which the current steering DAC circuit is applied, the bandgap reference module in the device can be used, and if not, the bandgap reference module needs to be additionally arranged in the current steering DAC circuit.

[0096] The high-speed current steering DAC circuit provided by the embodiment of the application adopts high-voltage devices for the bias circuit module and the current source array module, and adopts low-voltage devices for the rest of the modules. Because the rising and falling times of the low-voltage devices are fast, the DAC speed can be effectively improved, and the problem that the current source conversion speed is slowed down due to the simultaneous turn-off of the current mirror array switches caused by the excessively high cross-point voltage is solved. Moreover, compared with the scheme in which a high-voltage device DAC needs to be implemented by using a cross-point voltage reduction circuit, the scheme of the application can simplify the circuit, improve the synchronization of the multi-path logic circuit, and optimize the timing inconsistency.

[0097] Further, the high and low bias voltages in the bias circuit module are matched separately, which facilitates layout matching, reduces current mirror mismatch, and effectively improves the DAC precision.

[0098] Further, the bias current detection module can limit the bias current size of the current source, prevent overshoot caused by excessively large current, avoid the breakdown of the low-voltage device switch, and improve the safety and reliability of the circuit.

[0099] Compared with the existing current steering DAC circuit, the high-speed current steering DAC circuit provided by the embodiment of the application has the following advantages:

[0100] 1. The rising and falling times of the low-voltage devices are fast, which can improve the DAC speed and solve the problem that the current source conversion speed is slowed down due to the simultaneous turn-off of the current mirror array switches caused by the excessively high cross-point voltage.

[0101] 2. Compared with the scheme in which a high-voltage device DAC needs to be implemented by using a cross-point voltage reduction circuit, the design can simplify the circuit, improve the synchronization of the multi-path logic circuit, and optimize the timing inconsistency.

[0102] 3. The high and low bias voltages are matched separately, which facilitates layout matching, reduces current mirror mismatch, and effectively improves the DAC precision without increasing the layout area.

[0103] 4. The bias current detection module can limit the bias current size of the current source, prevent overshoot caused by excessively large current, and avoid the breakdown of the low-voltage device switch.

[0104] The simulation test comparison between the high-speed current steering DAC circuit provided by the embodiment of the present application and the conventional current steering DAC circuit designed by using high-voltage devices and one-way biasing can further illustrate the above effects of the present application relative to the conventional scheme.

[0105] The simulation test results are shown in Figure 7 and Figure 8 , wherein, Figure 7 the DAC simulation result obtained by the simulation test of the high-speed current steering DAC circuit provided by the embodiment of the present application is shown in Figure 8 , and the simulation result of the conventional current steering DAC circuit designed by using high-voltage devices and one-way biasing is shown in

[0106] Figure 7 and Figure 8 The simulation results of and are obtained by inputting the step signals into the differential signals output by the two different current steering DAC circuits with a sampling frequency of 500 MHz.

[0107] As can be seen from the simulation results, Figure 8 the INL (Integral Nonlinearity) and DNL (Differential nonlinearity) of the differential signals output by the current steering DAC circuit provided by the embodiment of the present application shown in are both very poor, greater than 2LSB (Least Significant Bit). While Figure 7 the INL and DNL of the differential signals output by the current steering DAC circuit provided by the embodiment of the present application shown in are both less than 1LSB, which is obviously superior to the prior art.

[0108] Correspondingly, the embodiment of the present application also provides a chip comprising the high-speed current steering DAC circuit.

[0109] The various modules / units included in the various devices and products described in the above embodiments can be software modules / units or hardware modules / units, or can be partially software modules / units and partially hardware modules / units. For example, for the various devices and products applied to or integrated into a chip, the various modules / units included therein can all be implemented in the form of hardware such as circuitry, or at least some of the modules / units can be implemented in the form of a software program running on a processor integrated in the chip, and the remaining (if any) modules / units can be implemented in the form of hardware such as circuitry; for the various devices and products applied to or integrated into a chip module, the various modules / units included therein can all be implemented in the form of hardware such as circuitry, and different modules / units can be located in the same component (e.g., a chip, a circuit module, etc.) or different components of the chip module, or at least some of the modules / units can be implemented in the form of a software program running on a processor integrated in the chip module, and the remaining (if any) modules / units can be implemented in the form of hardware such as circuitry; for the various devices and products applied to or integrated into a terminal device, the various modules / units included therein can all be implemented in the form of hardware such as circuitry, and different modules / units can be located in the same component (e.g., a chip, a circuit module, etc.) or different components of the terminal device, or at least some of the modules / units can be implemented in the form of a software program running on a processor integrated in the terminal device, and the remaining (if any) modules / units can be implemented in the form of hardware such as circuitry.

[0110] It should be noted that "multiple" appearing in the embodiments of the present application means two or more.

[0111] The first, second, and the like appearing in the embodiments of the present application are only for illustrative and distinguishing purposes, and do not have an order, nor do they particularly limit the number of devices in the embodiments of the present application, and cannot constitute any limitation on the embodiments of the present application.

[0112] The above-described embodiments can be implemented in whole or in part by software, hardware, firmware, or any combination thereof. When implemented by software, the above-described embodiments can be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions or computer programs. When the computer instructions or computer programs are loaded or executed on a computer, the processes or functions described in the embodiments of the present application are wholly or partially generated. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable devices. The computer instructions can be stored in a computer-readable storage medium or transferred from one computer-readable storage medium to another computer-readable storage medium, for example, the computer instructions can be transferred from one website, computer, server, or data center to another website, computer, server, or data center through a wired or wireless manner.

[0113] It should be understood that the size of the sequence number of each process described above in various embodiments of the present application does not mean the order of execution, and the execution order of each process should be determined by its function and inherent logic, and should not constitute any limitation on the implementation process of the embodiments of the present application.

[0114] In several embodiments provided in the present application, it should be understood that the disclosed methods, devices and systems can be implemented in other ways. For example, the device embodiments described above are only schematic; for example, the division of the units is only a logical function division, and actual implementation can have another division manner; for example, a plurality of units or components can be combined or integrated into another system, or some features can be omitted or not executed. In addition, the coupling or direct coupling or communication connection between the units shown or discussed can be indirect coupling or communication connection through some interfaces, devices or units, which can be electrical, mechanical or other forms.

[0115] The units described as separate components can or can not be physically separated, and the components shown as units can or can not be physical units, that is, they can be located in one place, or can be distributed on a plurality of network units. Part or all of the units can be selected according to actual needs to achieve the purpose of the embodiments of the present application.

[0116] In addition, each functional unit in each embodiment of the present application can be integrated in one processing unit, or each unit can be physically included separately, or two or more units can be integrated in one unit. The integrated unit can be realized in the form of hardware or in the form of hardware plus software functional unit.

[0117] The integrated unit implemented in the form of software functional units can be stored in a computer readable storage medium. The software functional units stored in the storage medium can include a number of instructions for causing a computer device (which can be a personal computer, a server, or a network device, etc.) to execute part of the steps of the methods described in the various embodiments of the present application.

[0118] Although the present application is disclosed by the above, the present application is not limited thereto. Any person skilled in the art, without departing from the spirit and scope of the present application, can make various changes and modifications, therefore the protection scope of the present application should be subject to the range defined by the claims.

Claims

1. A high speed current steering DAC circuit, characterized by, The circuit comprises a bias circuit module, a current source array, a decoder module, a latch control array and a current source control array; the current source array and the bias circuit module are implemented by high-voltage devices, and the decoder module, the latch control array and the current source control array are implemented by low-voltage devices; The current source array is configured to generate multiple current sources based on a reference current source; The bias circuit module is configured to provide bias voltage for the current source array, so that each current source in the current source array mirrors the reference current in a set proportion; The decoder module is configured to decode a digital signal and output a decoded signal; The latch control array comprises multiple latches, which are configured to latch the decoded signal and control the current source control array to work; The current source control array is configured to control each current source in the current source array to flow through a resistor in sequence, so as to output an analog voltage signal; the current source control array comprises multiple control switches, each of which is connected to the output end of a latch and the output end of a current source in the current source array, and is configured to control the output or disconnection of the current source connected thereto according to the output signal of the latch connected thereto.

2. The high-speed current steering DAC circuit of claim 1, wherein, The bias circuit module comprises two bias circuits, i.e., a first bias circuit and a second bias circuit; the first bias circuit provides bias voltage for a high-N1 current source array in the current source array, and the second bias circuit provides bias voltage for a low-N2 current source array in the current source array, wherein N1+N2=N, and N is the total number of current sources in the current source array.

3. The high-speed current steering DAC circuit of claim 2, wherein, Each bias circuit outputs two bias voltages to a current source.

4. The high-speed current steering DAC circuit of claim 1, wherein, The decoder module decodes the low bits and high bits of the digital signal in different decoding manners.

5. The high-speed current steering DAC circuit of claim 4, wherein, The decoder module comprises a binary decoder and a thermometer decoder; The binary decoder is configured to decode low-bit digital signals; The thermometer decoder is configured to decode high-bit digital signals.

6. The high-speed current steering DAC circuit of claim 5, wherein, The digital signal is N bits; the binary decoder decodes low-N1 bits of the digital signal, the thermometer decoder decodes high-N2 bits of the digital signal, N1+N2=N, and N2≥N1.

7. The high-speed current steering DAC circuit of claim 2, wherein, Each latch in the latch control array is connected to an output end of the decoder module.

8. The high-speed current steering DAC circuit of claim 1, wherein, Each control switch is a differential switch composed of a first PMOS transistor and a second PMOS transistor.

9. The high-speed current steering DAC circuit of claim 8, wherein, The circuit further comprises: a bias current detection module configured to control the bias current output by the bias circuit module.

10. The high-speed current steering DAC circuit of claim 9, wherein, The bias current detection module comprises: a voltage acquisition unit configured to acquire the bias current output by the bias circuit module and generate a monitoring voltage; a comparator configured to compare the monitoring voltage with a reference voltage, and feed back a high level to the bias circuit module if the monitoring voltage is greater than the reference voltage.

11. The high-speed current steering DAC circuit of claim 10, wherein, The circuit further comprises: a bandgap reference module configured to provide the reference current source and the reference voltage.

12. A chip, characterized by The high-speed current steering DAC circuit comprises any one of the circuits according to claims 1 to 11.

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