Gradual approximation register analog-digital conversion device and signal conversion method

Abstract

The present application relates to a gradually approaching register type analog-digital conversion device and a signal conversion method. The gradually approaching register type analog-digital conversion device comprises a first and a second digital-analog converter (DAC) circuit, a comparator circuit, a controller circuit and a dynamic element matching circuit. The first and the second DAC circuit sample an input signal. The comparator circuit and the controller circuit generate a plurality of first and second bits according to the outputs of the first and the second DAC circuit. The dynamic element matching circuit encodes the first bits to generate third bits to refresh the first DAC circuit. After the first DAC circuit is refreshed, the controller circuit also resets some bits in the second bits. After the some bits are reset, the comparator circuit generates a plurality of comparison results according to the outputs of the first and the second DAC circuit. The controller circuit generates a plurality of fourth bits according to the comparison results, and generates a digital output according to the first, the second and the fourth bits.

Description

TECHNICAL FIELD

[0001] The present application relates to analog-to-digital converters, and more particularly to a successive approximation register analog-to-digital converter and a signal conversion method using dynamic element matching technique and statistical operation. BACKGROUND

[0002] In a successive approximation register analog-to-digital converter, the capacitance values of each capacitor in a capacitor array can be mismatched due to process errors, environmental temperature changes, etc., thus causing errors in the digital output and affecting the linearity of the successive approximation register analog-to-digital converter. In conventional designs, to solve this problem, a larger capacitor is usually used to reduce the mismatch. However, using a larger capacitor will significantly increase the overall area of the circuit. On the other hand, if an over sampling circuit technique is used in the successive approximation register analog-to-digital converter to reduce errors, the usable frequency of the input signal will be reduced. SUMMARY

[0003] In some embodiments, a successive approximation register analog-to-digital converter includes a first digital-to-analog converter circuit, a second digital-to-analog converter circuit, a comparator circuit, a controller circuit, and a dynamic element matching circuit. The second digital-to-analog converter circuit is configured to operate in conjunction with the first digital-to-analog converter circuit to sample an input signal. The comparator circuit is configured to generate a plurality of first comparison results based on an output of the first digital-to-analog converter circuit and an output of the second digital-to-analog converter circuit. The controller circuit is configured to generate a plurality of first bits and a plurality of second bits based on the first comparison results, and store the first bits and the second bits, wherein the second bits are used to switch the second digital-to-analog converter circuit. The dynamic element matching circuit is configured to encode the first bits to generate a plurality of third bits to refresh the first digital-to-analog converter circuit. After refreshing the first digital-to-analog converter circuit, the controller circuit is further configured to reset a portion of the second bits. The comparator circuit is further configured to generate a plurality of second comparison results based on the output of the first digital-to-analog converter circuit and the output of the second digital-to-analog converter circuit after the portion of the second bits are reset, and the controller circuit is further configured to generate a plurality of fourth bits based on the second comparison results, and generate a digital output based on the first bits, the second bits, and the fourth bits.

[0004] In some embodiments, a signal conversion method includes the following operations: sampling an input signal by a first digital-to-analog converter circuit and a second digital-to-analog converter circuit operating cooperatively to generate a plurality of first comparison results according to an output of the first digital-to-analog converter circuit and an output of the second digital-to-analog converter circuit; generating a plurality of first bits and a plurality of second bits according to the first comparison results, and storing the first bits and the second bits, wherein the second bits are used to switch the second digital-to-analog converter circuit; encoding the first bits to generate a plurality of third bits to refresh the first digital-to-analog converter circuit; resetting a portion of the second bits after the first digital-to-analog converter circuit is refreshed; generating a plurality of second comparison results according to the output of the first digital-to-analog converter circuit and the output of the second digital-to-analog converter circuit after the portion of the second bits is reset; generating a plurality of fourth bits according to the second comparison results; and generating a digital output according to the first bits, the second bits, and the fourth bits.

[0005] The features, implementation, and effects of the present application are described in detail below with reference to the drawings. BRIEF DESCRIPTION OF DRAWINGS

[0006] [ Figure 1 ] is a gradually approaching register analog-to-digital converter device according to some embodiments of the present application;

[0007] [ Figure 2 ] is a schematic diagram of a plurality of digital-to-analog converter circuits in Figure 1 according to some embodiments of the present application; and

[0008] [ Figure 3 ] is a flowchart of a signal conversion method according to some embodiments of the present application. DETAILED DESCRIPTION

[0009] All the terms used herein have their usual meanings. The definitions of the above-mentioned terms in the commonly used dictionaries are included in the content of the present application, and any use examples of the terms discussed herein are only examples and should not limit the scope and meaning of the present application. Similarly, the present application is not limited to only the various embodiments shown in the specification.

[0010] As to "coupled" or "connected" used herein, it can mean that two or more elements are in direct physical or electrical contact with each other, or are not in direct physical or electrical contact with each other but are connected to each other by other elements. As used herein, the term "circuitry" can be a single system formed by at least one circuit, and the term "circuit" can be a device that processes signals by connecting at least one transistor and / or at least one passive element in a certain way.

[0011] As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items. In the following description, like reference numerals will be used across different drawings to refer to like elements unless context dictates otherwise.

[0012] Figure 1 A schematic diagram of a successive approximation register (SAR) analog-to-digital converter device 100 (hereinafter referred to as SAR analog-to-digital converter device 100) according to some embodiments of the present disclosure is shown. The SAR analog-to-digital converter device 100 can generate a digital output DOUT according to an input signal VIP and an input signal VIN.

[0013] The SAR analog-to-digital converter device 100 includes a switch SW1, a switch SW2, a digital-to-analog converter circuit 110, a digital-to-analog converter circuit 115, a digital-to-analog converter circuit 120, and a digital-to-analog converter circuit 125, a comparator circuit 130, a controller circuit 140, and a dynamic element matching circuit 150.

[0014] The switch SW1 and the switch SW2 are turned on in a sampling phase. As such, the input signal VIP and the input signal VIN can be transmitted to a node N1 and a node N2, respectively. Under this condition, the digital-to-analog converter circuit 110 can operate in conjunction with the digital-to-analog converter circuit 115 to sample the input signal VIP, and the digital-to-analog converter circuit 120 can operate in conjunction with the digital-to-analog converter circuit 125 to sample the input signal VIN.

[0015] The digital-to-analog converter circuit 110 and the digital-to-analog converter circuit 120 correspond to high weight bits (e.g., most significant bits) in the digital output DOUT, and the digital-to-analog converter circuit 115 and the digital-to-analog converter circuit 125 correspond to low weight bits (e.g., least significant bits) in the digital output DOUT. In other words, the digital-to-analog converter circuit 110 corresponds to a higher weight than the digital-to-analog converter circuit 115, and the digital-to-analog converter circuit 120 corresponds to a higher weight than the digital-to-analog converter circuit 125. The arrangement of the digital-to-analog converter circuits 110, 115, 120, and 125 will be described later with reference to Figure 2 Description.

[0016] In the digital-to-analog conversion phase, switch SWl and switch SW2 are not conducting. In this phase, digital-to-analog converter circuit 110 can generate a corresponding output at node Nl based on the high weight bits, and digital-to-analog converter circuit 115 can generate a corresponding output at node Nl based on the low weight bits. In other words, the outputs of digital-to-analog converter circuits 110 and 115 can be used to adjust the level of node Nl. Similarly, digital-to-analog converter circuit 120 can generate a corresponding output at node N2, and digital-to-analog converter circuit 125 can generate a corresponding output at node N2. In other words, the outputs of digital-to-analog converter circuits 120 and 125 can be used to adjust the level of node N2.

[0017] Comparator circuit 130 is configured to generate decision signal VOP and decision signal VON based on the outputs of each of digital-to-analog converter circuits 110, 115, 120, and 125. For example, if the level of node Nl is higher than the level of node N2, decision signal VOP has a logic value of 1 and decision signal VON has a logic value of 0, but the present application is not limited thereto. Alternatively, if the level of node Nl is lower than the level of node N2, decision signal VOP has a logic value of 0 and decision signal VON has a logic value of 1, but the present application is not limited thereto. In the digital-to-analog conversion phase, comparator circuit 130 can sequentially generate a plurality of comparison results (i.e., a plurality of sets of decision signal VOP and decision signal VON). Controller circuit 140 can sequentially generate a plurality of bits Dl-Dl4 based on the comparison results and store the plurality of bits Dl-Dl4. In this example, bits Dl-D3 are the most significant bits and bits D4-Dl4 are the least significant bits, which can be used to switch digital-to-analog converter circuit 115. In some embodiments, controller circuit 140 also outputs bits Db4-Db 14 to switch digital-to-analog converter circuit 125, wherein a corresponding one of bits D4-Dl4 and a corresponding one of bits Db4-Db 14 have opposite logic values. For example, when bit D4 has a logic value of 1, bit Db4 has a logic value of 0. Similarly, when bit Dl4 has a logic value of 0, bit Db 14 has a logic value of 1.

[0018] In some embodiments, controller circuit 140 can perform a successive approximation algorithm with redundancy operation to generate the plurality of bits Dl-Dl4, but the present application is not limited thereto. In some embodiments, depending on the configuration of digital-to-analog converters 110, 115, 120, and 125, the successive approximation algorithm can be a binary search algorithm or a non-binary search algorithm.

[0019] The dynamic element matching circuit 150 is used to encode multiple bits D1 to D3 to generate multiple bits EB to refresh the digital-to-analog converter circuit 110. In some embodiments, the dynamic element matching circuit 150 is also used to encode multiple bits D1 to D3 to generate multiple bits EB' to refresh the digital-to-analog converter circuit 120. In some embodiments, each of the controller circuit 140 and the dynamic element matching circuit 150 may be implemented by a digital signal processing circuit. In some embodiments, the controller circuit 140 and the dynamic element matching circuit 150 may be integrated into a digital control logic circuit system.

[0020] After the multiple digital-to-analog converter circuits 110 and 120 are refreshed, the controller circuit 140 also resets a portion of bits D4 to D14 and a portion of bits D4b to D14b. The comparator circuit 130, after these partial bit resets, generates multiple comparison results based on the outputs of the multiple digital-to-analog converter circuits 110, 115, 120, and 125. The controller circuit 140 also generates multiple bits based on these comparison results and generates a digital output DOUT based on multiple bits D1 to D14 and multiple bits (e.g., multiple bits D10_F to D14_F, described later). A detailed explanation of this will be provided later. Figure 3 illustrate.

[0021] Figure 2 Drawing based on some embodiments of this case Figure 1 A schematic diagram of multiple digital-to-analog converter circuits 110, 115, 120, and 125 is shown. In this example, each of the multiple digital-to-analog converter circuits 110, 115, 120, and 125 can be a capacitive digital-to-analog converter circuit.

[0022] The digital-to-analog converter circuit 110 includes a control logic circuit 211, a switching circuit 212, and multiple capacitors C. mu1 ~C mu3 Multiple capacitors C mu1 ~C mu3 It is based on the temperature code setting. For example, capacitor C mu1 Contains 4 unit capacitors C m (i.e., capacitance C) mu1 The corresponding weight is 4), and the capacitor C mu2 Contains 2 unit capacitors C m (i.e., capacitance C) mu2 The corresponding weight is 2), and the capacitor C mu3 Contains 1 unit capacitor C m (i.e., capacitance C) mu3 The corresponding weight is 1). In the digital-to-analog converter circuit 110, multiple unit capacitors C mOne end is coupled to node N1, and multiple unit capacitors C m The other end is coupled to switching circuit 212. Control logic circuit 211 controls switching circuit 212 based on multiple bits EB. Switching circuit 212, based on the control of control logic circuit 211, transmits reference voltage Vp or reference voltage Vn to the corresponding unit capacitor C. m .

[0023] Similarly, the digital-to-analog converter circuit 120 includes a control logic circuit 221, a switching circuit 222, and multiple capacitors C. du1 ~C du3 Multiple capacitors C du1 ~C du3 It is based on the temperature code setting. For example, capacitor C du1 Contains 4 unit capacitors C m (i.e., capacitance C) du1 The corresponding weight is 4), and the capacitor C du2 Contains 2 unit capacitors C m (i.e., capacitance C) du2 The corresponding weight is 2), and the capacitor C du3 Contains 1 unit capacitor C m (i.e., capacitance C) du3 The corresponding weight is 1). In the digital-to-analog converter circuit 120, multiple unit capacitors C m One end is coupled to node N2, and multiple unit capacitors C m The other end is coupled to switching circuit 222. Control logic circuit 221 controls switching circuit 222 according to multiple bits EB'. Switching circuit 222, based on the control of control logic circuit 221, transmits reference voltage Vp or reference voltage Vn to the corresponding unit capacitor C. m .

[0024] The digital-to-analog converter circuit 115 includes a control logic circuit 213, a switching circuit 214, and multiple capacitors C. M1 ~C MY (Several parts are omitted in the diagram). Multiple capacitors C M1 ~C MY The capacitance values ​​of the capacitors are different from each other, corresponding to different weights. For example, in multiple capacitors C M1 ~C MY In the middle, capacitor C MY Corresponding to the largest weight, it has the largest capacitance value, and the capacitance C M1 Corresponding to the smallest weight, it therefore has the smallest capacitance value. Control logic circuit 213 controls switching circuit 214 based on multiple bits D4 to D14. Switching circuit 214, based on the control logic circuit 213, transmits reference voltage Vp or reference voltage Vn to multiple capacitors C. M1 ~C MY.

[0025] Similarly, the digital-to-analog converter circuit 125 includes a control logic circuit 223, a switching circuit 224, and a plurality of capacitors C L1 ~C LY The plurality of capacitors C L1 ~C LY have different capacitance values from each other to correspond to different weights. For example, among the plurality of capacitors C L1 ~C LY , the capacitor C LY corresponding to the largest weight has the largest capacitance value, and the capacitor C L1 corresponding to the smallest weight has the smallest capacitance value. The control logic circuit 223 controls the switching circuit 224 according to a plurality of bits Db4~Db14. The switching circuit 224 transmits the reference voltage Vp or the reference voltage Vn to the plurality of capacitors C L1 ~C LY based on the control of the control logic circuit 223.

[0026] In some embodiments, Figure 1 The SAR analog-to-digital conversion device 100 further includes a capacitor C1 and a capacitor C2. The capacitor C1 is coupled to the node N1 and used to receive the reference voltage Vn. The capacitor C2 is coupled to the node N2 and used to receive the reference voltage Vn. In some embodiments, the capacitor C1 and the capacitor C2 are used to attenuate the effect of the reference voltage Vp and the reference voltage Vn on the node N1 and the node N2 when the capacitors are switched, i.e., to attenuate the gain of the reference voltage Vp and the reference voltage Vn equivalent to the input signal of the comparator circuit 130, which allows the use of higher reference voltage Vp and reference voltage Vn. In some embodiments, the capacitor C1 and the capacitor C2 can be regarded as parasitic capacitors of the node N1 and the node N2 to ground. In some embodiments, the capacitance value of the capacitor C1 can be the same as the capacitance value of the capacitor C M1 , and the capacitance value of the capacitor C2 can be the same as the capacitance value of the capacitor C L1 .

[0027] Figure 2 Only binary digital-to-analog converters are taken as examples, but the present application is not limited thereto. In some embodiments, Figure 2 The plurality of capacitors in the SAR analog-to-digital conversion device 100 can be implemented by non-binary coding or segmented coding. In some embodiments, the control logic circuit (such as the control logic circuit 211, 213, 221, or 223) and the switching circuit (such as the switching circuit 212, 214, 222, or 224) can be implemented by digital circuits and / or switching circuits.

[0028] Figure 3A flowchart of a signal conversion method 300 according to some embodiments. In some embodiments, the signal conversion method 300 can be performed by the SAR ADC 100. Figure 1 For ease of understanding, the relevant operations of the SAR ADC 100 will be explained below with reference to the signal conversion method 300.

[0029] At operation S310, a first SAR ADC conversion is performed to generate a plurality of first bits (e.g., bits D1-D3) and a plurality of second bits (e.g., bits D4-D14). Operation S310 includes step S31 and step S32.

[0030] At step S31, the input signal is sampled. For example, switches SW1 and SW2 are turned on, and all the capacitors in the DAC circuits 110, 115, 120, and 125 receive the reference voltage Vp. In this condition, the DAC circuit 110 can operate in conjunction with the DAC circuit 115 to sample the input signal VIP, and the DAC circuit 120 can operate in conjunction with the DAC circuit 125 to sample the input signal VIN. After sampling is completed, switches SW1 and SW2 are turned off, and all the capacitors in the DAC circuits 110, 115, 120, and 125 continue to receive the reference voltage Vp. At step S32, a plurality of first comparison results (i.e., a plurality of sets of decision signals VOP and VON corresponding to the first SAR ADC conversion) are generated based on the outputs of the DAC circuits, and a plurality of first bits (e.g., bits D1-D3) and a plurality of second bits (e.g., bits D4-D14) are generated based on the first comparison results.

[0031] At operation S320, the first bits are encoded to generate a plurality of third bits (e.g., bits EB) to refresh the DAC circuits corresponding to the high-weight bits.

[0032] In some embodiments, the DEM circuit 150 can encode the first bits D1-D3 into a plurality of bits corresponding to a thermometer code, and perform a randomization (or pseudo-randomization) algorithm based on the bits to generate a plurality of bits EB, and generate a plurality of bits EB' corresponding to the bits EB based on the bits EB. The bits EB can be used to refresh the DAC circuit 110, and the bits EB' can be used to refresh the DAC circuit 120. In general, the bits EB' are defined based on the bits EB to control the capacitors C m coupled to the voltage Vn or the voltage Vp, but not limited thereto. In some embodiments, the bits EB can be (but not limited to) the logical complement of the bits EB'.

[0033] For example, if the plurality of bits D1-D3 are 100, the digital code of the plurality of bits D1-D3 is +1 (i.e., +4-2-1 = +1), which corresponds to one unit capacitance C m Assume that in the initial SAR analog-to-digital conversion, the digital-to-analog converter circuit 110 uses the first unit capacitance C mu1 in the capacitor bank C m to generate an output corresponding to the digital code. For example, the first unit capacitance C m receives the voltage Vn, and the remaining unit capacitances C m in the digital-to-analog converter circuit 110 and all the unit capacitances C m in the digital-to-analog converter circuit 120 receive the voltage Vp to generate an output corresponding to the digital code. m After processing by the dynamic element matching circuit 150, the digital-to-analog converter circuit 110 can use another unit capacitance C mu1 (e.g., the second unit capacitance C m in the capacitor bank C m ) to generate an output corresponding to the digital code according to the plurality of bits EB. For example, the second unit capacitance C m receives the voltage Vn, and the remaining unit capacitances C m in the digital-to-analog converter circuit 110 and all the unit capacitances C m in the digital-to-analog converter circuit 120 receive the voltage Vp to generate an output corresponding to the digital code.

[0034] In other words, in the initial SAR analog-to-digital conversion, the digital-to-analog converter circuit 110 can use at least a first capacitance (e.g., the first unit capacitance C m ) of the plurality of unit capacitances C m to generate an output corresponding to the plurality of first comparison results. Through the dynamic element matching circuit 150, the digital-to-analog converter circuit 110 can use at least a second capacitance (e.g., the second unit capacitance C m ) of the plurality of unit capacitances C m to generate an output corresponding to the plurality of first comparison results according to the plurality of bits EB, where the at least a first capacitance is not identical to the at least a second capacitance. In other words, the digital-to-analog converter circuit 110 can respond to the plurality of bits EB being refreshed to select different unit capacitances C m to generate the same output. In this way, the effects of mismatch between the plurality of unit capacitances C m can be reduced to improve the linearity of the digital-to-analog converter circuit 110.

[0035] At operation S330, after the DAC circuits corresponding to the high weight bits are refreshed, a portion of the second bits are reset. At operation S340, after the portion of the second bits are reset, a plurality of second comparison results are generated based on the outputs of the plurality of DAC circuits. At operation S350, a plurality of fourth bits are generated based on the second comparison results, and a digital output is generated based on the first bits, the second bits, and the fourth bits.

[0036] For example, after the DAC circuits 110 are refreshed, the controller circuit 140 can reset a portion of the bits D4-D14 and maintain the remaining bits of the bits D4-D14 unchanged from the bits D1-D3. In some embodiments, the remaining bits correspond to higher weights than the portion of the bits. For example, the portion of the bits can be the bits D10-D14 of the bits D4-D14 corresponding to lower weights, and the remaining bits can be the bits D4-D9 of the bits D4-D14 corresponding to higher weights. It should be understood that since the remaining bits D4-D9 are unchanged, the corresponding bits Db4-Db9 of the bits Db4-Db14 are also unchanged. The plurality of DAC circuits 110, 115, 120, and 125 can be switched in response to the plurality of bits to generate corresponding outputs. Accordingly, after the bits D10-D14 (and the bits Db10-Db14) are reset, the comparator circuit 130 can generate a plurality of second comparison results (i.e., a plurality of sets of decision signals VOP and decision signals VON) based on the outputs of the plurality of DAC circuits 110, 115, 120, and 125. The controller circuit 140 can generate a plurality of fourth bits (e.g., the bits D10_F-D14_F as described below) based on the second comparison results, and generate a digital output DOUT based on the bits D1-D3, the bits D4-D14, and the fourth bits.

[0037] In one example, the SAR ADC 100 is a 12-bit SAR ADC and generates 2 redundant bits after generating the most significant bits (e.g., the bits D1-D3). Thus, the SAR ADC 100 can generate 14 bits (e.g., the bits D1-D14) in the analog-to-digital conversion. Under this condition, the bits generated by the controller circuit 140 can be arranged as the following table through the above operations:

[0038] Corresponding comparison results Stored bits First comparison result D1, D2, D3,..., D9, D10, D11,..., D14 Second comparison result D1, D2, D3,..., D9, D10_F, D11_F,..., D14_F

[0039] The first comparison result corresponds to the initial SAR analog-to-digital conversion, and the second comparison result is generated after the digital-to-analog converter circuit 110 is reset. Through the above operations, the controller circuit 140 can obtain multiple sets of bits (e.g., the first set of bits D1-D14 and the second set of bits D1-D9 and D10_F-D14_F). In this way, the controller circuit 140 can perform statistical operations according to the sets of bits to generate the digital output DOUT.

[0040] For example, the controller circuit 140 can average the partial bits (e.g., the bits D10-D14) and the fourth bits (e.g., the bits D10_F-D14_F) to generate fifth bits (e.g., the average of the bits D10-D14 and the bits D10_F-D14_F), and combine the bits D1-D3, the remaining bits D4-D9, and the fifth bits to generate the digital output DOUT. Alternatively, the controller circuit 140 can directly average the sets of bits in the above table to generate the digital output DOUT. Through the dynamic element matching circuit 150 and the above statistical operations, the effects of element (e.g., capacitor) mismatch can be reduced. In this way, the linearity of the SAR analog-to-digital conversion device 100 can be improved without increasing the element area. In some embodiments, the statistical operation can be an average operation or a weighted average operation, but the present application is not limited thereto. In addition, since the above operations do not use over sampling, the frequency of the input signal VIN is not limited by the sampling frequency, so the usable frequency of the input signal VIN is not reduced.

[0041] The operations of the signal conversion method 300 are only examples, and are not limited to being performed in the order in the examples. Without departing from the operation manner and scope of the embodiments of the present application, various operations in the signal conversion method 300 can be appropriately added, replaced, omitted, or performed in different orders (e.g., simultaneously or partially simultaneously).

[0042] The above description is merely an example, and the present disclosure is not limited thereto. For example, in other embodiments, the operations S320, S330, and S340 can be repeated multiple times to obtain more sets of bits (e.g., more sets of bits D10_F~D14_F) to generate a more accurate digital output DOUT. For example, after obtaining the second set of bits after the above table, the dynamic element matching circuit 150 can re-encode the bits D1~D3 to generate the bits EB and EB’ to refresh the digital-to-analog converter circuits 110 and 120. Then, the controller circuit 140 can reset the bits D10_F~D14_F and Db10~Db14. After the bits D10~D14 (and the bits Db10~Db14) are reset, the comparator circuit 130 can repeat the comparison of the outputs of the digital-to-analog converter circuit 110 (and the digital-to-analog converter circuit 115) and the outputs of the digital-to-analog converter circuit 120 (and the digital-to-analog converter circuit 125) to generate more second comparison results. The controller circuit 140 can generate bits (e.g., bits D10_F1~D14_F1) from the second comparison results and store the bits as a third set of bits (e.g., the bits D1~D9 and D10_F1~D14_F1). In this way, the controller circuit 140 can generate the digital output DOUT from the first set of bits, the second set of bits, and the third set of bits. For example, the controller circuit 140 can average the sets of bits to generate the digital output DOUT. In some embodiments, the more the number of times of repeating the comparison and / or the number of sets of bits, the more accurate the digital output DOUT can be.

[0043] In addition, the above embodiments are merely described by way of differential mode, but the present disclosure is not limited thereto. In some embodiments, the above embodiments can be implemented by single-ended mode. In some embodiments, in the single-ended mode, the SAR analog-to-digital conversion device 100 can operate the digital-to-analog converter circuit coupled to one input terminal (e.g., the node N1 or the node N2) of the comparator circuit 130 among the digital-to-analog converter circuits 110, 115, 120, and 125. For example, the SAR analog-to-digital conversion device 100 can be a single-ended device based on common-mode voltage (VCM-based) switching, which can only include the digital-to-analog converter circuits 110 and 115.

[0044] In summary, the SAR analog-to-digital conversion device and the signal conversion method in some embodiments of the present disclosure can use the dynamic element matching technique to refresh the digital-to-analog converter circuit corresponding to the high-weight bit and use statistical operation to generate the final digital output. In this way, the influence of the mismatch of elements in the device can be reduced to improve the linearity without increasing the element area. In addition, the above related operations do not use the super-sampling technique, so the usable frequency of the input signal is not reduced.

[0045] Although the present application has been described with reference to specific embodiments, it will be apparent to those skilled in the art that various modifications can be made to the described embodiments, which modifications will fall within the scope of the application. Accordingly, the scope of the application is not intended to be limited to the described embodiments, but is to be accorded the full scope consistent with the claims, and any equivalents thereof.

[0046]

Symbol Description

[0047] 100: Gradually approaching register type analog-digital conversion device

[0048] 110, 115, 120, 125: Digital-analog converter circuit

[0049] 130: Comparator circuit

[0050] 140: Controller circuit

[0051] 150: Dynamic element matching circuit

[0052] 211, 213, 221, 223: Control logic circuit

[0053] 212, 214, 222, 224: Switching circuit

[0054] 300: Signal conversion method

[0055] C1, C2, C L1 ~ C LY , C M1 ~ C MY : Capacitance

[0056] C du1 ~ C du3 , C mu1 ~ C mu3 : Capacitance

[0057] C m : Unit capacitance

[0058] D1 ~ D14, Db4 ~ Db14, EB, EB': Bit

[0059] DOUT: Digital output

[0060] N1, N2: Node

[0061] S310, S320, S330, S340, S350: Operation

[0062] S31, S32: Step

[0063] SW1, SW2: Switch

[0064] VIN, VIP: input signals

[0065] VON, VOP: decision signals

[0066] Vn, Vp: reference voltages.

Claims

1. A successive approximation register analog-to-digital conversion device, comprising: a first digital-to-analog converter circuit; a second digital-to-analog converter circuit configured to operate in conjunction with the first digital-to-analog converter circuit to sample an input signal; a comparator circuit configured to generate a plurality of first comparison results based on an output of the first digital-to-analog converter circuit and an output of the second digital-to-analog converter circuit; a controller circuit configured to generate a plurality of first bits and a plurality of second bits based on the first comparison results and to store the first bits and the second bits, wherein the second bits are configured to switch the second digital-to-analog converter circuit; and a dynamic element matching circuit configured to encode the first bits to generate a plurality of third bits to refresh the first digital-to-analog converter circuit, wherein after the first digital-to-analog converter circuit is refreshed, the controller circuit is further configured to reset a portion of the second bits, the comparator circuit is further configured to generate a plurality of second comparison results based on the output of the first digital-to-analog converter circuit and the output of the second digital-to-analog converter circuit after the portion of the second bits are reset, and the controller circuit is further configured to generate a plurality of fourth bits based on the second comparison results and to generate a digital output based on the first bits, the second bits, and the fourth bits.

2. The successive approximation register analog-to-digital conversion device of claim 1, wherein the first bits are a plurality of most significant bits and the second bits are a plurality of least significant bits.

3. The successive approximation register analog-to-digital conversion device of claim 1, wherein the first digital-to-analog converter circuit is further configured to be repeatedly refreshed to reset the portion of the bits, and the comparator circuit is further configured to repeatedly compare the output of the first digital-to-analog converter circuit and the output of the second digital-to-analog converter circuit to generate the second comparison results after the portion of the bits are reset.

4. The successive approximation register analog-to-digital conversion device of claim 1, wherein the first digital-to-analog converter circuit corresponds to a higher weight than the second digital-to-analog converter circuit.

5. The successive approximation register analog-to-digital conversion device of claim 1, wherein the controller circuit is configured to perform a statistical operation on the portion of the bits and the fourth bits to generate a plurality of fifth bits and to combine the first bits, a remaining portion of the second bits, and the fifth bits as the digital output.

6. The successive approximation register analog-to-digital conversion device of claim 5, wherein the remaining portion of the bits corresponds to a higher weight than the portion of the bits.

7. The successive approximation register analog-to-digital conversion device of claim 5, wherein the controller circuit is configured to average the portion of the bits and the fourth bits to generate the fifth bits.

8. The successive approximation register analog-to-digital conversion device of claim 1, wherein the dynamic element matching circuit is configured to encode the first bits as a thermometer code and to generate the third bits based on the thermometer code. ​ ​ ​ ​ ​ ​ ​ 9. The successive approximation register analog-to-digital conversion apparatus of claim 1, wherein the first digital-to-analog converter circuit includes a plurality of capacitors, and the first digital-to-analog converter circuit generates an output corresponding to the first comparison result based on the third bit.

10. A signal conversion method, comprising: sampling an input signal by a first digital-to-analog converter circuit and a second digital-to-analog converter circuit to generate a plurality of first comparison results based on an output of the first digital-to-analog converter circuit and an output of the second digital-to-analog converter circuit; generating a plurality of first bits and a plurality of second bits based on the first comparison results, and storing the first bits and the second bits, wherein the second bits are used to switch the second digital-to-analog converter circuit; encoding the first bits to generate a plurality of third bits to refresh the first digital-to-analog converter circuit; resetting a portion of the second bits after the first digital-to-analog converter circuit is refreshed; generating a plurality of second comparison results based on the output of the first digital-to-analog converter circuit and the output of the second digital-to-analog converter circuit after the portion of the second bits is reset; generating a plurality of fourth bits based on the second comparison results; and generating a digital output based on the first bits, the second bits, and the fourth bits.

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