Wiring substrate and its manufacturing method

Abstract

This invention provides a wiring substrate and a method for manufacturing the wiring substrate, such that the thickness of a conductor layer having a shape embedded in an insulating layer in a printed wiring board is precisely controlled. The method for manufacturing the wiring substrate according to an embodiment includes the following steps: forming a first resin insulating layer (111) and a second resin insulating layer (112) in contact with the upper surface of the first resin insulating layer (111); forming recesses (op1, op2) by laser irradiation, the recesses (op1, op2) penetrating the second resin insulating layer (112) and exposing the first resin insulating layer (111) at the bottom; and filling the recesses (op1, op2) with a conductor to form a first conductor layer (121) having a shape embedded in the second resin insulating layer (112). The first resin insulating layer (111) and the second resin insulating layer (112) have different processability relative to the laser.

Description

Technical Field

[0001] This invention relates to wiring substrates and methods for manufacturing wiring substrates. Background Technology

[0002] Patent Document 1 discloses a printed wiring substrate comprising a first insulating layer, a second insulating layer formed on the first insulating layer, a recess formed in the second insulating layer, and a second conductor circuit formed by filling the recess of the second insulating layer. By laser processing the second insulating layer, the recess for filling the conductor constituting the second conductor circuit is formed to a depth less than the thickness of the second insulating layer.

[0003] Patent Document 1: International Publication No. 2010 / 004841 Summary of the Invention

[0004] In the method for manufacturing a printed wiring substrate disclosed in Patent Document 1, during the formation of the recess, laser processing needs to be stopped at the middle of the thickness direction of the second insulating layer. Therefore, it is considered difficult to precisely control the depth of the recess. It is also considered difficult to precisely adjust the thickness of the second conductor circuit formed within the recess to achieve the desired thickness.

[0005] The method for manufacturing a wiring substrate according to an embodiment of the present invention includes the following steps: forming a first resin insulating layer and a second resin insulating layer in contact with the upper surface of the first resin insulating layer; forming a recess by laser irradiation, the recess penetrating the second resin insulating layer and exposing the first resin insulating layer at its bottom; and filling the recess with a conductor to form a first conductor layer having a shape embedded in the second resin insulating layer. The first resin insulating layer and the second resin insulating layer have different processability relative to the laser.

[0006] The wiring substrate of an embodiment of the present invention has: a first resin insulating layer; and a second resin insulating layer formed in contact with the upper surface of the first resin insulating layer. The wiring substrate also has a recess that penetrates the second resin insulating layer and exposes the first resin insulating layer at its bottom, the recess being filled by a first conductor layer.

[0007] According to embodiments of the present invention, it is possible to provide a wiring substrate in which the thickness of a conductor layer having a shape embedded in an insulating layer is precisely controlled. Attached Figure Description

[0008] Figure 1 This is a cross-sectional view illustrating an example of a wiring substrate according to one embodiment of the present invention.

[0009] Figure 2 This is an example of a wiring substrate according to one embodiment of the present invention. Figure 1 A magnified view of a portion of the image.

[0010] Figure 3A This is a cross-sectional view illustrating a method for manufacturing a wiring substrate according to one embodiment.

[0011] Figure 3B This is a cross-sectional view illustrating a method for manufacturing a wiring substrate according to one embodiment.

[0012] Figure 3C This is a cross-sectional view illustrating a method for manufacturing a wiring substrate according to one embodiment.

[0013] Figure 3D This is a cross-sectional view illustrating a method for manufacturing a wiring substrate according to one embodiment.

[0014] Figure 3E This is a partially enlarged cross-sectional view showing a method for manufacturing a wiring substrate according to one embodiment.

[0015] Figure 3F This is a partially enlarged cross-sectional view showing a method for manufacturing a wiring substrate according to one embodiment.

[0016] Figure 3G This is a partially enlarged cross-sectional view showing a method for manufacturing a wiring substrate according to one embodiment.

[0017] Figure 3H This is a cross-sectional view illustrating a method for manufacturing a wiring substrate according to one embodiment.

[0018] Figure 3I This is a cross-sectional view illustrating a method for manufacturing a wiring substrate according to one embodiment.

[0019] Figure 3J This is a cross-sectional view illustrating a method for manufacturing a wiring substrate according to one embodiment.

[0020] Label Explanation

[0021] 1: Wiring substrate; 101, 11, 21: Insulating layer; 111: First resin insulating layer; 112: Second resin insulating layer; 102, 12, 22: Conductor layer; 121: First conductor layer; 10: First stacked layer; 20: Second stacked layer; 110, 210: Insulating layer (solder resist layer); op1, op2: Recess; FW: Wiring; L: Pad; D: Depth; T: Thickness. Detailed Implementation

[0022] A wiring substrate according to one embodiment of the present invention will be described with reference to the accompanying drawings. Furthermore, the accompanying drawings are not intended to show exact proportions of the constituent elements, but are depicted in a manner that facilitates understanding of the features of the present invention. One example of a structure that the wiring substrate according to one embodiment can have is... Figure 1A cross-sectional view of the wiring substrate 1 is shown.

[0023] like Figure 1 As shown, the wiring substrate 1 has a core substrate 100, which includes an insulating layer (core insulating layer) 101 and conductor layers (core conductor layers) 102 formed on both sides of the core insulating layer 101. The insulating layer and conductor layer are stacked on both sides of the core substrate 100. In the illustrated example, a first stacked portion 10 is formed on one side F1 of the core substrate 100, in which insulating layers 11, 111, and 112 and conductor layers 12 and 121 are stacked. Furthermore, a second stacked portion 20 is formed on the other side F2 of the core substrate 100, in which an insulating layer 21 and conductor layer 22 are stacked.

[0024] Furthermore, in the description of the wiring substrate in this embodiment, the side away from the core insulating layer 101 is referred to as "upper," "upper side," "outer side," or "outer," and the side close to the core insulating layer 101 is referred to as "lower," "lower side," "inner side," or "inner." Moreover, in each insulating layer and conductor layer, the surface facing the side opposite to the core substrate 100 is also referred to as the "upper surface," and the surface facing the core substrate 100 is also referred to as the "lower surface." Therefore, for example, in the description of each component of the first stacking portion 10 and the second stacking portion 20, the side away from the core substrate 100 is also referred to as "upper side," "above," "upper layer side," "outer side," or simply "upper" or "outer," and the side close to the core substrate 100 is also referred to as "lower side," "below," "lower layer side," "inner side," or simply "lower" or "inner."

[0025] An insulating layer 110, for example, serving as a solder resist layer, is formed on the first laminate portion 10. An insulating layer 210, for example, serving as a solder resist layer, is formed on the second laminate portion 20. The insulating layer 110 has an opening 110a, through which the conductor pad 12p of the outermost conductor layer 12 of the first laminate portion 10 is exposed. The insulating layer 210 has an opening 210a, through which the conductor pad 22p of the outermost conductor layer 22 of the second laminate portion 20 is exposed.

[0026] The outermost surface of the wiring substrate 1, formed by the exposed surfaces of the conductor layer 12 (conductor pad 12p) and the insulating layer 110, is called the first surface FA. The outermost surface of the wiring substrate 1, formed by the exposed surfaces of the insulating layer 210 and the conductor layer 22 (conductor pad 22p), is called the second surface FB. That is, the wiring substrate 1 has two surfaces, the first surface FA and the second surface FB, which are opposite to the first surface FA, extending in a direction perpendicular to the thickness direction of the wiring substrate 1.

[0027] The insulating layer 101 of the core substrate 100 has a through-hole conductor 103, which connects the conductor layer 102 constituting one surface F1 of the core substrate 100 with the conductor layer 102 constituting the other surface F2. Insulating layers 11, 111, and 21 have through-hole conductors 13 and 23 respectively, which connect the conductor layers separated by insulating layers 11, 111, and 21.

[0028] The conductor layer 121 of the first stacked portion 10 of the wiring substrate 1 shown in the figure has a structure different from the other conductor layers 102, 12, and 22 constituting the wiring substrate 1. Specifically, the conductor layers 102, 12, and 22 have the following configuration: the side and upper surfaces of the conductor patterns are covered by insulating layers 11, 111, 110, 21, and 210, respectively, covering the upper sides of the conductor layers 102, 12, and 22. The conductor layer 121 has a structure different from these conductor layers 102, 12, and 22, with its upper surface in contact with the insulating layer 11 and its side surface in contact with the insulating layer 112. In other words, the conductor layer 121 is embedded in the insulating layer 112. Furthermore, the conductor layer 121 penetrates the insulating layer 112 in the thickness direction, and its lower surface is in contact with the insulating layer 111. That is, the conductor layer 121 has a configuration that penetrates the thickness direction of the insulating layer 112, and the thickness of the conductor layer 121 is approximately equal to the thickness of the insulating layer 112. In this specification, for the purpose of explanation, a conductor layer having a shape that is embedded in an insulating layer like conductor layer 121 and penetrates the insulating layer, and having a thickness that is approximately equal to that of the insulating layer, is referred to as a "through conductor layer".

[0029] Conductor layers 102, 12, 121, 22, via conductors 13, 23, and through-hole conductors 103 are formed using any metal such as copper or nickel, for example, from metal foil such as copper foil, and / or metal films formed by plating or sputtering. Conductor layers 102, 12, 121, 22, via conductors 13, 23, and through-hole conductors 103 are... Figure 1 The structure is shown as a single layer, but it can also have a multi-layer structure with two or more metal layers. For example, the conductor layer 102 formed on the surface of the insulating layer 101 can have a three-layer structure including a metal foil, a chemically plated film, and an electroplated film. Moreover, conductor layers 12, 121, 22, via conductors 13, 23, and through-hole conductor 103 can, for example, have a two-layer structure including a chemically plated film and an electroplated film.

[0030] The conductor layers 102, 12, 121, and 22 of the wiring substrate 1 are patterned with a predetermined conductor pattern. In particular, in the illustrated example, as detailed below, conductor layer 121 fills the recesses through which insulating layer 112, formed on the outside of insulating layer 111, is formed with a finer pattern. Specifically, conductor layer 121 may have wiring FW as a finer pattern. Furthermore, conductor layer 121 may also have pad portions L as connection portions for connecting via conductor 13, which contacts the outside of conductor layer 121.

[0031] In the following description, insulating layer 111 is also referred to as first resin insulating layer 111, insulating layer 112 is also referred to as second resin insulating layer 112, and conductor layer 121 is also referred to as first conductor layer 121. The wiring substrate of this embodiment has at least a first resin insulating layer 111, a second resin insulating layer 112 stacked on the upper surface of the first resin insulating layer 111, and a first conductor layer 121 penetrating the second resin insulating layer 112 and having a thickness substantially equal to that of the second resin insulating layer 112.

[0032] The outermost conductor layer 12 of the first stacked layer 10 is formed with a pattern including conductor pads 12p. The conductor pads 12p are formed to support components (not shown) mounted on the wiring substrate 1 when it is used. That is, the conductor pads 12p are component mounting pads used as connection portions when external components are mounted on the wiring substrate 1, and the first surface FA of the wiring substrate 1 can be a component mounting surface capable of supporting components. The component mounting pads (conductor pads) 12p are electrically or mechanically connected to electrodes of electronic components, for example, via bonding materials (not shown) such as solder. Examples of components that can be mounted on the wiring substrate 1 include, for example, active components such as semiconductor integrated circuit devices or transistors.

[0033] When the wiring board 1 is mounted on an external wiring board, such as the motherboard of any electrical device or other external element, Figure 1 In the example, the second surface FB of the wiring substrate 1, which is the side opposite to the first surface FA, can be a connection surface for connecting to external elements. Furthermore, the second surface FB, like the first surface FA, can also be a component mounting surface for mounting electronic components such as semiconductor integrated circuit devices. The conductor pads 22p constituting the second surface FB can be connected to any substrate, electrical component, or mechanical component, etc., which are not limited thereto.

[0034] Insulating layers 101, 11, 111, 112, and 21 are formed, for example, using insulating resins such as epoxy resin, bismaleimide triazine resin (BT resin), or phenolic resin. For example, insulating layers 110 and 210, serving as solder resist layers, can be formed using photosensitive epoxy resin or polyimide resin. Each insulating layer 101, 11, 111, 112, 21, 110, and 210 may contain inorganic fillers such as silica or alumina. Each insulating layer 101, 11, 111, and 21 may also sometimes contain reinforcing materials (core materials) such as glass fiber.

[0035] As detailed below, in the second resin insulating layer 112 and the first resin insulating layer 111 in which the first conductor layer 121 is embedded, the volume content of filler may sometimes differ. Specifically, the volume content of filler in the second resin insulating layer 112 may sometimes be less than that in the first resin insulating layer 111. Furthermore, the average particle size of the filler contained in the second resin insulating layer 112 may sometimes be less than the average particle size of the filler contained in the first resin insulating layer 111. Due to the aforementioned relationship between the fillers contained in the first resin insulating layer 111 and the second resin insulating layer 112, in the wiring substrate manufacturing method, as described below, the formation of the first conductor layer 121 having a through-conductor layer shape is sometimes performed more precisely.

[0036] Furthermore, the aforementioned relationship between the fillers contained in the first resin insulating layer 111 and the second resin insulating layer 112 can sometimes suppress undesirable short circuits or insulation issues in the wiring patterns of the first conductor layer 121. During the formation of the first conductor layer 121, when a recess is formed in the second resin insulating layer 112, the filler contained in the second resin insulating layer 112 may sometimes be exposed within the recess. This exposed filler protrudes inwards from the recess, sometimes causing a localized increase in impedance in the wiring pattern of the first conductor layer 121. Moreover, the exposed filler may sometimes detach during cleaning of the recess, resulting in perforations in the filler in the second resin insulating layer 112. This can lead to conductors filling the perforations, causing adjacent wiring to become too close together, thus increasing the likelihood of short circuits.

[0037] In particular, the finer wiring (FW) in the first conductor layer 121 is susceptible to the effects of such filler, which may lead to poor signal transmission by the wiring FW. The more filler exposed in the recesses, and the larger the size of the filler exposed in the recesses, the more significant this problem may become. Therefore, when the volume fraction and average particle size of the filler in the second resin insulating layer 112 are smaller than those of the filler in the first resin insulating layer 111, the occurrence of these problems can sometimes be suppressed.

[0038] Next, refer to Figure 2 The structure of the first conductor layer 121 having the form of a through conductor layer, the second resin insulating layer 112 through which the first conductor layer 121 penetrates, and the first resin insulating layer 111 which is an insulating layer directly below the second resin insulating layer 112 will be described in detail. Figure 2 Is Figure 1 An enlarged view of the region, indicated by reference numeral II and enclosed by a dashed line, containing the first resin insulating layer 111, the second resin insulating layer 112, and the first conductor layer 121. Figure 2 In the example shown, conductor layer 12 and via conductor 13 are composed of two layers: a metal film layer (chemical plating layer) 12a and an electroplated film layer 12b. The first conductor layer 121 is also composed of a metal film layer 12a and an electroplated film layer 12b.

[0039] The first conductor layer 121 penetrates the second resin insulating layer 112 and is in contact with both the insulating layer 11 and the first resin insulating layer 111. The insulating layer 11 and the first resin insulating layer 111 are in contact with the upper and lower sides of the second resin insulating layer 112. The first conductor layer 121 has a two-layer structure of a metal film layer 12a and an electroplated film layer 12b. The metal film layer 12a covers the inner surface of the recesses op1 and op2 formed in the second resin insulating layer 112, and the electroplated film layer 12b fills the inner side of the metal film layer 12a. In detail, in the description of the method for manufacturing the wiring substrate, as described later, the recesses op1 and op2 are formed by irradiating the second resin insulating layer 112 from the upper side with a laser. The resin component is removed by ablation using the irradiated laser, thereby forming recesses op1 and op2 that penetrate in the thickness direction of the second resin insulating layer 112. In addition, the recess op1 corresponds to the wiring FW that the first conductor layer 121 can have, and the recess op2 corresponds to the pad portion L.

[0040] In detail, as described later in the method for manufacturing the wiring substrate, the processability (cutting capability) of the second resin insulating layer 112 and the first resin insulating layer 111 differs from that of the irradiated laser. The laser processing is effectively stopped when the laser penetrates the second resin insulating layer 112 and reaches the upper surface of the first resin insulating layer 111. Therefore, the depth D of the recesses op1 and op2 is formed to be approximately the same as the thickness T of the second resin insulating layer 112. Specifically, the thickness T of the second resin insulating layer 112 is set to approximately 10 μm to 20 μm, and the thickness of the first conductor layer 121 can also be formed to have substantially the same thickness. The processability of the resin insulating layers (the second resin insulating layer 112 and the first resin insulating layer 111) relative to the laser can be controlled by adjusting the absorption coefficient relative to the laser or the content of the filler contained therein. In addition, the depth D of the recesses op1 and op2 can be greater than the thickness T of the second resin insulating layer 112, and the bottom surface of the recesses op1 and op2 can also be formed from the first resin insulating layer 111 starting from the interface between the first resin insulating layer 111 and the second resin insulating layer 112.

[0041] exist Figure 2 In the cross-sectional view, the wiring FW, shown as multiple (four in the illustrated example) wires extending parallel to the direction perpendicular to the paper surface (i.e., from the front side of the paper surface towards the inside), has a relatively small line width and spacing. For example, in the wiring FW, the minimum line width and spacing are approximately 2 μm to 5 μm. As mentioned above, especially from the viewpoint of suppressing short circuits and insulation of the wiring FW, it is sometimes preferable that the volume content and average particle size of the filler contained in the second resin insulating layer 112 are smaller than those of the filler contained in the first resin insulating layer 111.

[0042] Specifically, from the viewpoint of suppressing short circuits and open circuits in the wiring FW and ensuring the machinability of the first and second resin insulating layers 111 and 112 relative to the laser, for example, the filler volume content of the second resin insulating layer 112 can be set to about 5% to 15%, and the filler volume content of the first resin insulating layer 111 can be set to about 50% to 80%. Furthermore, the average particle size of the included filler is set to about 0.25 μm in the second resin insulating layer 112 and about 0.5 μm in the first resin insulating layer 111. Moreover, especially from the viewpoint of suppressing short circuits and insulation problems in the wiring FW, the maximum particle size of the filler included in the second resin insulating layer 112 preferably has a value less than a predetermined proportion relative to the line width and inter-line spacing of the wiring FW. For example, the maximum particle size of the filler included in the second resin insulating layer 112 can be less than 50% relative to the line width and inter-line spacing of a finer wiring FW.

[0043] The above description illustrates a wiring substrate 1 as an example where only one layer of the first conductor layer 121 with a through conductor layer configuration is formed in the first stacking section 10. However, through conductor layers can be formed at any location and in any number within the wiring substrate. For example, in the second stacking section 20, through conductor layers with the same number of layers as the first conductor layer 121 can also be formed. Furthermore, "number of layers" refers to the number assigned to each conductor layer when, starting from the core substrate 100 side, an increasing number is assigned to each of the multiple conductor layers stacked in the first stacking section 10 and the second stacking section 20 respectively. By forming through conductor layers with the same number of layers as the first stacking section 10 of the second stacking section 20, the symmetry in the thickness direction of the wiring substrate is sometimes improved, and warpage of the wiring substrate is suppressed.

[0044] Reference Figures 3A to 3J To manufacture Figure 1 Taking the example of the wiring substrate 1 shown, a method for manufacturing a wiring substrate according to one embodiment will be described. First, as Figure 3A As shown, a core substrate 100 is prepared. In the preparation of the core substrate 100, for example, a double-sided copper-clad laminate containing a core insulating layer 101 is prepared. Then, a conductor layer 102 containing a predetermined conductor pattern is formed on both sides of the insulating layer 101 by a subtractive process or the like, and a through-hole conductor 103 is formed in the insulating layer 101, thereby preparing the core substrate 100.

[0045] Next, as Figure 3B As shown, an insulating layer 11 is formed on one side F1 of the core substrate 100, and a conductor layer 12 is stacked on the insulating layer 11. An insulating layer 21 is formed on the other side F2 of the core substrate 100, and a conductor layer 22 is stacked on the insulating layer 21. For example, each insulating layer 11 and 21 is formed by hot-pressing a thin film of insulating resin onto the core substrate 100. The conductor layers 12 and 22 and the via conductors 13 and 23 are formed simultaneously using a method for forming arbitrary conductor patterns, such as a semi-additive method. The via conductors 13 and 23 fill openings 13a and 23a in the insulating layers 11 and 21, for example, which can be formed by laser.

[0046] Next, as Figure 3C As shown, on one side F1 of the core substrate 100, a first insulating layer 111 and a second insulating layer 112 are stacked. On the other side F2, an insulating layer 21 is stacked on the conductor layer 22. The first resin insulating layer 111 and the second resin insulating layer 112 are formed using materials with different processability relative to the laser when forming recesses in the second resin insulating layer 112, as described later. The processability of the first and second resin insulating layers 111 and 112 relative to the laser can be adjusted, for example, by the amount of additives (curing accelerators and / or curing inhibitors) added, and / or the volume content of the fillers contained therein, average particle size, etc.

[0047] Next, as Figure 3D As shown, for example, an opening vo is formed by laser processing, continuously penetrating the second insulating layer 112 and the first resin insulating layer 111, exposing the conductor layer 12 on the bottom surface. The opening vo is formed in the through-hole conductor 13 penetrating the first insulating layer 111 (see reference). Figure 1 The desired location. For example, the formation of an opening VO can be achieved using a carbon dioxide gas laser with a longer wavelength of about 10 μm.

[0048] Next, as Figure 3E As shown, recesses op1 and op2 are formed in the second resin insulating layer 112. Additionally, in... Figures 3E to 3G The diagram shows the first resin insulating layer 111, the second resin insulating layer 112, and the areas near the recesses op1 and op2 during the formation process of the wiring substrate 1. Figure 2 A magnified view of the corresponding area.

[0049] For example, by using a short-wavelength excimer laser or similar processing method that has excellent linearity in the processing of insulating layers, recesses op1 and op2 are formed at the bottom, exposing the first resin insulating layer 111. Recesses op1 and op2 are formed according to the wiring pattern that the first conductor layer 121 formed through the second resin insulating layer 112 should have. The recess op1 in the illustration corresponds to the pad portion L of the formed first conductor layer 121, and the recess op2 corresponds to the wiring FW (see reference). Figure 1 It is possible to perform decontamination treatment on the inner surfaces of the formed recesses op1, op2 and opening vo using a solution containing an oxidizing agent such as permanganate.

[0050] In the formation of the recesses op1 and op2, the recesses op1 and op2 penetrating the second resin insulating layer 112 are perforated by ablation with a laser, such as an excimer laser, irradiated from the upper side of the second resin insulating layer 112. The second resin insulating layer 112 is made of a material with high machinability relative to the laser, while the first resin insulating layer 111 is made of a material with low machinability relative to the laser. Therefore, after the processing (perforation) of the second resin insulating layer 112 using the irradiated laser is completed, and the first resin insulating layer 111 is exposed at the bottom of the recesses op1 and op2, the first resin insulating layer 111 is practically difficult to be processed by the laser. For example, a certain amount of time can be ensured until the first resin insulating layer 111 is actually processed. By stopping the laser irradiation within this time, the recesses op1 and op2 penetrating only the second resin insulating layer 112 can be formed. In other words, recesses op1 and op2 that penetrate the second resin insulating layer 112 and have a depth D approximately the same as the thickness T of the second resin insulating layer 112 can be achieved by the difference in the machinability of the first resin insulating layer 111 and the second resin insulating layer 112 relative to the laser. Furthermore, the depth D of the formed recesses op1 and op2 can be greater than the thickness T of the second resin insulating layer 112, and the bottom surface of the recesses op1 and op2 can also be formed from the first resin insulating layer 111 starting from the interface between the first resin insulating layer 111 and the second resin insulating layer 112.

[0051] The processability of the resin insulating layer relative to the laser can be adjusted, for example, by adjusting the absorption coefficient relative to the wavelength of the laser used. When adjusting the processability relative to the laser wavelength by adjusting the absorption coefficient, the absorption coefficient of the second resin insulating layer 112 can be set to be larger than that of the first resin insulating layer 111. For example, to make the absorption coefficient of the second resin insulating layer 112 relative to the laser different from that of the first resin insulating layer 111, the amounts of additives that can be included in the second resin insulating layer 112 and the first resin insulating layer 111 can be adjusted. Examples of additives include, for example, curing inhibitors for pigments such as carbon black. Furthermore, additives are sometimes curing accelerators, such as imidazole, triphenylphosphine, or sulfonium salts.

[0052] Additionally, for example, differences in processability relative to the laser can sometimes be achieved through the composition or structure of the resin materials constituting the second resin insulating layer 112 and the first resin insulating layer 111. For example, sometimes the second resin insulating layer 112 uses a non-crystalline resin (e.g., ABS resin, etc.), while the first resin insulating layer 111 uses a crystalline resin (e.g., liquid crystal polymer (LCP), etc.).

[0053] Furthermore, the machinability relative to the laser can sometimes be differentiated by adjusting the volumetric content of the filler contained in the second resin insulating layer 112 and the first resin insulating layer 111. Sometimes, a higher volumetric content of the filler hinders laser processing along the thickness direction of the resin insulating layer. Therefore, sometimes the volumetric content of the filler in the second resin insulating layer 112 is smaller, while the volumetric content of the filler in the first resin insulating layer 111 is larger. Moreover, by differentiating the average particle size of the filler contained in the first and second resin insulating layers 111 and 112, the machinability relative to the laser can be differentiated. For example, by making the average particle size of the filler contained in the first resin insulating layer 111 larger than the average particle size of the filler contained in the second resin insulating layer 112, the machinability of the second resin insulating layer 112 relative to the laser can sometimes be made higher than that of the first resin insulating layer 111. Additionally, the term "particle size" in the description of the filler refers to the straight-line distance between the two furthest points on the outer surface of the filler. When the processability relative to the laser is set differently by adjusting the filler volume content, during the formation stage of the first and second resin insulating layers 111 and 112, for example, a second resin insulating layer 112 with a filler volume content of about 5% to 15% and a first resin insulating layer 111 with a filler volume content of about 50% to 80% can be formed. Furthermore, in the second resin insulating layer 112, the average particle size of the filler can be set to about 0.25 μm, and in the first resin insulating layer 111, the average particle size of the filler can be set to about 0.5 μm. Moreover, sometimes the maximum particle size of the filler included in the formed second resin insulating layer 112 is limited to less than 50% of the width of the recess op1 to be formed and the width of adjacent recess op1s relative to each other.

[0054] Additionally, refer to Figures 3D to 3E The order in which the opening vo and the recesses op1 and op2 are formed can be arbitrarily changed. For example, the recesses op1 and op2 can be formed before the opening vo. Alternatively, they can be formed in the stacked... Figure 3C After the first resin insulating layer 111 and the second resin insulating layer 112 are shown, and before the openings vo and the recesses op1 and op2 are formed, the surface of the exposed insulating layer 21 is properly protected on the other side F2 of the core substrate 100, for example, using a mask such as a PET film.

[0055] Then as Figure 3FAs shown, a conductor layer 121p is formed that covers the entire upper surface of the second resin insulating layer 112 and fills the inner sides of the recesses op1 and op2 and the opening vo. For example, firstly, a metal film layer 12a is formed by chemical plating or sputtering. The metal film layer 12a covers the entire area of ​​the inner surfaces of the opening vo, the recesses op1 and op2, and the upper surface of the second resin insulating layer 112. Next, the metal film layer 12a is electroplated as a power supply layer to form a plating film layer 12b. The inner sides of the metal film layer 12a of the openings op1 and op2 are filled with conductors, thereby forming a conductor layer 121p that covers the entire area of ​​the upper surface of the second resin insulating layer 112.

[0056] Next, as Figure 3G As shown, the portion of the conductor layer 121p that is above the upper surface of the second resin insulating layer 112 in the thickness direction is removed by grinding. The grinding of the conductor layer 121p can be performed, for example, by chemical mechanical polishing (CMP). At the stage after grinding, the upper surface of the second resin insulating layer 112 is approximately on the same plane as the upper surface of the first conductor layer 121.

[0057] As described above, the depth D of the recesses op1 and op2 formed through the second resin insulating layer 112 is approximately equal to the thickness T of the second resin insulating layer 112. Therefore, the thickness of the first conductor layer 121, which is composed of the metal film layer 12a and the plating film layer 12b filling the recesses op1 and op2, is also approximately equal to the thickness T of the second resin insulating layer 112. That is, according to the wiring substrate manufacturing method of this embodiment, the thickness of the conductor layer embedded in the resin insulating layer can be controlled by controlling the thickness of the resin insulating layer. The thickness of the conductor layer embedded in the insulating layer is precisely controlled.

[0058] Through the above processes, the wiring substrate becomes Figure 3H The state shown is as follows. The formation of the first conductor layer 121 is completed as follows: the second resin insulating layer 121 is exposed and embedded in the second resin insulating layer 112, having wiring FW and pad portion L, and having a shape that penetrates the conductor layer.

[0059] Next, as Figure 3I As shown, on the other side F2 of the core substrate 100, the conductor layer 22 and the via conductor 23 are integrally formed.

[0060] On one side F1 of the core substrate 100, an insulating layer 11 and a conductor layer 12 are further formed on the upper side of the conductor layer 112 using the same method as described above for forming an insulating layer 11 and a conductor layer 12 on the core substrate 100. The formation of the first stacked portion 10 on one side F1 of the core substrate 100 is completed. On the other side F2 of the core substrate 100, another insulating layer 21 and a conductor layer 22 are alternately stacked. The formation of the second stacked portion 20 on the other side F2 is completed. The outermost conductor layer 12 of the first stacked portion 10 is formed with a pattern including conductor pads 12p, and the outermost conductor layer 22 of the second stacked portion 20 is formed with a pattern including conductor pads 22p.

[0061] Next, as Figure 3J As shown, insulating layers 110 and 210, for example, serving as solder resist layers, are formed on the first and second laminated portions 10 and 20, respectively. For example, a photosensitive epoxy resin film is formed by spraying, curtain coating, or film bonding, and openings 110a and 210a are formed by exposure and development. Conductor pads 12p and 22p are exposed through the openings 110a and 210a of the insulating layers 110 and 210. Through the above processes, the formation of the wiring substrate 1 is completed. Alternatively, after forming the openings 110a and 210a, a protective film (not shown) can be formed on the surface of the exposed conductor pads 12p and 22p. For example, a protective film composed of Ni / Au, Ni / Pd / Au, or Sn can be formed by plating. An OSP film can also be formed by spraying an organic material.

[0062] The wiring substrate of this embodiment is not limited to the wiring substrate having the structure illustrated in the accompanying drawings and the structure, shape, and material illustrated in this specification. For example, the conductor layer having the form of a through conductor layer can be any single or multiple conductor layers within the conductor layers constituting the wiring substrate. The wiring substrate of this embodiment only needs to include a first conductor layer, a first resin insulating layer, and a second resin insulating layer having the form of a through conductor layer, and its shape is not limited to having a core substrate. The first and second stacked portions can have any number of insulating and conductor layers. The number of insulating and conductor layers in the first stacked portion formed on both sides of the core substrate can also be different from the number of insulating and conductor layers in the second stacked portion. The manufacturing method of the wiring substrate of this embodiment is not limited to the method described with reference to the accompanying drawings, and its conditions or sequence can be appropriately changed. Depending on the structure of the currently manufactured wiring substrate, some processes can be omitted, and other processes can be added.

Claims

1. A method for manufacturing a wiring substrate, the method comprising the following steps: A first resin insulating layer and a second resin insulating layer in contact with the upper surface of the first resin insulating layer are formed; A recess is formed by laser irradiation, the recess penetrating the second resin insulating layer and exposing the first resin insulating layer at the bottom; and The recess is filled with a conductor to form a first conductor layer having a shape embedded in the second resin insulating layer, wherein... The first resin insulating layer and the second resin insulating layer have different machinability relative to the laser.

2. The method for manufacturing a wiring substrate according to claim 1, wherein, The depth of the recess and the thickness of the first conductor layer are formed to be approximately equal to the thickness of the second resin insulating layer.

3. The method for manufacturing a wiring substrate according to claim 1, wherein, The absorption coefficient of the second resin insulating layer relative to the laser is greater than that of the first resin insulating layer relative to the laser.

4. The method for manufacturing a wiring substrate according to claim 3, wherein, The volume fraction of the curing accelerator contained in the second resin insulating layer is smaller than that contained in the first resin insulating layer.

5. The method for manufacturing a wiring substrate according to claim 3, wherein, The volumetric content of the curing inhibitor contained in the second resin insulating layer is greater than that contained in the first resin insulating layer.

6. The method for manufacturing a wiring substrate according to claim 5, wherein, The curing inhibitor is a pigment.

7. The method for manufacturing a wiring substrate according to claim 1, wherein, The second resin insulating layer comprises a non-crystalline resin. The first resin insulating layer comprises a crystalline resin.

8. The method for manufacturing a wiring substrate according to claim 1, wherein, The volumetric content of the inorganic filler contained in the first resin insulating layer is greater than that contained in the second resin insulating layer.

9. The method for manufacturing a wiring substrate according to claim 8, wherein, The average particle size of the inorganic filler contained in the first resin insulation layer is larger than the average particle size of the inorganic filler contained in the second resin insulation layer.

10. The method for manufacturing a wiring substrate according to claim 1, wherein, The recess is formed by irradiation with an excimer laser.

11. A wiring substrate, comprising: First resin insulating layer; and A second resin insulating layer is formed in contact with the upper surface of the first resin insulating layer. in, The wiring substrate also has a recess that penetrates the second resin insulating layer and exposes the first resin insulating layer at the bottom. The recess is filled with the first conductor layer. All the conductor layers formed on the upper surface of the first resin insulating layer are the first conductor layers filling the recesses. The second resin insulating layer has different machinability relative to the laser compared to the first resin insulating layer.

12. The wiring substrate according to claim 11, wherein, The thickness of the first conductor layer is approximately equal to the thickness of the second resin insulating layer.

13. The wiring substrate according to claim 11, wherein, The volumetric content of the inorganic filler contained in the second resin insulation layer is smaller than that contained in the first resin insulation layer.

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