Antifuse device and method of manufacturing the same

Abstract

The present application provides a kind of antifuse device and its manufacturing method.The antifuse device includes substrate, doped region, dielectric layer, first contact window, antifuse material layer and second contact window.Doped region is located in substrate.Dielectric layer is located on substrate, and has first opening and second opening.First opening and second opening respectively expose doped region.First contact window is located in first opening.Antifuse material layer is located between first contact window and doped region.Second contact window is located in second opening, and is electrically connected to doped region.The antifuse device can prevent misjudgment of data.

Description

Technical Field

[0001] This invention relates to a semiconductor device and a method for manufacturing the same, and more particularly to an anti-fuse device and a method for manufacturing the same. Background Technology

[0002] An antifuse device with an antifuse material layer has been developed. Initially, the antifuse material layer has a high resistance, and the antifuse device is in an open-circuit state. When the antifuse device is operated, the antifuse material layer breaks down, forming a conductive path, and the antifuse device is in a short-circuit state. Currently, common antifuse devices are operated via a gate. However, due to the large contact area between the gate and the antifuse material layer, the location of the breakdown is highly uncertain. Consequently, after the antifuse material layer breaks down, the resistance of the antifuse device becomes highly uncertain, easily leading to misinterpretations of data. Summary of the Invention

[0003] This invention provides an antifuse device and its manufacturing method, which can prevent data misinterpretation.

[0004] This invention proposes an antifuse device, comprising a substrate, a doped region, a dielectric layer, a first contact window, an antifuse material layer, and a second contact window. The doped region is located in the substrate. The dielectric layer is located on the substrate and has a first opening and a second opening. The first opening and the second opening expose the doped region, respectively. The first contact window is located in the first opening. The antifuse material layer is located between the first contact window and the doped region. The second contact window is located in the second opening and is electrically connected to the doped region.

[0005] This invention provides a method for manufacturing an antifuse device, comprising the following steps: Providing a substrate. Forming a doped region in the substrate. Forming a dielectric layer on the substrate. Forming a first opening in the dielectric layer. Exposing the doped region through the first opening. Forming an antifuse material layer in the first opening. Forming a first contact window in the first opening. The first contact window is located on the antifuse material layer. Forming a second opening in the dielectric layer. The second opening exposes the doped region. Forming a second contact window in the second opening. The second contact window is electrically connected to the doped region.

[0006] Based on the above, in the antifuse device and its manufacturing method proposed in this invention, since the first contact window is formed in the first opening, the contact area between the first contact window and the antifuse material layer can be reduced by controlling the size of the first opening. Therefore, when operating the antifuse device, the breakdown portion of the antifuse material layer can be made to converge and concentrate in a smaller area, thereby reducing the uncertainty of the resistance value of the antifuse device and preventing data misjudgment. Furthermore, since the antifuse device operates by applying voltage to the first contact window and the second contact window, the antifuse device may not have a gate, thus allowing for a smaller device area and increasing device density.

[0007] To make the above features and advantages of the present invention more apparent and understandable, specific embodiments are described below in conjunction with the accompanying drawings. Attached Figure Description

[0008] Figures 1A to 1I This is a top view of the manufacturing process of an antifuse device according to an embodiment of the present invention;

[0009] Figures 2A to 2I For along Figures 1A to 1I A cross-sectional view of the I-I' section line in the diagram;

[0010] Figure 3 This is a cross-sectional view of an antifuse device according to another embodiment of the present invention;

[0011] Figures 4A to 4E This is a top view of the manufacturing process of an antifuse device according to another embodiment of the present invention;

[0012] Figures 5A to 5E For along Figures 4A to 4E A cross-sectional view of section line II-II' in the middle;

[0013] Figure 6 and Figure 7 This is a cross-sectional view of an antifuse device according to other embodiments of the present invention.

[0014] Explanation of icon numbers:

[0015] 10a, 10b, 20a, 30a, 30b: Anti-fuse devices

[0016] 100: Base

[0017] 102: Tunnel

[0018] 104: Isolation Structure

[0019] 106: Doped region

[0020] 108: Dielectric layer

[0021] 110, 114, 208: Patterned hard mask layer

[0022] 112: Anti-fuse material layer

[0023] 116,210: Metal silicide layer

[0024] 118,124,202,212,300: Contact window

[0025] 120, 126, 134, 138, 204, 214, 222, 226: Conductor layer

[0026] 122,128,136,140,206,216,224,228: Barrier layer

[0027] 130, 132, 218, 220: Conductors

[0028] OP1, OP2: Openings Detailed Implementation

[0029] Figures 1A to 1I This is a top view of the manufacturing process of an antifuse device according to an embodiment of the present invention. Figures 2A to 2I For along Figures 1A to 1I The cross-sectional view along section line I-I' in the diagram. Please refer to... Figure 1A and Figure 2A A substrate 100 is provided. The substrate 100 may be a semiconductor substrate, such as a silicon substrate. Furthermore, a well region 102 may be formed in the substrate 100. The well region 102 may be formed, for example, by ion implantation. Additionally, an isolation structure 104 may be formed in the substrate 100. The isolation structure 104 may be, for example, a shallow trench isolation (STI) structure. The material of the isolation structure 104 may be, for example, an oxide (e.g., silicon oxide). Next, a doped region 106 is formed in the substrate 100. The isolation structure 104 may surround the doped region 106. Figure 1A In some embodiments, the doped region 106 may be formed in the well region 102. The doped region 106 may be formed by, for example, ion implantation. The doped region 106 and the well region 102 may have different conductivity types. For example, the doped region 106 and the well region 102 may be one of N-type conductivity and the other of P-type conductivity.

[0030] Please refer to Figure 1B and Figure 2B A dielectric layer 108 is formed on a substrate 100. The material of the dielectric layer 108 is, for example, an oxide (e.g., silicon oxide). The method for forming the dielectric layer 108 is, for example, chemical vapor deposition. In some embodiments, the dielectric layer 108 may be subjected to a chemical mechanical polishing process to planarize the surface of the dielectric layer 108.

[0031] Please refer to Figure 1C and Figure 2C A patterned hard mask layer 110 can be formed on the dielectric layer 108. The patterned hard mask layer 110 can expose a portion of the dielectric layer 108. The material of the patterned hard mask layer 110 is, for example, a nitride (e.g., silicon nitride). The patterned hard mask layer 110 can be formed by deposition, photolithography, and etching processes.

[0032] Next, a portion of the dielectric layer 108 exposed by the patterned hard mask layer 110 can be removed using the patterned hard mask layer 110 as a mask. This forms an opening OP1 in the dielectric layer 108. The opening OP1 exposes the doped region 106. In this embodiment, an over-etching process can be performed to remove part of the doped region 106, resulting in an arc-shaped cross-section at the bottom of the opening OP1. Figure 2C In other embodiments, an etching process may not be performed, and the cross-sectional shape of the bottom of the opening OP1 may be flat. The removal method for the portion of the dielectric layer 108 exposed by the patterned hard mask layer 110 is, for example, dry etching.

[0033] Please refer to Figure 1D and Figure 2D An antifuse material layer 112 is formed in the opening OP1. The antifuse material layer 112 can be formed directly on the doped region 106. The material of the antifuse material layer 112 is, for example, an oxide (e.g., silicon oxide). The method for forming the antifuse material layer 112 is, for example, thermal oxidation or plasma oxidation.

[0034] Please refer to Figure 1E and Figure 2E A patterned hard mask layer 114 can be formed on the patterned hard mask layer 110. The patterned hard mask layer 114 can fill the opening OP1. The material of the patterned hard mask layer 114 is, for example, a nitride (e.g., silicon nitride). The patterned hard mask layer 114 can be formed by deposition, photolithography, and etching processes. In some embodiments, a portion of the patterned hard mask layer 110 exposed by the patterned hard mask layer 114 can be removed, exposing a portion of the dielectric layer 108. Then, using the patterned hard mask layer 114 and the patterned hard mask layer 110 as masks, the portion of the dielectric layer 108 exposed by the patterned hard mask layer 114 and the patterned hard mask layer 110 can be removed. Thus, an opening OP2 can be formed in the dielectric layer 108. The opening OP2 exposes the doped region 106. In this embodiment, an etching process can be performed to remove part of the doped region 106, so that the cross-sectional shape of the bottom of the opening OP2 becomes arc-shaped. Figure 2EIn other embodiments, an etching process may not be performed, and the bottom of the opening OP2 may be flat. The method for removing the portion of the dielectric layer 108 exposed by the patterned hard mask layer 114 and the patterned hard mask layer 110 is, for example, dry etching.

[0035] Please refer to Figure 1F and Figure 2F A metal silicide layer 116 can be directly formed on the doped region 106 exposed by the opening OP2. The material of the metal silicide layer 116 is, for example, cobalt silicide (CoSi) or nickel silicide (NiSi). The method for forming the metal silicide layer 116 is, for example, performing a self-aligned metal silicide process.

[0036] Please refer to Figure 1G and Figure 2G The patterned hard mask layer 114 and the patterned hard mask layer 110 can be removed. The removal method for the patterned hard mask layer 114 and the patterned hard mask layer 110 is, for example, wet etching.

[0037] Please refer to Figure 1H and Figure 2H A contact window 118 is formed in the opening OP1. The contact window 118 is located on the antifuse material layer 112. The contact window 118 can directly contact the antifuse material layer 112. In this embodiment, since the cross-sectional shape of the bottom of the opening OP1 is arc-shaped, the cross-sectional shape of the interface between the contact window 118 and the antifuse material layer 112 can be arc-shaped. In other embodiments, when the cross-sectional shape of the bottom of the opening OP1 is flat, the cross-sectional shape of the interface between the contact window 118 and the antifuse material layer 112 can be flat. The contact window 118 can be a single-layer structure or a multi-layer structure. In this embodiment, the contact window 118 is exemplified by a multi-layer structure including a conductor layer 120 and a barrier layer 122. The conductor layer 120 is located in the opening OP1. The material of the conductor layer 120 is, for example, tungsten or aluminum. The barrier layer 122 is located between the conductor layer 120 and the antifuse material layer 112 and between the conductor layer 120 and the dielectric layer 108. The material of the barrier layer 122 is, for example, titanium, titanium nitride, or a combination thereof.

[0038] Furthermore, a contact window 124 is formed in the opening OP2. The contact window 124 may be formed on the metal silicide layer 116. The contact window 124 may directly contact the metal silicide layer 116. The contact window 124 is electrically connected to the doped region 106. In this embodiment, the contact window 124 can be electrically connected to the doped region 106 through the metal silicide layer 116. The contact window 118 may be a single-layer structure or a multi-layer structure. In this embodiment, the contact window 124 is exemplified by a multi-layer structure including a conductor layer 126 and a barrier layer 128. The conductor layer 126 is located in the opening OP2. The material of the conductor layer 126 is, for example, tungsten. The barrier layer 128 is located between the conductor layer 126 and the metal silicide layer 116 and between the conductor layer 126 and the dielectric layer 108. The material of the barrier layer 128 is, for example, titanium, titanium nitride, or a combination thereof.

[0039] In this embodiment, contact window 118 and contact window 124 can be formed simultaneously by the same process. In some embodiments, the method for forming contact window 118 and contact window 124 is, for example, to first form a contact window material layer (not shown) filling the openings OP1 and OP2, and then remove the contact window material layer located outside the openings OP1 and OP2 by chemical mechanical polishing.

[0040] Please refer to Figure 1I and Figure 2I Conductors 130 and 132 can be formed on dielectric layer 108. Conductors 130 and 132 are electrically connected to contact windows 118 and 124, respectively. Conductors 130 and 132 can be single-layer or multi-layer structures. In this embodiment, conductors 130 and 132 are multi-layer structures. For example, conductor 130 may include conductor layer 134 and barrier layer 136, and conductor 132 may include conductor layer 138 and barrier layer 140. Conductor layer 134 is located on dielectric layer 108 and contact window 118. Barrier layer 136 is located between conductor layer 134 and dielectric layer 108 and between conductor layer 134 and contact window 118. Conductor layer 138 is located on dielectric layer 108 and contact window 124. Barrier layer 140 is located between conductor layer 138 and dielectric layer 108 and between conductor layer 138 and contact window 124. The materials for conductor layers 134 and 138 are, for example, tungsten or aluminum. The materials for barrier layers 136 and 140 are, for example, titanium, titanium nitride, or a combination thereof. Wires 130 and 132 can be formed by deposition, photolithography, and etching processes.

[0041] The following is through Figure 1I and Figure 2I The antifuse device 10a of this embodiment will be described below. Furthermore, although the method for forming the antifuse device 10a is described using the method described above as an example, the present invention is not limited thereto.

[0042] Please refer to Figure 1I and Figure 2I The antifuse device 10a includes a substrate 100, a doped region 106, a dielectric layer 108, a contact window 118, an antifuse material layer 112, and a contact window 124. In this embodiment, the antifuse device 10a can be applied to a one-time programmable (OTP) memory. The doped region 106 is located in the substrate 100. The dielectric layer 108 is located on the substrate 100 and has openings OP1 and OP2. Openings OP1 and OP2 expose the doped region 106, respectively. The contact window 118 is located in opening OP1. The antifuse material layer 112 is located between the contact window 118 and the doped region 106. The antifuse material layer 112 can be directly located on the doped region 106. The contact window 124 is located in opening OP2 and is electrically connected to the doped region 106. The vertical projections of the contact window 118 and the contact window 124 can both be located on the doped region 106. Furthermore, the antifuse device 10a may also include at least one of a well region 102, an isolation structure 104, a metal silicide layer 116, and wires 130 and 132. The well region 102 is located in the substrate 100. A doped region 106 may be located in the well region 102. The doped region 106 and the well region 102 may have different conductivity types. The isolation structure 104 is located in the substrate 100 and surrounds the doped region 106. Figure 1A A metal silicide layer 116 is located between contact window 124 and doped region 106. The metal silicide layer 116 can be directly located on doped region 106. Wires 130 and 132 are electrically connected to contact window 118 and contact window 124, respectively.

[0043] Based on the above embodiments, in the antifuse device 10a and its manufacturing method, since the contact window 118 is formed in the opening OP1, the contact area between the contact window 118 and the antifuse material layer 112 can be reduced by controlling the size of the opening OP1. Therefore, when operating the antifuse device 10a, the breakdown portion of the antifuse material layer 112 can be made to converge and concentrate in a smaller area, thereby reducing the uncertainty of the resistance value of the antifuse device 10a and preventing data misjudgment. In addition, since the antifuse device 10a is operated by applying voltage to the contact window 118 and the contact window 124, the antifuse device 10a may not have a gate, thus the antifuse device 10a can have a smaller device area, thereby increasing device density. In some embodiments, when the cross-sectional shape of the interface between the contact window 118 and the antifuse material layer 112 is arc-shaped, the electric field can be more concentrated, thus making the breakdown portion of the antifuse material layer 112 more convergent and concentrated.

[0044] Figure 3 This is a cross-sectional view of an antifuse device according to another embodiment of the present invention. Please refer to... Figure 2I and Figure 3, Figure 3 antifuse device 10b and Figure 2I The differences in the antifuse device 10a are explained below. Figures 2A to 2I In this embodiment, opening OP1 and antifuse material layer 112 are formed first, followed by opening OP2 and metal silicide layer 116. Figure 3 In this embodiment, opening OP1 and the metal silicide layer 116 are formed first, followed by opening OP2 and the antifuse material layer 112. Furthermore, Figure 3 antifuse device 10b and Figure 2I The same components in the antifuse device 10a are represented by the same symbols and their descriptions are omitted.

[0045] Figures 4A to 4E This is a top view of the manufacturing process of an antifuse device according to another embodiment of the present invention. Figures 4A to 4E To continue Figure 1D The following is a cross-sectional view of the production process after the steps. Figures 5A to 5E For along Figures 4A to 4E A cross-sectional view of section line II-II' in the diagram. Figures 5A to 5E To continue Figure 2D The following is a cross-sectional view of the production process after the steps.

[0046] Please refer to Figure 1D , Figure 2D , Figure 4A and Figure 5A In forming the antifuse material layer 112 ( Figure 1D and Figure 2D After that, the patterned hard mask layer 110 can be removed. Figure 1D and Figure 2D The removal method for the patterned hard mask layer 110 is, for example, wet etching. Next, a contact window 202 is formed in the opening OP1. The contact window 202 is located on the antifuse material layer 112. The contact window 202 can directly contact the antifuse material layer 112. In this embodiment, the contact window 202 may include a conductor layer 204 and a barrier layer 206. Furthermore, for details regarding the contact window 202, please refer to the contact window 118 in the above embodiment (…). Figure 2H The explanation of ) will not be repeated here.

[0047] Please refer to Figure 4B and Figure 5B A patterned hard mask layer 208 can be formed on the dielectric layer 108. The patterned hard mask layer 208 can expose a portion of the dielectric layer 108. The material of the patterned hard mask layer 208 is, for example, a nitride (e.g., silicon nitride). The patterned hard mask layer 208 can be formed by deposition, photolithography, and etching processes.

[0048] Next, a portion of the dielectric layer 108 exposed by the patterned hard mask layer 208 can be removed using the patterned hard mask layer 208 as a mask. This forms an opening OP2 in the dielectric layer 108. The opening OP2 exposes the doped region 106. The method for removing the portion of the dielectric layer 108 exposed by the patterned hard mask layer 208 is, for example, dry etching.

[0049] Please refer to Figure 4C and Figure 5C A metal silicide layer 210 can be directly formed on the doped region 106 exposed by the opening OP2. The material of the metal silicide layer 210 is, for example, cobalt silicide or nickel silicide. The method for forming the metal silicide layer 210 is, for example, performing a self-aligned metal silicide process.

[0050] Please refer to Figure 4D and Figure 5D The patterned hard mask layer 208 can be removed. The removal method for the patterned hard mask layer 208 is, for example, wet etching.

[0051] Next, a contact window 212 is formed in the opening OP2. In this embodiment, contact window 202 and contact window 212 are formed by different processes. Contact window 212 may be formed on the metal silicide layer 210. Contact window 212 may directly contact the metal silicide layer 210. Contact window 212 is electrically connected to the doped region 106. In this embodiment, contact window 212 can be electrically connected to the doped region 106 through the metal silicide layer 210. In this embodiment, contact window 212 may include a conductor layer 214 and a barrier layer 216. Furthermore, for details regarding contact window 212, please refer to contact window 124 in the above embodiment. Figure 2H The explanation of ) will not be repeated here.

[0052] Please refer to Figure 4E and Figure 5E Conductors 218 and 220 can be formed on dielectric layer 108. Conductors 218 and 220 are electrically connected to contact windows 202 and 212, respectively. In this embodiment, conductor 218 may include conductor layer 222 and barrier layer 224, and conductor 220 may include conductor layer 226 and barrier layer 228. Furthermore, for details regarding conductors 218 and 220, please refer to conductors 130 and 132 in the above embodiments. Figure 2I The explanation of ) will not be repeated here.

[0053] Figure 6 This is a cross-sectional view of an antifuse device according to another embodiment of the present invention. Please refer to... Figure 5E and Figure 6 , Figure 6 Anti-fuse device 30a and Figure 5E The differences in the antifuse device 20a are explained below. Figure 6 In this embodiment, the antifuse device 30a may further include a contact window 300. The contact window 300 is located between the antifuse material layer 112 and the doped region 106. The antifuse material layer 112 may be directly located on the contact window 300. Furthermore, the manufacturing method of the antifuse device 30a may further include the following steps: Before forming the antifuse material layer 112, the contact window 300 may be formed in the opening OP1. The material of the contact window 300 may be, for example, a silicon-containing material such as doped polysilicon. When the material of the contact window 300 is a silicon-containing material such as doped polysilicon, since the resistance of silicon-containing materials is greater than that of metals, the operating current of the antifuse device 30a is smaller. Therefore, under the same bias voltage, the power loss of the antifuse device 30a is reduced. The method for forming the contact window 300 may be, for example, forming a contact window material layer (not shown) in the opening OP1, and then performing a back etching process on the contact window material layer. The antifuse material layer 112 may be directly formed on the contact window 300. In this embodiment, the cross-sectional shape of the interface between the contact window 202 and the antifuse material layer 112 can be flat. Furthermore, depending on process requirements, the height of the contact window 300 can be greater than or less than the height of the contact window 202. In this embodiment, the height of the contact window 300 can be less than the height of the contact window 202. Additionally, Figure 6 Anti-fuse device 30a and Figure 5E The same components in the antifuse device 20a are represented by the same symbols and their descriptions are omitted.

[0054] Figure 7 This is a cross-sectional view of an antifuse device according to another embodiment of the present invention. Please refer to... Figure 6 and Figure 7 , Figure 7 antifuse device 30b and Figure 6 The differences in the antifuse device 30a are explained below. Figure 6 In this embodiment, opening OP1 and antifuse material layer 112 are formed first, followed by opening OP2 and metal silicide layer 210. Figure 7 In this embodiment, opening OP1 and metal silicide layer 210 are formed first, followed by opening OP2 and antifuse material layer 112. In antifuse device 30b, metal silicide layer 210 is located between contact window 202 and contact window 300. Metal silicide layer 210 can be directly located on contact window 300. Alternatively, in the process of antifuse device 30b, metal silicide layer 210 is formed directly on contact window 300. Contact window 202 can be formed on metal silicide layer 210. Furthermore, Figure 7 antifuse device 30b and Figure 6 The same components in the antifuse device 30a are represented by the same symbols and their descriptions are omitted.

[0055] In summary, in the antifuse device and its manufacturing method described in the above embodiments, the contact area between the contact window and the antifuse material layer can be reduced by controlling the size of the opening. This reduces the uncertainty in the resistance value of the antifuse device, preventing misjudgment of data. Furthermore, the antifuse device can have a smaller device area, thereby increasing device density.

[0056] Although the present invention has been disclosed above with reference to embodiments, it is not intended to limit the present invention. Any person skilled in the art can make some modifications and refinements without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the claims.

Claims

1. An antifuse device, comprising: include: Base; The doped region is located in the substrate; A dielectric layer is located on the substrate and has a first opening and a second opening, wherein the first opening and the second opening respectively expose the doped region; The first contact window is located in the first opening; An antifuse material layer is located between the first contact window and the doped region; as well as The second contact window is located in the second opening and is electrically connected to the doped region, wherein The vertical projections of the first contact window and the second contact window are both located on the same doped region.

2. The antifuse device of claim 1, wherein, The first contact window directly contacts the antifuse material layer.

3. The antifuse device of claim 1, wherein, The cross-sectional shape of the interface between the first contact window and the antifuse material layer includes an arc shape.

4. The antifuse device of claim 1, wherein, The material of the antifuse layer includes oxides.

5. The antifuse device of claim 1, wherein, Also includes: A metal silicide layer is located between the second contact window and the doped region, wherein the metal silicide layer is directly located on the doped region.

6. The antifuse device of claim 1, wherein, Also includes: The third contact window is located between the antifuse material layer and the doped region, wherein the material of the third contact window includes a silicon-containing material.

7. The antifuse device of claim 1, wherein, Also includes: The third contact window is located between the second contact window and the doped region; as well as A metal silicide layer is located between the second contact window and the third contact window, wherein the metal silicide layer is directly located on the third contact window.

8. The antifuse device of claim 1, wherein, Also includes: An isolation structure is located in the substrate and surrounds the doped region; as well as A well region is located in the substrate, wherein the doped region is located in the well region and the doped region and the well region have different conductivity types.

9. A method for manufacturing an antifuse device, characterized in that, include: Provide a base; A doped region is formed in the substrate; A dielectric layer is formed on the substrate; A first opening is formed in the dielectric layer, wherein the first opening exposes the doped region; An antifuse material layer is formed in the first opening; A first contact window is formed in the first opening, wherein the first contact window is located on the antifuse material layer; A second opening is formed in the dielectric layer, wherein the second opening exposes the doped region; as well as A second contact window is formed in the second opening, wherein the second contact window is electrically connected to the doped region, wherein The vertical projections of the first contact window and the second contact window are both located on the same doped region.

10. The method of claim 9, wherein First, the first opening and the anti-fuse material layer are formed, and then the second opening is formed.

11. The method of claim 9, wherein the method further comprises: First, the second opening is formed, and then the first opening and the anti-fuse material layer are formed.

12. The method of claim 9, wherein the method further comprises: The method for forming the antifuse material layer includes thermal oxidation or plasma oxidation.

13. The method of claim 9, wherein the method further comprises: The first contact window and the second contact window are formed simultaneously using the same process.

14. The method of claim 9, wherein the method further comprises: The first contact window and the second contact window are formed by different processes.

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