Semiconductor structure and manufacturing method thereof

Abstract

The presently disclosed embodiment discloses a semiconductor structure and a method for manufacturing the same, wherein the semiconductor structure includes: a substrate and a conductive via located within the substrate, a first conductive type transistor, and a second conductive type transistor; wherein the first conductive type transistor is disposed on both sides of the conductive via along a first direction; and the second conductive type transistor is disposed on the other two sides of the conductive via along a second direction; the first direction is perpendicular to the second direction; a first metal layer located on the substrate, the first metal layer including at least one first metal wire extending along the first direction, the first metal wire being electrically connected to the gate of the first conductive type transistor; a second metal layer located on the first metal layer, the second metal layer including at least one second metal wire extending along the second direction, the second metal wire being electrically connected to the gate of the second conductive type transistor; wherein the first metal wire and the second metal wire intersect with each other to form a grid structure covering the conductive via.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor manufacturing, and in particular to a semiconductor structure and a manufacturing method thereof. Background Art

[0002] The vertical interconnect stacking packaging method based on conductive through silicon via (TSV) interconnection technology has gradually led the development trend of packaging technology with its advantages of short-distance interconnection and high-density integration.

[0003] However, the conductive vias tend to protrude outward from the substrate after thermal expansion, affecting the flatness of the substrate and further affecting the performance of the semiconductor structure. Summary of the Invention

[0004] In view of this, embodiments of the present disclosure provide a semiconductor structure and a method for manufacturing the same in order to solve at least one problem existing in the background technology.

[0005] The technical solution of the present disclosure is implemented as follows: The present disclosure provides a semiconductor structure, including:

[0006] A substrate and a conductive via, a first conductive type transistor, and a second conductive type transistor located within the substrate; wherein the first conductive type transistor is disposed on two sides of the conductive via along a first direction; and the second conductive type transistor is disposed on the other two sides of the conductive via along a second direction; and the first direction is perpendicular to the second direction.

[0007] a first metal layer located on the substrate, the first metal layer comprising at least one first metal line extending along a first direction, the first metal line being electrically connected to a gate of the first conductive type transistor;

[0008] a second metal layer located on the first metal layer, the second metal layer comprising at least one second metal line extending along a second direction, the second metal line being electrically connected to a gate of the second conductive type transistor;

[0009] The first metal wires and the second metal wires cross each other to form a grid structure covering the conductive through-holes.

[0010] In some embodiments, there are a plurality of first metal wires, and the plurality of first metal wires are uniformly arranged along the second direction; and / or there are a plurality of second metal wires, and the plurality of second metal wires are uniformly arranged along the first direction.

[0011] In some embodiments, a spacing between the plurality of first metal lines is between 0.5 micrometers and 2 micrometers; and / or a spacing between the plurality of second metal lines is between 0.5 micrometers and 2 micrometers.

[0012] In some embodiments, the first conductivity type transistor is an n-type transistor, and the second conductivity type transistor is a p-type transistor.

[0013] In some embodiments, a channel direction of the first conductive type transistor is parallel to the first direction; and a channel direction of the second conductive type transistor is perpendicular to the second direction.

[0014] In some embodiments, a channel direction of the first conductive type transistor is perpendicular to the first direction; and a channel direction of the second conductive type transistor is parallel to the second direction.

[0015] In some embodiments, the semiconductor structure further includes an intermediate metal layer and a conductive plug; the intermediate metal layer is located between the first metal layer and the substrate, and the conductive plug includes at least one first sub-plug located between the intermediate metal layer and the first metal layer, and at least one second sub-plug located between the first metal layer and the second metal layer.

[0016] In some embodiments, the first metal line is electrically connected to the gate of the first conductive type transistor, including: the first metal line is electrically connected to the gate of the first conductive type transistor through the first sub-plug and the intermediate metal layer.

[0017] In some embodiments, the first metal layer also includes a first wiring structure; the second metal wire is electrically connected to the gate of the second conductive type transistor, including: the second metal wire is electrically connected to the gate of the second conductive type transistor through the second sub-plug, the first wiring structure, the first sub-plug, and the intermediate metal layer.

[0018] In some embodiments, at least one of the first metal lines and at least one of the second metal lines are electrically connected at an intersection through the second sub-plug.

[0019] In some embodiments, the intermediate metal layer includes a metal pad, and the metal pad is located on an upper surface of the conductive via;

[0020] At least one first metal line is electrically connected to the metal pad through the first sub-plug.

[0021] In some embodiments, the substrate includes a corner region sandwiched between the first conductivity type transistor and the second conductivity type transistor, and a distance between the corner region and the conductive via is between 1 micrometer and 20 micrometers.

[0022] In some embodiments, the semiconductor structure further includes a passive device, and the passive device is disposed in the corner region of the substrate.

[0023] The present disclosure also provides a method for manufacturing a semiconductor structure, including:

[0024] Providing a substrate, the substrate comprising a predetermined area, the predetermined area being used to form a conductive through hole;

[0025] forming a first conductive type transistor and a second conductive type transistor in the substrate; wherein the first conductive type transistor is arranged on two sides of the predetermined area along a first direction, and the second conductive type transistor is arranged on the other two sides of the predetermined area along a second direction, wherein the first direction is perpendicular to the second direction;

[0026] forming a conductive through hole in the predetermined area of ​​the substrate;

[0027] forming a first metal layer on the substrate, wherein the first metal layer includes at least one first metal line extending along a first direction, and the first metal line is electrically connected to the gate of the first conductive type transistor;

[0028] forming a second metal layer on the first metal layer, wherein the second metal layer includes at least one second metal line extending along a second direction, and the second metal line is electrically connected to the gate of the second conductive type transistor;

[0029] The first metal wires and the second metal wires cross each other to form a grid structure covering the conductive through-holes.

[0030] In some embodiments, the semiconductor structure further includes an intermediate metal layer and a first sub-plug; before forming the first metal layer on the substrate, the method includes:

[0031] forming an intermediate metal layer on the substrate, wherein the intermediate metal layer is electrically connected to the gates of the first conductive type transistor and the second conductive type transistor;

[0032] A first sub-plug is formed on the middle metal layer, where the first sub-plug is used to electrically connect the first metal layer and the middle metal layer.

[0033] In some embodiments, the semiconductor structure further includes a second sub-plug; before forming the second metal layer on the first metal layer, the method includes:

[0034] The second sub-plug is formed on the first metal layer, and the second sub-plug is used to electrically connect the first metal layer and the second metal layer.

[0035] The present disclosure provides a semiconductor structure and a manufacturing method thereof, wherein the semiconductor structure includes: a substrate and a conductive via located within the substrate, a first conductive type transistor, and a second conductive type transistor; wherein the first conductive type transistor is disposed on either side of the conductive via along a first direction; and the second conductive type transistor is disposed on the other two sides of the conductive via along a second direction; the first direction is perpendicular to the second direction; a first metal layer located on the substrate, the first metal layer including at least one first metal wire extending along the first direction, the first metal wire being electrically connected to the gate of the first conductive type transistor; and a second metal layer located on the first metal layer, the second metal layer including at least one second metal wire extending along the second direction, the second metal wire being electrically connected to the gate of the second conductive type transistor; wherein the first metal wire and the second metal wire intersect to form a grid structure covering the conductive via. In this way, the conductive via can be improved from bulging outward due to thermal expansion; and furthermore, the first metal wire and the second metal wire are connected to the gates of the first conductive type transistor and the second conductive type transistor, respectively, to provide electrical connections.

[0036] The details of one or more embodiments of the present disclosure are set forth in the accompanying drawings and the description below. Other features and advantages of the present disclosure will become apparent from the accompanying drawings and the claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the following briefly introduces the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0038] Figure 1 is a schematic diagram of an exemplary semiconductor structure;

[0039] Figure 2a A schematic top view of a semiconductor structure provided in an embodiment of the present disclosure is shown. Figure 2b The semiconductor structure provided by the embodiment of the present disclosure is along Figure 2a A schematic diagram of the cross-sectional structure taken along line AA', Figure 2c The semiconductor structure provided by the embodiment of the present disclosure is along Figure 2a A schematic cross-sectional structural diagram taken along line BB';

[0040] Figure 3 A flowchart of a method for manufacturing a semiconductor structure provided by an embodiment of the present disclosure;

[0041] Figures 4a-4hThe steps in the method for manufacturing the semiconductor structure provided in the embodiment of the present disclosure are as follows: Figure 2a Schematic diagram of the cross-sectional structure taken along line AA'. DETAILED DESCRIPTION

[0042] Exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although exemplary embodiments of the present disclosure are shown in the accompanying drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the specific embodiments described herein. Instead, these embodiments are provided to enable a more thorough understanding of the present disclosure and to fully convey the scope of the present disclosure to those skilled in the art.

[0043] In the following description, numerous specific details are provided to provide a more thorough understanding of the present disclosure. However, it will be apparent to those skilled in the art that the present disclosure can be practiced without one or more of these details. In other instances, certain technical features known in the art are not described to avoid confusion with the present disclosure; that is, all features of actual embodiments are not described herein, nor are well-known functions and structures described in detail.

[0044] In the drawings, the sizes of layers, regions, elements and their relative sizes may be exaggerated for clarity. Like reference numerals denote like elements throughout.

[0045] It should be understood that when an element or layer is referred to as being "on, adjacent to, connected to, or coupled to" another element or layer, it may be directly on, adjacent to, connected to, or coupled to the other element or layer, or there may be intervening elements or layers. In contrast, when an element is referred to as being "directly on, directly adjacent to, directly connected to, or directly coupled to" another element or layer, there may be no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, and / or parts, these elements, components, regions, layers, and / or parts should not be limited by these terms. These terms are merely used to distinguish one element, component, region, layer, or part from another element, component, region, layer, or part. Therefore, without departing from the teachings of the present disclosure, the first element, component, region, layer, or part discussed below may be represented as a second element, component, region, layer, or part. However, when the second element, component, region, layer, or part is discussed, it does not necessarily mean that the first element, component, region, layer, or part exists in the present disclosure.

[0046] Spatially relative terms such as "under," "beneath," "below," "under," "above," "above," etc., may be used herein for convenience of description to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that in addition to the orientations shown in the figures, the spatially relative terms are intended to include different orientations of the device in use and operation. For example, if the device in the drawings is flipped, then the elements or features described as "under the other elements" or "under it" or "under it" will be oriented as "on" the other elements or features. Thus, the exemplary terms "under" and "under" may include both upper and lower orientations. The device may be oriented otherwise (rotated 90 degrees or in other orientations) and the spatial descriptors used herein are interpreted accordingly.

[0047] The purpose of the terms used herein is only to describe specific embodiments and is not intended to limit the present disclosure. When used herein, the singular forms "a", "an", and "the" are intended to include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "comprising" and / or "comprising", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0048] Figure 1 The figure is a schematic diagram of an exemplary semiconductor structure. As shown in the figure, the semiconductor structure includes a substrate 10 and an insulating layer 12 located on the substrate 10; a conductive via 11 located within the substrate 10, with the upper surface of the conductive via 11 flush with the upper surface of the insulating layer 12; a dielectric layer 13 located on the insulating layer 12; and a metal pad 14 located within the dielectric layer 13 and electrically connected to the conductive via 11. When the semiconductor structure is bonded to another structure, the conductive via 11 can provide vertical interconnection between the semiconductor structure and the other structure.

[0049] However, when the semiconductor structure is bonded to other structures, the semiconductor structure is heated. During this process, the conductive vias 11 expand due to the heat and protrude outward from the substrate 10, reducing the flatness of the substrate 10 and affecting the performance of the semiconductor structure.

[0050] Based on this, the following technical solutions are proposed in the embodiments of the present disclosure:

[0051] An embodiment of the present disclosure provides a semiconductor structure, comprising: a substrate and a conductive via, a first conductive type transistor and a second conductive type transistor located within the substrate; wherein the first conductive type transistor is arranged on both sides of the conductive via along a first direction; the second conductive type transistor is arranged on the other two sides of the conductive via along a second direction; the first direction is perpendicular to the second direction; a first metal layer, located on the substrate, the first metal layer including at least one first metal wire extending along the first direction, the first metal wire being electrically connected to the gate of the first conductive type transistor; a second metal layer, located on the first metal layer, the second metal layer including at least one second metal wire extending along the second direction, the second metal wire being electrically connected to the gate of the second conductive type transistor; wherein the first metal wire and the second metal wire intersect with each other to form a grid structure covering the conductive via.

[0052] The semiconductor structure provided by the embodiment of the present disclosure can improve the situation where the conductive through hole bulges outward after thermal expansion by forming the grid structure on the conductive through hole; in addition, the first metal wire and the second metal wire are respectively connected to the gate of the first conductive type transistor and the second conductive type transistor, thereby serving as an electrical connection.

[0053] The semiconductor structure provided in the embodiments of the present disclosure may be a dynamic random access memory (DRAM), but is not limited thereto, and may also be any semiconductor structure having conductive through-holes.

[0054] The following is a detailed description of the specific embodiments of the present disclosure in conjunction with the accompanying drawings. When describing the embodiments of the present disclosure in detail, for the sake of convenience, the schematic diagrams will not be partially enlarged according to the general scale, and the schematic diagrams are only examples and should not limit the scope of protection of the present disclosure.

[0055] Figure 2a A schematic top view of a semiconductor structure provided in an embodiment of the present disclosure is shown. Figure 2b The semiconductor structure provided by the embodiment of the present disclosure is along Figure 2a A schematic diagram of the cross-sectional structure taken along line AA', Figure 2c The semiconductor structure provided by the embodiment of the present disclosure is along Figure 2a The following is a schematic diagram of the cross-sectional structure taken along the line BB'. Figures 2a-2c The method for manufacturing the semiconductor structure provided by the embodiment of the present disclosure is further described in detail.

[0056] As shown in the figure, the semiconductor structure includes: a substrate 20 and a conductive through-hole 21, a first conductive type transistor 23 and a second conductive type transistor 24 located in the substrate 20; wherein the first conductive type transistor 23 is arranged on both sides of the conductive through-hole 21 along a first direction; the second conductive type transistor 24 is arranged on the other two sides of the conductive through-hole 21 along a second direction; the first direction is perpendicular to the second direction; a first metal layer M1 is located on the substrate 20, the first metal layer M1 includes at least one first metal wire 30 extending along the first direction, and the first metal wire 30 is electrically connected to the gate 233 of the first conductive type transistor 23; a second metal layer M2 is located on the first metal layer M1, the second metal layer M2 includes at least one second metal wire 31 extending along the second direction, and the second metal wire 31 is electrically connected to the gate 241 of the second conductive type transistor 24; wherein the first metal wire 30 and the second metal wire 31 cross each other to form a grid structure 32 covering the conductive through-hole 21.

[0057] The substrate may be a semiconductor substrate, and may include at least one elemental semiconductor material (e.g., a silicon (Si) substrate, a germanium (Ge) substrate), at least one III-V compound semiconductor material, at least one II-VI compound semiconductor material, at least one organic semiconductor material, or other semiconductor materials known in the art. In a specific embodiment, the substrate is a silicon (Si) substrate.

[0058] In an actual process, the thickness of the substrate may be selected to be between 40-70 μm, for example, between 50-60 μm.

[0059] In actual processes, the conductive via 21 includes a through hole (not labeled) that penetrates the substrate 20 and a conductive material located within the through hole (not labeled). The conductive via 21 is used to conduct signals in the semiconductor structure. In one embodiment, the through hole (not labeled) is formed by etching downward from the upper surface of the substrate 20. However, this is not limiting. The through hole (not labeled) can also be formed by etching from the back side of the substrate 20 toward the upper surface of the substrate 20. In some embodiments, the characteristic size of the conductive via 21 is between 2-10 μm and the depth is between 5-100 μm.

[0060] During the preparation process, the conductive via undergoes a cooling process from high temperature to low temperature. During the cooling process, the conductive via and the substrate shrink to different degrees, which will generate stress in the substrate. This stress will affect the migration speed of carriers in the substrate near the conductive via. Therefore, when designing semiconductor structures, technicians usually set a restricted area around the conductive via, and no active devices such as transistors are set in the restricted area. With the center of the conductive via as the center of the circle, the radius of the restricted area is usually between 5-15μm. It is understandable that the existence of the restricted area reduces the utilization rate of the substrate.

[0061] The applicant has discovered through research that the rational arrangement of transistors of different conductivity types within the restricted area can not only improve the utilization of the restricted area, but also improve certain performance characteristics of the semiconductor structure. For example, in one embodiment of the present disclosure, n-type transistors are arranged on both sides of the conductive via along a first direction, with the channel direction of the n-type transistor parallel to the first direction; p-type transistors are arranged on the other two sides of the conductive via along a second direction, with the channel direction of the p-type transistor perpendicular to the second direction. In this way, the mobility of the n-type transistor and the p-type transistor can be simultaneously improved, thereby increasing the conduction speed of the n-type transistor and the p-type transistor. Optionally, the n-type transistor and the p-type transistor are interconnected via the first metal layer and the second metal layer to form an inverter, and the input end of the inverter is electrically connected to the conductive via, that is, the signal is conducted to the input end of the inverter through the conductive via. Due to the high mobility of the n-type transistor and the p-type transistor constituting the inverter, the inverter has a faster conduction speed, which speeds up the transmission of the signal.

[0062] In another embodiment of the present disclosure, n-type transistors are arranged on both sides of the conductive through-hole along a first direction, and the channel direction of the n-type transistor is perpendicular to the first direction; p-type transistors are arranged on the other two sides of the conductive through-hole along a second direction, and the channel direction of the p-type transistor is parallel to the second direction. In this way, the mobility of the n-type transistor and the p-type transistor can be reduced at the same time, the leakage current flowing through the n-type transistor and the p-type transistor can be reduced, and the power consumption of the semiconductor structure can be reduced. Optionally, the n-type transistor and the p-type transistor are interconnected through the first metal layer and the second metal layer to form an inverter, and the input end of the inverter is electrically connected to the conductive through-hole, that is, the signal is conducted to the input end of the inverter through the conductive through-hole. Since the mobility of the n-type transistor and the p-type transistor constituting the inverter is low, the inverter has a smaller leakage current, which reduces the power consumption of the semiconductor structure.

[0063] It should be noted that the selection of the first direction is related to the crystal orientation of the substrate surface. In one embodiment of the present disclosure, the first direction may be parallel to the crystal orientation of the substrate surface.

[0064] See also Figure 2b and Figure 2c The first conductive type transistor 23 includes a gate 233, a gate dielectric layer 234, a first source / drain doped region 231 and a second source / drain doped region 232; the second conductive type transistor 24 includes a gate 241, a gate dielectric layer 242, a first source / drain doped region (not shown) and a second source / drain doped region (not shown).

[0065] In one embodiment, the semiconductor structure further includes an insulating layer 25 located on the substrate 20 and an isolation structure 22 located within the substrate 20 .

[0066] Specifically, the insulating layer is located between the gates of the first conductive type transistor and the second conductive type transistor, and the upper surface of the insulating layer is flush with the upper surface of the gate, and is used to electrically isolate the gates of the first conductive type transistor and the second conductive type transistor. The insulating layer is also used to protect the substrate from oxidation, nitridation, damage or contamination, etc.; the isolation structure is used to electrically isolate device structures located in the substrate and adjacent to each other. The isolation structure can be, for example, a shallow trench isolation structure, and the device structure can be a transistor formed in the substrate, such as the first conductive type transistor and the second conductive type transistor in the embodiment of the present disclosure.

[0067] like Figure 2a As shown, the substrate 20 includes a corner region 33 sandwiched between the first conductivity type transistor 23 and the second conductivity type transistor 24. The distance between the corner region 33 and the conductive via 21 is between 1 micron and 20 microns. In one embodiment, the semiconductor structure further includes passive devices (not shown), which are disposed within the corner region 33 of the substrate 20. The passive devices (not shown) include, but are not limited to, resistors and capacitors. Providing stress-insensitive passive devices (not shown) within the corner region 33 can improve the utilization of the restricted area.

[0068] There are a plurality of first metal lines 30, each of which is evenly arranged along the second direction; and / or there are a plurality of second metal lines 31, each of which is evenly arranged along the first direction. In one embodiment, the spacing between the plurality of first metal lines 30 is between 0.5 microns and 2 microns; and / or the spacing between the plurality of second metal lines 31 is between 0.5 microns and 2 microns.

[0069] See also Figure 2b and 2c The semiconductor structure also includes an intermediate metal layer M0 and conductive plugs V1 and V2; the intermediate metal layer M0 is located between the first metal layer M1 and the substrate 20, and the conductive plugs V1 and V2 include at least one first sub-plug V1 located between the intermediate metal layer M0 and the first metal layer M1, and at least one second sub-plug V2 located between the first metal layer M1 and the second metal layer M2.

[0070] In a specific embodiment, the intermediate metal layer M0 includes a metal pad 28, which is located on the upper surface of the conductive through-hole 21. At least one first metal line 30 is electrically connected to the metal pad 28 through the first sub-plug V1, so that the signal can be transmitted to the first metal line 30 through the conductive through-hole 21.

[0071] In a more specific embodiment, the first metal wire 30 is electrically connected to the gate 233 of the first conductive type transistor 23, including: the first metal wire 30 is electrically connected to the gate 233 of the first conductive type transistor 23 through the first sub-plug V1 and the intermediate metal layer M0, so that the signal can be transmitted to the gate 233 of the first conductive type transistor 23 through the conductive through hole 21.

[0072] In addition, the first metal layer M1 further includes a first wiring structure 29; the second metal line 31 is electrically connected to the gate 241 of the second conductive type transistor 24, including: the second metal line 31 is electrically connected to the gate 241 of the second conductive type transistor 24 through the second sub-plug V2, the first wiring structure 29, the first sub-plug V1, and the intermediate metal layer M0, as shown in FIG. Figure 2c shown.

[0073] Here, at least one first metal line 30 and at least one second metal line 31 may be electrically connected at the intersection through the second sub-plug V2 , so that a signal is conducted to the gate 241 of the second conductive type transistor 24 through the conductive via 21 .

[0074] In one embodiment, the semiconductor structure further includes an annular shielding layer 27, and the annular shielding layer 27 is disposed around the conductive via 21. Figure 2a The function of the annular shielding layer 27 is to reduce the crosstalk effect generated by the conductive via 21 and the metal conductive structure nearby when transmitting signals.

[0075] In a specific embodiment, the number of layers of the annular shielding layer 27 is a single layer, such as Figure 2b and Figure 2cOptionally, the annular shielding layer 27 and the intermediate metal layer M0 are formed simultaneously in the same process step. However, the annular shielding layer 27 is not limited thereto, and the number of layers of the annular shielding layer 27 can be multiple layers.

[0076] In one embodiment, the semiconductor structure further includes a dielectric layer 26 , which covers the intermediate metal layer M0 , the first metal layer M1 , the second metal layer M2 , the annular shielding layer 27 , and the first sub-plug V1 and the second sub-plug V2 .

[0077] It should be noted that the dielectric layer 26 is not a single-layer structure, but is formed by multiple layers of insulating materials in multiple process steps.

[0078] In an embodiment of the present disclosure, the first metal wire and the second metal wire intersect to form a grid structure on the conductive via, which can improve the situation where the conductive via expands and bulges outward due to heat. In addition, in an embodiment of the present disclosure, a first conductivity type transistor and a second conductivity type transistor are rationally arranged around the restricted area of ​​the conductive via. The first conductivity type transistor and the second conductivity type transistor are electrically connected via the first metal wire and the second metal wire to form a device, such as an inverter, which can improve substrate utilization and certain performance of the device, such as conduction speed and power consumption.

[0079] The present disclosure also provides a method for manufacturing a semiconductor structure. Figure 3 As shown, the method includes the following steps:

[0080] Step 301: providing a substrate, wherein the substrate includes a predetermined area, and the predetermined area is used to form a conductive through hole;

[0081] Step 302: forming a first conductivity type transistor and a second conductivity type transistor in the substrate; wherein the first conductivity type transistor is arranged on two sides of the predetermined region along a first direction, and the second conductivity type transistor is arranged on the other two sides of the predetermined region along a second direction, and the first direction is perpendicular to the second direction;

[0082] Step 303: forming a conductive through hole in the predetermined area of ​​the substrate;

[0083] Step 304: forming a first metal layer on the substrate, wherein the first metal layer includes at least one first metal line extending along a first direction, and the first metal line is electrically connected to the gate of the first conductivity type transistor;

[0084] Step 305: Form a second metal layer on the first metal layer, wherein the second metal layer includes at least one second metal wire extending along a second direction, and the second metal wire is electrically connected to the gate of the second conductive type transistor; wherein the first metal wire and the second metal wire intersect with each other to form a grid structure covering the conductive through hole.

[0085] Next, combine Figures 4a-4h The method for manufacturing the semiconductor structure according to the embodiment of the present disclosure is further described in detail.

[0086] First, step 301 is performed to provide a substrate 20, wherein the substrate 20 includes a predetermined area 21a, and the predetermined area 21a is used to form a conductive through hole 21 (see Figure 4d ),like Figure 4a shown.

[0087] The substrate may be a semiconductor substrate, and may include at least one elemental semiconductor material (e.g., a silicon (Si) substrate, a germanium (Ge) substrate), at least one III-V compound semiconductor material, at least one II-VI compound semiconductor material, at least one organic semiconductor material, or other semiconductor materials known in the art. In some embodiments, in a specific embodiment, the substrate is a silicon (Si) substrate.

[0088] In an actual process, the thickness of the substrate may be selected to be between 40-70 μm, for example, between 50-60 μm.

[0089] In one embodiment, the predetermined area 21 a is a cylindrical area, and the diameter of the cylindrical area is between 2 μm and 10 μm.

[0090] Next, step 302 is performed to form a first conductive type transistor 23 and a second conductive type transistor 24 in the substrate 20; wherein the first conductive type transistor 23 is arranged on both sides of the predetermined area 21a along a first direction, and the second conductive type transistor 24 is arranged on the other two sides of the predetermined area 21a along a second direction, and the first direction is perpendicular to the second direction. Figure 4b shown.

[0091] The first conductive type transistor 23 may be, for example, an n-type transistor, and the second conductive type transistor 24 may be, for example, a p-type transistor.

[0092] In the subsequent process, a conductive via will be formed in the preset area. During the preparation process, the conductive via will undergo a cooling process from high temperature to low temperature. During the cooling process, the conductive via and the substrate shrink to different degrees, which will generate stress in the substrate. This stress will affect the migration speed of carriers in the substrate near the conductive via. Therefore, when designing semiconductor structures, technicians usually set a restricted area around the conductive via, and no active devices such as transistors are set in the restricted area. With the center of the conductive via as the center of the circle, the radius of the restricted area is usually between 5-15μm. It can be understood that the existence of the restricted area reduces the utilization rate of the substrate.

[0093] The applicant has discovered through research that the rational arrangement of transistors of different conductivity types within the restricted area can not only improve the utilization of the restricted area, but also improve certain performance characteristics of the semiconductor structure. For example, in one embodiment of the present disclosure, n-type transistors are arranged on both sides of the conductive via along a first direction, with the channel direction of the n-type transistor parallel to the first direction; p-type transistors are arranged on the other two sides of the conductive via along a second direction, with the channel direction of the p-type transistor perpendicular to the second direction. In this way, the mobility of the n-type transistor and the p-type transistor can be simultaneously improved, thereby increasing the conduction speed of the n-type transistor and the p-type transistor.

[0094] In another embodiment of the present disclosure, n-type transistors are arranged on both sides of the conductive via along a first direction, with the channel direction of the n-type transistor perpendicular to the first direction; p-type transistors are arranged on the other two sides of the conductive via along a second direction, with the channel direction of the p-type transistor parallel to the second direction. In this way, the mobility of the n-type transistor and the p-type transistor can be reduced simultaneously, reducing the leakage current flowing through the n-type transistor and the p-type transistor, and reducing the power consumption of the semiconductor structure.

[0095] It should be noted that the selection of the first direction is related to the crystal orientation of the substrate surface. In one embodiment of the present disclosure, the first direction may be parallel to the crystal orientation of the substrate surface.

[0096] Specifically, the first conductive type transistor 23 includes a gate 233, a gate dielectric layer 234, a first source / drain doping region 231 and a second source / drain doping region 232. Figure 4b As shown; the second conductive type transistor 24 includes a gate 241, a gate dielectric layer 242, a first source / drain doped region (not shown) and a second source / drain doped region (not shown), as Figure 2c shown.

[0097] See again Figure 4bIn one embodiment, the method further includes: forming an isolation structure 22 within the substrate 20. In a specific embodiment, the isolation structure 22 is formed before forming the first conductivity type transistor 23 and the second conductivity type transistor 24. The isolation structure 22 is used to electrically isolate device structures located within the substrate 20 and adjacent to each other. The isolation structure 22 may be, for example, a shallow trench isolation structure. The device structure may be a transistor formed within the substrate 20, such as the first conductivity type transistor 23 and the second conductivity type transistor 24 in the embodiment of the present disclosure.

[0098] like Figure 4c As shown, after forming the first conductive type transistor 23 and the second conductive type transistor 24 in the substrate 20 , the method further includes: forming an insulating layer 25 on the substrate 20 .

[0099] Specifically, the insulating layer is formed between the gates of the first conductive type transistor and the second conductive type transistor, and the upper surface of the insulating layer is flush with the upper surface of the gate, and is used to electrically isolate the gates of the first conductive type transistor and the second conductive type transistor. The insulating layer is also used to protect the substrate from oxidation, nitridation, damage or contamination, etc.

[0100] In one embodiment, the substrate 20 further includes a corner region 33 sandwiched between the first conductive type transistor 23 and the second conductive type transistor 24, and the corner region 33 is adjacent to the conductive via 21 (see FIG. Figure 4d ) is between 1 micron and 20 microns, as shown in FIG2 . In one embodiment, the semiconductor structure further includes passive components (not shown) disposed within the corner region 33 of the substrate 20. The passive components (not shown) include, but are not limited to, resistors and capacitors. Placing stress-insensitive passive components (not shown) within the corner region 33 can improve utilization of the restricted area.

[0101] Next, step 303 is performed to form a conductive through hole 21 in the predetermined area 21a of the substrate 20. Figure 4d shown.

[0102] Specifically, the method for forming the conductive via 21 includes: forming a via in the substrate 20, the via penetrating the substrate 20 and the insulating layer 25; and forming a conductive material in the via to form the conductive via 21. The conductive via 21 is used to conduct signals in the semiconductor structure. The conductive material may be copper. In some embodiments, the conductive via 21 has a characteristic size between 2 and 10 μm and a depth between 5 and 100 μm.

[0103] More specifically, the conductive via further comprises an insulating film formed on the inner wall of the via, and a barrier layer formed between the insulating film and the conductive material. The insulating film may be made of an oxide, such as silicon oxide, and the thickness of the insulating film may be between 100 and 200 nm. The barrier layer can be a metal, such as tantalum, and the thickness of the barrier layer is between between.

[0104] Next, step 304 is performed to form a first metal layer M1 on the substrate 20. The first metal layer M1 includes at least one first metal line 30 extending along a first direction. The first metal line 30 is electrically connected to the gate 233 of the first conductive type transistor 23. Figure 4g shown.

[0105] Specifically, forming a first metal layer M1 on the substrate 20 includes:

[0106] A dielectric layer 26 is formed on the substrate, the dielectric layer 26 is patterned, and a first metal layer M1 is formed in the patterned dielectric layer.

[0107] In one embodiment, there are a plurality of first metal lines 30 , and the plurality of first metal lines 30 are evenly arranged along the second direction. In a specific embodiment, the spacing between the plurality of first metal lines 30 is between 0.5 microns and 2 microns.

[0108] In one embodiment, the semiconductor structure further includes an intermediate metal layer M0 and a first sub-plug V1; before forming the first metal layer M1 on the substrate 20, the steps include:

[0109] An intermediate metal layer M0 is formed on the substrate 20, and the intermediate metal layer M0 is electrically connected to the gates 233 and 241 of the first conductive type transistor 23 and the second conductive type transistor 24. Figure 4e As shown;

[0110] A first sub-plug V1 is formed on the middle metal layer M0. The first sub-plug V1 is used to electrically connect the first metal layer M1 and the middle metal layer M0. Figure 4f .

[0111] In a specific embodiment, forming the intermediate metal layer M0 and the first sub-plug V1 includes:

[0112] forming a dielectric layer on the substrate, patterning the dielectric layer, and forming an intermediate metal layer M0 in the patterned dielectric layer;

[0113] A dielectric layer covering the intermediate metal layer M0 is formed, a through hole is formed in the dielectric layer, and the first sub-plug V1 is formed in the through hole.

[0114] In one embodiment, the intermediate metal layer M0 includes a metal pad 28, which is located on the upper surface of the conductive via 21. At least one first metal line 30 is electrically connected to the metal pad 28 through the first sub-plug V1, so that the signal can be transmitted to the first metal line 30 through the conductive via 21.

[0115] In a specific embodiment, the first metal wire 30 is electrically connected to the gate 233 of the first conductive type transistor 23, including: the first metal wire 30 is electrically connected to the gate 233 of the first conductive type transistor 23 through the first sub-plug V1 and the intermediate metal layer M0, so that the signal can be transmitted to the gate 233 of the first conductive type transistor 23 through the conductive through hole 21.

[0116] In one embodiment, the first metal layer M1 further includes a first wiring structure 29, and the first wiring structure 29 is electrically connected to the middle metal layer M0 through the first sub-plug V1. Figure 2c shown.

[0117] See again Figure 4e In one embodiment, the method further includes: forming an annular shielding layer 27 on the substrate 20, wherein the annular shielding layer 27 is disposed around the conductive via 21. The function of the annular shielding layer 27 is to reduce the crosstalk effect generated by the conductive via 21 and the metal conductive structure nearby when transmitting signals. In a specific embodiment, the annular shielding layer 27 has a single layer, and the annular shielding layer 27 and the intermediate metal layer M0 are formed simultaneously in the same process step. However, the present invention is not limited thereto, and the annular shielding layer 27 may have multiple layers.

[0118] Finally, step 305 is performed to form a second metal layer M2 on the first metal layer M1. The second metal layer M2 includes at least one second metal line 31 extending along the second direction. The second metal line 31 is electrically connected to the gate 241 of the second conductive type transistor 24. The first metal line 30 and the second metal line 31 intersect with each other to form a grid structure 32 covering the conductive through hole 21. Figures 2a-2c shown.

[0119] Specifically, forming the second metal layer M2 on the first metal layer M1 includes:

[0120] A dielectric layer covering the first metal layer is formed, the dielectric layer is patterned, and a second metal layer M2 is formed in the patterned dielectric layer.

[0121] In one embodiment, there are a plurality of second metal lines 31 , and the plurality of second metal lines 31 are evenly arranged along the first direction. In a specific embodiment, the spacing between the plurality of second metal lines 31 is between 0.5 microns and 2 microns.

[0122] In one embodiment, the semiconductor structure further includes a second sub-plug V2; before forming the second metal layer M2 on the first metal layer M1, the method includes: forming the second sub-plug V2 on the first metal layer M1, wherein the second sub-plug V2 is used to electrically connect the first metal layer M1 and the second metal layer M2. Figure 4h shown.

[0123] Specifically, forming the second sub-plug V2 on the first metal layer M1 includes:

[0124] A dielectric layer is formed on the first metal layer M1 , a through hole is formed in the dielectric layer, and the second sub-plug V2 is formed in the through hole.

[0125] In one embodiment, the second metal wire 31 is electrically connected to the gate 241 of the second conductive type transistor 24, including: the second metal wire 31 is electrically connected to the gate 241 of the second conductive type transistor 24 through the second sub-plug V2, the first wiring structure 29, the first sub-plug V1, and the intermediate metal layer M0.

[0126] In a specific embodiment, at least one first metal line 30 and at least one second metal line 31 are electrically connected at the intersection through the second sub-plug V2 , so that the signal is conducted to the gate 241 of the second conductive type transistor 24 through the conductive via 21 .

[0127] It should be noted that those skilled in the art can change the order of the above steps without departing from the scope of protection of the present disclosure. The above is only an optional embodiment of the present disclosure and is not intended to limit the scope of protection of the present disclosure. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present disclosure should be included in the scope of protection of the present disclosure.

Claims

1. A semiconductor structure, characterized in that include: A substrate and a conductive via, a first conductive type transistor, and a second conductive type transistor located within the substrate; wherein the first conductive type transistor is disposed on two sides of the conductive via along a first direction; and the second conductive type transistor is disposed on the other two sides of the conductive via along a second direction; and the first direction is perpendicular to the second direction. a first metal layer located on the substrate, the first metal layer comprising at least one first metal line extending along a first direction, the first metal line being electrically connected to a gate of the first conductive type transistor; a second metal layer located on the first metal layer, the second metal layer comprising at least one second metal line extending along a second direction, the second metal line being electrically connected to a gate of the second conductive type transistor; The first metal wires and the second metal wires cross each other to form a grid structure covering the conductive through-holes.

2. The semiconductor structure according to claim 1, wherein: There are a plurality of first metal wires, and the plurality of first metal wires are evenly arranged along the second direction; and / or there are a plurality of second metal wires, and the plurality of second metal wires are evenly arranged along the first direction.

3. The semiconductor structure according to claim 2, wherein: The spacing between the plurality of first metal lines is between 0.5 micrometers and 2 micrometers; and / or the spacing between the plurality of second metal lines is between 0.5 micrometers and 2 micrometers.

4. The semiconductor structure according to claim 1, wherein: The first conductive type transistor is an n-type transistor, and the second conductive type transistor is a p-type transistor.

5. The semiconductor structure according to claim 4, wherein: A channel direction of the first conductive type transistor is parallel to the first direction; a channel direction of the second conductive type transistor is perpendicular to the second direction. The semiconductor structure according to claim 4 , wherein: A channel direction of the first conductive type transistor is perpendicular to the first direction; a channel direction of the second conductive type transistor is parallel to the second direction.

7. The semiconductor structure according to claim 1, wherein: The semiconductor structure also includes an intermediate metal layer and a conductive plug; the intermediate metal layer is located between the first metal layer and the substrate, and the conductive plug includes at least one first sub-plug located between the intermediate metal layer and the first metal layer, and at least one second sub-plug located between the first metal layer and the second metal layer.

8. The semiconductor structure according to claim 7, wherein: The first metal line is electrically connected to the gate of the first conductive type transistor, including: the first metal line is electrically connected to the gate of the first conductive type transistor through the first sub-plug and the intermediate metal layer.

9. The semiconductor structure according to claim 7, wherein: The first metal layer also includes a first wiring structure; the second metal wire is electrically connected to the gate of the second conductive type transistor, including: the second metal wire is electrically connected to the gate of the second conductive type transistor through the second sub-plug, the first wiring structure, the first sub-plug, and the intermediate metal layer.

10. The semiconductor structure according to claim 7, wherein: At least one of the first metal lines and at least one of the second metal lines are electrically connected at an intersection through the second sub-plug.

11. The semiconductor structure according to claim 7, wherein: The intermediate metal layer includes a metal pad, and the metal pad is located on the upper surface of the conductive through hole; At least one first metal line is electrically connected to the metal pad through the first sub-plug.

12. The semiconductor structure according to claim 1, wherein: The substrate includes a corner region sandwiched between the first conductive type transistor and the second conductive type transistor, and a distance between the corner region and the conductive via is between 1 micrometer and 20 micrometers.

13. The semiconductor structure according to claim 12, wherein: The semiconductor structure further includes a passive device, which is disposed in the corner region of the substrate.

14. A method for preparing a semiconductor structure, characterized in that: include: Providing a substrate, the substrate comprising a predetermined area, the predetermined area being used to form a conductive through hole; forming a first conductive type transistor and a second conductive type transistor in the substrate; wherein the first conductive type transistor is arranged on two sides of the predetermined area along a first direction, and the second conductive type transistor is arranged on the other two sides of the predetermined area along a second direction, wherein the first direction is perpendicular to the second direction; forming a conductive through hole in the predetermined area of ​​the substrate; forming a first metal layer on the substrate, wherein the first metal layer includes at least one first metal line extending along a first direction, and the first metal line is electrically connected to the gate of the first conductive type transistor; forming a second metal layer on the first metal layer, wherein the second metal layer includes at least one second metal line extending along a second direction, and the second metal line is electrically connected to the gate of the second conductive type transistor; The first metal wires and the second metal wires cross each other to form a grid structure covering the conductive through-holes.

15. The preparation method according to claim 14, characterized in that The semiconductor structure further includes an intermediate metal layer and a first sub-plug; before forming the first metal layer on the substrate, the method includes: forming an intermediate metal layer on the substrate, wherein the intermediate metal layer is electrically connected to the gates of the first conductive type transistor and the second conductive type transistor; A first sub-plug is formed on the middle metal layer, where the first sub-plug is used to electrically connect the first metal layer and the middle metal layer.

16. The preparation method according to claim 14, characterized in that The semiconductor structure further includes a second sub-plug; before forming the second metal layer on the first metal layer, the method includes: The second sub-plug is formed on the first metal layer, and the second sub-plug is used to electrically connect the first metal layer and the second metal layer.

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