A schottky barrier diode with a silicon carbide non-uniform mixed p+ structure and a manufacturing method thereof

Abstract

The application provides a silicon carbide non-uniform mixed P+ structure Schottky junction barrier diode and a manufacturing method thereof, which comprises a metallized cathode, an N+ substrate and an epitaxial region arranged in sequence; a plurality of P+ ring regions and a plurality of P+ regions are arranged on the upper layer of the epitaxial region, the upper end of the plurality of P+ regions is covered by a metallized anode, the top of the plurality of P+ ring regions and the part of the top of the P+ regions adjacent to the P+ ring regions are covered by a silicon oxide layer, and the upper end surface of the silicon oxide layer is covered by a polyimide layer. The application improves the distribution of the current in the device by adopting a non-uniform mixed P+ ion implantation region structure in the P+ region of the device, improves the surge resistance of the device, reduces the reverse leakage current without reducing the forward conduction resistance, and makes more current pass through the peripheral region of the device with strong heat dissipation capacity and less current pass through the middle region with poor heat dissipation capacity when the device is in forward conduction, so that the device is prevented from being damaged due to the heat concentration in the region with poor heat dissipation capacity.

Description

TECHNICAL FIELD

[0001] The application relates to a silicon carbide Schottky junction barrier diode with a non-uniform mixed P+ structure and a manufacturing method thereof. BACKGROUND

[0002] In a silicon carbide Schottky junction barrier diode device, the performance of the diode depends largely on the layout design. In the mainstream devices of the current silicon carbide Schottky junction barrier diode device, the P+ injection region is designed as a single strip or dot, and the area of the P+ injection region is not fully utilized, resulting in waste of internal space of the device.

[0003] In order to improve the utilization rate of the internal space of the device, many patents change the cell structure of the P+ injection region. For example, a silicon carbide junction barrier Schottky diode suitable for a high-temperature environment disclosed in CN114284343A forms a P+ region through a square injection region and a strip-shaped injection region, the strip-shaped injection region is uniformly distributed in the P+ region, and the direction injection region is also uniformly distributed between the strip-shaped injection regions but does not contact each other. Although the area utilization rate of the P+ region is increased and the contact area of the Schottky is increased through the method, the P+ region is an area for preventing current from passing through. The current of each region is the same in the P+ injection region with the same structure, but the problem in the central region of the P+ region is not easy to dissipate. When the current is large, the temperature of the central region of the P+ region increases rapidly, which leads to a sharp rise in the temperature of the device and thus damages the device, thereby limiting the reliability of the device. SUMMARY

[0004] To solve the above technical problems, the application provides a silicon carbide Schottky junction barrier diode with a non-uniform mixed P+ structure and a manufacturing method thereof.

[0005] The application is implemented through the following technical solutions.

[0006] The application provides a silicon carbide Schottky junction barrier diode with a non-uniform mixed P+ structure and a manufacturing method thereof, which comprises a metallized cathode, an N+ substrate and an epitaxial region arranged in sequence; a plurality of P+ ring regions and a plurality of P+ regions are arranged on the upper layer of the epitaxial region, the upper ends of the plurality of P+ regions are covered by a metallized anode, the top of the plurality of P+ ring regions and the part of the top of the plurality of P+ regions adjacent to the plurality of P+ ring regions are covered by a silicon oxide layer, and the upper end surface of the silicon oxide layer is covered by a polyimide layer.

[0007] The plurality of P+ regions comprises a first strip-shaped cell region, a dot-shaped cell region and a second strip-shaped cell region, the first strip-shaped cell region is arranged at the center of the plurality of P+ regions, the dot-shaped cell region is arranged on the corners of the plurality of P+ regions, and the second strip-shaped cell region is arranged at the edges of the plurality of P+ regions.

[0008] The plurality of P+ regions, the first strip-shaped cell region, the dot-shaped cell region, and the second strip-shaped cell region are collectively square-shaped.

[0009] The width and the pitch of the cells in the first strip-shaped cell region are greater than the width and the pitch of the cells in the second strip-shaped cell region.

[0010] The cells in the dot-shaped cell region are square-shaped.

[0011] A manufacturing method of a Schottky barrier diode with a silicon carbide non-uniform mixed P+ structure, comprising the following steps:

[0012] An N+ substrate is manufactured, and an epitaxial region is grown on the N+ substrate;

[0013] A sacrificial oxide layer is grown on the epitaxial region, and then the sacrificial oxide layer is removed and cleaned, and a field oxide layer is grown by thermal oxidation;

[0014] Photolithography is performed on the field oxide layer to process P+ region and P+ ring region implantation windows;

[0015] Aluminum is implanted in the P+ region and the P+ ring region, and then annealing and activation are performed to form a plurality of P+ regions and a P+ ring region;

[0016] After the surface field oxide layer is removed, a sputtered Schottky metal is formed to form a metallized anode, and then Schottky contact region photolithography and etching are performed;

[0017] Silicon dioxide is grown on the P+ ring region and the surface of the metallized anode, silicon dioxide passivation layer photolithography is performed, and then etching and gel removal are performed to form a silicon oxide layer;

[0018] Top polyimide layer passivation layer photolithography is performed;

[0019] A back thinning process is performed, and back metallization is performed by sputtering titanium, nickel, and silver in sequence.

[0020] The N+ substrate is made of 4H SiC, and an epitaxial region is grown on one side of the N+ substrate, the thickness of the epitaxial region is 11 µm, and the doping concentration is 7.0E15 cm -3 .

[0021] During the aluminum implantation process of the P+ ring region, the implantation is performed in multiple times at a temperature of 773℃, and the ion concentration and the implantation energy are sequentially reduced.

[0022] The ion concentration and the implantation energy are 7E14 cm - 2 - 8. 5E14 cm - 2 , 4.5E14 cm - 2 ~5. 5E14 cm -2and 150~250KeV, 3.2E14cm - 2 ~4.2E14cm -2 and 80~140KeV, 1.8E14cm -2 ~2.8E14cm -2 and 30~70KeV, total doping concentration is 4e19cm -3 , and the junction is 0.5-0.6μm.

[0023] The metallized anode is in turn Ti with thickness of 1000Å, TiN with thickness of 100Å, and AlCu with thickness of 4μm from bottom to top.

[0024] The beneficial effect of the present application is that the current distribution in the device is improved by using the non-uniform mixed P+ ion implantation region structure in the P+ region of the device, the surge resistance of the device is improved, the reverse leakage current is reduced without reducing the forward conduction resistance; when the device is in forward conduction, more current passes through the peripheral area of the device with strong heat dissipation capacity, and less current passes through the middle area with poor heat dissipation capacity, so as to avoid damage to the device caused by heat concentration in the area with poor heat dissipation capacity. BRIEF DESCRIPTION OF DRAWINGS

[0025] Figure 1 is a structural schematic diagram of the present application;

[0026] Figure 2 is a P+ region ion implantation structure schematic diagram of the present application;

[0027] Figure 3 is a P+ region middle ion implantation structure schematic diagram of the present application;

[0028] Figure 4 is a P+ region four-corner ion implantation structure schematic diagram of the present application;

[0029] Figure 5 is a P+ region four-side ion implantation structure schematic diagram of the present application;

[0030] Figure 6 is a diode heating schematic diagram of the present application;

[0031] In the figure: 1-N+ substrate, 2-N- epitaxial region, 3-P+ ring region, 4-P+ region, 41-first strip-shaped cell region, 42-point-shaped cell region, 43-second strip-shaped cell region, 5-metallized anode, 6-silicon oxide layer, 7-polyimide layer, 8-metallized cathode. DETAILED DESCRIPTION

[0032] The technical solutions of the present application are further described below, but the scope of protection is not limited to the description.

[0033] Embodiment 1: A Schottky junction barrier diode with a silicon carbide non-uniform mixed P+ structure and a method for manufacturing the same, comprising a metallized cathode 8, an N+ substrate 1, and an epitaxial region 2 arranged in sequence; the substrate material is 4H SiC, the thickness is 350±25μm, the substrate resistivity is (0.012-0.025) Ω / cm, the N-type epitaxial region thickness is 11µm, the doping concentration is 8.5E15 / cm3, a plurality of P+ ring regions 3 and a plurality of P+ regions 4 are arranged on the upper layer of the epitaxial region 2, the upper end of the plurality of P+ regions 4 is covered by a metallized anode 5, the top of the plurality of P+ ring regions 3 and the part of the top of the P+ region 4 adjacent to the P+ ring region 3 are covered by a silicon oxide layer 6, and the upper end surface of the silicon oxide layer 6 is covered by a polyimide layer 7.

[0034] The P+ region 4 has a size of 3.8mm*3.8mm, including a first strip-shaped cell region 41 with a cell ratio of 2:3(μm), a cell area of 2.52mm*2.52mm, a dot-shaped cell region 42 with a cell area of 1(μm2), a cell region size of 0.63mm*0.63mm, and a second strip-shaped cell region 43 with a cell region ratio of 2:5(μm) and a cell region size of 0.63mm*2.52mm; the first strip-shaped cell region 41 is arranged at the center of the P+ region 4, the dot-shaped cell region 42 is arranged at the corner of the P+ region 4, and the second strip-shaped cell region 43 is arranged at the edge of the P+ region 4.

[0035] The P+ region 4, the first strip-shaped cell region 41, the dot-shaped cell region 42, and the second strip-shaped cell region 43 are collectively square-shaped.

[0036] The width and spacing of the cells in the first strip-shaped cell region 41 are greater than the width and spacing of the cells in the second strip-shaped cell region 43.

[0037] The cells in the dot-shaped cell region 42 are square-shaped.

[0038] The above-mentioned Schottky junction barrier diode with a silicon carbide non-uniform mixed P+ structure is manufactured by the following steps:

[0039] 1. An N+ substrate 1 with a thickness of 350±25μm and a substrate resistivity of 0.012-0.025Ω / cm is made of 4H SiC, and an epitaxial region 2 with a thickness of 11µm and a doping concentration of 8.5E15 / cm 3 is grown on the N+ substrate 1;

[0040] 2. A sacrificial oxide layer is grown on the epitaxial region 2, and then the sacrificial oxide layer is removed and cleaned, and a field oxide layer with a thickness of 1.5μm is grown by thermal oxidation;

[0041] 3. The field oxide layer is etched at the upper end of the epitaxial region 2 corresponding to the P+ region and the P+ ring region to form a P+ region and a P+ ring region injection window;

[0042] 4. The P+ region and the P+ ring region are implanted with aluminum, and the ion concentration and the implantation energy are 7E14 cm -2 and 250 KeV, 4.5E14 cm -2 and 150 KeV, 3.2E14 cm -2 and 80 KeV, 1.8E14 cm - and 30 KeV, respectively. Then, the P region and the P+ ring region are annealed and activated to form a P+ region 4 and a P+ ring region 3.

[0043] 5. After removing the surface field oxide layer, Ti with a thickness of 1000 Å, TiN with a thickness of 100 Å, and AlCu with a thickness of 4 μm are sputtered to form a metallized anode 5. Then, the Schottky metal above the P+ ring region 3 is etched.

[0044] 6. A silicon dioxide passivation layer is grown on the surface of the P+ ring region 3 and the metallized anode 5 by PECVD, and the growth thickness is 1.2 μm. The silicon dioxide passivation layer is etched by dry etching to remove the silicon dioxide passivation layer.

[0045] 7. A polyimide passivation layer is coated, and the thickness is about 4 μm.

[0046] 8. A back thinning process is performed, and the back is metallized. Titanium, nickel, and silver are sputtered in sequence, and the thicknesses are 0.2±0.01 um / 0.3±0.1 um / 2.0±0.1 um, respectively.

[0047] Embodiment 2, a Schottky junction barrier diode with a non-uniform mixed P+ structure and a manufacturing method thereof, includes a metallized cathode 8, an N+ substrate 1, and an epitaxial region 2 arranged in sequence. The substrate material is 4H SiC, the thickness is 350±25 μm, the substrate resistivity is (0.012-0.025) Ω / cm, the N-type epitaxial region thickness is 11 µm, the doping concentration is 8.5E15 / cm3, a plurality of P+ ring regions 3 and a plurality of P+ regions 4 are arranged on the upper layer of the epitaxial region 2, the upper end of the plurality of P+ regions 4 is covered by the metallized anode 5, the top of the plurality of P+ ring regions 3 and the part of the top of the P+ region 4 adjacent to the P+ ring region 3 are covered by the silicon oxide layer 6, and the upper end surface of the silicon oxide layer 6 is covered by the polyimide layer 7.

[0048] The P+ region 4 has a size of 3.8 mm*3.8 mm, and includes a first strip-shaped cell region 41, a cell ratio of 2:3 (μm), a cell area of 2.52 mm*2.52 mm, a dot-shaped cell region 42, a cell area of 1 (μm2), a cell region size of 0.63 mm*0.63 mm, and a second strip-shaped cell region 43, a cell region ratio of 2:5 (μm), a cell region size of 0.63 mm*2.52 mm. The first strip-shaped cell region 41 is arranged at the center of the P+ region 4, the dot-shaped cell region 42 is arranged at the corner of the P+ region 4, and the second strip-shaped cell region 43 is arranged at the edge of the P+ region 4.

[0049] The P+ region 4, the first strip-shaped cell region 41, the dot-shaped cell region 42, and the second strip-shaped cell region 43 are collectively square-shaped.

[0050] The width and the pitch of the cells in the first strip-shaped cell region 41 are greater than the width and the pitch of the cells in the second strip-shaped cell region 43.

[0051] The cells in the dot-shaped cell region 42 are square-shaped.

[0052] The above-mentioned silicon carbide non-uniform mixed P+ structure Schottky barrier diode is manufactured by the following steps:

[0053] 1. An N+ substrate 1 with a thickness of 350±25 μm and a substrate resistivity of 0.012-0.025 Ω / cm is prepared from 4H SiC, and an epitaxial region 2 with a thickness of 11 μm and a doping concentration of 8.5E15 / cm 3 is grown on the N+ substrate 1;

[0054] 2. A sacrificial oxide layer is grown on the epitaxial region 2, and then the sacrificial oxide layer is removed and cleaned, and a field oxide layer with a thickness of 1.5 μm is grown by thermal oxidation;

[0055] 3. The field oxide layer is subjected to oxide lithography at the end face of the epitaxial region 2 corresponding to the P+ region and the P+ ring region, and a P+ region and a P+ ring region implantation window is processed;

[0056] 4. P+ region and P+ ring region aluminum implantation is performed, and the ion concentration and the implantation energy are 8.0E14 cm -2 and 350 KeV, 5.2E14 cm -2 and 220 KeV, 4.0E14 cm -2 and 120 KeV, 2.5E14 cm -2 and 55 KeV, respectively, and then P region and P+ ring region annealing activation is performed to form a P+ region 4 and a P+ ring region 3;

[0057] 5. After removing the surface field oxide layer, sputtering Ti with a thickness of 1000 Å, TiN with a thickness of 100 Å, and AlCu with a thickness of 4 μm to form the metallized anode 5, and then removing the Schottky metal photoetching above the P+ ring region 3;

[0058] 6. PECVD is used to grow a silicon dioxide passivation layer on the surface of the P+ ring region 3 and the metallized anode 5, with a thickness of 1.2 μm, and then performing silicon dioxide passivation layer photoetching and dry etching to remove the silicon dioxide, and the silicon oxide layer 6 passivation layer;

[0059] 7. Polyimide passivation layer coating is performed, with a thickness of about 4 μm;

[0060] 8. Back thinning process is performed, and back metallization is performed, with titanium, nickel, and silver being sputtered in sequence, with thicknesses of 0.2±0.01 um, 0.3±0.1 um, and 2.0±0.1 um, respectively.

[0061] Embodiment 3, a Schottky junction barrier diode with a silicon carbide non-uniform mixed P+ structure and a manufacturing method thereof, includes a metallized cathode 8, an N+ substrate 1, and an epitaxial region 2 arranged in sequence; the substrate material is 4H SiC, with a thickness of 350±25 μm and a substrate resistivity of (0.025) Ω / cm; the N-type epitaxial region has a thickness of 11 µm and a doping concentration of 8.5E15 / cm3; a plurality of P+ ring regions 3 and a plurality of P+ regions 4 are arranged on the upper layer of the epitaxial region 2; the upper end of the plurality of P+ regions 4 is covered by the metallized anode 5; the top of the plurality of P+ ring regions 3 and the portion of the top of the P+ regions 4 adjacent to the P+ ring regions 3 are covered by the silicon oxide layer 6; and the upper end surface of the silicon oxide layer 6 is covered by the polyimide layer 7.

[0062] The P+ region 4 has a size of 3.8 mm*3.8 mm, including a first strip-shaped cell region 41 with a cell ratio of 2:3 (μm), a cell area of 2.52 mm*2.52 mm, a dot-shaped cell region 42 with a cell area of 1 (μm2) and a cell region size of 0.63 mm*0.63 mm, and a second strip-shaped cell region 43 with a cell region ratio of 2:5 (μm) and a cell region size of 0.63 mm*2.52 mm; the first strip-shaped cell region 41 is arranged at the center of the P+ region 4, the dot-shaped cell region 42 is arranged at the corners of the P+ region 4, and the second strip-shaped cell region 43 is arranged at the edges of the P+ region 4.

[0063] The P+ region 4, the first strip-shaped cell region 41, the dot-shaped cell region 42, and the second strip-shaped cell region 43 are collectively square-shaped.

[0064] The width and spacing of the cells in the first strip-shaped cell region 41 are both greater than the width and spacing of the cells in the second strip-shaped cell region 43.

[0065] The cells in the point-like cell region 42 are square.

[0066] The Schottky barrier diode of the silicon carbide non-uniform mixed P+ structure is manufactured through the following steps:

[0067] 1. An N+ substrate 1 with a thickness of 350±25 μm and a substrate resistivity of 0.012-0.025 Ω / cm is made of 4H SiC, and an epitaxial region 2 with a thickness of 11 μm and a doping concentration of 8.5E15 / cm 3 is grown on the N+ substrate 1;

[0068] 2. A sacrificial oxide layer is grown on the epitaxial region 2, and then the sacrificial oxide layer is removed and cleaned, and a field oxide layer with a thickness of 1.5 μm is grown by thermal oxidation;

[0069] 3. The field oxide layer is subjected to photoetching at the end surface of the epitaxial region 2 corresponding to the P+ region and the P+ ring region, and P+ region and P+ ring region implantation windows are processed;

[0070] 4. P+ region and P+ ring region aluminum implantation is performed, and the ion concentration and implantation energy are 8.5E14 cm - 2 and 2380 KeV, 5.5E14 cm -2 and 250 KeV, 4.2E14 cm -2 and 140 KeV, 2.8E14 cm -2 and 70 KeV, respectively, and then P region and P+ ring region annealing activation is performed to form a P+ region 4 and a P+ ring region 3;

[0071] 5. After removing the surface field oxide layer, Ti with a thickness of 1000 Å, TiN with a thickness of 100 Å, and AlCu with a thickness of 4 μm are sputtered and grown to form a metallized anode 5, and then the Schottky metal above the P+ ring region 3 is photoetched and removed;

[0072] 6. A silicon dioxide passivation layer with a growth thickness of 1.2 μm is grown on the P+ ring region 3 and the metallized anode 5 surface by PECVD, and the silicon dioxide passivation layer is photoetched and dry etched to remove the silicon dioxide, and the silicon oxide layer 6 passivation layer is formed;

[0073] 7. A polyimide passivation layer with a thickness of about 4 μm is coated;

[0074] 8. A back thinning process is performed, and back metallization is performed, and titanium, nickel, and silver are sputtered in sequence, with thicknesses of 0.2±0.01 um / 0.3±0.1 um / 2.0±0.1 um, respectively.

[0075] It is found through simulation that, for example, Figure 6As shown, the four corners of the device dissipate heat best, thus flowing greater current, while the four sides, which are higher in temperature than the four corners, thus flow slightly less current, and the center of the device, which dissipates heat worst, thus has the highest temperature and lowest current.

[0076] The three different Schottky regions of the cell designed in the application are respectively located in the center of the device, the four corners of the device and the four sides. The width and pitch of the strip-shaped cell in the central region are the largest, the width and pitch of the strip-shaped cell in the edge are smaller, and the dot-shaped cell in the four corners is the densest. The element thermal conditions are met, the temperature distribution is matched to the greatest extent, and the device obtains better characteristics.

Claims

1. A Schottky junction barrier diode with a non-uniformly mixed P+ structure in silicon carbide, comprising a metallized cathode (8), an N+ substrate (1), and an epitaxial region (2) stacked sequentially, characterized in that: Multiple P+ring regions (3) and multiple P+ regions (4) are disposed on the upper layer of the epitaxial region (2). The upper ends of the multiple P+ regions (4) are covered by a metallized anode (5). The top of the multiple P+ring regions (3) and the top of the multiple P+ regions (4) adjacent to the multiple P+ring regions (3) are covered by a silicon oxide layer (6). The upper end face of the silicon oxide layer (6) is covered by a polyimide layer (7). The plurality of P+ regions (4) include a first strip cell region (41), a dot cell region (42), and a second strip cell region (43). The first strip cell region (41) is located at the center of the plurality of P+ regions (4), the dot cell region (42) is located at the corner of the plurality of P+ regions (4), and the second strip cell region (43) is located at the edge of the plurality of P+ regions (4). The multiple P+ regions (4), the first strip of cell region (41), the dotted cell region (42), and the second strip of cell region (43) are generally square in shape; The width and spacing of cells in the first strip of cell region (41) are both greater than the width and spacing of cells in the second strip of cell region (43).

2. The Schottky junction barrier diode with a non-uniformly mixed P+ structure in silicon carbide as described in claim 1, characterized in that: The cells in the dotted cell region (42) are square.

3. The method for manufacturing a Schottky junction barrier diode with a non-uniformly mixed P+ structure of silicon carbide as described in claim 1, comprising the following steps: An N+ substrate (1) is fabricated, and an epitaxial region (2) is grown on the N+ substrate (1). A sacrificial oxide layer is grown on the epitaxial region (2), then the sacrificial oxide layer is removed and cleaned, and a field oxide layer is grown by thermal oxidation. Photolithography was performed on the field oxide layer to fabricate the P+ region and the P+ ring region implantation window; Aluminum is injected into the P+ region and P+ ring region, and then annealed and activated to form the P+ region (4) and P+ ring region (3). After removing the surface field oxide layer, Schottky metal is sputtered to form a metallized anode (5), and photolithography is performed on the Schottky contact area, followed by etching. Silicon dioxide is grown on the surface of the P+ring region (3) and the metallized anode (5), and photolithography of the silicon dioxide passivation layer is performed. Then, etching and resist removal are performed to form a silicon oxide layer (6). Photolithography was performed on the top polyimide layer (7) passivation layer; The back side is thinned and then metallized, followed by the sequential sputtering of titanium, nickel, and silver.

4. The method for manufacturing a Schottky junction barrier diode with a non-uniformly mixed P+ structure of silicon carbide as described in claim 3, characterized in that: The N+ substrate (1) is made of 4H SiC. An epitaxial region (2) is grown on one side of the N+ substrate (1). The thickness of the epitaxial region (2) is 11µm and the doping concentration is 7.0E15cm. -3 .

5. The method for manufacturing a Schottky junction barrier diode with a non-uniformly mixed P+ structure of silicon carbide as described in claim 3, characterized in that: During the aluminum implantation process in the P+ ring region, the implantation was carried out in multiple stages at a temperature of 773°C, with the implanted ion concentration and implantation energy decreasing sequentially.

6. The method for manufacturing a Schottky junction barrier diode with a non-uniformly mixed P+ structure of silicon carbide as described in claim 3, characterized in that: The metallized anode (5) consists of Ti with a thickness of 1000 Å, TiN with a thickness of 100 Å, and AlCu with a thickness of 4 μm, from bottom to top.

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