Refresh Circuit, Refresh Method, and Semiconductor Memory

Abstract

Embodiments of the present disclosure relate to the field of semiconductor circuit design, and particularly to a refresh circuit, a refresh method, and a semiconductor memory, including: a signal generation module configured to generate a flip signal and a carry signal based on a refresh command; an adjustment unit configured to, if a first refresh signal and a second refresh signal are generated based on the refresh command, generate a flip adjustment signal according to the flip signal, and if only the first refresh signal is generated based on the refresh command, generate a flip adjustment signal according to the flip signal corresponding to the first refresh signal generated by the current refresh command, and generate a flip adjustment signal only according to the flip signal corresponding to the second refresh signal generated by the next refresh command; a counting module that generates a first output signal and a second output signal, and the counting module is configured to flip the first output signal based on the flip adjustment signal and accumulate the second output signal based on the carry signal to achieve accurate refresh counting in a multi-pulse refresh mode.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor circuit design, and particularly to a refresh circuit, a refresh method, and a semiconductor memory. Background Art

[0002] With the rapid development of the capacity and speed of semiconductor memory devices widely used in electronic devices, the power consumption of semiconductor memory devices has been increasing.

[0003] A dynamic random access memory (DRAM) is a volatile semiconductor memory device that stores data by using the charge stored in a capacitor. Since the charge stored in the capacitor can leak in various ways over time, the DRAM has limited data retention characteristics. To address the limited data retention, the DRAM generally needs to be refreshed periodically according to the data stored in the DRAM to charge or discharge the capacitor.

[0004] During the execution of the refresh operation, whether the refresh counter can count reliably directly affects the success or failure of the refresh operation. Summary of the Invention

[0005] Embodiments of the present disclosure provide a refresh circuit, a refresh method, and a semiconductor memory to achieve accurate refresh counting in a multi-pulse refresh mode.

[0006] Embodiments of the present disclosure provide a refresh circuit, including: a signal generation module configured to generate a flip signal and a carry signal based on a refresh command; wherein the refresh command is used to sequentially generate a first refresh signal and a second refresh signal, both the first refresh signal and the second refresh signal generate the flip signal, and the carry signal is generated based on the second refresh signal; an adjustment unit configured to, if the first refresh signal and the second refresh signal are generated based on the refresh command, generate a flip adjustment signal according to the flip signal, if only the first refresh signal is generated based on the refresh command, generate a flip adjustment signal according to the flip signal corresponding to the first refresh signal generated by the current refresh command, and generate a flip adjustment signal only according to the flip signal corresponding to the second refresh signal generated by the next refresh command; a counting module that generates a first output signal and a second output signal, and the counting module is configured to flip the first output signal based on the flip adjustment signal and accumulate the second output signal based on the carry signal; wherein the data formed by using the second output signal as the high bit and the first output signal as the low bit is used to represent the number of refreshes based on the refresh command.

[0007] Through an adjustment unit, the timing when the second refresh signal is missing is adjusted. For the first refresh command, the second refresh signal is missing. For the second refresh command, a flip adjustment signal is generated only based on the flip signal corresponding to the second refresh signal. That is, there is one valid carry signal in the first refresh command and the second refresh command, and there are two valid flip signals, that is, the flip adjustment signals, which is equivalent to the refresh process of a normal refresh command. Thus, the flip process of the first output signal and the counting process of the second output signal are corrected, and thus the counting of the third output signal is corrected.

[0008] In addition, the counting module includes: a first counting unit for generating a first output signal, configured to flip the first output signal based on the flip adjustment signal; a second counting unit for generating a second output signal, configured to accumulate the second output signal based on the carry signal; an output unit connected to the first counting unit and the second counting unit, configured to output a third output signal according to the first output signal and the second output signal, and the third output signal is used to represent the number of refreshes based on the refresh command.

[0009] In addition, the first counting unit is specifically configured to: output a digital high-level signal or a digital low-level signal; wherein, whenever the first counting unit receives the flip adjustment signal, the level of the digital high-level signal or the digital low-level signal currently output by the first counting unit is flipped once.

[0010] In addition, the first counting unit includes a flip-flop and multiple inverters; the output Q port of the flip-flop is connected to the input end of an inverter, and the output end of the inverter is connected to the input D port of the flip-flop; the clock CLK port of the flip-flop is used to receive the flip adjustment signal; the output Q port of the flip-flop is used to output the first output signal.

[0011] In addition, the second counting unit includes multiple flip-flops and multiple inverters; the output Q port of the low-order flip-flop is connected to the clock CLK port of the higher-order flip-flop; the output Q port of each flip-flop is connected to the input end of an inverter, and the output end of the inverter is connected to the input D port of the flip-flop; the clock CLK port of the lowest-order flip-flop is used to receive the carry signal; the output Q ports of each flip-flop are jointly used to output the second output signal.

[0012] In addition, the adjustment unit is specifically configured to generate a flip adjustment signal according to the flip signal, the first refresh signal, and the first output signal.

[0013] In addition, the adjustment unit includes a first NAND gate and a second NAND gate; one input terminal of the first NAND gate is used to receive the first output signal, and the other input terminal is used to receive the previous refresh signal generated by the first refresh signal based on the refresh command; one input terminal of the second NAND gate is connected to the output terminal of the first NAND gate, and the other input terminal is used to receive the flip signal; the output terminal of the second NAND gate is connected to the input terminal of an inverter, and the output terminal of the inverter is used to output the flip adjustment signal.

[0014] In addition, the signal generation module includes: a first signal generation unit configured to generate a flip signal according to the first refresh signal and the second refresh signal; a second signal generation unit configured to generate a carry signal according to the second refresh signal.

[0015] The embodiment of the present disclosure also provides a refresh method applied to the above refresh circuit, including: receiving a refresh command; wherein the refresh command is used to sequentially generate a first refresh signal and a second refresh signal; generating a flip signal based on the first refresh signal, generating a flip signal based on the second refresh signal, and generating a carry signal based on the second refresh signal; generating a flip adjustment signal based on the flip signal; flipping the first output signal based on the flip adjustment signal, and accumulating the second output signal based on the carry signal; wherein the data formed by taking the second output signal as the high bit and the first output signal as the low bit is used to represent the refresh times based on the refresh command.

[0016] The second refresh signal of the first refresh command is missing. For the second refresh command, the flip adjustment signal is generated only according to the flip signal corresponding to the second refresh signal. That is, there is one valid carry signal and two valid flip signals, i.e., the flip adjustment signals, in the first refresh command and the second refresh command, which is equivalent to the refresh process of a normal refresh command Ref. Thus, the flip process of the first output signal and the counting process of the second output signal are corrected, and thus the counting of the third output signal is corrected.

[0017] In addition, generating a flip adjustment signal based on the flip signal includes: if the first refresh signal and the second refresh signal are generated based on the same refresh command, synchronizing the flip signal to the flip adjustment signal.

[0018] In addition, if the second refresh signal generated based on the current refresh command is missing, generating a flip adjustment signal according to the flip signal corresponding to the first refresh signal generated by the current refresh command, and generating a flip adjustment signal only according to the flip signal corresponding to the second refresh signal generated by the next refresh command.

[0019] In addition, flipping the first output signal based on the flip adjustment signal includes: whenever the flip adjustment signal is received, performing a signal flip on the level of the currently output first output signal.

[0020] In addition, accumulating the second output signal based on the carry signal includes: whenever a carry signal is received, the second output signal is cumulatively incremented by one.

[0021] An embodiment of the present disclosure further provides a semiconductor memory, including the above-mentioned refresh circuit.

[0022] In addition, the semiconductor memory is a dynamic random access memory (DRAM) chip. Description of the Drawings

[0023] Figure 1 It is a schematic diagram of the refresh timing of the refresh circuit in the normal refresh mode provided by an embodiment of the present disclosure;

[0024] Figure 2 It is a schematic diagram of the refresh timing of the refresh circuit after the second refresh signal is missing provided by an embodiment of the present disclosure;

[0025] Figure 3 It is a schematic diagram of the refresh timing of the refresh circuit after the second refresh signal is missing and adjusted by the newly added adjustment unit provided by an embodiment of the present disclosure;

[0026] Figure 4 It is a schematic diagram of the structure of the refresh circuit provided by an embodiment of the present disclosure;

[0027] Figure 5 It is a schematic diagram of the structure of the signal generation module provided by an embodiment of the present disclosure;

[0028] Figure 6 It is a schematic diagram of the structure of the counting module provided by an embodiment of the present disclosure;

[0029] Figure 7 It is a schematic diagram of the structure of the first counting unit provided by an embodiment of the present disclosure;

[0030] Figure 8 It is a schematic diagram of the structure of the adjustment unit provided by an embodiment of the present disclosure;

[0031] Figure 9 It is a schematic diagram of the structure of the second counting unit provided by an embodiment of the present disclosure;

[0032] Figure 10 It is a schematic diagram of the flow of the refresh method provided by another embodiment of the present disclosure. Detailed Embodiments

[0033] Dynamic Random Access Memory (DRAM) is a volatile semiconductor memory device that stores data by using the charge stored in capacitors. Since the charge stored in the capacitors can leak in various ways over time, DRAM has limited data retention characteristics. To address the limited data retention, DRAM typically needs to be refreshed periodically according to the data stored in the DRAM to charge or discharge the capacitors.

[0034] During the process of performing the refresh operation, whether the refresh counter can count reliably directly affects the success or failure of the refresh operation.

[0035] An embodiment of the present disclosure provides a refresh circuit to achieve accurate refresh counting in a multi-pulse refresh mode.

[0036] Those of ordinary skill in the art can understand that in various embodiments of the present disclosure, many technical details are provided to help readers better understand the present disclosure. However, even without these technical details and various changes and modifications based on the following embodiments, the technical solutions claimed in the present disclosure can still be implemented.

[0037] The refresh mode mentioned in the embodiments of the present disclosure is a two-pulse refresh mode. In the two-pulse refresh mode, each refresh command generates two refresh signals. Refer to Figures 1 to 3 , each refresh command Ref generates two refresh signals, which are the first refresh signal 1st pulse and the second refresh signal 2nd pulse respectively. Among them, one refresh signal corresponds to one refresh operation, that is, a refresh operation is performed on one row address.

[0038] In some embodiments, the refresh command is a refresh command for a given bank. For example, a given bank may include 8 banks, and when performing all bank refresh operations on the given bank, access to any of the 8 banks in the given bank is not allowed. The waiting time for all bank refresh operations is a constant value. For example, the waiting time for all bank refresh operations can be about 130 nanoseconds (ns). The waiting time can also be measured in multiple clock cycles. It should be noted that the semiconductor memory can include any number of banks.

[0039] In some embodiments, the latency of a single-bank refresh operation is generally less than that of all-bank refresh operations. In a specific example, the latency of a single-bank refresh operation can reach 60 ns. However, while one of the eight banks is being refreshed and is inaccessible, the other seven banks can be accessed. In a specific example, when the memory controller determines that the predicted latency of a given bank is less than that of all-bank refresh operations, the memory controller can choose to perform a single-bank refresh operation.

[0040] When performing a refresh operation on a semiconductor memory, a refresh counter for counting the refresh address is required inside the semiconductor memory. Especially in the double-pulse refresh mode, each refresh command generates two refresh signals. In other words, each refresh command requires two refresh addresses. Here, the refresh address is the row address of the bank. Since each refresh signal corresponds to a refresh address, the counting of the refresh address can also be understood as the counting of the refresh signals.

[0041] In the double-pulse refresh mode, for all-bank refresh commands, since each refresh signal simultaneously refreshes all banks, each time a refresh is performed according to a refresh signal and the refresh counter is incremented by 1, all refresh addresses can be guaranteed to be refreshed. However, for per-bank refresh commands, its refresh signal is only valid for the corresponding bank, and the carry condition of the refresh counter is that each refresh address is traversed by all banks. Therefore, the carry of the refresh counter cannot be incremented by 1 each time a refresh is performed according to a refresh signal as in the case of all-bank refresh. For example, if the starting address of the refresh counter is 0000 and three all-bank refresh operations are continuously performed, the address change of the refresh counter is 0000 -> 0001 -> 0002 -> 0003 -> 0004 -> 0005. But if three single-bank refresh operations are continuously performed, the address change of the refresh counter is 0000 -> 0001 -> 0000 -> 0001 -> 0000 -> 0001... until all banks have refreshed the two addresses 0000 and 0001, the refresh counter will carry over to 0002.

[0042] Figure 1 Schematic diagram of the refresh timing of the refresh circuit in the normal refresh mode provided for this embodiment Figure 2 Schematic diagram of the refresh timing of the refresh circuit after the second refresh signal is missing provided for this embodiment Figure 3 Schematic diagram of the refresh timing of the refresh circuit after the second refresh signal is missing and adjusted by the newly added adjustment unit provided for this embodiment Figure 4Schematic diagram of the refresh circuit provided in this embodiment Figure 5 Schematic diagram of the signal generation module provided in this embodiment Figure 6 Schematic diagram of the counting module provided in this embodiment Figure 7 Schematic diagram of the first counting unit provided in this embodiment Figure 8 Schematic diagram of the adjustment unit provided in this embodiment Figure 9 Schematic diagram of the second counting unit provided in this embodiment. The refresh circuit provided in this embodiment will be further described in detail below with reference to the accompanying drawings, specifically as follows:

[0043] Refer to Figure 4 , the refresh circuit includes:

[0044] A signal generation module 101, configured to generate a flip signal CBRcountclk and a carry signal CBRincr based on a refresh command Ref; wherein, the refresh command Ref is used to sequentially generate a first refresh signal 1st pulse and a second refresh signal 2nd pulse, both the first refresh signal 1st pulse and the second refresh signal 2nd pulse generate the flip signal CBRcountclk, and the carry signal CBRincr is generated based on the second refresh signal 2nd pulse.

[0045] An adjustment unit 102, configured to, if the first refresh signal 1st pulse and the second refresh signal 2nd pulse are generated based on the refresh command Ref, generate a flip adjustment signal CBRcountclkmix according to the flip signal CBRcountclk, and if only the first refresh signal 1st pulse is generated based on the refresh command, generate a flip adjustment signal CBRcountclkmix according to the flip signal CBRcountclk corresponding to the first refresh signal 1st pulse generated by the current refresh command Ref, and generate a flip adjustment signal CBRcountclkmix only according to the flip signal CBRcountclk corresponding to the second refresh signal 2nd pulse generated by the next refresh command Ref.

[0046] A counting module 103, generating a first output signal CBRAdd<0> and a second output signal CBRAdd<14:1>. The counting module 103 is configured to flip the first output signal CBRAdd<0> based on the flip adjustment signal CBRcountclkmix, and accumulate the second output signal CBRAdd<14:1> based on the carry signal CBRincr; wherein, the data formed by taking the second output signal CBRAdd<14:1> as the high bit and the first output signal CBRAdd<0> as the low bit is used to represent the refresh times based on the refresh command Ref.

[0047] It should be noted that in this embodiment, the data formed by taking the second output signal CBRAdd<14:1> as the high bit and the first output signal CBRAdd<0> as the low bit is specifically described as the third output signal CBRAdd<14:0>.

[0048] For the refresh circuit provided above, the counting principle refers to Figures 1 to 3 , referring to Figure 1 , if both the first refresh signal 1st pulse and the second refresh signal 2nd pulse generated based on the refresh command Ref exist, at this time, the flip signal CBRcountclk and the carry signal CBRincr are normally generated; since both the first refresh signal 1st pulse and the second refresh signal 2nd pulse exist, at this time, the timing of the flip adjustment signal CBRcountclkmix ( Figure 1 not shown) generated by the adjustment unit 102 is the same as that of the flip signal CBRcountclk. At this time, the first output signal CBRAdd<0> is normally generated based on the flip adjustment signal CBRcountclkmix, and the second output signal CBRAdd<14:1> is normally counted based on the carry signal, and the generated third output signal can perform correct address jumps.

[0049] However, in practical applications, the first refresh signal 1st pulse is triggered according to the refresh command Ref, and the possibility of its absence is relatively small. The second refresh signal 2nd pulse is generated according to the internal circuit, and there may be a situation where the second refresh signal 2nd pulse is missing due to some external reasons. When the second refresh signal 2nd pulse generated by a certain refresh command Ref is missing, referring to Figure 2 , due to the absence of a second refresh signal 2nd pulse, in the timing of the first refresh command Ref, the generated carry signal CBRincr and a flip signal CBRcountclk are missing. If the flip signal CBRcountclk is directly synchronized to the flip adjustment signal CBRcountclkmix ( Figure 2 not shown) at this time, the first output signal CBRAdd<0> generated at this time will cause all subsequent first output signals CBRAdd<0> to be incorrect due to the absence of a flip process, while the second output signal CBRAdd<14:1> lacks a carry process, resulting in an incorrect count of the third output signal CBRAdd<14:0>, and the third output signal CBRAdd<14:0> cannot represent the number of refreshes based on the refresh command Ref.

[0050] The present disclosure passes through the adjustment unit 102 (refer to Figure 4) Adjust the timing when the second refresh signal 2nd pulse is missing, refer to Figure 3 , the second refresh signal 2nd pulse of the first refresh command Ref is missing. For the second refresh command, only the flip signal CBRcountclk corresponding to the second refresh signal 2nd pulse is used to generate the flip adjustment signal CBRcountclkmix. That is, there is one valid carry signal CBRincr in the first refresh command Ref and the second refresh command Ref, and there are two valid flip signals CBRcountclk, that is, the flip adjustment signal CBRcountclkmix. This is equivalent to the refresh process of a normal refresh command Ref, so as to correct the flip process of the first output signal CBRAdd<0> and the counting process of the second output signal CBRAdd<14:1>, and thus correct the counting of the third output signal CBRAdd<14:0>.

[0051] In the embodiments of the present disclosure, the refresh command is an all-bank refresh command or a single-bank refresh command; wherein, the refresh signal generated by the all-bank refresh command is used to simultaneously refresh all banks. Here, simultaneous refresh means to simultaneously refresh the same row address in all banks. The refresh signal generated by the single-bank refresh command is used to sequentially refresh all banks before repeating the refresh of any bank. Here, sequential refresh means to refresh a row address in a certain bank among all banks.

[0052] It should be noted that for the single-bank refresh command, when performing the single-bank refresh operation, all banks need to be refreshed by the single-bank refresh command before repeating the refresh of any bank. In other words, the single-bank refresh operation is a non-repeating sequential refresh operation for all banks. Here, for each single-bank refresh command, the refresh order of all banks during the sequential refresh process can be adjusted according to actual needs.

[0053] It should also be noted that all banks in the embodiments of the present disclosure refer to all given banks targeted by the refresh command, rather than all banks in the semiconductor memory. Only when the given banks targeted by the refresh command are all banks in the semiconductor memory, all banks mean all banks in the semiconductor memory.

[0054] In some embodiments, refer to Figure 5, the signal generation module 101 includes: a first signal generation unit 111 and a second signal generation unit 121. Among them, the first signal generation unit 111 is configured to generate a flip signal CBRcountclk according to the first refresh signal 1stpulse and the second refresh signal 2nd pulse; the second signal generation unit 121 is configured to generate a carry signal CBRincr according to the second refresh signal 2nd pulse.

[0055] In some embodiments, refer to Figure 6 , the counting module 103 includes: a first counting unit 113, a second counting unit 123 and an output unit 133. Among them, the first counting unit 113 is used to generate a first output signal CBRAdd<0>, and the first counting unit 113 is configured to flip the first output signal CBRAdd<0> based on the flip adjustment signal CBRcountclkmix; the second counting unit 123 is used to generate a second output signal CBRAdd<14:1>, and the second counting unit 123 is configured to accumulate the second output signal CBRAdd<14:1> based on the carry signal CBRincr; the output unit 133 is connected to the first counting unit 113 and the second counting unit 123, and is configured to output a third output signal CBRAdd<14:0> according to the first output signal CBRAdd<0> and the second output signal CBRAdd<14:1>.

[0056] In an example, the first counting unit 113 (refer to Figure 6 ) is specifically configured to output a digital high-level signal or a digital low-level signal; among them, whenever the first counting unit 113 (refer to Figure 6 ) receives the flip adjustment signal CBRcountclkmix, the level of the digital high-level signal or the digital low-level signal currently output by the first counting unit 113 (refer to Figure 6 ) is flipped once (in combination with Figures 1 to 3 ). That is, the first counting unit 113 flips the signal between signal 1 and signal 0 according to the flip adjustment signal CBRcountclkmix.

[0057] Specifically, refer to Figure 7 , the first counting unit 113 (refer to Figure 6 ) includes: a flip-flop and a plurality of inverters. Among them, the output Q port of the flip-flop is connected to the input end of an inverter, the output end of the inverter is connected to the input D port of the flip-flop, the clock ClkN port of the flip-flop is used to receive the flip adjustment signal CBRcountclkmix, and the output Q port of the flip-flop is used to output the first output signal CBRAdd<0>.

[0058] The working principle of the first counting unit 113 is as follows: When the falling edge of the flip adjustment signal CBRcountclkmix arrives, the flip-flop is triggered, and the data at the input D port is transmitted to the output Q port; before being triggered, the data at the input D port and the data at the output Q port of the flip-flop are anti-phase signals. Therefore, after the flip-flop is triggered by the flip adjustment signal CBRcountclkmix, the output signal at the output Q port of the flip-flop is inverted.

[0059] Correspondingly, referring to Figure 9 , the second counting unit 123 (refer to Figure 6 ) includes: a plurality of flip-flops and a plurality of inverters, wherein the output Q port of the low-order flip-flop is connected to the clock ClkN port of the higher-order flip-flop, the output Q port of each flip-flop is connected to the input end of an inverter, the output end of the inverter is connected to the input D port of the flip-flop, the clock ClkN port of the lowest-order flip-flop is used to receive the carry signal CBRincr, and the output Q port of each flip-flop is used to output the second output signal CBRAdd<14:1>.

[0060] It should be noted that each flip-flop in the second counting unit 123 is used to output one bit in the second output signal CBRAdd<14:1>, such as CBRAdd<1>, CBRAdd<2>, CBRAdd<3>... CBRAdd<14>. The data combinations output by each flip-flop constitute the second output signal CBRAdd<14:1>.

[0061] The working principle of the second counting unit 123 is as follows: When the falling edge of the carry signal CBRincr arrives, the low-order flip-flop is triggered, and the data at the input D port is transmitted to the output Q port; before being triggered, the input data at the input D port and the output data at the output Q port of the flip-flop are anti-phase signals. Therefore, after the flip-flop is triggered by the carry signal CBRincr, the output signal at the output Q port of the flip-flop is inverted. That is, the low-order flip-flop realizes a jump from "1 to 0" or "0 to 1" based on the carry signal CBRincr; when the low-order flip-flop jumps from "1 to 0", the output signal triggers the higher-order flip-flop. After the higher-order flip-flop is triggered, the data at the input D port is transmitted to the output Q port, and the input data at the input D port and the output data at the output Q port of the flip-flop are anti-phase signals, thereby realizing the carry operation of binary data from low order to high order.

[0062] In the double-pulse refresh mode of the embodiments of the present disclosure, since the second counting unit 123 counts according to the carry signal CBRincr, and the carry signal CBRincr is generated based on the second refresh signal 2nd pulse generated according to the received refresh command Ref. Correspondingly, when applied to the multi-pulse refresh mode, CBRincr is generated based on the last refresh signal generated according to the received refresh command Ref. Then, whether it is the case of refreshing all memory banks or a single memory bank, the carry signal CBRincr will only appear after the refresh command is executed to the last refresh signal, and thus the second counting unit 123 will count the refresh command. In the embodiments of the present disclosure, the carry signal CBRincr generated by the signal generation module 101 can count the refresh command in the multi-pulse refresh mode.

[0063] Furthermore, according to the second output signal CBRAdd<14:1> that counts the refresh command Ref and the first output signal CBRAdd<0> that flips with each refresh signal, the third output signal CBRAdd<14:0> that represents the count of the refresh signals generated by the refresh command Ref can be obtained, thereby realizing the counting of the refresh signals generated by the refresh command Ref. Since each refresh signal corresponds to a refresh address, the counting of the refresh address can also be realized.

[0064] It should be noted that Figure 7 and Figure 9 the shown flip-flops are all reset based on the reset signal Reset, and the flip-flops are all output based on two consecutive inverters. The purpose of setting two inverters is to enhance the driving ability of the output signal without changing the phase of the output signal and the represented count value. In other embodiments, the output of the flip-flop can be directly output through the output Q terminal. Correspondingly, the output of the flip-flop can also be serially output through an even number of inverters greater than 2. In some embodiments, the above flip-flop can be a D flip-flop, and the inverter can be a logical NOT gate.

[0065] In addition, for the above-mentioned flip adjustment signal CBRcountclkmix, the adjustment unit 102 (refer to Figure 4 ) is specifically configured to generate the flip adjustment signal CBRcountclkmix according to the flip signal CBRcountclk, the first refresh signal 1st pulse, and the first output signal CBRAdd<0>.

[0066] Specifically, refer to Figure 8 , the adjustment unit 102 (refer to Figure 4)It includes a NAND gate and an AND gate. One input terminal of the NAND gate is used to receive the first input signal CBRAdd<0>, and the other input terminal is used to receive the first refresh signal 1st pulse. One input terminal of the AND gate is connected to the output terminal of the NAND gate, and the other input terminal is used to receive the inversion signal CBRcountclk. The output terminal of the AND gate is used to output the inversion adjustment signal CBRcountclkmix.

[0067] That is, the principle of generating the inversion adjustment signal CBRcountclkmix based on the inversion signal CBRcountclk is as follows: For a logic AND gate, it follows the output logic of "1 when both inputs are 1, 0 when there is a 0", and for a logic NAND gate, it follows the output logic of "0 when both inputs are 1, 1 when there is a 0". Under normal output timing, refer to Figure 1 , the inversion signal CBRcountclk corresponding to the first refresh signal 1st pulse is used to invert the first output signal CBRAdd<0> from low level to high level, and the inversion signal CBRcountclk corresponding to the second refresh signal 2ndpulse is used to invert the first output signal CBRAdd<0> from high level to low level; Under the output timing after the second refresh signal 2nd pulse is missing, refer to Figure 2 , the inversion signal CBRcountclk corresponding to the first refresh signal 1st pulse generated by the current refresh command Ref inverts the first output signal CBRAdd<0> from low level to high level, but the missing second refresh signal 2nd pulse causes the first output signal CBRAdd<0> to remain high level. The inversion signal CBRcountclk corresponding to the first refresh signal 1st pulse generated by the next refresh command Ref is used to invert the first output signal CBRAdd<0> from high level to low level, and the inversion signal CBRcountclk corresponding to the second refresh signal 2nd pulse generated by the next refresh command Ref is used to invert the first output signal CBRAdd<0> from low level to high level, thus resulting in an output error.

[0068] For the AND gate, when the output of the NAND gate is high level, it is used to generate the inversion adjustment signal CBRcountclkmix according to the inversion signal CBRcountclk.

[0069] For the NAND gate, when the first refresh signal 1st pulse appears after the second refresh signal 2nd pulse is not missing, the first output signal CBRAdd<0> is at a low level at this time, that is, before the first refresh signal 1st pulse refreshes, the first output signal CBRAdd<0> is at a low level. At this time, the output of the NAND gate is at a high level, generating a flip adjustment signal CBRcountclkmix for normal refresh operation; when the first refresh signal 1st pulse appears after the second refresh signal 2nd pulse is missing, the first output signal CBRAdd<0> is at a high level at this time, that is, before the first refresh signal 1st pulse refreshes, the first output signal CBRAdd<0> is at a high level. At this time, the output of the NAND gate is at a low level, and no flip adjustment signal CBRcountclkmix is generated to correct the incorrect jump of the first output signal CBRAdd<0> caused by the missing second refresh signal 2nd pulse. Refer to Figure 3 . When the first output signal CBRAdd<0> is at a low level, that is, before the first refresh signal 1st pulse refreshes, the first output signal CBRAdd<0> is at a low level, corresponding to the above normal output timing. At this time, the output of the NAND gate is at a high level, generating a flip adjustment signal to maintain the correct refresh timing.

[0070] It should be noted that the above logical AND gate can be implemented by connecting the output terminal of a NAND gate to an inverter in a specific application.

[0071] Through the adjustment unit, the timing when the second refresh signal is missing is adjusted. For the first refresh command, the second refresh signal is missing. For the second refresh command, a flip adjustment signal is generated only according to the flip signal corresponding to the second refresh signal, that is, there is one valid carry signal and two valid flip signals, that is, flip adjustment signals, in the first refresh command and the second refresh command, which is equivalent to the refresh process of a normal refresh command, so as to correct the flip process of the first output signal and the counting process of the second output signal, and thus correct the counting of the third output signal.

[0072] Based on the refresh circuit provided in the above embodiment, another embodiment of the present disclosure provides a refresh method. Figure 10 It is a schematic flowchart of the refresh method provided in this embodiment, as Figure 10 shown. The method mainly includes the following steps:

[0073] Step 201, receive a refresh command.

[0074] Specifically, receive a refresh command, and the refresh command is used to generate a first refresh signal and a second refresh signal at one time.

[0075] Step 202, generate a flip signal and a carry signal.

[0076] Specifically, a flip signal is generated based on the first refresh signal, a flip signal is generated based on the second refresh signal, and a carry signal is generated based on the second refresh signal.

[0077] Step 203: Generate a flip adjustment signal.

[0078] Specifically, a flip adjustment signal is generated based on the flip signal.

[0079] More specifically, if the first refresh signal and the second refresh signal are generated based on the same refresh command, the flip signal is synchronized to the flip adjustment signal; if the second refresh signal generated based on the current refresh command is missing, the flip adjustment signal is generated according to the flip signal corresponding to the first refresh signal generated according to the current refresh command, and the flip adjustment signal is generated only according to the flip signal corresponding to the second refresh signal generated according to the next refresh command.

[0080] Step 204: Generate a first output signal and a second output signal.

[0081] Specifically, the first output signal is flipped based on the flip adjustment signal, and the second output signal is accumulated based on the carry signal, where the data composed of the second output signal as the high bit and the first output signal as the low bit is used to represent the refresh times based on the refresh command.

[0082] In some embodiments, it further includes: generating a third output signal according to the first output signal and the second output signal, and the third output signal is used to represent the refresh times based on the refresh command.

[0083] In one example, flipping the first output signal based on the flip adjustment signal includes: whenever the flip adjustment signal is received, the level of the currently output first output signal is flipped once.

[0084] In one example, accumulating the second output signal based on the carry signal includes: whenever the carry signal is received, the second output signal is incremented by one.

[0085] The second refresh signal of the first refresh command is missing. For the second refresh command, the flip adjustment signal is generated only according to the flip signal corresponding to the second refresh signal, that is, there is one valid carry signal and two valid flip signals, that is, the flip adjustment signal, in the first refresh command and the second refresh command, which is equivalent to the refresh process of a normal refresh command Ref, so as to correct the flip process of the first output signal and the counting process of the second output signal, and thus correct the counting of the third output signal.

[0086] It should be noted that the description of the above refresh method is similar to the description of the above refresh circuit embodiment, and has beneficial effects similar to those of the refresh circuit embodiment. Therefore, it will not be elaborated here. For the technical details not disclosed in the refresh method of the embodiments of the present disclosure, please refer to the description of the refresh circuit in the embodiments of the present disclosure for understanding.

[0087] Another embodiment of the present disclosure further provides a semiconductor memory, including the refresh circuit provided in the above embodiment. The semiconductor memory referred to in the present disclosure includes, but is not limited to, dynamic random access memories, etc. The semiconductor memory uses the refresh circuit provided in the above embodiment to implement the counting of refresh commands, refresh signals, and refresh addresses in the multi-pulse refresh mode.

[0088] In some embodiments, the semiconductor memory is a dynamic random access memory DRAM chip, wherein the memory of the dynamic random access memory DRAM chip conforms to the DDR2 memory specification.

[0089] In some embodiments, the semiconductor memory is a dynamic random access memory DRAM chip, wherein the memory of the dynamic random access memory DRAM chip conforms to the DDR3 memory specification.

[0090] In some embodiments, the semiconductor memory is a dynamic random access memory DRAM chip, wherein the memory of the dynamic random access memory DRAM chip conforms to the DDR4 memory specification.

[0091] In some embodiments, the semiconductor memory is a dynamic random access memory DRAM chip, wherein the memory of the dynamic random access memory DRAM chip conforms to the DDR5 memory specification.

[0092] It should be noted that the features disclosed in the refresh circuit provided in the above embodiments can be arbitrarily combined without conflict to obtain new circuit embodiments; the methods disclosed in the refresh methods provided in the above embodiments can be arbitrarily combined without conflict to obtain new method embodiments.

[0093] Those of ordinary skill in the art can understand that the above embodiments are specific embodiments for implementing the present disclosure, and in practical applications, various changes can be made in form and details without departing from the spirit and scope of the present disclosure.

Claims

1. A refresh circuit, characterized in that, Including: A signal generation module configured to generate a flip signal and a carry signal based on a refresh command; wherein, the refresh command is used to sequentially generate a first refresh signal and a second refresh signal, both the first refresh signal and the second refresh signal generate the flip signal, and the carry signal is generated based on the second refresh signal; An adjustment unit configured to, if the first refresh signal and the second refresh signal are generated based on the refresh command, generate a flip adjustment signal according to each flip signal corresponding to the first refresh signal and the second refresh signal, and if only the first refresh signal is generated based on the refresh command, generate the flip adjustment signal according to the flip signal corresponding to the first refresh signal generated by the current refresh command, and generate the flip adjustment signal only according to the flip signal corresponding to the second refresh signal generated by the next refresh command; A counting module that generates a first output signal and a second output signal, the counting module being configured to flip the first output signal based on the flip adjustment signal and accumulate the second output signal based on the carry signal; wherein, the data formed with the second output signal as the high bit and the first output signal as the low bit is used to represent the refresh times based on the refresh command.

2. The refresh circuit according to claim 1, wherein The counting module includes: A first counting unit for generating the first output signal, configured to flip the first output signal based on the flip adjustment signal; A second counting unit for generating the second output signal, configured to accumulate the second output signal based on the carry signal; An output unit connected to the first counting unit and the second counting unit, configured to output a third output signal according to the first output signal and the second output signal, the third output signal being used to represent the refresh times based on the refresh command.

3. The refresh circuit according to claim 2, wherein The first counting unit is specifically configured to: output a digital high level signal or a digital low level signal; wherein, whenever the first counting unit receives the flip adjustment signal, the level of the digital high level signal or the digital low level signal currently output by the first counting unit is flipped once.

4. The refresh circuit according to claim 3, wherein The first counting unit includes a flip-flop and multiple inverters; the output Q port of the flip-flop is connected to the input end of an inverter, and the output end of this inverter is connected to the input D port of the flip-flop; the clock CLK port of the flip-flop is used to receive the flip adjustment signal; the output Q port of the flip-flop is used to output the first output signal.

5. The refresh circuit according to claim 2, wherein The second counting unit includes multiple flip-flops and multiple inverters; the output Q port of the low-order flip-flop is connected to the clock CLK port of the high-order flip-flop; the output Q port of each flip-flop is connected to the input end of an inverter, and the output end of this inverter is connected to the input D port of the flip-flop; the clock CLK port of the lowest-order flip-flop is used to receive the carry signal; the output Q ports of each flip-flop are jointly used to output the second output signal.

6. The refresh circuit according to claim 1, wherein The adjustment unit is specifically configured to generate a flip adjustment signal according to the flip signal, the first refresh signal and the first output signal.

7. The refresh circuit according to claim 6, wherein The adjustment unit includes a NAND gate and an AND gate; One input terminal of the NAND gate is used to receive the first output signal, and the other input terminal is used to receive the first refresh signal; One input terminal of the AND gate is connected to the output terminal of the NAND gate, and the other input terminal is used to receive the inversion signal; The output terminal of the AND gate is used to output the inversion adjustment signal.

8. The refresh circuit according to claim 1, characterized in that, The signal generation module includes: A first signal generation unit configured to generate the inversion signal according to the first refresh signal and the second refresh signal; A second signal generation unit configured to generate the carry signal according to the second refresh signal.

9. A refreshing method, characterized in that, Applied to the refresh circuit according to any one of claims 1 to 8, including: Receiving a refresh command; wherein, the refresh command is used to sequentially generate a first refresh signal and a second refresh signal; Generating an inversion signal based on the first refresh signal, generating the inversion signal based on the second refresh signal, and generating a carry signal based on the second refresh signal; Generating an inversion adjustment signal based on the inversion signal; Inverting the first output signal based on the inversion adjustment signal, and accumulating the second output signal based on the carry signal; wherein, the data formed by using the second output signal as the high bit and the first output signal as the low bit is used to represent the refresh times based on the refresh command.

10. The refreshing method according to claim 9, wherein The generating the inversion adjustment signal based on the inversion signal includes: if the first refresh signal and the second refresh signal are generated based on the same refresh command, synchronizing the inversion signal to the inversion adjustment signal.

11. The refreshing method according to claim 10, wherein If the second refresh signal generated based on the current refresh command is missing, generating the inversion adjustment signal according to the inversion signal corresponding to the first refresh signal generated by the current refresh command, and generating the inversion adjustment signal only according to the inversion signal corresponding to the second refresh signal generated by the next refresh command.

12. The refreshing method according to claim 9, wherein The inverting the first output signal based on the inversion adjustment signal includes: whenever the inversion adjustment signal is received, performing a signal inversion on the level of the currently output first output signal.

13. The refreshing method according to claim 9, wherein The accumulating the second output signal based on the carry signal includes: whenever the carry signal is received, the second output signal is cumulatively incremented by one.

14. A semiconductor memory, including the refresh circuit according to any one of claims 1 to 8.

15. The semiconductor memory according to claim 14, wherein, The semiconductor memory is a dynamic random access memory DRAM chip.

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