Electronic device and method of manufacturing the same

Abstract

A method of manufacturing an electronic device includes providing a substrate, forming a solder and a flux on the substrate, joining an electronic component on the solder, and removing at least a portion of the flux. An electronic device is also provided.

Description

Technical Field

[0001] This disclosure relates to an electronic device, and more particularly to an electronic device having a bonding pad and a method of manufacturing the same. Background Technology

[0002] Currently, electronic components are soldered onto thin-film transistor (TFT) glass substrates. However, after reliability testing (such as thermal shock), cracks may appear in the glass directly beneath the electronic component, resulting in bright / dark spots or even the electronic component peeling off the substrate. These anomalies occur because of the difference in the coefficient of thermal expansion (CTE) between the electronic component and the glass. After the thermal expansion and contraction process of thermal shock, tensile stress is generated, eventually leading to a crack initiation point at the location of maximum stress in the structure, which then extends outwards. Summary of the Invention

[0003] According to one embodiment of the present disclosure, a method for manufacturing an electronic device is provided, comprising: providing a substrate; forming a solder and a flux on the substrate; bonding an electronic component to the solder; and removing at least a portion of the flux.

[0004] According to one embodiment of the present disclosure, an electronic device is provided, comprising: a substrate; an electronic component including a plurality of bonding pads located on the substrate; and an adhesive material located between the plurality of bonding pads. Attached Figure Description

[0005] The embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. It should be noted that the various feature components are not drawn to scale and are only used for illustrative purposes. In fact, the dimensions of the components may be enlarged or reduced to clearly show the technical features of the embodiments of this disclosure.

[0006] Figures 1A-1F This is a cross-sectional schematic diagram of a method for manufacturing an electronic device according to an embodiment of the present disclosure;

[0007] Figure 1G According to one embodiment of this disclosure, for Figure 1F Top view;

[0008] Figures 2A-2D This is a schematic diagram of removing flux from an electronic device according to an embodiment of the present disclosure.

[0009] Symbol Explanation

[0010] 10: Substrate

[0011] 12: First insulating layer

[0012] 14: Second insulating layer

[0013] 16: Patterned metal layer

[0014] 18: Pixel Definition Layer

[0015] 18': Top surface of the pixel definition layer

[0016] 20: Metal layer

[0017] 22a: First joint structure

[0018] 22b: Second joint structure

[0019] 24: Solder

[0020] 26: Flux

[0021] 27: Electronic Components

[0022] 28: Main Body

[0023] 28': Top surface of the main body

[0024] 30a: First bonding pad

[0025] 30b: Second bonding pad

[0026] 32: Reflow process

[0027] 34: Adhesive materials

[0028] 34': Top of the adhesive material

[0029] 40: Electronic devices

[0030] 42: Figure 1D The structure shown

[0031] 42': Figure 1D The upper surface of the structure shown

[0032] 44: Container

[0033] 46: Cleaning fluid

[0034] 46': The level of the cleaning fluid

[0035] 48: Ultrasonic Oscillator

[0036] 50: Ultrasonic washing steps

[0037] 52: Deionized water

[0038] 54: Structure after ultrasonic washing step

[0039] 56: Drying Steps

[0040] H: Thickness of electronic components

[0041] h: Thickness of the adhesive material

[0042] K: Height from the top surface of the pixel definition layer to the top surface of the main body of the electronic component Detailed Implementation

[0043] The following disclosure provides many different embodiments to implement the various features of this invention. The following disclosure describes specific examples of the various components and their arrangements to simplify the explanation. Of course, these specific examples are not intended to be limiting. For example, if the embodiments of this disclosure describe a first feature formed on or above a second feature, it means that it may include embodiments where the first feature and the second feature are in direct contact, or it may include embodiments where an additional feature is formed between the first feature and the second feature, so that the first feature and the second feature may not be in direct contact.

[0044] It should be understood that additional operational steps may be performed before, during, or after the method, and in other embodiments of the method, some operational steps may be replaced or omitted.

[0045] Furthermore, spatially related terms may be used, such as "below," "below," "lower," "above," "above," "higher," and similar terms. These spatially related terms are used to facilitate the description of the relationship between one or more components or features in the illustrations and to another component or feature(s). These spatially related terms include different orientations of the device in use or operation, as well as the orientations described in the accompanying drawings. When the device is turned to a different orientation (rotated 45 degrees or other orientations), the spatially related adjectives used will also be interpreted according to the orientation after the turn. Moreover, when it is mentioned that a first material layer is located on or above a second material layer, this includes situations where the first material layer and the second material layer are in direct contact, or situations where there may be one or more other material layers in between, in which case the first material layer and the second material layer may not be in direct contact. In some embodiments of this disclosure, terms such as "connection" and "interconnection," unless specifically defined, may refer to two structures being in direct contact, or they may refer to two structures not being in direct contact, with other structures disposed between them. Furthermore, these terms regarding joining and connection may also include cases where both structures are movable or both structures are fixed.

[0046] In the specification, the terms "about," "approximately," "roughly," "generally," "substantially," "same," and "similar" generally indicate a range of a characteristic value within ±15%, ±10%, ±5%, ±3%, ±2%, ±1%, or ±0.5% of a given value. The quantities given here are approximate; that is, even without specific mention of "about," "approximately," "roughly," "generally," or "substantially," the meaning of these terms may be implied.

[0047] It should be understood that although the terms "first," "second," "third," etc., are used herein to describe different components, parts, regions, layers, and / or sections, these components, parts, regions, layers, and / or sections should not be limited by these terms. These terms may only be used to distinguish one component, part, region, layer, or section from another component, part, region, layer, or section. Therefore, without departing from the technology of this disclosure, the first component, part, region, layer, or section discussed below may be referred to as the second component, part, region, layer, or section.

[0048] Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. It is understood that these terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning consistent with the relevant art and the background or context of this disclosure, and should not be interpreted in an idealized or overly formal manner, unless specifically defined in the embodiments of this disclosure.

[0049] Please see Figures 1A-1F According to one embodiment of the present disclosure, a method for manufacturing an electronic device is provided. Figures 1A-1F A cross-sectional schematic diagram of an electronic device manufacturing method.

[0050] like Figure 1A As shown, a substrate 10 is provided. A first insulating layer 12 is formed on the substrate 10. A second insulating layer 14 is formed on the first insulating layer 12. A patterned metal layer 16 is formed on the second insulating layer 14, exposing a portion of the second insulating layer 14. A pixel defining layer (PDL) 18 is formed on the patterned metal layer 16 and the exposed second insulating layer 14, exposing a portion of the patterned metal layer 16. A metal layer 20 is formed on the exposed patterned metal layer 16 to define a first bonding structure 22a and a second bonding structure 22b, corresponding to the bonding pads of subsequently bonded electronic components.

[0051] In some embodiments, substrate 10 may include a rigid substrate or a flexible substrate, such as a glass substrate or a polyimide (PI) substrate, but this disclosure is not limited thereto. In some embodiments, the first insulating layer 12 and the second insulating layer 14 are insulating materials, which may include silicon oxide, silicon nitride, or silicon oxynitride, but this disclosure is not limited thereto. In some embodiments, the patterned metal layer 16 is a metallic material, which may include copper, but this disclosure is not limited thereto. In some embodiments, the pixel defining layer 18 is an organic or inorganic material, which may include resin, organosilicon, silicon nitride, or silicon oxide, but this disclosure is not limited thereto. In some embodiments, the metal layer 20 is a metallic material, which may include nickel, but this disclosure is not limited thereto.

[0052] Next, as Figure 1B As shown, solder 24 and flux 26 are formed on the first bonding structure 22a and the second bonding structure 22b of the substrate 10. Figure 1B In this process, solder 24 is first formed on the first bonding structure 22a and the second bonding structure 22b, and then flux 26 is formed on the solder 24. In some embodiments, solder 24 and flux 26 may be mixed first to form a mixture, and then the mixture may be formed on the first bonding structure 22a and the second bonding structure 22b. In this disclosure, solder 24 and flux 26 may be formed on the first bonding structure 22a and the second bonding structure 22b by, for example, injection coating. In some embodiments, solder 24 is first formed on the first bonding structure 22a and the second bonding structure 22b by injection coating, and then flux 26 is formed on the solder 24 again by injection coating. In some embodiments, solder 24 and flux 26 are first mixed to form a mixture, and then the mixture is formed on the first bonding structure 22a and the second bonding structure 22b by injection coating. In some embodiments, the solder 24 is a metal or alloy material, which may include tin or a tin-bismuth alloy, but this disclosure is not limited thereto. In some embodiments, the flux 26 is a mixture of resin and organic solvent, which may include rosin, organic acids, ethanol, thickeners, etc., but this disclosure is not limited thereto.

[0053] Next, as Figure 1C As shown, electronic component 27 is bonded to solder 24 and flux 26, wherein electronic component 27 includes a first bonding pad 30a, a second bonding pad 30b, and a body 28. Figure 1CIn this embodiment, electronic component 27 is bonded to solder 24 and flux 26 via first bonding pad 30a and second bonding pad 30b. In some embodiments, electronic component 27 may include passive or active components, such as capacitors, resistors, inductors, diodes, transistors, etc. Diodes may include light-emitting diodes or photodiodes, such as organic light-emitting diodes (OLEDs), mini LEDs, micro LEDs, or quantum dot LEDs, but this disclosure is not limited thereto. In some embodiments, the thickness H of electronic component 27 is approximately 600 micrometers. In some embodiments, the first bonding pad 30a and second bonding pad 30b may include copper, but this disclosure is not limited thereto.

[0054] Next, as Figure 1D As shown, a reflow process 32 is performed. In some embodiments, the reflow process 32 may include low-temperature reflow (reflow temperature approximately below 170°C). After reflow, flux 26 exhibits a distribution pattern surrounding the electronic component 27 and located between the first bonding structure 22a and the second bonding structure 22b.

[0055] Next, as Figure 1E As shown, remove flux 26. The removal method will be described in detail below.

[0056] Next, as Figure 1F As shown, adhesive material 34 is formed on substrate 10 and surrounds electronic component 27 and is located between first bonding structure 22a and second bonding structure 22b, as shown. Figure 1G As shown. Figure 1G for Figure 1F A top view. In this disclosure, adhesive 34 can be formed on substrate 10 by, for example, spray coating, and surrounds electronic component 27 and is located between first bonding structure 22a and second bonding structure 22b. In some embodiments, the Young's modulus of adhesive 34 is between about 1 MPa and about 100 MPa. In some embodiments, adhesive 34 may include white glue (e.g., silicone-based), optical glue, or waterproof glue, but this disclosure is not limited thereto. In some embodiments, the thickness h of adhesive 34 (from the upper surface 18' of pixel definition layer 18 to the top 34' of adhesive 34) is between about 50 micrometers and about 600 micrometers. Here, the height from the upper surface 18' of pixel definition layer 18 to the upper surface 28' of body 28 of electronic component 27 is defined as K. In some embodiments, the height K is between about 600 micrometers and about 640 micrometers. It is worth noting that the thickness h of adhesive 34 does not exceed the height K. Thus, the fabrication of electronic device 40 is completed.

[0057] The following details the removal methods for flux 26.

[0058] Please see Figures 2A-2D According to one embodiment of the present disclosure, a method for removing flux in an electronic device is provided. Figures 2A-2D This is a schematic diagram of the removal method described above.

[0059] like Figure 2A As shown, Figure 1D The structure 42 shown (containing flux) is placed in container 44 and cleaning solution 46 is added. Figure 2A In the middle, the liquid level 46' of the cleaning fluid 46 is approximately higher than Figure 1D The upper surface 42' of the structure 42 shown. In some embodiments, the liquid level 46' of the cleaning fluid 46 is approximately equal to... Figure 1D The upper surface 42' of the structure 42 shown. In some embodiments, the liquid level 46' of the cleaning fluid 46 is approximately lower than... Figure 1D The upper surface 42' of the structure 42 shown. In this disclosure, Figure 1D The flux in structure 42 shown can be removed by immersing it in cleaning solution 46, and... Figure 1D The upper surface 42' of the structure 42 shown may be approximately below, above, or equal to the liquid surface 46' of the cleaning fluid 46. In some embodiments, the cleaning fluid 46 may comprise an alkaline solution, such as 2-amino-2-methyl-1-propanol, diethylene glycol monobutyl ether, triethylene glycol monobutyl ether, ethylaminoethanol, diethanol, benzyl alcohol, or a mixture thereof, or optionally a mixture of several of the foregoing, but this disclosure is not limited thereto. In some embodiments, the temperature of the cleaning fluid 46 is approximately between 55°C and 65°C.

[0060] Next, as Figure 2B As shown, it will contain Figure 1D The structure 42 shown, along with the container 44 containing the cleaning fluid 46, is placed in an ultrasonic vibrator 48 for an ultrasonic washing step 50. In some embodiments, the frequency of the ultrasonic washing step 50 is approximately 40 kHz. In some embodiments, the temperature of the ultrasonic washing step 50 is approximately between 55°C and 65°C. In some embodiments, the duration of the ultrasonic washing step 50 is approximately between 1 minute and 2 minutes. Figure 2B In the middle, it will be equipped with Figure 1D The structure 42 shown is placed in an ultrasonic oscillator 48 along with a container 44 containing the cleaning fluid 46 for an ultrasonic cleaning step 50 to remove the flux. In some embodiments, a separate container containing the cleaning fluid 46 can also be used. Figure 1D The container 44 of the structure 42 shown is placed in an ultrasonic oscillator 48 for an ultrasonic oscillation step to remove flux. In some embodiments, a container containing... Figure 1DThe structure 42 shown is placed in an ultrasonic oscillator 48 with a container 44 containing a general solution (e.g., deionized water) for an ultrasonic cleaning step to remove flux.

[0061] Next, as Figure 2C As shown, the structure 54 after ultrasonic rinsing step 50 is cleaned with deionized water 52 to remove all residue from the cleaning solution 46, which takes about 1 to 2 minutes.

[0062] Next, as Figure 2D As shown, a drying step 56 is performed on structure 54 to remove moisture and dry it. This completes the flux removal step, resulting in the desired product. Figure 1E The structure is shown. In some embodiments, an air gun can be used to remove and dry the moisture on structure 54, but this disclosure is not limited thereto. In some embodiments, other suitable methods can also be used to remove and dry the moisture on structure 54.

[0063] Please see Figure 1F According to one embodiment of the present disclosure, an electronic device 40 is provided. Figure 1F This is a cross-sectional schematic diagram of electronic device 40.

[0064] like Figure 1F As shown, the electronic device 40 includes a substrate 10, a first insulating layer 12, a second insulating layer 14, a patterned metal layer 16, a pixel defining layer (PDL) 18, a metal layer 20 (including a first bonding structure 22a and a second bonding structure 22b), solder 24, a first bonding pad 30a, a second bonding pad 30b, a body 28, and an adhesive 34. The first insulating layer 12 is formed on the substrate 10. The second insulating layer 14 is formed on the first insulating layer 12. The patterned metal layer 16 is formed on the second insulating layer 14, exposing a portion of the second insulating layer 14. The pixel defining layer 18 is formed on the patterned metal layer 16 and the exposed second insulating layer 14, exposing a portion of the patterned metal layer 16. The metal layer 20 is formed on the exposed patterned metal layer 16 to define the first bonding structure 22a and the second bonding structure 22b, corresponding to the bonding pads of subsequently bonded electronic components. Solder 24 is formed on the first bonding structure 22a and the second bonding structure 22b of the substrate 10. Electronic component 27 is bonded to solder 24 via first bonding pad 30a and second bonding pad 30b. Adhesive 34 is formed on the substrate 10 and surrounds the electronic component 27 and is located between the first bonding structure 22a and the second bonding structure 22b.

[0065] In some embodiments, substrate 10 may include a rigid substrate or a flexible substrate, such as a glass substrate or a polyimide (PI) substrate, but this disclosure is not limited thereto. In some embodiments, the first insulating layer 12 and the second insulating layer 14 may include silicon oxide, silicon nitride, or silicon oxynitride, but this disclosure is not limited thereto. In some embodiments, the patterned metal layer 16 may include copper, but this disclosure is not limited thereto. In some embodiments, the pixel defining layer 18 may include resin, silicone, or silicon oxide, but this disclosure is not limited thereto. In some embodiments, the metal layer 20 (including the first bonding structure 22a and the second bonding structure 22b) may include nickel, but this disclosure is not limited thereto. In some embodiments, the solder 24 may include tin or a tin-bismuth alloy, but this disclosure is not limited thereto.

[0066] In some embodiments, electronic component 27 may include a light-emitting diode (LED), such as an organic light-emitting diode (OLED), a mini LED, a micro LED, or a quantum dot LED, but this disclosure is not limited thereto. In some embodiments, the thickness H of electronic component 27 is approximately 600 micrometers. In some embodiments, the first bonding pad 30a and the second bonding pad 30b may include copper, but this disclosure is not limited thereto.

[0067] In some embodiments, the Young's modulus of the adhesive 34 is between approximately 1 MPa and approximately 100 MPa. In some embodiments, the adhesive 34 may comprise white glue (e.g., silicone-based), optical glue, or waterproof glue, but this disclosure is not limited thereto. In some embodiments, the thickness h of the adhesive 34 (from the upper surface 18' of the pixel definition layer 18 to the top 34' of the adhesive 34) is between approximately 50 micrometers and approximately 600 micrometers. Here, the height from the upper surface 18' of the pixel definition layer 18 to the upper surface 28' of the body 28 of the electronic component 27 is defined as K. In some embodiments, the height K is between approximately 600 micrometers and approximately 640 micrometers. It is noteworthy that the thickness h of the adhesive 34 does not exceed the height K.

[0068] Experimental Examples

[0069] The proportion of electronic devices that develop cracks in their substrate after thermal shock.

[0070] Provide such as Figure 1FThe electronic device 40 shown has the following components, layers, materials, and dimensions: Substrate 10 is a glass substrate. The first insulating layer 12 and the second insulating layer 14 are made of silicon oxide. The patterned metal layer 16 is made of copper. The pixel definition layer 18 is made of silicon nitride. The metal layer 20 (including the first bonding structure 22a and the second bonding structure 22b) is made of nickel. The solder 24 is made of tin. The electronic component 27 is a sub-millimeter light-emitting diode (mini LED) with a thickness H of approximately 600 micrometers. The first bonding pad 30a and the second bonding pad 30b are made of copper. The adhesive 34 is white adhesive with a thickness h of approximately 100 micrometers. In this embodiment, the electronic device is constructed by forming the adhesive 34 on the substrate 10 after removing the flux, surrounding the electronic component 27 and located between the first bonding structure 22a and the second bonding structure 22b.

[0071] Next, the electronic device was subjected to a thermal shock test. The thermal shock test conditions were as follows: the temperature was approximately between -40°C and 80°C, and the test was conducted for 339 cycles. After the test, the proportion of cracks appearing on the substrate was observed, and the results are shown in Table 1 below.

[0072] Experimental Example 1

[0073] The proportion of electronic devices that develop cracks in their substrate after thermal shock.

[0074] Provide such as Figure 1D The electronic device shown is described below. The materials and dimensions of each component and layer are as follows: Substrate 10 is a glass substrate. The materials of the first insulating layer 12 and the second insulating layer 14 are silicon oxide. The material of the patterned metal layer 16 is copper. The material of the pixel definition layer 18 is resin, silicone, or silicon oxide. The material of the metal layer 20 (including the first bonding structure 22a and the second bonding structure 22b) is nickel. The material of the solder 24 is tin. The composition of the flux 26 includes rosin, organic acid, ethanol, and thickener. The electronic component 27 is a sub-millimeter light-emitting diode (mini LED) with a thickness H of approximately 600 micrometers. The materials of the first bonding pad 30a and the second bonding pad 30b are copper. In this comparative example electronic device, the flux 26 was not removed, and no adhesive was applied. The flux 26 is formed on the substrate 10 and surrounds the electronic component 27 and is located between the first bonding structure 22a and the second bonding structure 22b.

[0075] Next, the electronic device was subjected to a thermal shock test. The thermal shock test conditions were as follows: the temperature was approximately between -40°C and 80°C, and the test was conducted for 339 cycles. After the test, the proportion of cracks appearing on the substrate was observed, and the results are shown in Table 1 below.

[0076] Comparative Example 2

[0077] The proportion of electronic devices that develop cracks in their substrate after thermal shock.

[0078] Provide similar Figure 1D The electronic device shown is described below. The materials and dimensions of each component and layer are as follows: Substrate 10 is a glass substrate. The materials of the first insulating layer 12 and the second insulating layer 14 are silicon oxide. The material of the patterned metal layer 16 is copper. The material of the pixel definition layer 18 is resin, silicone, or silicon oxide. The material of the metal layer 20 (including the first bonding structure 22a and the second bonding structure 22b) is nickel. The material of the solder 24 is tin. The composition of the flux 26 includes rosin, organic acid, ethanol, and thickener. The electronic component 27 is a sub-millimeter light-emitting diode (mini LED) with a thickness H of approximately 600 micrometers. The materials of the first bonding pad 30a and the second bonding pad 30b are copper. The difference between this comparative example electronic device and the electronic device of Comparative Example 1 is that the flux 26 in this comparative example electronic device is not removed, but some adhesive is applied.

[0079] Next, the electronic device was subjected to a thermal shock test. The thermal shock test conditions were as follows: the temperature was approximately between -40°C and 80°C, and the test was conducted for 339 cycles. After the test, the proportion of cracks appearing on the substrate was observed, and the results are shown in Table 1 below.

[0080] Table 1

[0081]

[0082] Here, the "proportion" of substrate cracks is defined as the number of cracks found in a sample of 100 units. Table 1 shows that when flux was not removed from the electronic device and no adhesive was applied, the proportion of substrate cracks was as high as 100% (Comparative Example 1). Although Comparative Example 2 applied some adhesive without removing flux, the proportion of substrate cracks remained quite high, decreasing by only about 6%. This reduction was insufficient to improve product reliability, likely due to the flux affecting the adhesion of the adhesive to the substrate. In contrast, the electronic device of this disclosure, after removing flux, continued to form adhesive on the substrate, surrounding the electronic components and the first and second bonding pads. After thermal shock testing, the proportion of substrate cracks significantly decreased, demonstrating that applying adhesive after removing flux can effectively improve product reliability.

[0083] This disclosure involves cleaning residual flux after the substrate is soldered and applying white adhesive, which significantly reduces the proportion of glass cracks on the substrate and effectively improves product reliability. After soldering the glass substrate to the electronic component (e.g., a light-emitting diode (LED)), the flux on the substrate is removed with a cleaning solution. After flux removal, an adhesive (e.g., white adhesive, optical adhesive, waterproof adhesive, etc.) is applied to the substrate to absorb stress, reduce the maximum stress between the electronic component and the thin-film transistor (TFT) glass substrate, further reduce the proportion of glass cracking after thermal shock, and ultimately improve product reliability. This disclosure reduces the proportion of cracks in the glass beneath the electronic component from 100% to 0%.

[0084] The components of some embodiments described above are provided to enable those skilled in the art to better understand the viewpoints of the embodiments described herein. Those skilled in the art should understand that they can design or modify other processes and structures based on the embodiments described herein to achieve the same purpose and / or advantages as the embodiments described herein. Those skilled in the art should also understand that such equivalent structures do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and replacements can be made without departing from the spirit and scope of this disclosure. Therefore, the scope of protection of this disclosure is determined by the claims. Furthermore, although this disclosure has been described above with reference to several preferred embodiments, it is not intended to limit this disclosure.

[0085] References to features, advantages, or similar language throughout this specification are not intended to imply that all features and advantages achievable using this disclosure should or may be implemented in any single embodiment of this disclosure. Rather, language relating to features and advantages is to be understood as meaning that a particular feature, advantage, or characteristic described in connection with an embodiment is included in at least one embodiment of this disclosure. Thus, the discussion of features and advantages, as well as similar language, throughout this specification may, but does not necessarily, represent the same embodiments.

[0086] Furthermore, in one or more embodiments, the features, advantages, and characteristics described in this disclosure may be combined in any suitable manner. Based on the description herein, those skilled in the art will recognize that this disclosure may be implemented without one or more specific features or advantages of a particular embodiment. In other instances, additional features and advantages may be identified in certain embodiments that may not be present in all embodiments of this disclosure.

Claims

1. A method for manufacturing an electronic device, characterized in that: Provide a substrate; A patterned metal layer is formed on the substrate; A solder and a flux are formed on the substrate; An electronic component is bonded to the solder, wherein the electronic component is bonded to the patterned metal layer through the solder. as well as Remove at least a portion of the flux; as well as An adhesive is formed on the substrate, wherein the Young's coefficient of the adhesive is between 1 MPa and 100 MPa, in order to absorb the stress caused by the mismatch in the coefficients of thermal expansion between the electronic component and the substrate.

2. The method for manufacturing an electronic device as claimed in claim 1, characterized in that, The step of removing at least a portion of the flux includes immersing the substrate to which the electronic component is bonded in a cleaning solution.

3. The method for manufacturing an electronic device as described in claim 2, characterized in that, The step of removing at least a portion of the flux further includes drying the substrate to which the electronic component is bonded.

4. The method for manufacturing an electronic device as claimed in claim 1, characterized in that, The step of removing at least a portion of the flux includes ultrasonically cleaning the substrate to which the electronic component is bonded.

5. The method for manufacturing an electronic device as claimed in claim 1, characterized in that, The electronic component includes a bonding pad that bonds the solder, and an adhesive material that surrounds the bonding pad in a top view of the electronic device.

6. The method for manufacturing an electronic device as claimed in claim 1, characterized in that, The adhesive material surrounds the electronic components in the top view of the electronic device.

7. An electronic device, characterized in that: One substrate; A patterned metal layer is applied to the substrate; An electronic component, including a plurality of bonding pads on the patterned metal layer; and An adhesive material is located between the plurality of bonding pads, wherein the Young's coefficient of the adhesive material is between 1 MPa and 100 MPa, to absorb the stress caused by the mismatch of the coefficients of thermal expansion between the electronic component and the substrate.

8. The electronic device as claimed in claim 7, characterized in that, The thickness of the adhesive material ranges from 50 micrometers to 600 micrometers.

9. The electronic device of claim 7, further comprising a metal layer located between the substrate and the plurality of bonding pads of the electronic component.

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