Low-voltage chip detects external high-voltage circuit

Abstract

The application discloses a low-voltage chip detection external high-voltage circuit and relates to the field of integrated circuit design. The low-voltage chip detection external high-voltage circuit comprises a chip external detection module, a chip internal detection module and an auxiliary comparison module. The chip external detection module is used for detecting the external voltage of the chip, sampling whether the external voltage exceeds the reference voltage, and outputting the voltage when the external voltage exceeds the reference voltage. The chip internal detection module is used for detecting the internal voltage of the chip, sampling whether the internal voltage exceeds the reference voltage, and outputting the voltage when the internal voltage exceeds the reference voltage. The auxiliary comparison module is used for confirming whether the sampled external voltage is normal. Compared with the prior art, the application has the beneficial effects that the chip external detection module can detect the to-be-detected voltage exceeding the highest withstand voltage of the chip itself, the detection output module outputs a high level to indicate when the to-be-detected voltage is too large, and the chip internal detection module is arranged at the same time, and the to-be-detected voltage lower than the highest withstand voltage of the chip itself is detected when the chip external detection module is faulty.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of integrated circuit design, and particularly relates to a low-voltage chip detecting external high-voltage circuit. BACKGROUND

[0002] The high-voltage detection circuit is used for detecting whether the current to-be-detected voltage reaches the "high-voltage" standard, and then selecting whether to take protective measures according to whether the "high-voltage" is reached. Please refer to Figure 1 The conventional detection circuit is generally composed of to-be-detected voltage VEE, resistors R1 and R2 for voltage division, an LDO voltage stabilizer, a comparator A0 and an RS flip-flop. The resistors R1 and R2 can be externally connected or integrated in the chip. As shown in Figure 2 VREF is generally much greater than Vcs. After power-on, the R end positive pulse resets the RS flip-flop, and the Q end is reset to 0 level. At this time, since Vcs is much smaller than VREF, the S end is 0. When VEE starts to increase, Vcs increases through resistor voltage division. When Vcs is greater than VREF, the comparator A0 outputs S from 0 to 1, and the Q end flips to 1 level, and VEE exceeds the set maximum value.

[0003] The chip needs to withstand the VEE voltage. The high-voltage detection circuit in the chip usually detects the highest voltage that does not exceed the highest voltage of the chip itself. The cost is high, and the applicability is not strong, which needs to be improved. SUMMARY

[0004] The present application aims to provide a low-voltage chip detecting external high-voltage circuit to solve the problems in the background art.

[0005] To achieve the above-mentioned purpose, the present application provides the following technical scheme:

[0006] A low-voltage chip detecting external high-voltage circuit, comprising:

[0007] A chip external detection module for detecting the voltage outside the chip, sampling whether the external voltage exceeds the reference voltage, and outputting the voltage when exceeding;

[0008] A chip internal detection module for detecting the voltage inside the chip, sampling whether the internal voltage exceeds the reference voltage, and outputting the voltage when exceeding;

[0009] An auxiliary comparison module for confirming whether the sampled external voltage is normal. When normal, the first RS trigger module is driven to work. When abnormal, the second RS trigger module is driven to work;

[0010] A first RS trigger module for triggering the detection output module to output the voltage when the chip external detection module outputs the voltage;

[0011] A second RS trigger module for triggering the detection output module to output the voltage when the chip internal detection module outputs the voltage;

[0012] The detection output module is configured to output a voltage indicating that the to-be-detected voltage is too large.

[0013] The chip-external detection module is connected with the first RS trigger module and the auxiliary comparison module, the chip-internal detection module is connected with the second RS trigger module, the auxiliary comparison module is connected with the first RS trigger module and the second RS trigger module, the first RS trigger module is connected with the detection output module, and the second RS trigger module is connected with the detection output module.

[0014] As a further scheme of the present application, the chip-external detection module comprises a to-be-detected voltage VEE, a resistor R12, a resistor R11, a field effect transistor M2 and an amplifier A2, one end of the resistor R12 is connected with the to-be-detected voltage VEE, the other end of the resistor R12 is connected with one end of the resistor R11, the auxiliary comparison module, the non-inverting terminal of the amplifier A2 and the first end of the field effect transistor M2, the second end of the field effect transistor M2 is grounded, the third end of the field effect transistor M2 is connected with the inverting terminal of the amplifier A2 and the reference voltage VREF, and the output terminal of the amplifier A2 is connected with the first RS trigger module.

[0015] As a further scheme of the present application, the chip-internal detection module comprises a to-be-detected voltage VDD, a resistor R2, a resistor R1 and an amplifier A1, one end of the resistor R2 is connected with the to-be-detected voltage VDD, the other end of the resistor R2 is connected with one end of the resistor R1 and the non-inverting terminal of the amplifier A1, the other end of the resistor R1 is grounded, the inverting terminal of the amplifier A1 is connected with the reference voltage VREF, and the output terminal of the amplifier A1 is connected with the second RS trigger module.

[0016] As a further scheme of the present application, the auxiliary comparison module comprises an amplifier A3 and an inverter U3, the non-inverting terminal of the amplifier A3 is connected with the chip-external detection module, the inverting terminal of the amplifier A3 is connected with the reference voltage VREF1, the output terminal of the amplifier A3 is connected with the first RS trigger module and the input terminal of the inverter U3, and the output terminal of the inverter U3 is connected with the second RS trigger module.

[0017] As a further scheme of the present application, the first RS trigger module comprises an RS flip-flop U2 and a NAND gate U5, the S terminal of the RS flip-flop U2 is connected with the chip-external detection module, the R terminal of the RS flip-flop U2 is connected with a reset signal, one end of the input terminal of the NAND gate U5 is connected with the Q terminal of the RS flip-flop U2, the other end of the input terminal of the NAND gate U5 is connected with the output terminal of the amplifier A3, and the output terminal of the NAND gate U5 is connected with the detection output module.

[0018] As a further scheme of the present application: the second RS trigger module comprises an RS flip-flop U1 and a NAND gate U4, the S terminal of the RS flip-flop U1 is connected with the chip internal detection module, the R terminal of the RS flip-flop U1 is connected with the reset signal, the Q terminal of the RS flip-flop U1 is connected with one end of the input terminal of the NAND gate U4, the other end of the input terminal of the NAND gate U4 is connected with the output terminal of the inverter U3, and the output terminal of the NAND gate U4 is connected with the detection output module.

[0019] As a further scheme of the present application: the detection output module comprises a NAND gate U6, one end of the input terminal of the NAND gate U6 is connected with the first RS trigger module, and the other end of the input terminal of the NAND gate U6 is connected with the second RS trigger module.

[0020] Compared with the prior art, the present application has the beneficial effects that: the chip external detection module can detect the to-be-detected voltage exceeding the highest withstand voltage of the chip itself, and the detection output module outputs a high level to indicate when the to-be-detected voltage is too large; meanwhile, the chip internal detection module is arranged to detect the to-be-detected voltage lower than the highest withstand voltage of the chip itself when the chip external detection module fails. BRIEF DESCRIPTION OF DRAWINGS

[0021] Figure 1 It is a schematic diagram of a conventional detection circuit.

[0022] Figure 2 It is a node waveform diagram of the conventional detection circuit.

[0023] Figure 3 It is a schematic diagram of a low-voltage chip detection external high-voltage circuit. DETAILED DESCRIPTION

[0024] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor fall within the scope of protection of the present application.

[0025] Please refer to Figure 3 A low-voltage chip detection external high-voltage circuit comprises:

[0026] A chip external detection module is used to detect the external voltage of the chip, sample whether the external voltage exceeds the reference voltage, and output a voltage when it exceeds.

[0027] A chip internal detection module is used to detect the internal voltage of the chip, sample whether the internal voltage exceeds the reference voltage, and output a voltage when it exceeds.

[0028] An auxiliary comparison module is configured to determine whether the sampled external voltage is normal, and drive the first RS trigger module to work when the external voltage is normal, and drive the second RS trigger module to work when the external voltage is abnormal.

[0029] The first RS trigger module is configured to trigger the detection output module to output a voltage when the chip external detection module outputs a voltage.

[0030] The second RS trigger module is configured to trigger the detection output module to output a voltage when the chip internal detection module outputs a voltage.

[0031] The detection output module is configured to output a voltage indicating that the to-be-detected voltage is too large.

[0032] The chip external detection module is connected with the first RS trigger module and the auxiliary comparison module, the chip internal detection module is connected with the second RS trigger module, the auxiliary comparison module is connected with the first RS trigger module and the second RS trigger module, the first RS trigger module is connected with the detection output module, and the second RS trigger module is connected with the detection output module.

[0033] In the embodiment, as shown in Figure 3 , the chip external detection module comprises a to-be-detected voltage VEE, a resistor R12, a resistor R11, a field effect transistor M2, and an amplifier A2, one end of the resistor R12 is connected with the to-be-detected voltage VEE, the other end of the resistor R12 is connected with one end of the resistor R11, the auxiliary comparison module, the non-inverting terminal of the amplifier A2, and the first end of the field effect transistor M2, the second end of the field effect transistor M2 is grounded, the third end of the field effect transistor M2 is connected with the inverting terminal of the amplifier A2 and the reference voltage VREF, and the output end of the amplifier A2 is connected with the first RS trigger module.

[0034] The to-be-detected voltage VEE is divided by the resistor R11 and the resistor R12 and then output to the non-inverting terminal of the amplifier A2, wherein the field effect transistor M2 functions as a voltage clamping device, when the to-be-detected voltage VEE is very high, the voltage at the non-inverting terminal of the amplifier A2 is clamped at the reference voltage VREF plus the opening voltage of the field effect transistor M2, so that the amplifier A2 will not be broken down due to the to-be-detected voltage VEE being too high. When the to-be-detected voltage VEE exceeds the normal voltage, the voltage at the non-inverting terminal of the amplifier A2 is higher than the reference voltage VREF at the inverting terminal, the amplifier A2 outputs a high level, and outputs the high level to the first RS trigger module.

[0035] In the embodiment, as shown in Figure 3 , the chip internal detection module comprises a to-be-detected voltage VDD, a resistor R2, a resistor R1, and an amplifier A1, one end of the resistor R2 is connected with the to-be-detected voltage VDD, the other end of the resistor R2 is connected with one end of the resistor R1 and the non-inverting terminal of the amplifier A1, the other end of the resistor R1 is grounded, the inverting terminal of the amplifier A1 is connected with the reference voltage VREF, and the output end of the amplifier A1 is connected with the second RS trigger module.

[0036] When the voltage VDD to be measured exceeds the normal voltage, the voltage at the non-inverting terminal of the amplifier A1 is higher than the reference voltage VREF at the inverting terminal, the amplifier A1 outputs a high level, and the output is provided to the second RS trigger module.

[0037] In the embodiment, as shown in Figure 3 , the auxiliary comparison module comprises an amplifier A3 and an inverter U3, the non-inverting terminal of the amplifier A3 is connected to the chip external detection module, the inverting terminal of the amplifier A3 is connected to the reference voltage VREF1, the output terminal of the amplifier A3 is connected to the input terminal of the inverter U3 and the first RS trigger module, and the output terminal of the inverter U3 is connected to the first RS trigger module.

[0038] The reference voltage VREF1 is much smaller than the reference voltage VREF, so that when the chip external detection module is normal, the voltage at the non-inverting terminal of the amplifier A3 is higher than the reference voltage VREF1 at the inverting terminal, the amplifier A3 outputs a high level, and the output is provided to the second RS trigger module; when the chip external detection module is abnormal and disconnected, the voltage at the non-inverting terminal of the amplifier A3 is lower than the reference voltage VREF1 at the inverting terminal, the amplifier A3 outputs a low level, and the output is provided to the second RS trigger module after being inverted by the inverter U3.

[0039] In the embodiment, as shown in Figure 3 , the first RS trigger module comprises an RS flip-flop U2 and a NAND gate U5, the S terminal (S2 in the figure) of the RS flip-flop U2 is connected to the chip external detection module, the R terminal of the RS flip-flop U2 is connected to a reset signal, the Q terminal (Q2 in the figure) of the RS flip-flop U2 is connected to one input terminal of the NAND gate U5, the other input terminal of the NAND gate U5 is connected to the output terminal of the amplifier A3, and the output terminal of the NAND gate U5 is connected to the detection output module.

[0040] When the high level output by the chip external detection module and the high level output by the auxiliary comparison module are received, a trigger signal is provided for the detection output module.

[0041] In the embodiment, as shown in Figure 3 , the second RS trigger module comprises an RS flip-flop U1 and a NAND gate U4, the S terminal (S1 in the figure) of the RS flip-flop U1 is connected to the chip internal detection module, the R terminal of the RS flip-flop U1 is connected to a reset signal, the Q terminal (Q1 in the figure) of the RS flip-flop U1 is connected to one input terminal of the NAND gate U4, the other input terminal of the NAND gate U4 is connected to the output terminal of the inverter U3, and the output terminal of the NAND gate U4 is connected to the detection output module.

[0042] When the high level output by the chip internal detection module and the high level output by the auxiliary comparison module are received, a trigger signal is provided for the detection output module.

[0043] In the embodiment, as shown inFigure 3 The detection output module is connected with the NOT gate U6, one end of the input end of the NOT gate U6 is connected with the first RS trigger module, and the other end of the input end of the NOT gate U6 is connected with the second RS trigger module.

[0044] Compared with the prior art, the chip process no longer uses the high-voltage process compatible with VEE, but uses a low-voltage process with a lower cost, such as a 5V CMOS process, the amplifier A1 is a comparator for detecting the internal voltage VDD after voltage division by resistors R1 and R2, the amplifier A2 is a comparator for detecting the external voltage to be measured VEE after voltage division by resistors R12 and R11, and the amplifier A3 is an auxiliary comparator, after power-on, the reset signal R resets the two RS flip-flops U1 and U2, at this time, Q1 and Q2 are both low, the output of the NOT gate U6 is 0, the reference voltage VREF1 is much smaller than VREF, and the amplifier A3 detects the size of the sampling voltage Vcs2 of the chip external detection module, if Vcs2 is greater than VREF1, it is proved that the resistors R12 and R11 are effectively connected, at this time, Ext_if1 is high, and the chip selects the voltage detection path of the external resistor (the chip external detection module), if Vcs2 is less than VREF1, it is judged that the resistors R12 and R11 are invalidly connected, Int_if1 is high, and the chip selects the voltage detection path of the built-in resistors R2 and R1 (the chip internal detection module). When the external resistor R12 and R11 path is selected, if the voltage to be measured VEE is high enough, Vcs2>VREF, the output of the NOT gate U6 is high, and when the built-in resistors R2 and R1 are selected, if the voltage to be measured VDD is high enough, Vcs1>VREF, the output of the NOT gate U6 is high. Due to the existence of the field effect transistor M2, when the voltage to be measured VEE is very high, the voltage of Vcs2 is clamped at VREF plus the opening voltage Vth of M2, so that A2 is prevented from being broken down due to too high VEE.

[0045] The working principle of the application is that: the chip external detection module detects the chip external voltage, samples whether the external voltage exceeds the reference voltage, and outputs the voltage when exceeding; the chip internal detection module detects the chip internal voltage, samples whether the internal voltage exceeds the reference voltage, and outputs the voltage when exceeding; the auxiliary comparison module confirms whether the sampled external voltage is normal, drives the first RS trigger module to work when normal, and drives the second RS trigger module to work when abnormal; the first RS trigger module triggers the detection output module to output the voltage when the chip external detection module outputs the voltage; the second RS trigger module triggers the detection output module to output the voltage when the chip internal detection module outputs the voltage; and the detection output module outputs the voltage to indicate that the voltage to be measured is too large.

[0046] It will be obvious to a person skilled in the art that the application is not limited to the details of the foregoing exemplary embodiments and can be implemented in other concrete forms without departing from the spirit or essential characteristics of the application. The embodiments are therefore to be considered in all respects as illustrative and not restrictive, the scope of the application being indicated by the appended claims rather than by the foregoing description, and all changes which come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein. No reference signs in the claims should be considered as limiting the scope of the claims to the identity of the reference signs therein.

[0047] Furthermore, it should be understood that although the description is made on the basis of the embodiments, not every embodiment contains only one independent technical solution, and the description of the specification is only for the sake of clarity, and those skilled in the art should consider the specification as a whole, and the technical solutions in each embodiment can also be appropriately combined to form other embodiments that those skilled in the art can understand.

Claims

1. A low-voltage chip detects external high-voltage circuit, characterized in that: The low-voltage chip detects external high-voltage circuit includes: Chip external detection module, for detecting chip external voltage, sampling external voltage is beyond the reference voltage, when output voltage; Chip internal detection module, for detecting chip internal voltage, sampling internal voltage is beyond the reference voltage, when output voltage; Auxiliary comparison module, for confirming whether the sampling external voltage is normal, when driving the first RS trigger module to work; when driving the second RS trigger module to work; The first RS trigger module is used for triggering the detection output module to output voltage when the chip external detection module outputs voltage; The second RS trigger module is used for triggering the detection output module to output voltage when the chip internal detection module outputs voltage; Detection output module, for output voltage indication to be measured voltage is too large; Chip external detection module connects the first RS trigger module, auxiliary comparison module, chip internal detection module connects the second RS trigger module, auxiliary comparison module connects the first RS trigger module, second RS trigger module, first RS trigger module connects detection output module, second RS trigger module connects detection output module.

2. The low voltage chip detects external high voltage circuit according to claim 1, characterized in that, Chip external detection module includes the voltage to be measured VEE, resistance R12, resistance R11, field effect tube M2, amplifier A2, one end of resistance R12 is connected with the voltage to be measured VEE, the other end of resistance R12 is connected with one end of resistance R11, auxiliary comparison module, the same phase end of amplifier A2, the first end of field effect tube M2, the second end of field effect tube M2 is grounded, the third end of field effect tube M2 is connected with the opposite phase end of amplifier A2, reference voltage VREF, the output end of amplifier A2 is connected with the first RS trigger module.

3. The low voltage chip to detect external high voltage circuit of claim 1, wherein, Chip internal detection module includes the voltage to be measured VDD, resistance R2, resistance R1, amplifier A1, one end of resistance R2 is connected with the voltage to be measured VDD, the other end of resistance R2 is connected with one end of resistance R1, the same phase end of amplifier A1, the other end of resistance R1 is grounded, the opposite phase end of amplifier A1 is connected with reference voltage VREF, the output end of amplifier A1 is connected with the second RS trigger module.

4. The low voltage chip to detect external high voltage circuit of claim 1, wherein, Auxiliary comparison module includes amplifier A3, inverter U3, the same phase end of amplifier A3 is connected with chip external detection module, the opposite phase end of amplifier A3 is connected with reference voltage VREF1, the output end of amplifier A3 is connected with the first RS trigger module, the input end of inverter U3, the output end of inverter U3 is connected with the second RS trigger module.

5. The low voltage chip to detect external high voltage circuit of claim 4, wherein, The first RS trigger module includes RS trigger U2, NAND gate U5, the S end of RS trigger U2 is connected with chip external detection module, the R end of RS trigger U2 is connected with reset signal, the Q end of RS trigger U2 is connected with one end of the input end of NAND gate U5, the other end of the input end of NAND gate U5 is connected with the output end of amplifier A3, the output end of NAND gate U5 is connected with detection output module.

6. The low voltage chip to detect external high voltage circuit of claim 4, wherein, The second RS trigger module comprises an RS flip-flop U1 and a NAND gate U4, the S terminal of the RS flip-flop U1 is connected with the chip internal detection module, the R terminal of the RS flip-flop U1 is connected with a reset signal, the Q terminal of the RS flip-flop U1 is connected with one end of the input terminal of the NAND gate U4, the other end of the input terminal of the NAND gate U4 is connected with the output terminal of an inverter U3, and the output terminal of the NAND gate U4 is connected with the detection output module.

7. The low voltage chip to detect external high voltage circuit of claim 1, wherein, The detection output module comprises a NAND gate U6, one end of the input terminal of the NAND gate U6 is connected with the first RS trigger module, and the other end of the input terminal of the NAND gate U6 is connected with the second RS trigger module.

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