An LDO circuit

Abstract

The present invention discloses an LDO circuit, comprising: an error amplifier circuit, whose positive input terminal is connected to a reference voltage; a first adjustment circuit, whose input terminal is connected to the output terminal of the error amplifier circuit; the first adjustment circuit includes an NMOS adjustment transistor, and the gate terminal of the NMOS adjustment transistor is the input terminal of the first adjustment circuit; a second adjustment circuit, whose input terminal is connected to the output terminal of the first adjustment circuit; the second adjustment circuit includes an NPN adjustment transistor, and the base of the NPN adjustment transistor is the input terminal of the second adjustment circuit; a feedback circuit, which is connected to the output terminal of the second adjustment circuit; the feedback circuit includes a first feedback resistor and a second feedback resistor connected in series, and the negative input terminal of the error amplifier circuit is connected between the first feedback resistor and the second feedback resistor. In the LDO circuit of the present invention, its frequency compensation circuit is relatively simple, has high stability, high power supply rejection ratio, and low load regulation rate.

Description

Technical Field

[0001] The present invention relates to the field of analog integrated circuit technology, and particularly to an LDO circuit. Background Art

[0002] A Low Dropout Regulator (LDO) is a voltage regulator that can only output a regulated power supply voltage lower than the input voltage (external power supply): Analyzing from the working principle of the LDO, the LDO adjusts the on-resistance of the output adjustment transistor according to the change of the resistance-capacitance load at the output end, changes the voltage division ratio of the resistors in the feedback network, so as to achieve a stable voltage output at the output end; the output adjustment transistor can be regarded as a variable resistor, which is connected in series with the resistor in the feedback network in the loop at the output end, so the LDO linear regulator can only output an output voltage lower than the input voltage (external power supply) voltage.

[0003] Traditional LDOs need to externally connect a large output capacitor to play the roles of voltage regulation and filtering, and its self-equivalent series resistance (ESR) can also play the role of generating a zero point on the compensation plane to compensate for loop stability. However, since the large capacitor occupies a large area, it is not conducive to integration on the chip, and even when placed outside the chip, it requires additional pins, increasing the available cost; secondly, considering the characteristics of the large capacitor itself, the stability of the compensation depends on the value of the ESR. However, the ESR value of the capacitor will be affected by various characteristics such as temperature, process, and usage time. Deviating from the available range will cause the performance of the LDO to deteriorate, greatly increasing the unreliability of the application. And stability is an important index of the LDO. The traditional LDO circuit uses a PMOS transistor as the adjustment transistor. Due to the existence of structures such as an error amplifier in the circuit itself, the system itself will form a multi-stage amplifier. According to the Barkhausen criterion, it can be known that if the multi-stage amplifier structure is not compensated, it is very easy to have circuit oscillations and make the system unstable. Therefore, a complex compensation circuit needs to be added to maintain the stability of the system. Summary of the Invention

[0004] Therefore, in order to solve the above problems in the prior art, the present application provides an LDO circuit with a relatively simple frequency compensation circuit, high stability, and high power supply rejection ratio.

[0005] The present invention provides an LDO circuit, including:

[0006] An error amplifier circuit, whose positive input terminal is connected to a reference voltage;

[0007] The first adjustment circuit, the input end of which is connected to the output end of the error amplifier circuit; the first adjustment circuit includes an NMOS adjustment transistor, and the gate terminal of the NMOS adjustment transistor is the input end of the first adjustment circuit;

[0008] The second adjustment circuit, the input end of which is connected to the output end of the first adjustment circuit; the second adjustment circuit includes an NPN adjustment transistor, and the base of the NPN adjustment transistor is the input end of the second adjustment circuit;

[0009] The feedback circuit, which is connected to the output end of the second adjustment circuit; the feedback circuit includes a first feedback resistor and a second feedback resistor connected in series, and the inverting input end of the error amplifier circuit is connected between the first feedback resistor and the second feedback resistor.

[0010] In a possible implementation, the first adjustment circuit includes:

[0011] A first NMOS transistor and a second NMOS transistor, the gate terminals of both are connected to the output end of the error amplifier circuit, and the drain terminals of both are connected to the high-level output terminal of the driving power supply;

[0012] A first PMOS transistor, a second PMOS transistor and a first current source, the source terminals of the first PMOS transistor and the second PMOS transistor are respectively connected to the source terminals of the first NMOS transistor and the second NMOS transistor, the gate terminal of the first PMOS transistor is connected to the gate terminal and the drain terminal of the second PMOS transistor, and the drain terminal of the second PMOS transistor is connected to the first current source.

[0013] In a possible implementation, the second adjustment circuit includes:

[0014] A first NPN transistor and a second NPN transistor, the base terminals of both are connected to the source terminal of the first NMOS transistor, and the collector terminals of both are connected to the high-level output terminal of the driving power supply;

[0015] A third PMOS transistor, a fourth PMOS transistor and a second current source, the source terminals of the third PMOS transistor and the fourth PMOS transistor are respectively connected to the emitter terminals of the first NPN transistor and the second NPN transistor, the gate terminal of the third PMOS transistor is connected to the gate terminal and the drain terminal of the fourth PMOS transistor, and the drain terminal of the fourth PMOS transistor is connected to the second current source.

[0016] In a possible implementation, the second adjustment circuit further includes:

[0017] A first adjustment resistor and a second adjustment resistor, the first adjustment resistor is connected between the collector of the first NPN transistor and the high-level output terminal of the driving power supply, and the second adjustment resistor is connected between the collector of the second NPN transistor and the high-level output terminal of the driving power supply.

[0018] In a possible implementation, the error amplifier circuit includes:

[0019] A fifth PMOS transistor and a sixth PMOS transistor, whose gate terminals are connected to each other, source terminals are both connected to the high-level output terminal of the driving power supply, and the gate terminal of the fifth PMOS transistor is also connected to its own drain terminal;

[0020] A third NMOS transistor and a fourth NMOS transistor, whose drain terminals are respectively connected to the drain terminals of the fifth PMOS transistor and the sixth PMOS transistor, and source terminals are both grounded;

[0021] A fifth NMOS transistor and a sixth NMOS transistor, whose source terminals are both grounded; the gate terminal and drain terminal of the fifth NMOS transistor are both connected to the gate terminal of the third NMOS transistor, and the gate terminal and drain terminal of the sixth NMOS transistor are both connected to the gate terminal of the fourth NMOS transistor;

[0022] A seventh PMOS transistor, an eighth PMOS transistor and a ninth PMOS transistor, the gate terminal of the seventh PMOS transistor is connected to the high-level output terminal of the driving power supply, a bias voltage is applied to the gate terminal, and the drain terminal is connected to the source terminals of the eighth PMOS transistor and the ninth PMOS transistor; the drain terminals of the eighth PMOS transistor and the ninth PMOS transistor are respectively connected to the drain terminal of the fifth NMOS transistor and the drain terminal of the sixth NMOS transistor

[0023] The gate terminal of the eighth PMOS transistor is connected to an inverting input signal, the gate terminal of the ninth PMOS transistor is connected to a non-inverting input signal, and the drain terminal of the sixth PMOS transistor outputs an output signal.

[0024] In a possible implementation, the error amplifier circuit further includes:

[0025] A first capacitor and a fifth resistor, which are connected in series, one end is connected to the drain terminal of the sixth PMOS transistor, and the other end is grounded.

[0026] The technical solution provided by the present invention has the following advantages:

[0027] 1. For the LDO circuit provided by the present invention, by setting the first adjustment circuit to include an NMOS adjustment transistor whose gate-source voltage Vgs is not affected by the power supply ripple, the power supply rejection ratio of the LDO circuit can be improved; by setting the first adjustment circuit including the NMOS adjustment transistor and the second adjustment circuit including the NPN adjustment transistor, the stability of the circuit can be improved, and it has the advantages of simple circuit structure, capable of driving a large load current, and low load regulation rate.

[0028] 2. For the LDO circuit provided by the present invention, by setting that the second adjustment circuit further includes a first adjustment resistor and a second adjustment resistor, the influence of power supply noise on the output can be reduced, and the stability of the circuit can be further improved.

[0029] 3. The error amplifier circuit provided by the present invention can improve the load regulation rate of the LDO circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] In order to more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the following will briefly introduce the drawings required for the description of the specific embodiments or the prior art. Obviously, the drawings in the following description are some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0031] Figure 1 It is a schematic diagram of the LDO circuit provided by a specific embodiment of the present invention;

[0032] Figure 2 It is a schematic diagram of the error amplifier circuit provided by a specific embodiment of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0033] The following will clearly and completely describe the technical solutions of the present invention with reference to the drawings. Obviously, the described embodiments are some embodiments of the present invention, rather than all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts fall within the protection scope of the present invention.

[0034] In the description of the present invention, it should be noted that the orientation or positional relationship indicated by terms such as "upper" and "lower" is based on the orientation or positional relationship shown in the drawings. It is only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation of the present invention. In addition, the terms "first", "second", and "third" are only used for descriptive purposes and cannot be understood as indicating or implying relative importance.

[0035] Figure 1 The structural schematic diagram of the LDO circuit in an embodiment of this embodiment is shown. Specifically, as Figure 1 shown, it includes an error amplifier circuit, a first adjustment circuit, a second adjustment circuit, and a feedback circuit.

[0036] Among them, the positive input terminal of the error amplifier circuit is connected to a reference voltage; the input terminal of the first adjustment circuit is connected to the output terminal of the error amplifier circuit; the first adjustment circuit includes an NMOS adjustment transistor, and the gate terminal of the NMOS adjustment transistor is the input terminal of the first adjustment circuit; the input terminal of the second adjustment circuit is connected to the output terminal of the first adjustment circuit; the second adjustment circuit includes an NPN adjustment transistor, and the base terminal of the NPN adjustment transistor is the input terminal of the second adjustment circuit; the feedback circuit is connected to the output terminal of the second adjustment circuit; the feedback circuit includes a first feedback resistor and a second feedback resistor connected in series, and the negative input terminal of the error amplifier circuit is connected between the first feedback resistor and the second feedback resistor.

[0037] Figure 1 The structural schematic diagram of the first adjustment circuit in a specific embodiment is also shown, as Figure 1 shown, the first adjustment circuit includes: a first NMOS transistor MN1 and a second NMOS transistor MN2, the gate terminals of both are connected to the output terminal of the error amplifier circuit, and the drain terminals are both connected to the high-level output terminal VDD of the drive power supply; a first PMOS transistor MP1, a second PMOS transistor MP2, and a first current source I1, the source terminals of the first PMOS transistor MP1 and the second PMOS transistor MP2 are respectively connected to the source terminals of the first NMOS transistor MN1 and the second NMOS transistor MN2, the gate terminal of the first PMOS transistor MP1 is connected to the gate terminal and the drain terminal of the second PMOS transistor MP2, and the drain terminal of the second PMOS transistor MP2 is connected to the first current source I1.

[0038] Specifically, the first NMOS transistor MN1 is the first-stage power transistor of the LDO circuit, used to reduce the static current of the circuit, and the second PMOS transistor MN2, the first PMOS transistor MP1, and the first current source I1 form a detection circuit to detect the output voltage of the error amplifier and feedback the voltage to the gate terminal of the second PMOS transistor MP2 to adjust the current of the second PMOS transistor MP2 branch. Specifically, both the first NMOS transistor MN1 and the second NMOS transistor MN2 are deep N-well isolation devices, thus eliminating the problem of increased threshold voltage caused by the body effect.

[0039] Figure 1 The structural schematic diagram of the second adjustment circuit in a specific embodiment is also shown, as Figure 1As shown, the second adjustment circuit includes: a first NPN transistor Q1 and a second NPN transistor Q2. The bases of both are connected to the source terminal of the first NMOS transistor MN1, and the collectors of both are connected to the high-level output terminal VDD of the driving power supply; a third PMOS transistor MP3, a fourth PMOS transistor MP4, and a second current source I2. The source terminals of the third PMOS transistor MP3 and the fourth PMOS transistor MP4 are respectively connected to the emitter terminals of the first NPN transistor Q1 and the second NPN transistor Q2. The gate terminal of the third PMOS transistor MP3 is connected to the gate terminal and the drain terminal of the fourth PMOS transistor MP4, and the drain terminal of the fourth PMOS transistor MP4 is connected to the second current source I2.

[0040] Specifically, the first NPN transistor Q1 serves as the second-stage power transistor of the LDO circuit and can drive a large load current. The second NPN transistor Q2, the fourth PMOS transistor MP4, and the second current source I2 form a second detection circuit to detect the output voltage of the first-stage power transistor (MN1) and feedback the result to the gate terminal of the third PMOS transistor MP3 to adjust the current in the branch of the third PMOS transistor MP3. Specifically, the ratio of the first NPN transistor Q1 to the second NPN transistor Q2 can be 8:1, which improves the current driving ability of the first NPN transistor Q1 on the premise of considering matching.

[0041] Figure 1 The structural schematic diagram of the second adjustment circuit in another specific implementation manner is also shown. As Figure 1 shown, on the basis of the above structure, the second adjustment circuit further includes a first adjustment resistor R3 and a second adjustment resistor R4. The first adjustment resistor R3 is connected between the collector of the first NPN transistor Q1 and the high-level output terminal VDD of the driving power supply, and the second adjustment resistor R4 is connected between the collector of the second NPN transistor Q2 and the high-level output terminal VDD of the driving power supply.

[0042] Specifically, the first adjustment resistor R3 and the second adjustment resistor R4 can reduce the influence of power supply noise on the output and further improve the stability of the circuit.

[0043] Figure 1 The structural schematic diagram of the feedback circuit in a specific implementation manner is also shown. As Figure 1 shown, the first feedback resistor and the second feedback resistor are respectively resistor R1 and resistor R2. In other specific implementation manners, both the first feedback resistor and the second feedback resistor can be multiple series resistors.

[0044] Figure 2 The structural schematic diagram of the error amplifier circuit in a specific implementation manner is shown. As Figure 2As shown, the error amplifier circuit includes a fifth PMOS transistor MP5 and a sixth PMOS transistor MP6. The gate terminals of the two are connected to each other, and the source terminals are both connected to the high-level output terminal VDD of the driving power supply. Moreover, the gate terminal of the fifth PMOS transistor MP5 is also connected to its own drain terminal; a third NMOS transistor MN3 and a fourth NMOS transistor MN4. The drain terminals of the two are respectively connected to the drain terminals of the fifth PMOS transistor MP5 and the sixth PMOS transistor MP6, and the source terminals of the two are both grounded; a fifth NMOS transistor MN5 and a sixth NMOS transistor MN6. The source terminals of the two are both grounded. The gate terminal and the drain terminal of the fifth NMOS transistor MN5 are both connected to the gate terminal of the third NMOS transistor MN3, and the gate terminal and the drain terminal of the sixth NMOS transistor MN6 are both connected to the gate terminal of the fourth NMOS transistor MN4; a seventh PMOS transistor MP7, an eighth PMOS transistor MP8, and a ninth PMOS transistor MP9. The gate terminal of the seventh PMOS transistor MP7 is connected to the high-level output terminal VDD of the driving power supply, and a bias voltage VB is connected to the gate terminal. The drain terminal is connected to the source terminal of the eighth PMOS transistor MP8 and the source terminal of the ninth PMOS transistor MP9; the drain terminal of the eighth PMOS transistor MP8 and the drain terminal of the ninth PMOS transistor MP9 are respectively connected to the drain terminal of the fifth NMOS transistor MN5 and the drain terminal of the sixth NMOS transistor MN6; the gate terminal of the eighth PMOS transistor MP8 is connected to an inverting input signal VIN, the gate terminal of the ninth PMOS transistor MP9 is connected to a non-inverting input signal VIP, and the drain terminal of the sixth PMOS transistor MP6 outputs an output signal.

[0045] Specifically, the gain of the error amplifier circuit can be adjusted by adjusting the ratio of MN3, MN4, MN5, and MN6. The gain of the error amplifier can be expressed by the following formula:

[0046] A V = g m Br out ,

[0047] where A V is the gain of the error amplifier, g m is the transconductance of the input pair transistors MP8 and MP9, B is the ratio of the aspect ratios of MN3, MN4 to MN5, MN6, and r out is the equivalent impedance at the output terminal of the error amplifier.

[0048] Figure 2 The structural schematic diagram of the error amplifier circuit in another specific implementation manner is also shown. As Figure 2 shown, the error amplifier circuit further includes a first capacitor C1 and a fifth resistor R5. After being connected in series, one end is connected to the drain terminal of the sixth PMOS transistor MP6, and the other end is grounded.

[0049] Finally, the working principle of the LDO in the embodiments of the present invention is described:

[0050] The output voltage VOUT of the LDO circuit and the reference voltage VREF always maintain the following relationship within the working range under the influence of the first feedback resistor and the second feedback resistor (R1 and R2 in the following formula are the resistance values of the first feedback resistor and the second feedback resistor respectively):

[0051]

[0052] That is to say, the LDO output voltage VOUT always maintains a linear relationship with the reference voltage VREF within the working range, and the output voltage VOUT of the LDO can be changed by adjusting the ratio between the first feedback resistor and the second feedback resistor.

[0053] Obviously, the above embodiments are only examples given for clear illustration and are not limitations on the implementation manners. For those of ordinary skill in the art, other different forms of changes or variations can be made on the basis of the above description. It is not necessary and impossible to enumerate all the implementation manners here. And the obvious changes or variations derived therefrom are still within the protection scope of the present invention.

Claims

1. An LDO circuit, characterized in that, Comprising: An error amplifier circuit, whose non-inverting input terminal is connected to a reference voltage; A first adjustment circuit, whose input terminal is connected to the output terminal of the error amplifier circuit; the first adjustment circuit includes an NMOS adjustment transistor, and the gate terminal of the NMOS adjustment transistor is the input terminal of the first adjustment circuit; A second adjustment circuit, whose input terminal is connected to the output terminal of the first adjustment circuit; the second adjustment circuit includes an NPN adjustment transistor, and the base terminal of the NPN adjustment transistor is the input terminal of the second adjustment circuit; A feedback circuit, which is connected to the output terminal of the second adjustment circuit; the feedback circuit includes a first feedback resistor and a second feedback resistor connected in series, and the inverting input terminal of the error amplifier circuit is connected between the first feedback resistor and the second feedback resistor; The first adjustment circuit includes: A first NMOS transistor and a second NMOS transistor, whose gate terminals are both connected to the output terminal of the error amplifier circuit, and whose drain terminals are both connected to the high-level output terminal of the drive power supply; A first PMOS transistor, a second PMOS transistor and a first current source, the source terminals of the first PMOS transistor and the second PMOS transistor are respectively connected to the source terminals of the first NMOS transistor and the second NMOS transistor, the gate terminal of the first PMOS transistor is connected to the gate terminal and the drain terminal of the second PMOS transistor, and the drain terminal of the second PMOS transistor is connected to the first current source.

2. The LDO circuit according to claim 1, wherein The second adjustment circuit includes: A first NPN transistor and a second NPN transistor, whose base terminals are both connected to the source terminal of the first NMOS transistor, and whose collector terminals are both connected to the high-level output terminal of the drive power supply; A third PMOS transistor, a fourth PMOS transistor and a second current source, the source terminals of the third PMOS transistor and the fourth PMOS transistor are respectively connected to the emitter terminals of the first NPN transistor and the second NPN transistor, the gate terminal of the third PMOS transistor is connected to the gate terminal and the drain terminal of the fourth PMOS transistor, and the drain terminal of the fourth PMOS transistor is connected to the second current source.

3. The LDO circuit according to claim 2, wherein The second adjustment circuit further includes: A first adjustment resistor and a second adjustment resistor, the first adjustment resistor is connected between the collector terminal of the first NPN transistor and the high-level output terminal of the drive power supply, and the second adjustment resistor is connected between the collector terminal of the second NPN transistor and the high-level output terminal of the drive power supply.

4. The LDO circuit according to any one of claims 1-3, characterized in that, The error amplifier circuit includes: A fifth PMOS transistor and a sixth PMOS transistor, whose gate terminals are connected to each other, source terminals are both connected to the high-level output terminal of the drive power supply, and the gate terminal of the fifth PMOS transistor is also connected to its own drain terminal; A third NMOS transistor and a fourth NMOS transistor, whose drain terminals are respectively connected to the drain terminals of the fifth PMOS transistor and the sixth PMOS transistor, and whose source terminals are both grounded; A fifth NMOS transistor and a sixth NMOS transistor, whose source terminals are both grounded; the gate terminal and the drain terminal of the fifth NMOS transistor are both connected to the gate terminal of the third NMOS transistor, and the gate terminal and the drain terminal of the sixth NMOS transistor are both connected to the gate terminal of the fourth NMOS transistor; The seventh PMOS transistor, the eighth PMOS transistor, and the ninth PMOS transistor, the gate terminal of the seventh PMOS transistor is connected to the high-level output terminal of the driving power supply, a bias voltage is applied to the gate terminal, and the drain terminal is connected to the source terminal of the eighth PMOS transistor and the source terminal of the ninth PMOS transistor; the drain terminals of the eighth PMOS transistor and the ninth PMOS transistor are respectively connected to the drain terminal of the fifth NMOS transistor and the drain terminal of the sixth NMOS transistor; The gate terminal of the eighth PMOS transistor is applied with an inverted input signal, the gate terminal of the ninth PMOS transistor is applied with a non-inverted input signal, and the drain terminal of the sixth PMOS transistor outputs an output signal.

5. The LDO circuit according to claim 4, characterized in that, The error amplifier circuit further includes: A first capacitor and a fifth resistor, which are connected in series, one end of which is connected to the drain terminal of the sixth PMOS transistor, and the other end is grounded.

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