Display panel and manufacturing method thereof

Abstract

The present invention discloses a display panel and a method for manufacturing the same. The display panel comprises a substrate, a first metal layer, a spacer layer, and a device function layer. The first metal layer is disposed on the substrate and comprises a first subsection and a second subsection spaced apart from each other. The spacer layer covers the first and second subsections and comprises a groove between the first and second subsections. The device function layer is disposed on a side of the spacer layer away from the first metal layer and comprises a thin-film transistor device and a spacer portion filled in the groove. The present invention can reduce the step difference on the spacer layer and improve the flatness of the spacer layer. Furthermore, the spacer portion can be made of the same material as the thin-film transistor device, thereby saving process steps and reducing process costs.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and in particular to a display panel and a manufacturing method thereof. Background Art

[0002] Organic light-emitting diode (OLED) display panels have the advantages of simple preparation process, low cost, high luminous efficiency, easy formation of flexible structure, low power consumption, high color saturation and wide viewing angle. Display technology using electroluminescent diodes has become an important display technology.

[0003] Currently, in OLED display panels, in order to reduce impedance and improve voltage drop, thicker copper is usually used as routing. However, due to the large thickness of the copper routing, it is easy to produce step differences after covering the insulating layer. Due to the poor flatness of the insulating layer, the yield of the subsequently prepared film layer will be reduced. For example, the pixel opening area has a large step difference, which makes it impossible to fill the flat layer, thereby reducing the yield of the organic light-emitting layer and affecting the luminous efficiency of the display panel. Summary of the Invention

[0004] Embodiments of the present invention provide a display panel and a manufacturing method thereof, which can reduce the step difference of film layers in the display panel, improve the flatness, and increase the yield and luminous efficiency of the display panel.

[0005] An embodiment of the present invention provides a display panel, comprising:

[0006] substrate;

[0007] A first metal layer is provided on the substrate and includes a first sub-portion and a second sub-portion spaced apart from each other;

[0008] a spacer layer covering the first sub-section and the second sub-section, wherein the spacer layer is provided with a groove located between the first sub-section and the second sub-section;

[0009] The device function layer is arranged on a side of the spacer layer away from the first metal layer, and includes a thin film transistor device and a spacer portion filled in the groove.

[0010] In one embodiment of the present invention, the device functional layer includes a semiconductor layer provided on a side of the spacer layer away from the first metal layer, an insulating layer provided on a side of the semiconductor layer away from the spacer layer, and a second metal layer provided on a side of the insulating layer away from the semiconductor layer, the semiconductor layer includes an active portion provided on a side of the spacer layer away from the first sub-portion, the insulating layer includes a gate insulating portion provided on a side of the active portion away from the spacer layer, and the second metal layer includes a gate provided on a side of the gate insulating portion away from the active portion;

[0011] The thin film transistor device includes the active portion, the gate insulating portion, and the gate, and at least one of the semiconductor layer, the insulating layer, and the second metal layer is further filled in the groove.

[0012] In one embodiment of the present invention, the semiconductor layer further comprises a first spacer portion provided on a side of the spacer layer away from the substrate;

[0013] The spacer portion includes the first spacer portion, and the first spacer portion is disposed in the groove 0.

[0014] In one embodiment of the present invention, the insulating layer further comprises a second spacer portion provided on a side of the semiconductor layer away from the spacer layer;

[0015] Wherein, the spacer portion further includes a second spacer portion, and the second spacer portion is arranged in the groove and located on a side of the first spacer portion away from the spacing layer.

[0016] In one embodiment of the present invention, the second metal layer further includes a third spacer portion disposed on a side of the insulating layer away from the semiconductor layer;

[0017] Wherein, the spacer portion further includes the third spacer portion, and the third spacer portion is arranged in the groove and located on a side of the second spacer portion away from the first spacer portion.

[0018] In one embodiment of the present invention, the display panel further includes an interlayer dielectric layer disposed on a side of the second metal layer away from the insulating layer, and a third metal layer disposed on a side of the interlayer dielectric layer away from the second metal layer, wherein the third metal layer includes a source electrode, a drain electrode, and a signal line;

[0019] The source and the drain are both connected to the active portion through the interlayer dielectric layer, and the signal line is connected to the third spacer portion through the interlayer dielectric layer, so that the signal line and the third spacer portion are connected in parallel.

[0020] In one embodiment of the present invention, the display panel further comprises a first storage capacitor disposed on the substrate, the semiconductor layer further comprises a first electrode plate disposed on a side of the spacer layer away from the substrate, the third metal layer further comprises a second electrode plate disposed on a side of the first electrode plate away from the spacer layer, and the first storage capacitor comprises the first electrode plate and the second electrode plate disposed opposite to each other.

[0021] The display panel also includes a second storage capacitor arranged on the substrate, the third metal layer also includes an additional electrode plate arranged on the side of the second sub-portion away from the substrate, the second storage capacitor includes the second sub-portion and the additional electrode plate arranged opposite to each other, and the first storage capacitor is connected in parallel with the second storage capacitor.

[0022] In one embodiment of the present invention, the display panel includes a display area and a non-display area adjacent to the display area, and the semiconductor layer further includes a test terminal residue portion arranged on a side of the spacer away from the substrate and located in the non-display area.

[0023] In one embodiment of the present invention, an absolute value of a difference between a thickness of the spacer portion along a thickness direction of the display panel and a depth of the groove along the thickness direction of the display panel is less than or equal to 0.8 micrometers.

[0024] In accordance with the above-mentioned purpose of the present invention, an embodiment of the present invention provides a method for manufacturing a display panel, which includes the following steps:

[0025] providing a substrate;

[0026] forming a first metal material layer on the substrate, and patterning the first metal material layer to obtain a first metal layer, wherein the first metal layer is formed with a first sub-portion and a second sub-portion spaced apart from each other;

[0027] forming a spacer layer covering the first sub-section and the second sub-section, wherein the spacer layer has a groove formed between the first sub-section and the second sub-section;

[0028] A device function layer is formed on a side of the spacer layer away from the first metal layer, wherein the device function layer is formed with a thin film transistor device and a spacer portion filled in the groove.

[0029] Beneficial effects of the present invention: In the present invention, after the spacer layer covers the first sub-portion and the second sub-portion of the spacer, a groove will be formed between the first sub-portion and the second sub-portion, resulting in a step difference; the present invention fills the spacer portion in the groove formed by the spacer layer to reduce the step difference generated on the spacer layer and improve the flatness of the spacer layer; in addition, the spacer portion can be prepared using the same layer material as the thin film transistor device, thereby saving process steps and reducing process costs. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] The technical solutions and other beneficial effects of the present invention will be made apparent by describing in detail the specific embodiments of the present invention in conjunction with the accompanying drawings.

[0031] Figure 1 A schematic structural diagram of a display panel provided by an embodiment of the present invention;

[0032] Figure 2 A schematic diagram of a planar structure of a display panel provided by an embodiment of the present invention;

[0033] Figure 3 A flow chart of a method for manufacturing a display panel provided by an embodiment of the present invention;

[0034] Figures 4 to 8 A structural diagram of the manufacturing process of a display panel provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0035] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only some of the embodiments of the present invention, not all of them. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present invention.

[0036] The disclosure below provides many different embodiments or examples for realizing different structures of the present invention. In order to simplify the disclosure of the present invention, the components and settings of specific examples are described below. Of course, they are merely examples and are not intended to limit the present invention. In addition, the present invention may repeat reference numbers and / or reference letters in different examples. Such repetition is for the purpose of simplicity and clarity and does not in itself indicate the relationship between the various embodiments and / or settings discussed. In addition, the present invention provides examples of various specific processes and materials, but those skilled in the art will recognize the application of other processes and / or the use of other materials.

[0037] The embodiment of the present invention provides a display panel, please refer to Figure 1 The display panel includes a substrate 10 , a first metal layer 20 , a spacer layer 30 and a device function layer 40 .

[0038] Among them, the first metal layer 20 is arranged on the substrate 10 and includes a first sub-section 21 and a second sub-section 22 arranged at intervals; the spacer layer 30 covers the first sub-section 21 and the second sub-section 22, and a groove is provided in the spacer layer 30 between the first sub-section 21 and the second sub-section 22.

[0039] Furthermore, the device function layer 40 is disposed on a side of the spacer layer 30 away from the first metal layer 20 , and includes a thin film transistor device 41 and a spacer portion 42 filled in the groove.

[0040] In an embodiment of the present invention, after the spacer layer 30 covers the first sub-portion 21 and the second sub-portion 22 of the spacer, a groove will be formed between the first sub-portion 21 and the second sub-portion 22, resulting in a step difference; in an embodiment of the present invention, a spacer portion 42 is filled in the groove formed by the spacer layer 30 to reduce the step difference generated on the spacer layer 30 and improve the flatness of the spacer layer 30; in addition, the spacer portion 42 can be prepared using the same layer material as the thin film transistor device 41, thereby saving process steps and reducing process costs.

[0041] For details, please refer to Figure 1 In the embodiment of the present invention, the display panel includes a display area 101

[0042] and a non-display area 102 connected to the display area 101 .

[0043] Furthermore, the display panel includes a substrate 10, a first metal layer 20 disposed on the substrate 10, a spacer layer 30 disposed on the substrate 10 and covering the first metal layer 20, a device function layer 40 disposed on the spacer layer 30, an interlayer dielectric layer 61 disposed on the spacer layer 30 and covering the device function layer 40,

[0044] A third metal layer 50 is provided on the interlayer dielectric layer 61, a passivation layer 62 is provided on the interlayer dielectric layer 61 and covers the third metal layer 50, a planarization layer 63 is provided on the passivation layer 62, an anode 65 is provided on the planarization layer 63, and a pixel definition layer 64 is provided on the planarization layer 63, wherein a pixel opening 640 is provided in the pixel definition layer 64 to expose a portion of the upper surface of the anode 65.

[0045] 0 Wherein, the first metal layer 20 is provided on the substrate 10, and the first metal layer 20 includes spaced apart

[0046] a first sub-section 21 and a second sub-section 22 .

[0047] It should be noted that the material of the first metal layer 20 may include at least one of copper, molybdenum and titanium, and the first metal layer 20 may be a single-layer film layer or a multi-layer film layer stacked structure. At least one of the first sub-section 21 and the second sub-section 22 is a signal line in the display panel for transmitting electrical signals. In order to reduce impedance and improve voltage drop, the thickness of the first metal layer 20 needs to be set to be larger, for example

[0048] It can be 7500 angstroms to 12000 angstroms.

[0049] The spacer layer 30 covers the first sub-section 21 and the second sub-section 22. Since the thickness of the first metal layer 20 is relatively large, after the spacer layer 30 covers the first metal layer 20, the spacer layer 30 is away from the side of the substrate 10.

[0050] The surface will form an uneven topography; specifically, the spacer layer 30 will form a groove between the first sub-section 210 and the second sub-section 22 that are spaced apart.

[0051] In one embodiment, since the display panel needs to form thin film transistors on the substrate 10 , the first sub-portion 21 can serve as a light shielding layer disposed on the substrate 10 to improve the light stability of the thin film transistors.

[0052] Specifically, the device functional layer 40 is disposed on the spacer layer 30 and includes a thin film transistor device 41 and a spacer portion 42 disposed on the side of the spacer layer 30 away from the substrate 10. The thin film transistor device 41 is disposed on the side of the first sub-portion 21 away from the substrate 10, and the spacer portion 42 fills the groove on the spacer layer 30; thus, the first sub-portion 21 can block light for the thin film transistor device 41, and the spacer portion 42 fills the groove on the spacer layer 30 to reduce the step formed on the spacer layer 30, improve the flatness of the spacer layer 30, and thus improve the yield of subsequent film layers.

[0053] It should be noted that the thin film transistor device 41 is only a part of the thin film transistor device; Figure 1 and Figure 2 The ratio of the area of ​​the spacer portion 42 in the display area 101 to the area of ​​the thin film transistor device 41 in the display area 101 is greater than or equal to 30%, so as to effectively improve the overall flatness of the spacer layer 30, and the distance L between the orthographic projection of the spacer portion 42 on the substrate 10 and the orthographic projection of the first metal layer 20 on the substrate 10 is greater than or equal to 6 microns and less than or equal to 10 microns.

[0054] In the embodiment of the present invention, the device functional layer 40 includes a stacked semiconductor layer 401, an insulating layer 402 and a second metal layer 403, wherein the semiconductor layer 401 is located on the side of the spacer layer 30 away from the substrate 10, the insulating layer 402 is located on the side of the semiconductor layer 401 away from the spacer layer 30, and the second metal layer 403 is located on the side of the insulating layer 402 away from the semiconductor layer 401.

[0055] The semiconductor layer 401, the insulating layer 402 and the second metal layer 403 are stacked on the side of the first sub-portion 21 away from the substrate 10 to form a thin film transistor device 41. At least one of the semiconductor layer 401, the insulating layer 402 and the second metal layer 403 is filled in the groove, and the part of at least one of the semiconductor layer 401, the insulating layer 402 and the second metal layer 403 located in the groove forms a gasket portion 42.

[0056] In one embodiment, the semiconductor layer 401 includes an active portion 411 arranged on a side of the first sub-portion 21 away from the substrate 10, the insulating layer 402 includes a gate insulating portion 412 arranged on a side of the active portion 411 away from the first sub-portion 21, the second metal layer 403 includes a gate 413 arranged on a side of the gate insulating portion 412 away from the active portion 411, and the active portion 411, the gate insulating portion 412 and the gate 413 are stacked to form a thin film transistor device 41; wherein, the active portion 411 includes a channel region arranged corresponding to the gate 413 and doped regions located on both sides of the channel region, and the doped regions can be obtained by conducting the active portion 411.

[0057] In one embodiment, the semiconductor layer 401 includes a first spacer portion 421 located in the groove, the insulating layer 402 includes a second spacer portion 422 located on a side of the first spacer portion 421 away from the spacing layer 30, the second metal layer 403 includes a third spacer portion 423 located on a side of the second spacer portion 422 away from the first spacer portion 421, and the first spacer portion 421, the second spacer portion 422 and the third spacer portion 423 are stacked in the groove to form the spacer portion 42.

[0058] In other embodiments of the present invention, any one or any two of the semiconductor layer 401, the insulating layer 402 and the second metal layer 403 may be filled in the groove to form the spacer portion 42. In the embodiment of the present invention, the semiconductor layer 401, the insulating layer 402 and the second metal layer 403 are simultaneously filled in the groove as an example for explanation.

[0059] Optionally, the thickness of the semiconductor layer 401 may be 200 angstroms to 400 angstroms, the thickness of the insulating layer 402 may be 1000 angstroms to 2000 angstroms, and the thickness of the second metal layer 403 may be 4310 angstroms to 5500 angstroms.

[0060] Furthermore, the absolute value of the difference between the thickness of the spacer portion 42 along the thickness direction of the display panel and the depth of the groove along the thickness direction of the display panel is less than or equal to 0.8 microns, thereby reducing the step difference caused by the groove to 0.8 microns or less, for example, 0.8 microns, 0.7 microns, 0.6 microns, 0.5 microns, 0.4 microns, 0.3 microns, 0.2 microns, 0.1 microns, or 0. This can effectively improve the flatness of the spacer layer 30 and improve the yield of the film layer on the spacer layer 30.

[0061] In one embodiment, the semiconductor layer 401 also includes a test terminal residual portion 43 disposed in the non-display area 102; wherein, during the manufacturing process, the test terminal can be formed in the non-display area 102 through the semiconductor layer 401, and is subjected to a conductorization process in the same manufacturing process as the active portion 411 to achieve a conductive function. After completing the panel test function, the test terminal can be removed. However, after removal, part of the test terminal may remain, i.e., the test terminal residual portion 43 formed in the non-display area 102. In the related art, the third metal layer 50 is often used to prepare the test terminal, resulting in the test terminal being covered with only a passivation layer 62, an inorganic film layer, making it easy for the display panel to peel off at the test terminal during the cutting process. In the embodiment of the present invention, the semiconductor layer 401 is used to prepare the test terminal, which increases the thickness of the inorganic film layer on the test terminal, reduces the probability of peeling off at the test terminal during the cutting process of the display panel, and improves the yield of the display panel.

[0062] In the first metal layer 20, the first sub-section 21 and the second sub-section 22 can both be arranged in the display area 101 and can be used for shading or forming electrical components; in addition, the first metal layer 20 can also include a third sub-section 23 located in the non-display area 102, and the third sub-section 23 can be used as a signal routing to realize functions such as signal input or line switching; similarly, the third sub-section 23 and the first sub-section 21 are arranged at intervals, and the spacing layer 30 also forms a groove between the first sub-section 21 and the third sub-section 23, and a pad portion 42 is also formed in the groove to improve the flatness of the spacing layer 30.

[0063] An interlayer dielectric layer 61 is arranged on the spacer layer 30 and covers the device functional layer 40. A third metal layer 50 is arranged on the interlayer dielectric layer 61, and the third metal layer 50 includes a source 51, a drain 52, an additional electrode 53 and a signal line 54; wherein the source 51 and the drain 52 pass through the interlayer dielectric layer 61 to be connected to the doped region of the active portion 411, the signal line 54 passes through the interlayer dielectric layer 61 to be connected to the third pad portion 423 in the pad portion 42, and the additional electrode 53 is located on the side of the second sub-portion 22 away from the substrate 10 and is arranged opposite to the second sub-portion 22.

[0064] It should be noted that the signal line 54 can be a data line connecting a thin film transistor, or other signal routing. Since the two third spacer portions 423 implemented in the present invention are made of metal material and can conduct electricity, the signal line 54 is connected in parallel with the third spacer portion 423, which can reduce the resistance of the signal line 54 and improve the voltage drop phenomenon of the display panel, thereby achieving the display uniformity of the display panel.

[0065] In another embodiment of the present invention, the signal line 54 is not connected to the third spacer portion 423, that is, the spacer portion 42 is only used to improve the flatness of the spacing layer 30, or, the third spacer portion 423 in part of the spacer portion 42 is connected to the signal line 54 to reduce the resistance of the signal line 54, while the third spacer portion 423 in another spacer portion 42 is not connected to the signal line 54.

[0066] In addition, in one embodiment, the display panel also includes a first storage capacitor arranged on the substrate 10, and the first storage capacitor includes a first electrode plate and a second electrode plate (not shown in the figure) arranged opposite to each other, wherein the semiconductor layer 401 includes a first electrode plate arranged on the side of the spacer layer 30 away from the substrate 10, and the third metal layer 50 includes a second electrode plate arranged on the side of the interlayer dielectric layer 61 away from the substrate 10; further, the display panel also includes a second storage capacitor arranged on the substrate 10, and the second storage capacitor is composed of a second sub-portion 22 and an additional electrode plate 53 arranged opposite to each other, and the first storage capacitor and the second storage capacitor are connected in parallel, that is, the first electrode plate is connected to the second sub-portion 22, and the second electrode plate is connected to the additional electrode plate 53, thereby effectively increasing the capacitance of the storage capacitor in the display panel to improve the stability of the driving circuit and the display effect in the display panel.

[0067] Furthermore, the planar layer 63 is disposed on the passivation layer 62 , the anode 65 is disposed on the planar layer 63 , and the pixel definition layer 64 is disposed on the planar layer 63 and includes a pixel opening 640 , wherein the pixel opening 640 is disposed corresponding to the anode 65 .

[0068] It can be understood that, since the embodiment of the present invention provides a spacer portion 42 in the groove of the spacer layer 30 to reduce the step difference and improve the flatness, the flatness of the flat layer 63 located on the side of the spacer layer 30 away from the substrate 10 can be effectively improved, and the flatness of the anode 65 and the organic light-emitting layer subsequently prepared on the anode 65 can be improved, thereby improving the luminous efficiency and display effect of the display panel.

[0069] As mentioned above, in an embodiment of the present invention, after the spacer layer 30 covers the first sub-portion 21 and the second sub-portion 22 of the spacer, a groove will be formed between the first sub-portion 21 and the second sub-portion 22, resulting in a step difference; in an embodiment of the present invention, a spacer portion 42 is filled in the groove formed by the spacer layer 30 to reduce the step difference generated on the spacer layer 30 and improve the flatness of the spacer layer 30; in addition, the spacer portion 42 can be prepared using the same layer material as the thin film transistor device 41, thereby saving process steps and reducing process costs.

[0070] In addition, the embodiment of the present invention also provides a method for manufacturing the display panel described in the above embodiment. Figure 1 、 Figure 3 as well as Figures 4 to 8 .

[0071] The manufacturing method of the display panel comprises the following steps:

[0072] S10, providing a substrate 10.

[0073] S20 , forming a first metal material layer on the substrate 10 , and patterning the first metal material layer to obtain a first metal layer 20 , wherein the first metal layer 20 is formed with a first sub-portion 21 and a second sub-portion 22 that are spaced apart.

[0074] S30 , forming a spacer layer 30 covering the first sub-portion 21 and the second sub-portion 22 , wherein the spacer layer 30 forms a groove between the first sub-portion 21 and the second sub-portion 22 .

[0075] S40 , forming a device function layer 40 on a side of the spacer layer 30 away from the first metal layer 20 , wherein the device function layer 40 is formed with a thin film transistor device 41 and a spacer portion 42 filled in the groove.

[0076] In step S20, the first metal material layer is patterned to obtain a first sub-section 21 and a second sub-section 22 located in the display area 101, and a third sub-section 23 located in the non-display area 102, and the first sub-section 21 and the second sub-section 22 are spaced apart, the first sub-section 21 and the third sub-section 23 are spaced apart, and the second sub-section 22 and the third sub-section 23 are spaced apart.

[0077] Among them, the first sub-section 21 can be used as a light-shielding layer for the thin film transistor, the second sub-section 22 can be used to constitute the electrical components in the display panel, and the third sub-section 23 can be used for signal routing in the non-display area 102; and the thickness of the first metal layer 20 can be 7500 angstroms to 12000 angstroms.

[0078] In step S30, a spacer layer 30 covering the first sub-section 21, the second sub-section 22 and the third sub-section 23 is formed on the first metal layer 20. Since the thickness of the first sub-section 21, the second sub-section 22 and the third sub-section 23 is relatively large, after the spacer layer 30 covers the first metal layer 20, grooves will be formed between the first sub-section 21 and the second sub-section 22, and between the first sub-section 21 and the third sub-section 23.

[0079] In step S40, a semiconductor material layer is formed on the spacer layer 30 and patterned to obtain an active portion 411 located on a side of the first sub-portion 21 away from the substrate 10, a first spacer portion 421 located in the groove, and a test terminal 431 located in the non-display area 101. The active portion 411, the first spacer portion 421, and the test terminal 431 constitute a semiconductor layer 401. Figure 4 shown.

[0080] Optionally, the thickness of the semiconductor layer 401 may be 200 angstroms to 400 angstroms.

[0081] Furthermore, a stacked insulating material layer 4020 and a second metal material layer 4030 are formed on the semiconductor layer 401 , and the insulating material layer 4020 and the second metal material layer 4030 continuously cover the semiconductor layer 401 and the spacer layer 30 .

[0082] Optionally, the material of the insulating material layer 4020 includes at least one of silicon nitride and silicon oxide.

[0083] A photoresist layer 70 is formed on the second metal material layer 4030, and the photoresist layer 70 covers the side of the second metal material layer 4030 away from the active portion 411 and the portion of the second metal material layer 4030 corresponding to the groove, as shown in FIG. Figure 5 shown.

[0084] The second metal material layer 4030 and the insulating material layer 4020 not covered by the photoresist layer 70 are removed, and then the photoresist layer 70 is removed to obtain the gate insulating portion 412 and the gate 413 located on the active portion 411, and the second spacer portion 422 and the third spacer portion 423 located in the groove and sequentially located on the first spacer portion 421.

[0085] Conductive processing is performed on the portion of the active portion 411 that is not covered by the gate insulating portion 412 and the gate 413, and the test terminal 431, such as Figure 6 shown.

[0086] The active portion 411 , the gate insulating portion 412 and the gate 413 constitute a thin film transistor device 41 , the first spacer portion 421 , the second spacer portion 422 and the third spacer portion 423 constitute a spacer portion 42 , and the thin film transistor device 41 and the spacer portion 42 constitute a device functional layer 40 .

[0087] An interlayer dielectric layer 61 covering the device functional layer 40 is formed on the spacer layer 30, and the interlayer dielectric layer 61 is patterned to obtain a first contact hole 611 and a second contact hole 612, as shown in FIG. Figure 7 shown.

[0088] Next, a third metal material layer is formed on the interlayer dielectric layer 61 and patterned to obtain a third metal layer 50. The third metal layer 50 includes a source 51, a drain 52, an additional electrode 53 and a signal line 54. The source 51 and the drain 52 pass through the first contact hole 611 to connect with the conductor-treated portion of the active portion 411. The signal line 54 passes through the second contact hole 612 to connect with the third pad portion 423 in the pad portion 42. The additional electrode 53 is arranged opposite to the second sub-portion 22 to form a second storage capacitor.

[0089] It should be noted that when forming the semiconductor layer 401, a first electrode plate can be formed on the side of the spacer layer 30 away from the substrate 10, and when forming the third metal layer 50, a second electrode plate can be formed above the first electrode plate, and the first electrode plate and the second electrode plate are arranged opposite to each other to form a first storage capacitor, and the first storage capacitor and the second storage capacitor are connected in parallel to increase the capacitance of the storage capacitor in the display panel.

[0090] A passivation layer 62 and a planarization layer 63 covering the third metal layer 50 are sequentially formed on the interlayer dielectric layer 61. Figure 8 shown.

[0091] A fourth metal material layer is formed on the planar layer 63 and patterned to obtain the anode 65 .

[0092] A pixel definition layer 64 is formed on the planar layer 63 and patterned to form a pixel opening 640 . The pixel opening 640 is disposed corresponding to the anode 65 to expose a portion of the upper surface of the anode 65 .

[0093] It should be noted that after the display panel is tested, the display panel needs to be cut, and the test terminals 431 located in the non-display area 102 will also be cut. In one embodiment of the present invention, a portion of the test terminals 431 will remain after cutting to form a portion located in the non-display area 102.

[0094] The test terminal residual portion 43 within the Figure 1 shown.

[0095] In summary, in the embodiment of the present invention, after the spacer layer 30 covers the first sub-portion 21 and the second sub-portion 22 of the spacer, a groove is formed between the first sub-portion 21 and the second sub-portion 22, resulting in a step difference;

[0096] In the embodiment, the spacer portion 42 is filled in the groove formed in the spacer layer 30 to reduce the step difference of 0 on the spacer layer 30 and improve the flatness of the spacer layer 30; in addition, the spacer portion 42 can be prepared using the same layer material as the thin film transistor device 41, thereby saving process steps and reducing process costs.

[0097] In addition, an embodiment of the present invention further provides a display device, which includes a device body and a display panel as described in the above embodiment, wherein the display panel is integrated with the device body.

[0098] Specifically, the device body may include a frame and a driving component, etc.

[0099] In the above embodiments, the description of each embodiment has its own focus. For parts not described in detail in one embodiment, please refer to the relevant description of other embodiments.

[0100] The above describes in detail a display panel and a manufacturing method thereof provided by an embodiment of the present invention. This paper uses a specific example to illustrate the principle and implementation of the present invention.

[0101] The description of the examples is only used to help understand the technical solutions and core ideas of the present invention; ordinary technicians in this field should understand that they can still modify the technical solutions recorded in the aforementioned embodiments, or replace some of the technical features therein with equivalents; and these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A display panel, characterized in that: include: substrate; A first metal layer is provided on the substrate and includes a first sub-portion and a second sub-portion spaced apart from each other; a spacer layer covering the first sub-section and the second sub-section, wherein the spacer layer is provided with a groove located between the first sub-section and the second sub-section; a device function layer, disposed on a side of the spacer layer away from the first metal layer, and comprising a thin film transistor device and a spacer portion filled in the groove; The device functional layer includes a semiconductor layer provided on a side of the spacer layer away from the first metal layer, an insulating layer provided on a side of the semiconductor layer away from the spacer layer, and a second metal layer provided on a side of the insulating layer away from the semiconductor layer, the semiconductor layer includes an active portion provided on a side of the spacer layer away from the first sub-portion, the insulating layer includes a gate insulating portion provided on a side of the active portion away from the spacer layer, and the second metal layer includes a gate provided on a side of the gate insulating portion away from the active portion; The thin film transistor device includes the active portion, the gate insulating portion and the gate, and at least one of the semiconductor layer, the insulating layer and the second metal layer is further filled in the groove.

2. The display panel according to claim 1, wherein: The semiconductor layer further includes a first spacer portion provided on a side of the spacer layer away from the substrate; Wherein, the spacer portion includes the first spacer portion, and the first spacer portion is arranged in the groove.

3. The display panel according to claim 2, wherein: The insulating layer further comprises a second spacer portion provided on a side of the semiconductor layer away from the spacer layer; Wherein, the spacer portion further includes a second spacer portion, and the second spacer portion is arranged in the groove and located on a side of the first spacer portion away from the spacing layer.

4. The display panel according to claim 3, wherein: The second metal layer further includes a third spacer portion disposed on a side of the insulating layer away from the semiconductor layer; Wherein, the spacer portion further includes the third spacer portion, and the third spacer portion is arranged in the groove and located on a side of the second spacer portion away from the first spacer portion.

5. The display panel according to claim 4, wherein: The display panel further includes an interlayer dielectric layer disposed on a side of the second metal layer away from the insulating layer, and a third metal layer disposed on a side of the interlayer dielectric layer away from the second metal layer, wherein the third metal layer includes a source electrode, a drain electrode, and a signal line; The source and the drain are both connected to the active portion through the interlayer dielectric layer, and the signal line is connected to the third spacer portion through the interlayer dielectric layer, so that the signal line and the third spacer portion are connected in parallel.

6. The display panel according to claim 5, wherein: The display panel further includes a first storage capacitor disposed on the substrate, the semiconductor layer further includes a first electrode plate disposed on a side of the spacer layer away from the substrate, the third metal layer further includes a second electrode plate disposed on a side of the first electrode plate away from the spacer layer, and the first storage capacitor includes the first electrode plate and the second electrode plate disposed opposite to each other; The display panel also includes a second storage capacitor arranged on the substrate, the third metal layer also includes an additional electrode plate arranged on the side of the second sub-portion away from the substrate, the second storage capacitor includes the second sub-portion and the additional electrode plate arranged opposite to each other, and the first storage capacitor is connected in parallel with the second storage capacitor.

7. The display panel according to claim 1, wherein: The display panel includes a display area and a non-display area adjacent to the display area. The semiconductor layer further includes a test terminal residual portion disposed on a side of the spacer layer away from the substrate and located in the non-display area.

8. The display panel according to claim 1, wherein: An absolute value of a difference between a thickness of the spacer portion along a thickness direction of the display panel and a depth of the groove along the thickness direction of the display panel is less than or equal to 0.8 micrometers.

9. A method for manufacturing a display panel, characterized in that: The following steps are involved: providing a substrate; forming a first metal material layer on the substrate, and patterning the first metal material layer to obtain a first metal layer, wherein the first metal layer is formed with a first sub-portion and a second sub-portion spaced apart from each other; forming a spacer layer covering the first sub-section and the second sub-section, wherein the spacer layer has a groove formed between the first sub-section and the second sub-section; A device functional layer is formed on a side of the spacer layer away from the first metal layer, the device functional layer forming a thin film transistor device and a spacer portion filled in the groove, the device functional layer includes a semiconductor layer arranged on a side of the spacer layer away from the first metal layer, an insulating layer arranged on a side of the semiconductor layer away from the spacer layer, and a second metal layer arranged on a side of the insulating layer away from the semiconductor layer, the semiconductor layer includes an active portion arranged on a side of the spacer layer away from the first sub-portion, the insulating layer includes a gate insulating portion arranged on a side of the active portion away from the spacer layer, and the second metal layer includes a gate arranged on a side of the gate insulating portion away from the active portion; wherein the thin film transistor device includes the active portion, the gate insulating portion and the gate, and at least one of the semiconductor layer, the insulating layer and the second metal layer is also filled in the groove.

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