Chip cache scheduling method and system

Abstract

The embodiment of the present application discloses a chip cache scheduling method and system, the method comprising: when a chip cache scheduling request is received, obtaining the configuration connection relationship of the leaf node, the parent node and the tree base; the configuration connection relationship of the leaf node, the parent node and the tree base includes that the leaf nodes are all connected to the parent node and the parent nodes are all connected to the tree base, the leaf nodes are all connected to the tree base, some leaf nodes are connected to the parent node and the remaining leaf nodes are connected to the tree base; the number of the parent nodes is half of the number of the child nodes; the comprehensive priority of all transmission queues is determined according to the configuration connection relationship of the leaf node, the parent node and the tree base; the chip cache packets in the transmission queue are sent in order from high to low according to the comprehensive priority of all transmission queues. Transmission is performed according to the transmission queue priority determined by the configuration connection relationship of the leaf node, the parent node and the tree base, and the chip cache scheduling is completed efficiently, while reducing resource occupation and maintenance costs.

Description

Technical Field

[0001] The embodiments of the present application relate to the field of communication technology, and in particular to a chip cache scheduling method and system. Background Art

[0002] In Ethernet switching chips, the scheduling model generally adopts traffic monitoring and traffic shaping authorization distribution scheduling, which is generally divided into multiple levels of scheduling. For multi-level hierarchical scheduling, there can be many levels of tree structure, with multiple (dozens to thousands) leaf nodes at the bottom. Figure 1 As shown in the figure, taking a 3-layer tree structure with 12 leaf nodes as an example, the leaf node is called queue, the root parent node is called L1_node, and the tree base is called port. All leaf nodes are connected to the root by subsequently connecting to its parent node, and finally aggregated to a single tree base. In general, each leaf node has its own different weight and priority, so the number of the upper node must be at least the same as the number of its leaf node, so the number of parent nodes must be the same as the number of leaf nodes.

[0003] A very complex and expensive leaky bucket counter is required at each intermediate node and leaf node. Under the structure of the prior art, a total of 24 complex and expensive leaky bucket counters are required for the parent node and the leaf node, which have high resource occupation and maintenance costs. If there are thousands of parent nodes and leaf nodes, the implementation cost is also very high. Summary of the invention

[0004] To this end, an embodiment of the present application provides a chip cache scheduling method and system, which performs transmission according to the transmission queue priority determined by the configuration connection relationship between the leaf node, the parent node and the tree base, efficiently completes the chip cache scheduling, and reduces resource usage and maintenance costs.

[0005] In order to achieve the above objectives, the embodiments of the present application provide the following technical solutions:

[0006] According to a first aspect of an embodiment of the present application, a chip cache scheduling method is provided, the method comprising:

[0007] When a chip cache scheduling request is received, a configuration connection relationship among a leaf node, a parent node and a tree base is obtained; the configuration connection relationship among the leaf node, the parent node and the tree base includes that all leaf nodes are connected to the parent node and the parent node is connected to the tree base, all leaf nodes are connected to the tree base, some leaf nodes are connected to the parent node and the remaining leaf nodes are connected to the tree base; the number of the parent nodes is half the number of the child nodes;

[0008] Determine the comprehensive priority of all transmission queues according to the configuration connection relationship between leaf nodes, parent nodes and tree base;

[0009] The chip cache packets in the transmission queue are sent in order from high to low according to the comprehensive priority of all transmission queues.

[0010] Optionally, if the configuration connection relationship among the leaf nodes, parent nodes and tree base is that the leaf nodes are all connected to the parent nodes, and the parent nodes are all connected to the tree base;

[0011] The step of determining the comprehensive priorities of all transmission queues according to the configuration connection relationship among the leaf node, the parent node and the tree base includes:

[0012] Determine the priority of all parent nodes according to their own weights;

[0013] Determine the priority of all transmission queues of each parent node according to the weight of the transmission queue associated with each parent node;

[0014] The respective combined priorities of all transmit queues are determined based on the priorities of all parent nodes and the priorities of all transmit queues of each parent node.

[0015] Optionally, if the configuration connection relationship between the leaf node, the parent node and the tree base is that the leaf nodes are all connected to the tree base;

[0016] The step of determining the comprehensive priorities of all transmission queues according to the configuration connection relationship among the leaf node, the parent node and the tree base includes:

[0017] The combined priority of all transmission queues is determined according to their own weights.

[0018] Optionally, if the configuration connection relationship between the leaf node, the parent node and the tree base is that the leaf node is partially connected to the parent node and the remaining part is connected to the tree base;

[0019] The step of determining the comprehensive priorities of all transmission queues according to the configuration connection relationship among the leaf node, the parent node and the tree base includes:

[0020] For transmission queues connected to a parent node, the priorities of all parent nodes are determined according to the weight of the parent node itself; the priorities of all transmission queues of each parent node are determined according to the weight of the transmission queue associated with each parent node; the first comprehensive priority of each transmission queue connected to the parent node is determined according to the priorities of all parent nodes and the priorities of all transmission queues of each parent node;

[0021] For the transmission queues directly connected to the tree base, the second comprehensive priority of each of the transmission queues directly connected to the tree base is determined according to the weights of all the transmission queues themselves;

[0022] The respective comprehensive priorities of all transmission queues are determined according to the respective first comprehensive priorities of all transmission queues connected to the parent node and the respective second comprehensive priorities of all transmission queues directly connected to the tree base.

[0023] Optionally, the configuration connection relationship in which some leaf nodes are connected to the parent node and the remaining leaf nodes are connected to the tree base includes:

[0024] A parent node is connected to Q1 leaf nodes and all M1 parent nodes are connected to the tree base, Q1 is 0 or 1 or a positive integer less than P1, all leaf nodes are P1, and M1 is half of P1; or

[0025] A parent node is connected to Q2 leaf nodes, all M2 parent nodes and P3 leaf nodes that are not connected to the parent node are connected to the tree base; Q2 is 0 or 1 or a positive integer less than P2, the number of leaf nodes connected to the parent node is P2, and M2 is half of P2+P3; or

[0026] All leaf nodes are connected to one parent node and all parent nodes are connected to the base of the tree.

[0027] According to a second aspect of an embodiment of the present application, a chip cache scheduling system is provided, the system comprising:

[0028] A configuration connection relationship acquisition module is used to acquire the configuration connection relationship of the leaf node, the parent node and the tree base when receiving a chip cache scheduling request; the configuration connection relationship of the leaf node, the parent node and the tree base includes that the leaf nodes are all connected to the parent node and the parent node is all connected to the tree base, the leaf nodes are all connected to the tree base, some leaf nodes are connected to the parent node and the remaining leaf nodes are connected to the tree base; the number of the parent nodes is half the number of the child nodes;

[0029] A queue priority determination module, used to determine the respective comprehensive priorities of all transmission queues according to the configuration connection relationship between leaf nodes, parent nodes and tree bases;

[0030] The cache transmission module is used to send the chip cache packets in the transmission queue in order from high to low according to the comprehensive priority of all transmission queues.

[0031] Optionally, if the configuration connection relationship between the leaf node, the parent node and the tree base is that the leaf node is partially connected to the parent node and the remaining part is connected to the tree base;

[0032] The queue priority determination module is specifically used to:

[0033] For transmission queues connected to a parent node, the priorities of all parent nodes are determined according to the weight of the parent node itself; the priorities of all transmission queues of each parent node are determined according to the weight of the transmission queue associated with each parent node; the first comprehensive priority of each transmission queue connected to the parent node is determined according to the priorities of all parent nodes and the priorities of all transmission queues of each parent node;

[0034] For the transmission queues directly connected to the tree base, the second comprehensive priority of each of the transmission queues directly connected to the tree base is determined according to the weights of all the transmission queues themselves;

[0035] The respective comprehensive priorities of all transmission queues are determined according to the respective first comprehensive priorities of all transmission queues connected to the parent node and the respective second comprehensive priorities of all transmission queues directly connected to the tree base.

[0036] Optionally, the configuration connection relationship in which some leaf nodes are connected to the parent node and the remaining leaf nodes are connected to the tree base includes:

[0037] A parent node is connected to Q1 leaf nodes and all M1 parent nodes are connected to the tree base, Q1 is 0 or 1 or a positive integer less than P1, all leaf nodes are P1, and M1 is half of P1; or

[0038] A parent node is connected to Q2 leaf nodes, all M2 parent nodes and P3 leaf nodes that are not connected to the parent node are connected to the tree base; Q2 is 0 or 1 or a positive integer less than P2, the number of leaf nodes connected to the parent node is P2, and M2 is half of P2+P3; or

[0039] All leaf nodes are connected to one parent node and all parent nodes are connected to the base of the tree.

[0040] According to a third aspect of an embodiment of the present application, an electronic device is provided, comprising: a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the computer program to implement the method described in the first aspect above.

[0041] According to a fourth aspect of an embodiment of the present application, a computer-readable storage medium is provided, on which computer-readable instructions are stored. The computer-readable instructions can be executed by a processor to implement the method described in the first aspect above.

[0042] In summary, the embodiment of the present application provides a chip cache scheduling method and system. When a chip cache scheduling request is received, the configuration connection relationship of the leaf node, the parent node and the tree base is obtained; the configuration connection relationship of the leaf node, the parent node and the tree base includes that the leaf nodes are all connected to the parent node and the parent nodes are all connected to the tree base, the leaf nodes are all connected to the tree base, some leaf nodes are connected to the parent node and the remaining leaf nodes are connected to the tree base; the number of the parent nodes is half of the number of the child nodes; the comprehensive priority of all transmission queues is determined according to the configuration connection relationship of the leaf node, the parent node and the tree base; the chip cache packets in the transmission queue are sent in order from high to low according to the comprehensive priority of all transmission queues. The transmission is carried out according to the transmission queue priority determined by the configuration connection relationship of the leaf node, the parent node and the tree base, and the chip cache scheduling is completed efficiently, while reducing resource occupation and maintenance costs. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] In order to more clearly illustrate the implementation methods of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for the implementation methods or the description of the prior art. Obviously, the drawings in the following description are only exemplary, and for ordinary technicians in this field, other implementation drawings can be derived from the provided drawings without creative work.

[0044] The structures, proportions, sizes, etc. illustrated in this specification are only used to match the contents disclosed in the specification so as to facilitate understanding and reading by persons familiar with the technology. They are not used to limit the conditions under which the present invention can be implemented, and therefore have no substantial technical significance. Any structural modification, change in proportion or adjustment of size shall still fall within the scope of the technical contents disclosed in the present invention without affecting the effects and purposes that can be achieved by the present invention.

[0045] Figure 1 A schematic diagram of a three-layer tree-like hierarchical structure in the prior art provided for an embodiment of the present application;

[0046] Figure 2 A flow chart of a chip cache scheduling method provided in an embodiment of the present application;

[0047] Figure 3 A schematic diagram of the hierarchical tree structure leaf node level jump connection provided in an embodiment of the present application;

[0048] Figure 4 A schematic diagram of a tree hierarchy structure provided in an embodiment of the present application, wherein a parent node is connected to one or more leaf nodes;

[0049] Figure 5 A schematic diagram of a tree hierarchy structure provided in an embodiment of the present application in which a parent node connects all leaf nodes;

[0050] Figure 6 A schematic diagram of a tree hierarchy structure in which all leaf nodes are connected to a tree base by jumping according to an embodiment of the present application;

[0051] Figure 7 An example schematic diagram of a tree hierarchy structure provided in an embodiment of the present application where a parent node is connected to one or more leaf nodes;

[0052] Figure 8 A schematic diagram showing an example of a tree hierarchy structure in which a parent node connects all leaf nodes provided in an embodiment of the present application;

[0053] Fig. 9 A schematic diagram showing an example of a tree hierarchy structure in which all leaf nodes are connected to a tree base by jumping;

[0054] Fig.10 A block diagram of a chip cache scheduling system provided in an embodiment of the present application;

[0055] Fig.11 A schematic diagram of the structure of an electronic device provided in an embodiment of the present application is shown;

[0056] Fig.12 A schematic diagram of a computer-readable storage medium provided in an embodiment of the present application is shown. DETAILED DESCRIPTION

[0057] The following is a description of the implementation of the present invention by specific embodiments. People familiar with the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0058] Figure 2 A chip cache scheduling method provided in an embodiment of the present application is shown, and the method includes:

[0059] Step 201: when a chip cache scheduling request is received, a configuration connection relationship among a leaf node, a parent node and a tree base is obtained; the configuration connection relationship among the leaf node, the parent node and the tree base includes that all leaf nodes are connected to the parent node and the parent node is connected to the tree base, all leaf nodes are connected to the tree base, some leaf nodes are connected to the parent node and the remaining leaf nodes are connected to the tree base; the number of the parent nodes is half the number of the child nodes;

[0060] Step 202: Determine the comprehensive priority of all transmission queues according to the configuration connection relationship between the leaf node, the parent node and the tree base;

[0061] Step 203: Send the chip cache packets in the transmission queues in order from high to low according to the comprehensive priorities of all transmission queues.

[0062] In a possible implementation, if the configuration connection relationship among the leaf nodes, the parent nodes and the tree base is that the leaf nodes are all connected to the parent nodes, and the parent nodes are all connected to the tree base; in step 202, the comprehensive priorities of all transmission queues are determined according to the configuration connection relationship among the leaf nodes, the parent nodes and the tree base, including:

[0063] The priorities of all parent nodes are determined according to the weights of the parent nodes themselves; the priorities of all transmission queues of each parent node are determined according to the weights of the transmission queues associated with each parent node; the comprehensive priorities of all transmission queues are determined according to the priorities of all parent nodes and the priorities of all transmission queues of each parent node.

[0064] In a possible implementation, if the configuration connection relationship among the leaf nodes, the parent nodes and the tree base is that all leaf nodes are connected to the tree base; in step 202, the comprehensive priorities of all transmission queues are determined according to the configuration connection relationship among the leaf nodes, the parent nodes and the tree base, including:

[0065] The combined priority of all transmission queues is determined according to their own weights.

[0066] In a possible implementation manner, if the configuration connection relationship among the leaf node, the parent node and the tree base is that the leaf node is partially connected to the parent node and the remaining part is connected to the tree base; in step 202, the comprehensive priority of all transmission queues is determined according to the configuration connection relationship among the leaf node, the parent node and the tree base, including:

[0067] For transmission queues connected to a parent node, the priorities of all parent nodes are determined according to the weight of the parent node itself; the priorities of all transmission queues of each parent node are determined according to the weight of the transmission queue associated with each parent node; the first comprehensive priority of each transmission queue connected to a parent node is determined according to the priorities of all parent nodes and the priorities of all transmission queues of each parent node; for transmission queues directly connected to the tree base, the second comprehensive priority of all transmission queues directly connected to the tree base is determined according to the weight of all transmission queues themselves; the comprehensive priority of all transmission queues is determined according to the first comprehensive priority of all transmission queues connected to a parent node and the second comprehensive priority of all transmission queues directly connected to the tree base.

[0068] In a possible implementation manner, the configuration connection relationship in which some leaf nodes are connected to the parent node and the remaining leaf nodes are connected to the tree base includes:

[0069] A parent node is connected to Q1 leaf nodes and all M1 parent nodes are connected to the tree base, Q1 is 0 or 1 or a positive integer less than P1, all leaf nodes are P1, and M1 is half of P1; or

[0070] A parent node is connected to Q2 leaf nodes, all M2 parent nodes and P3 leaf nodes that are not connected to the parent node are connected to the tree base; Q2 is 0 or 1 or a positive integer less than P2, the number of leaf nodes connected to the parent node is P2, and M2 is half of P2+P3; or

[0071] All leaf nodes are connected to one parent node and all parent nodes are connected to the base of the tree.

[0072] In the configuration connection relationship provided in the embodiment of the present application, a leaf node can skip its parent node and directly connect to a higher level. Figure 3 As shown in the figure, a 3-layer tree hierarchy with 12 leaf nodes (queues) is used as an example. 6 leaf nodes (queues) are hung on the tree base port of a higher level, and 6 leaf nodes (queues) are hung on the parent node L1_node. In this way, the number of the upper level will be half of the number of leaf nodes below it. In this way, only 18 complex and expensive leaky bucket counters are needed for the parent node and the leaf node, which is a quarter less than the architecture in the prior art.

[0073] With a structure where the number of parent nodes is half the number of leaf nodes, the connection relationship of leaf nodes is more flexible. Every two leaf nodes can be connected to one parent node, every three leaf nodes can be connected to one parent node, every four leaf nodes can be connected to one parent node, and so on.

[0074] Figure 4 Another hierarchical hopping scheduling method provided by an embodiment of the present application is shown. A single parent node can be connected to one or more leaf nodes. Figure 5 All leaf nodes shown are connected to only one parent node; Figure 3 Some of the leaf nodes shown are connected to the parent node, and some of the leaf nodes jump to a higher level; Figure 6 All leaf nodes shown in the figure jump to the parent node and directly connect to the higher-level port. The connection relationship is flexible and can be combined at will.

[0075] However, the connection relationship must meet the following two points: (1) It is sufficient to ensure that a leaf node cannot be connected to both its parent node and a higher-level node at the same time, that is, a leaf node is either only connected to its parent node, or only connected to a higher-level node across its parent node. (2) If a leaf node is connected to a parent node, the parent node must be connected to the tree base.

[0076] The embodiment of the present application takes a 3-layer structure and 12 leaf nodes as an example for explanation, and the specific implementation includes but is not limited to a 3-layer structure and 12 leaf nodes, and may be a 4-layer, 5-layer structure, etc., and the leaf nodes may be 32, 64, 128, etc. In actual use, the leaf nodes are also called queues.

[0077] The embodiment of the present application can be run on an Ethernet switching chip to implement the scheduling function. When the switching chip inlet receives an Ethernet packet, it will parse the Ethernet packet and then cache the packet. If there is no congestion at the switching chip outlet, the packet will be scheduled out of the cache. Different packets have different priorities, and which packet goes out first is implemented by scheduling. The tree base can connect all parent nodes, some parent nodes, or no parent node. The tree base can connect all leaf nodes, some leaf nodes, or no leaf node. The parent node can connect all leaf nodes, some leaf nodes, or no leaf node.

[0078] If the connection relationship is configured so that queues are connected to the parent node, and the parent node is connected to the tree base, such as Figure 7 As shown, the scheduling process includes the following steps:

[0079] Step 1: The transmission egress is not congested, the cached packet can be transmitted, and a scheduling request is received;

[0080] Step 2: Determine the priority of all parent nodes based on the weight of the parent node itself. Queues of different priorities represent different service qualities. The higher the priority, the higher the service quality. Queues with high priority are discharged first, and queues with low priority are discharged later. The priority of the parent node is as follows: Figure 7 As shown, the priorities of parent nodes 0-5 are 7, 5, 4, 6, 3, and 2 respectively.

[0081] Step 3: Determine the priority of all transmission queues of each parent node according to the weight of the transmission queue associated with each parent node. From the parent nodes, select the parent node with the highest weight. The priority of all transmission queues of each parent node is as follows: Figure 7 As shown in the figure, the queues corresponding to parent node 0 are queue 0, queue 1, and queue 2. The priority of queue 0 is 4, the priority of queue 1 is 5, and the priority of queue 2 is 6. The queue priorities corresponding to other parent nodes are shown in the figure and will not be repeated here.

[0082] Step 4: Determine the respective comprehensive priorities of all transmission queues according to the priorities of all parent nodes and the priorities of all transmission queues of each parent node.

[0083] Step 5: Schedule the corresponding packets in the switch chip cache according to the comprehensive priority of the transmission queue from high to low. Figure 7For example, the comprehensive priority is ranked from high to low as follows: parent node 0 (queue 2, queue 1, queue 0), parent node 3 (queue 7, queue 6), parent node 1 (queue 3), parent node 2 (queue 5, queue 4), parent node 4 (queue 8, queue 9), parent node 5 (queue 11, queue 10).

[0084] If the connection relationship is configured so that all queues are connected to the tree base across parent nodes, such as Figure 8 As shown, the scheduling process includes the following steps:

[0085] Step 1: The transmission egress is not congested, the cached packet can be transmitted, and a scheduling request is received;

[0086] Step 2: Select the queue with the highest priority to directly send the transmission cache packet. Queues with different priorities represent different service qualities. The higher the priority, the higher the service quality. The queue with high priority is sent first, and then the queue with low priority is sent.

[0087] Step 3: Schedule the corresponding packets in the switch chip cache according to the priority from high to low. Figure 8 As shown, the queue priorities are arranged from high to low as follows: queue 5, queues 4 and 6, queue 7, queues 3 and 8, queues 2 and 9, queue 10, queues 0, 1, and 11.

[0088] If the configured connection relationship is that part of the queue is connected to the parent node, and part of the queue is connected to the tree base across the parent node, such as Fig. 9 As shown, the scheduling process includes the following steps:

[0089] Step 1: The transmission egress is not congested, the cached packet can be transmitted, and a scheduling request is received;

[0090] Step 2: For the transmission queues connected to the parent node, determine the priority of all parent nodes according to the weight of the parent node itself; determine the priority of all transmission queues of each parent node according to the weight of the transmission queue associated with each parent node; determine the first comprehensive priority of each transmission queue connected to the parent node according to the priority of all parent nodes and the priority of all transmission queues of each parent node. Fig. 9 As shown, the priority order of the parent nodes connected with the transmission queues is: parent node 2 (queue 5, queue 4), parent node 3 (queue 7, queue 6), parent node 1 (queue 3, queue 2), and parent node 0 (queue 1, queue 0).

[0091] Step 3: For the transmission queues directly connected to the tree base, determine the second comprehensive priority of all transmission queues directly connected to the tree base according to their own weights. Queues with different priorities represent different service qualities. The higher the priority, the higher the service quality. The queues with high priority will be discharged first, and then the queues with low priority will be discharged. Fig. 9 As shown, the priority order of the transmission queues directly connected to the tree base is: queue 10, queue 11, queue 9 and queue 8.

[0092] Step 4: Determine the respective comprehensive priorities of all transmission queues according to the respective first comprehensive priorities of all transmission queues connected to the parent node and the respective second comprehensive priorities of all transmission queues directly connected to the tree base.

[0093] Step 5: Schedule the corresponding packets in the switch chip cache according to the comprehensive priority from high to low. Fig. 9 As shown, the comprehensive priority ranking is: queue 10, queue 11, parent node 2 (queue 5, queue 4), parent node 3 (queue 7, queue 6), queue 9, parent node 1 (queue 3, queue 2), queue 8, parent node 0 (queue 1, queue 0).

[0094] In summary, the embodiment of the present application provides a chip cache scheduling method, when a chip cache scheduling request is received, the configuration connection relationship of the leaf node, the parent node and the tree base is obtained; the configuration connection relationship of the leaf node, the parent node and the tree base includes that the leaf nodes are all connected to the parent node and the parent nodes are all connected to the tree base, the leaf nodes are all connected to the tree base, some leaf nodes are connected to the parent node and the remaining leaf nodes are connected to the tree base; the number of the parent nodes is half of the number of the child nodes; the comprehensive priority of all transmission queues is determined according to the configuration connection relationship of the leaf node, the parent node and the tree base; the chip cache packets in the transmission queue are sent in order from high to low according to the comprehensive priority of all transmission queues. The transmission is carried out according to the transmission queue priority determined by the configuration connection relationship of the leaf node, the parent node and the tree base, and the chip cache scheduling is completed efficiently, while reducing resource occupation and maintenance costs.

[0095] Based on the same technical concept, the embodiment of the present application also provides a chip cache scheduling system, such as Fig.10 As shown, the system comprises:

[0096] The configuration connection relationship acquisition module 1001 is used to acquire the configuration connection relationship of the leaf node, the parent node and the tree base when receiving the chip cache scheduling request; the configuration connection relationship of the leaf node, the parent node and the tree base includes that the leaf nodes are all connected to the parent node and the parent node is all connected to the tree base, the leaf nodes are all connected to the tree base, some leaf nodes are connected to the parent node and the remaining leaf nodes are connected to the tree base; the number of the parent nodes is half of the number of the child nodes;

[0097] The queue priority determination module 1002 is used to determine the comprehensive priority of all transmission queues according to the configuration connection relationship between the leaf node, the parent node and the tree base;

[0098] The cache transmission module 1003 is used to send the chip cache packets in the transmission queue in order from high to low according to the comprehensive priorities of all transmission queues.

[0099] In a possible implementation manner, if the configuration connection relationship between the leaf node, the parent node and the tree base is that the leaf node is partially connected to the parent node and the remaining part is connected to the tree base; the queue priority determination module 1002 is specifically used to:

[0100] For transmission queues connected to a parent node, the priorities of all parent nodes are determined according to the weight of the parent node itself; the priorities of all transmission queues of each parent node are determined according to the weight of the transmission queue associated with each parent node; the first comprehensive priority of each transmission queue connected to a parent node is determined according to the priorities of all parent nodes and the priorities of all transmission queues of each parent node; for transmission queues directly connected to the tree base, the second comprehensive priority of all transmission queues directly connected to the tree base is determined according to the weight of all transmission queues themselves; the comprehensive priority of all transmission queues is determined according to the first comprehensive priority of all transmission queues connected to a parent node and the second comprehensive priority of all transmission queues directly connected to the tree base.

[0101] In a possible implementation manner, the configuration connection relationship in which some leaf nodes are connected to the parent node and the remaining leaf nodes are connected to the tree base includes:

[0102] A parent node is connected to Q1 leaf nodes and all M1 parent nodes are connected to the tree base, Q1 is 0 or 1 or a positive integer less than P1, all leaf nodes are P1, and M1 is half of P1; or

[0103] A parent node is connected to Q2 leaf nodes, all M2 parent nodes and P3 leaf nodes that are not connected to the parent node are connected to the tree base; Q2 is 0 or 1 or a positive integer less than P2, the number of leaf nodes connected to the parent node is P2, and M2 is half of P2+P3; or

[0104] All leaf nodes are connected to one parent node and all parent nodes are connected to the base of the tree.

[0105] The present application also provides an electronic device corresponding to the method provided in the above embodiment. Fig.11, which shows a schematic diagram of an electronic device provided by some embodiments of the present application. The electronic device 20 may include: a processor 200, a memory 201, a bus 202 and a communication interface 203, wherein the processor 200, the communication interface 203 and the memory 201 are connected via the bus 202; the memory 201 stores a computer program that can be run on the processor 200, and the processor 200 executes the method provided by any of the aforementioned embodiments of the present application when running the computer program.

[0106] The memory 201 may include a high-speed random access memory (RAM), and may also include a non-volatile memory, such as at least one disk memory. The communication connection between the system network element and at least one other network element is realized through at least one physical port 203 (which may be wired or wireless), and the Internet, wide area network, local area network, metropolitan area network, etc. may be used.

[0107] The bus 202 may be an ISA bus, a PCI bus, or an EISA bus, etc. The bus may be divided into an address bus, a data bus, a control bus, etc. The memory 201 is used to store programs, and the processor 200 executes the programs after receiving execution instructions. The method disclosed in any implementation of the aforementioned embodiment of the present application may be applied to the processor 200, or implemented by the processor 200.

[0108] The processor 200 may be an integrated circuit chip with signal processing capabilities. In the implementation process, each step of the above method can be completed by the hardware integrated logic circuit or software instructions in the processor 200. The above processor 200 can be a general-purpose processor, including a central processing unit (CPU), a network processor (NP), etc.; it can also be a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a readily available programmable gate array (FPGA) or other programmable logic devices, discrete gates or transistor logic devices, discrete hardware components. The methods, steps and logic block diagrams disclosed in the embodiments of the present application can be implemented or executed. The general-purpose processor can be a microprocessor or the processor can also be any conventional processor, etc. The steps of the method disclosed in the embodiments of the present application can be directly embodied as a hardware decoding processor to be executed, or the hardware and software modules in the decoding processor can be executed. The software module can be located in a mature storage medium in the field such as a random access memory, a flash memory, a read-only memory, a programmable read-only memory or an electrically erasable programmable memory, a register, etc. The storage medium is located in the memory 201, and the processor 200 reads the information in the memory 201 and completes the steps of the above method in combination with its hardware.

[0109] The electronic device provided in the embodiment of the present application and the method provided in the embodiment of the present application are based on the same inventive concept and have the same beneficial effects as the method adopted, operated or implemented by them.

[0110] The present application also provides a computer-readable storage medium corresponding to the method provided in the above embodiment. Fig.12 The computer-readable storage medium shown is a CD 30 on which a computer program (ie, a program product) is stored. When the computer program is run by a processor, the method provided in any of the aforementioned embodiments is executed.

[0111] It should be noted that examples of the computer-readable storage medium may also include, but are not limited to, phase change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other optical or magnetic storage media, which are not listed here one by one.

[0112] The computer-readable storage medium provided in the above-mentioned embodiments of the present application and the method provided in the embodiments of the present application are based on the same inventive concept and have the same beneficial effects as the method adopted, run or implemented by the application program stored therein.

[0113] It should be noted that:

[0114] The algorithm and display provided herein are not inherently related to any particular computer, virtual device or other equipment. Various general purpose devices can also be used together with the teachings based on this. According to the above description, it is obvious to construct the structure required for this type of device. In addition, the application is not directed to any specific programming language. It should be understood that the content of the application described herein can be realized using various programming languages, and the description of the specific language above is to disclose the best mode of implementation of the application.

[0115] In the description provided herein, a large number of specific details are described. However, it is understood that the embodiments of the present application can be practiced without these specific details. In some instances, well-known methods, structures and techniques are not shown in detail so as not to obscure the understanding of this description.

[0116] Similarly, it should be understood that in order to streamline the present application and help understand one or more of the various inventive aspects, in the above description of the exemplary embodiments of the present application, the various features of the present application are sometimes grouped together into a single embodiment, figure, or description thereof. However, the disclosed method should not be interpreted as reflecting the following intention: the claimed application requires more features than the features clearly stated in each claim. More specifically, as reflected in the claims below, the inventive aspects are less than all the features of the single embodiment disclosed above. Therefore, the claims following the specific embodiment are hereby expressly incorporated into the specific embodiment, wherein each claim itself serves as a separate embodiment of the present application.

[0117] Those skilled in the art will appreciate that the modules in the devices in the embodiments may be adaptively changed and arranged in one or more devices different from the embodiments. The modules or units or components in the embodiments may be combined into one module or unit or component, and in addition they may be divided into a plurality of submodules or subunits or subcomponents. Except that at least some of such features and / or processes or units are mutually exclusive, all features disclosed in this specification (including the accompanying claims, abstracts and drawings) and all processes or units of any method or device disclosed in this manner may be combined in any combination. Unless otherwise expressly stated, each feature disclosed in this specification (including the accompanying claims, abstracts and drawings) may be replaced by an alternative feature providing the same, equivalent or similar purpose.

[0118] In addition, those skilled in the art will appreciate that, although some embodiments described herein include certain features included in other embodiments but not other features, the combination of features of different embodiments is meant to be within the scope of the present application and form different embodiments. For example, in the claims below, any one of the claimed embodiments may be used in any combination.

[0119] The various component embodiments of the present application can be implemented in hardware, or in software modules running on one or more processors, or in a combination thereof. It should be understood by those skilled in the art that a microprocessor or digital signal processor (DSP) can be used in practice to implement some or all functions of some or all components in the creation device of the virtual machine according to the embodiment of the present application. The application can also be implemented as a device or device program (e.g., computer program and computer program product) for executing part or all of the methods described herein. Such a program implementing the present application can be stored on a computer-readable medium, or can have the form of one or more signals. Such a signal can be downloaded from an Internet website, or provided on a carrier signal, or provided in any other form.

[0120] It should be noted that the above embodiments illustrate the present application rather than limit the present application, and that those skilled in the art may design alternative embodiments without departing from the scope of the appended claims. In the claims, any reference symbol between brackets should not be constructed as a limitation to the claims. The word "comprising" does not exclude the presence of elements or steps not listed in the claims. The word "one" or "an" preceding an element does not exclude the presence of multiple such elements. The present application may be implemented by means of hardware including several different elements and by means of a suitably programmed computer. In a unit claim that lists several devices, several of these devices may be embodied by the same hardware item. The use of the words first, second, and third, etc. does not indicate any order. These words may be interpreted as names.

[0121] The above is only a preferred specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any changes or substitutions that can be easily thought of by a person skilled in the art within the technical scope disclosed in the present application should be included in the protection scope of the present application. Therefore, the protection scope of the present application shall be based on the protection scope of the claims.

Claims

1. A chip cache scheduling method, characterized in that: The method comprises: When a chip cache scheduling request is received, a configuration connection relationship among a leaf node, a parent node and a tree base is obtained; the configuration connection relationship among the leaf node, the parent node and the tree base includes that all leaf nodes are connected to the parent node and the parent node is connected to the tree base, all leaf nodes are connected to the tree base, some leaf nodes are connected to the parent node and the remaining leaf nodes are connected to the tree base; the number of the parent nodes is half of the number of the leaf nodes; Determine the comprehensive priority of all transmission queues according to the configuration connection relationship between leaf nodes, parent nodes and tree base; Send the chip cache packets in the transmission queue in order from high to low according to the comprehensive priority of all transmission queues; Wherein, if the configuration connection relationship among the leaf nodes, parent nodes and tree base is that the leaf nodes are all connected to the parent nodes, and the parent nodes are all connected to the tree base; the determination of the respective comprehensive priorities of all transmission queues according to the configuration connection relationship among the leaf nodes, parent nodes and tree base includes: determining the priorities of all parent nodes according to the weights of the parent nodes themselves; determining the priorities of all transmission queues of each parent node according to the weights of the transmission queues associated with each parent node; determining the respective comprehensive priorities of all transmission queues according to the priorities of all parent nodes and the priorities of all transmission queues of each parent node; or, If the configuration connection relationship among the leaf nodes, the parent nodes and the tree base is that the leaf nodes are all connected to the tree base; the step of determining the respective comprehensive priorities of all transmission queues according to the configuration connection relationship among the leaf nodes, the parent nodes and the tree base includes: determining the respective comprehensive priorities of all transmission queues according to the weights of all transmission queues themselves; or, If the configured connection relationship among the leaf node, parent node and tree base is that the leaf node is partially connected to the parent node and the remaining part is connected to the tree base; the method of determining the respective comprehensive priorities of all transmission queues according to the configured connection relationship among the leaf node, parent node and tree base includes: for transmission queues connected to a parent node, determining the priorities of all parent nodes according to the weight of the parent node itself; determining the priorities of all transmission queues of each parent node according to the weight of the transmission queue associated with each parent node; determining the respective first comprehensive priorities of transmission queues connected to a parent node according to the priorities of all parent nodes and the priorities of all transmission queues of each parent node; for transmission queues directly connected to the tree base, determining the respective second comprehensive priorities of all transmission queues directly connected to the tree base according to the weight of all transmission queues themselves; determining the respective comprehensive priorities of all transmission queues according to the respective first comprehensive priorities of all transmission queues connected to a parent node and the respective second comprehensive priorities of all transmission queues directly connected to the tree base.

2. The method according to claim 1, characterized in that The configuration connection relationship in which some leaf nodes are connected to the parent node and the remaining leaf nodes are connected to the tree base includes: A parent node is connected to Q1 leaf nodes and all M1 parent nodes are connected to the tree base, Q1 is 0 or 1 or a positive integer less than P1, all leaf nodes are P1, and M1 is half of P1; or A parent node is connected to Q2 leaf nodes, all M2 parent nodes and P3 leaf nodes that are not connected to the parent node are connected to the tree base; Q2 is 0 or 1 or a positive integer less than P2, the number of leaf nodes connected to the parent node is P2, and M2 is half of P2+P3; or All leaf nodes are connected to one parent node and all parent nodes are connected to the base of the tree.

3. A chip cache scheduling system, characterized in that: The system comprises: A configuration connection relationship acquisition module, used for acquiring the configuration connection relationship of the leaf node, the parent node and the tree base when receiving the chip cache scheduling request; the configuration connection relationship of the leaf node, the parent node and the tree base includes that the leaf nodes are all connected to the parent node and the parent node is all connected to the tree base, the leaf nodes are all connected to the tree base, some leaf nodes are connected to the parent node and the remaining leaf nodes are connected to the tree base, and the number of the parent nodes is half of the number of the leaf nodes; A queue priority determination module, used to determine the respective comprehensive priorities of all transmission queues according to the configuration connection relationship between the leaf node, the parent node and the tree base; A cache transmission module, used to send the chip cache packets in the transmission queue in order from high to low according to the comprehensive priority of all transmission queues; If the configuration connection relationship among the leaf node, parent node and tree base is that the leaf node is partially connected to the parent node and the remaining part is connected to the tree base; the queue priority determination module is specifically used to: for transmission queues connected to a parent node, determine the priorities of all parent nodes according to the weight of the parent node itself; determine the priorities of all transmission queues of each parent node according to the weight of the transmission queue associated with each parent node; determine the first comprehensive priority of each transmission queue connected to the parent node according to the priorities of all parent nodes and the priorities of all transmission queues of each parent node; for transmission queues directly connected to the tree base, determine the second comprehensive priority of each transmission queue directly connected to the tree base according to the weight of all transmission queues themselves; determine the comprehensive priority of each transmission queue according to the first comprehensive priority of each transmission queue connected to the parent node and the second comprehensive priority of each transmission queue directly connected to the tree base; If the configuration connection relationship between the leaf node, the parent node and the tree base is that the leaf nodes are all connected to the tree base; the queue priority determination module is specifically used to: determine the comprehensive priority of all transmission queues according to their own weights; If the configuration connection relationship among the leaf nodes, parent nodes and tree base is that all leaf nodes are connected to the parent nodes, and all parent nodes are connected to the tree base; the queue priority determination module is specifically used to: determine the priority of all parent nodes according to the weight of the parent node itself; determine the priority of all transmission queues of each parent node according to the weight of the transmission queue associated with each parent node; determine the comprehensive priority of all transmission queues according to the priority of all parent nodes and the priority of all transmission queues of each parent node.

4. The system according to claim 3, characterized in that The configuration connection relationship in which some leaf nodes are connected to the parent node and the remaining leaf nodes are connected to the tree base includes: A parent node is connected to Q1 leaf nodes and all M1 parent nodes are connected to the tree base, Q1 is 0 or 1 or a positive integer less than P1, all leaf nodes are P1, and M1 is half of P1; or A parent node is connected to Q2 leaf nodes, all M2 parent nodes and P3 leaf nodes that are not connected to the parent node are connected to the tree base; Q2 is 0 or 1 or a positive integer less than P2, the number of leaf nodes connected to the parent node is P2, and M2 is half of P2+P3; or All leaf nodes are connected to one parent node and all parent nodes are connected to the base of the tree.

5. An electronic device comprising: A memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the computer program to implement the method according to claim 1 or 2.

6. A computer-readable storage medium, characterized in that: Computer-readable instructions are stored thereon, and the computer-readable instructions can be executed by a processor to implement the method according to claim 1 or 2.

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