Infrared detector and control method thereof

Abstract

The embodiment of the present application provides an infrared detector and a control method thereof, which relates to the field of infrared imaging technology and is used to solve the problem that a bad column causes the infrared detector to be unusable. The infrared detector includes a pixel array and a readout circuit, the readout circuit includes a column compensation part and a column readout circuit part, the column compensation part includes a column compensation resistor unit and a first gating circuit, the first gating circuit is configured to control the pixel column and the column compensation resistor unit to be correspondingly turned on, and when the column compensation resistor unit connected to a certain pixel column fails to work, control the column and the subsequent pixel column to be connected to the next column compensation resistor unit. And / or, the column readout circuit part includes a column readout circuit and a second gating circuit, the second gating circuit is configured to control the pixel column and the column readout circuit to be correspondingly turned on, and when the column readout circuit connected to a certain pixel column fails to work, control the column and the subsequent pixel column to be connected to the next column readout circuit. The above scheme can be used in infrared imaging devices.

Description

Technical Field

[0001] The embodiments of the present application relate to the technical field of infrared imaging equipment, and in particular to an infrared detector and a control method thereof. Background Art

[0002] Infrared detectors typically consist of a pixel array and a readout integration circuit (RIOC). The pixel array includes multiple pixels arranged in multiple rows and columns. During operation, the pixels convert light or thermal radiation emitted by the target object into changes in their own resistance value, which is then amplified and read out by the readout circuit. Finally, the readout results are processed and output as an infrared image.

[0003] The readout circuitry used in infrared detectors includes column readout circuits and column-level compensation resistors corresponding to pixel columns. During the manufacture and use of infrared detectors, environmental factors such as dust and impurities, manufacturing process influences, or external forces such as impact can cause the column readout circuit to fail or the column-level compensation resistors to be damaged. Failure of the column readout circuit or damage to the column-level compensation resistors manifests itself in imaging as abnormal output from the entire column, known as a "bad column," rendering the entire infrared detector unusable and resulting in significant losses.

[0004] Furthermore, in high-resolution infrared detectors, pixel arrays have reached sizes of 1280×1024, 1920×1280, and above. This increase in pixel array size results in a larger pixel array area. Consequently, the number of column readout circuits and column-level compensation circuits in the readout circuitry has also exceeded one thousand. This larger pixel array area, along with the increased number of column readout circuits and column-level compensation resistors, further increases the likelihood of "bad columns" problems. Summary of the Invention

[0005] The embodiments of the present application provide an infrared detector and a control method thereof, which are used to solve the problem that a column failure of the infrared detector renders the entire infrared detector unusable.

[0006] To achieve the above objectives, the embodiments of the present application adopt the following technical solutions:

[0007] In one aspect, an infrared detector is provided, comprising a pixel array and a readout circuit; the pixel array comprises a plurality of pixel columns; the readout circuit is coupled to the pixel array and comprises a column compensation portion and a column readout circuit portion; wherein the column compensation portion comprises:

[0008] a plurality of column compensation resistor units, the plurality of column compensation resistor units including a first active portion and a first redundant portion, the first active portion including column compensation resistor units corresponding one-to-one to a plurality of columns of pixels in the pixel array, the first redundant portion including at least one column compensation resistor unit used as a redundant portion; and

[0009] a first gating circuit, the first gating circuit being configured to control a plurality of pixel columns in the pixel array to be electrically conductive in a one-to-one correspondence with the column compensation resistor units in the first active portion, and being configured to control the i-th column and all pixel columns subsequent thereto to be connected to the next column compensation resistor unit when the column compensation resistor unit connected to the i-th pixel column fails to operate;

[0010] and / or

[0011] The column readout circuit section includes:

[0012] a plurality of column readout circuits, the plurality of column readout circuits including a second active portion and a second redundant portion located on one side of the second active portion, the second active portion including column readout circuits corresponding one-to-one to a plurality of pixel columns in the pixel array, the second redundant portion including at least one column readout circuit for redundancy; and

[0013] a second gating circuit, the second gating circuit being configured to control a plurality of pixel columns in the pixel array to be electrically connected to the column readout circuits in the second active portion in a one-to-one correspondence, and being configured to control the i-th column and all pixel columns subsequent thereto to be connected to the next column readout circuit when the column readout circuit connected to the i-th pixel column fails to operate;

[0014] The i-th pixel column is any one of the multiple pixel columns.

[0015] When using the infrared detector provided in the embodiment of the present application, when a column compensation resistor unit / column readout circuit connected to a certain pixel column malfunctions and fails to work, that is, when a "bad column" occurs, the pixel column and all subsequent pixel columns are controlled to be connected to the next column compensation resistor unit / column readout circuit to implement "bad column" calibration of the infrared detector and ensure the normal operation of the infrared detector.

[0016] In some embodiments, the first gating circuit includes:

[0017] A plurality of first connection ends connected to the pixel columns in the pixel array in a one-to-one correspondence;

[0018] a plurality of second connection terminals connected to the column compensation resistor units in a one-to-one correspondence with the column compensation resistor units; and

[0019] a first control terminal configured to receive a first selection signal;

[0020] Wherein, when the first control terminal receives the first gating signal, the first gating circuit controls the first connection terminal to be connected to one of the second connection terminals;

[0021] The infrared detector further includes a controller coupled to a first control terminal in the readout circuit, and the controller is configured to output the first selection signal to the first control terminal.

[0022] In some embodiments, the pixel array includes N pixel columns, the column compensation resistor units are provided with N+A units, the first effective part includes N column compensation resistor units, and the first redundant part includes A column compensation resistor units;

[0023] The first gating circuit includes N first gating switches arranged corresponding to N columns of pixel columns, wherein the nth first gating switch includes:

[0024] One of the first connection ends connected to the n-th column of pixel columns;

[0025] A+1 second connection terminals respectively connected to the nth to n+Ath column compensation resistor units; and

[0026] A+1 first switch control terminals corresponding to the A+1 second connection terminals, the first switch control terminals being configured to control the corresponding second connection terminals to be connected to the first connection terminals when a conduction signal is input;

[0027] Wherein, N, A and n are all positive integers, N is greater than A, n = 1, 2, 3, ..., N;

[0028] The first control terminal includes the first switch control terminal of the N first gating switches, and the first gating signal includes a conduction signal corresponding to A+1 of the first switch control terminals.

[0029] In some embodiments, A is equal to 1.

[0030] In some embodiments, the first gating switch includes a first transistor and a second transistor, and the first transistor and the second transistor each include a control electrode, a first electrode, and a second electrode;

[0031] In the first transistor of the nth first gating switch, the first electrode is the first connection end connected to the nth column of pixel columns, the second electrode is the first second connection end connected to the nth column compensation resistor unit, and the control electrode is the first first switch control end;

[0032] In the second transistor of the nth first selection switch, the first pole is the first connection end connected to the nth column of the pixel column, the second pole is the second second connection end connected to the (n+1)th column compensation resistor unit, and the control pole is the second first switch control end.

[0033] In some embodiments, the second gating circuit includes:

[0034] A plurality of third connection terminals connected to the pixel columns in the pixel array in a one-to-one correspondence;

[0035] a plurality of fourth connection terminals connected to the column readout circuits in a one-to-one correspondence with the column readout circuits; and

[0036] a second control terminal configured to receive a second selection signal;

[0037] Wherein, when the second control terminal receives the second gating signal, the second gating circuit controls the third connection terminal to be connected to one of the fourth connection terminals;

[0038] The infrared detector further includes a controller coupled to the second control terminal in the readout circuit, and the controller is configured to output the second selection signal to the second control terminal.

[0039] In some embodiments, the pixel array includes N pixel columns, the column readout circuits are provided with N+B pieces, the second effective portion includes N of the column readout circuits, and the second redundant portion includes B of the column readout circuits;

[0040] The second gating circuit includes N second gating switches arranged corresponding to N columns of pixel columns, wherein the nth second gating switch includes:

[0041] A third connection end connected to the n-th column of pixel columns;

[0042] B+1 fourth connection terminals respectively connected to the nth to n+Bth column readout circuits; and

[0043] B+1 second switch control terminals corresponding to the B+1 fourth connection terminals, the second switch control terminals being configured to control the corresponding fourth connection terminals to be conductively connected to the third connection terminal when a conductive signal is input;

[0044] Wherein, N, B and n are all positive integers, N is greater than B, n = 1, 2, 3, ..., N;

[0045] The second control terminal includes the second switch control terminals of N second selection switches, and the second selection signal includes conduction signals corresponding to B+1 second switch control terminals.

[0046] In some embodiments, B is equal to 1.

[0047] In some embodiments, the second gating switch includes a third transistor and a fourth transistor, each of the third transistor and the fourth transistor includes a control electrode, a first electrode, and a second electrode;

[0048] In the third transistor of the nth second selection switch, the first electrode is the third connection terminal connected to the nth column of pixel columns, the second electrode is the first fourth connection terminal connected to the nth column readout circuit, and the control electrode is the first second switch control terminal;

[0049] In the fourth transistor of the nth second selection switch, the first pole is the third connection terminal connected to the nth column of the pixel column, the second pole is the second fourth connection terminal connected to the (n+1)th column readout circuit, and the control pole is the second second switch control terminal.

[0050] In another aspect, a control method for an infrared detector is provided, which is applied to the infrared detector according to any one of the above embodiments, and the control method includes:

[0051] Controlling the plurality of pixel columns in the pixel array and the plurality of column compensation resistor units in the first effective part to be turned on in a one-to-one correspondence;

[0052] When the column compensation resistor unit connected to the i-th column of pixels fails to work, controlling the i-th column and all the pixel columns behind the i-th column to be connected to the next column compensation resistor unit;

[0053] and / or

[0054] Controlling the plurality of pixel columns in the pixel array and the plurality of column readout circuits in the second effective part to be turned on in a one-to-one correspondence;

[0055] When the column readout circuit connected to the i-th column of pixels fails to work, controlling the i-th column and all the pixel columns behind the i-th column to be connected to the next column readout circuit;

[0056] The i-th pixel column is any one of the multiple pixel columns.

[0057] In some embodiments, the infrared detector includes N pixel columns, N+A column compensation resistor units, and a first gating circuit, wherein the first gating circuit includes N first gating switches arranged corresponding to the N pixel columns, the first gating switches being connected to the corresponding pixel columns, and the column compensation resistor units corresponding to the pixel columns and the adjacent A column compensation resistor units near the redundant portion being all connected to the same first gating switch; wherein N and A are both positive integers, and N is greater than A;

[0058] In the control method, the control method of connecting multiple pixel columns in the pixel array and multiple compensation resistor units in the first effective part in a one-to-one correspondence includes:

[0059] Controlling the gating states of the 1st to Nth first gating switches to connect the nth column of pixel elements to the nth column compensation resistor unit, where n=1, 2, 3, ..., N;

[0060] The method of controlling the pixel columns of the i-th column and all the pixel columns after the i-th column to be connected to the next column compensation resistor unit includes:

[0061] The gating states of the 1st to i-1th first gating switches are controlled to remain unchanged, and the gating states of the ith to Nth first gating switches are controlled to change, so that the ith to Nth pixel columns are all connected to the next column compensation resistor unit.

[0062] In some embodiments, the infrared detector includes N pixel columns, N+B column readout circuits, and a second gating circuit. The second gating circuit includes N second gating switches corresponding to the N pixel columns. The second gating switches are connected to the corresponding pixel columns. The column readout circuits corresponding to the pixel columns and the adjacent B column readout circuits near the redundant portion are all connected to the same second gating switch. Wherein, N and B are both positive integers, and N is greater than B.

[0063] In the control method, the control method of connecting multiple pixel columns in the pixel array and multiple compensation resistor units in the first effective part in a one-to-one correspondence includes:

[0064] Controlling the gating states of the first to Nth second gating switches to connect the nth column of pixel elements to the nth column compensation resistor unit, where n=1, 2, 3, ..., N;

[0065] The control method of connecting the i-th column and all pixel columns after the i-th column to the next column readout circuit includes:

[0066] The gating states of the 1st to i-1th second gating switches are controlled to remain unchanged, and the gating states of the ith to Nth second gating switches are controlled to change, so that the ith to Nth pixel columns are all connected to the next column compensation resistor unit.

[0067] In another aspect, an infrared detector is provided, comprising a pixel array and a readout circuit coupled to the pixel array; the pixel array comprises a plurality of pixel columns, the plurality of pixel columns comprising a third active portion and a third redundant portion located on one side of the third active portion; the third active portion comprises a plurality of pixel columns used for imaging, and the third redundant portion comprises at least one pixel column used as a redundant column;

[0068] The readout circuit comprises:

[0069] a plurality of circuit sub-sections, each of the plurality of circuit sub-sections corresponding one-to-one to a pixel column in the third active portion, the circuit sub-sections comprising a column compensation resistor unit and / or a column readout circuit; and

[0070] a third gating circuit, the third gating circuit being configured to control the circuit sub-sections in the readout circuit to be turned on in a one-to-one correspondence with the pixel columns of the third effective section, and being configured to control the i-th and all subsequent circuit sub-sections to be connected to the next pixel column when the pixel column connected to the i-th circuit sub-section is unable to operate;

[0071] The i-th circuit sub-part is any one of the multiple circuit sub-parts.

[0072] In some embodiments, the third gating circuit includes:

[0073] a plurality of fifth connection terminals connected to the circuit sub-parts in a one-to-one correspondence with the circuit sub-parts of the plurality of circuit sub-parts;

[0074] a plurality of sixth connection ends connected to the pixel columns in a one-to-one correspondence with the pixel columns; and

[0075] a third control terminal configured to receive a third selection signal;

[0076] Wherein, when the third control terminal receives the third gating signal, the third gating circuit controls the fifth connection terminal to be connected to one of the sixth connection terminals;

[0077] The infrared detector further includes a controller coupled to a third control terminal in the readout circuit, and the controller is configured to output the third selection signal to the third control terminal.

[0078] In some embodiments, the pixel array includes N+C pixel columns, the third valid portion includes N pixel columns, and the third redundant portion includes C pixel columns; and the circuit sub-sections are provided in N numbers;

[0079] The third gating circuit includes N third gating switches provided corresponding to the N circuit sub-sections, wherein the nth third gating switch includes:

[0080] a fifth connection terminal connected to the circuit sub-section in the nth column;

[0081] C+1 sixth connection ends respectively connected to the nth to n+Cth pixel columns; and

[0082] C+1 third switch control terminals corresponding to the C+1 sixth connection terminals, the third switch control terminals being configured to control the corresponding sixth connection terminals to be conductively connected to the fifth connection terminal when a conductive signal is input;

[0083] Wherein, N, C and n are all positive integers, N is greater than C, n = 1, 2, 3, ..., N;

[0084] The first control terminal includes the first switch control terminal of the N first gating switches, and the first gating signal includes a conduction signal corresponding to A+1 of the first switch control terminals.

[0085] In some embodiments, C is equal to 1.

[0086] In some embodiments, the third gating switch includes a fifth transistor and a sixth transistor, each of the fifth transistor and the sixth transistor includes a control electrode, a first electrode, and a second electrode;

[0087] In the fifth transistor of the nth third selection switch, the first electrode is the fifth connection terminal connected to the nth circuit sub-portion, the second electrode is the first of the sixth connection terminals connected to the nth pixel column, and the control electrode is the first of the third switch control terminals;

[0088] In the sixth transistor of the nth third selection switch, the first pole is the fifth connection terminal connected to the nth circuit sub-part, the second pole is the second sixth connection terminal connected to the n+1th pixel column, and the control pole is the second third switch control terminal.

[0089] In another aspect, a control method for an infrared detector is provided, which is applied to the infrared detector according to any one of the embodiments in the above aspect, and the control method includes:

[0090] Controlling the circuit sub-parts in the readout circuit and the pixel columns of the third effective part to be turned on in a one-to-one correspondence;

[0091] When the pixel column connected to the i-th circuit sub-section is unable to work, control the i-th and all subsequent circuit sub-sections to be connected to the next pixel column;

[0092] The i-th circuit sub-part is any one of the multiple circuit sub-parts.

[0093] In some embodiments, the infrared detector includes N+C pixel columns, N circuit sub-sections, and a third gating circuit, wherein the third gating circuit includes N third gating switches arranged corresponding to the N circuit sub-sections, the third gating switches being connected to the corresponding circuit sub-sections, and the pixel columns corresponding to the circuit sub-sections and the adjacent C pixel columns adjacent to the redundant portion are all connected to the same third gating switch; wherein N and C are both positive integers, and N is greater than C;

[0094] In the control method, the control circuit sub-parts in the readout circuit are turned on in a one-to-one correspondence with the pixel columns of the third effective part, including:

[0095] Controlling the gating states of the first to Nth third gating switches to connect the nth pixel column to the nth circuit sub-section, where n=1, 2, 3, ..., N;

[0096] The control circuit sub-parts of the i-th and i-th subsequent ones are connected to the next pixel column, including:

[0097] The gating states of the 1st to i-1th third gating switches are controlled to remain unchanged, and the gating states of the ith to Nth third gating switches are controlled to change, so that the ith to Nth column circuit sub-parts are all connected to the next column of pixel columns. BRIEF DESCRIPTION OF THE DRAWINGS

[0098] Figure 1 An architectural diagram of an infrared detector provided in an embodiment of the present application;

[0099] Figure 2 for Figure 1 Schematic diagram of the connection between the pixel array and the readout circuit;

[0100] Figure 3 A schematic diagram of a first gating switch provided in an embodiment of the present application;

[0101] Figure 4 A schematic diagram of a second gating switch provided in an embodiment of the present application;

[0102] Figure 5 A circuit diagram of an infrared detector provided in an embodiment of the present application;

[0103] Figure 6 A circuit diagram of a first gating switch and a second gating switch provided in an embodiment of the present application;

[0104] Figure 7 A flowchart of a method for controlling an infrared detector provided in an embodiment of the present application;

[0105] Figure 8 A flowchart of a method for controlling an infrared detector provided in an embodiment of the present application;

[0106] Figure 9 A circuit diagram of another infrared detector provided in an embodiment of the present application;

[0107] Figure 10 A schematic diagram of a third gating switch provided in an embodiment of the present application;

[0108] Figure 11 This is a flow chart of a method for controlling an infrared detector provided in an embodiment of the present application. DETAILED DESCRIPTION

[0109] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in some embodiments of the present application. Obviously, the embodiments described are only some embodiments of the present application, not all embodiments. Based on the embodiments provided in this application, all other embodiments obtained by ordinary technicians in this field are within the scope of protection of this application.

[0110] Unless the context requires otherwise, throughout the specification and claims, the term "including" is to be interpreted as having an open, inclusive meaning, that is, "including, but not limited to." In the description of the specification, the terms "one embodiment," "some embodiments," "exemplary embodiments," "examples," or "some examples" are intended to indicate that a particular feature, structure, material, or characteristic associated with the embodiment or example is included in at least one embodiment or example of the present application. The schematic representation of the above terms does not necessarily refer to the same embodiment or example. In addition, the particular features, structures, materials, or characteristics may be included in any one or more embodiments or examples in any appropriate manner.

[0111] In the following, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the embodiments of this application, unless otherwise specified, "plurality" means two or more.

[0112] When describing some embodiments, the expressions "coupled" and "connected" and their derivatives may be used. For example, when describing some embodiments, the term "connected" may be used to indicate that two or more components are in direct physical or electrical contact with each other. For another example, when describing some embodiments, the term "coupled" may be used to indicate that two or more components are in direct physical or electrical contact. However, the term "coupled" or "communicatively coupled" may also refer to two or more components that are not in direct contact with each other, but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the contents of this document.

[0113] "At least one of A, B and C" has the same meaning as "at least one of A, B or C", both including the following combinations of A, B and C: only A, only B, only C, the combination of A and B, the combination of A and C, the combination of B and C, and the combination of A, B and C.

[0114] "A and / or B" includes the following three combinations: A only, B only, and a combination of A and B.

[0115] As used herein, the term "if" is optionally interpreted to mean "when" or "upon" or "in response to determining" or "in response to detecting," depending on the context. Similarly, the phrase "if it is determined that" or "if [a stated condition or event] is detected" is optionally interpreted to mean "upon determining that" or "in response to determining that" or "upon detecting [a stated condition or event]" or "in response to detecting [a stated condition or event]," depending on the context. The use of "adapted to" or "configured to" herein is meant to be open and inclusive language that does not exclude devices adapted or configured to perform additional tasks or steps.

[0116] Additionally, the use of “based on” is meant to be open and inclusive, as a process, step, calculation, or other action “based on” one or more stated conditions or values ​​may, in practice, be based on additional conditions or values ​​beyond those stated.

[0117] As used herein, "about," "substantially," or "approximately" includes the stated value and an average value that is within an acceptable range of deviation from the particular value as determined by one of ordinary skill in the art taking into account the measurements in question and the errors associated with the measurement of the particular quantity (i.e., the limitations of the measurement system).

[0118] As used herein, "parallel", "perpendicular", and "equal" include the situations described and situations similar to the situations described, and the range of the similar situations is within an acceptable deviation range, wherein the acceptable deviation range is as determined by a person of ordinary skill in the art taking into account the measurement in question and the errors associated with the measurement of the specific quantity (i.e., the limitations of the measurement system). For example, "parallel" includes absolute parallelism and approximate parallelism, wherein the acceptable deviation range of approximate parallelism can be, for example, a deviation within 5°; "perpendicular" includes absolute perpendicularity and approximate perpendicularity, wherein the acceptable deviation range of approximate perpendicularity can also be, for example, a deviation within 5°. "Equal" includes absolute equality and approximate equality, wherein the acceptable deviation range of approximate equality can be, for example, that the difference between the two equals is less than or equal to 5% of either one.

[0119] Figure 1 This is a diagram of the architecture of an infrared detector provided in an embodiment of the present application, such as Figure 1 As shown, the infrared detector 1000 includes a pixel array 1, a readout integration circuit (RIOC) 3, and a controller 2. The pixel array 1 includes M×N pixels 101 arranged in M ​​rows and N columns. That is, the pixel array 1 includes N pixel columns 110, and each pixel column 110 includes M pixels 101.

[0120] Pixel 101 in pixel array 1 is an effective pixel capable of imaging, and may be a resistive imaging device, such as a vanadium oxide thermistor. During operation, pixel 101 converts light or thermal radiation emitted by a target object into a change in its own resistance.

[0121] In some embodiments, as Figure 1 As shown, the infrared detector 1000 is provided with a dummy pixel array 4 on one side of the pixel array 1. The dummy pixel array 4 includes M×K dummy pixels 401 arranged in M ​​rows and K columns. That is, the dummy pixel array 4 includes K dummy pixel columns 410, and each dummy pixel column 410 includes M dummy pixels 401. The dummy pixels 401 in the dummy pixel array 4 are "dummy" pixels that cannot form an image. One purpose of providing the dummy pixels 401 is to ensure that the surrounding environments of the first, last, and middle pixel columns 110 in the pixel array 1 are consistent, that is, to achieve matching.

[0122] The readout circuit 3 in the infrared detector 1000 is used to extract, integrate, sample / hold, and convert the resistance value change of the pixel 101 in the pixel array 1 to analog, and then output it to the controller 2. The controller 2 realizes infrared imaging based on the received signal.

[0123] It should be noted that the controller 2 is usually a host computer connected to the infrared detector 1000. However, in some scenarios, the controller 2 can be a part of the readout circuit 3. Although the embodiments of the present application are described by taking the readout circuit 3 not including the controller 2 as an example, the solution is also applicable to the case including the controller 2.

[0124] Figure 2 For Figure 1 the connection schematic diagram of the pixel array and the readout circuit, as Figure 2 shown, the pixel array 1 includes N columns of pixel columns 110, and the N columns of pixel columns 110 are Figure 2 successively represented by RS_1 to RS_N herein. The order of RS_1 to RS_N is used to represent the front-back relationship of the N columns of pixel columns 110. Exemplarily, the next column of the pixel column RS_1 is the pixel column RS_2, and the previous column of the pixel column RS_3 is the pixel column RS_2.

[0125] Please refer to Figure 2 , the readout circuit 3 includes a column compensation part 5 and a column readout circuit part 6. The column compensation part 5 includes a column compensation resistor unit 51 and a first gating circuit 52. The column compensation resistor unit 51 is used to achieve a certain compensation function, and can be a resistor, a group of resistors, or a circuit capable of realizing the resistor function. The embodiments of the present application do not limit this. In this embodiment, the column compensation resistor unit 51 is provided with N + A. The column readout circuit part 6 in the readout circuit 3 includes a column readout circuit 62 and a second gating circuit 61. The column readout circuit 62 is used to read the data in the pixel column 110. In this embodiment, the column readout circuit 62 is provided with N + B. Both A and B are positive integers, and N is greater than A, and N is greater than B; that is, the setting numbers of the column compensation resistor unit 51 and the column compensation circuit are both less than the number of columns of the pixel columns 110 in the pixel array 1.

[0126] In some embodiments, 1 ≤ A << N, 1 ≤ B << N. Here, A << N means that A is much smaller than N, and B << N means that B is much smaller than N. Generally, "much smaller" means that the two differ by at least one order of magnitude. Exemplarily, for the pixel array 1 of 1280×1024 and 1920×1280, both A and B should be in the order of no more than 100, such as 1, 10, 20, 100, etc. That is, in the readout circuit 3 provided by the embodiments of the present application, the number of the column compensation resistor units 51 is slightly larger than the number of columns of the pixel columns 110, and the number of the column readout circuits 62 is slightly larger than the number of columns of the pixel columns 110.

[0127] The N+A column compensation resistor units 51 include a first active portion and a first redundant portion. The first active portion includes N column compensation resistor units 51 corresponding one-to-one to the N pixel columns 110 in the pixel array 1. The first redundant portion is located to one side of the first active portion and includes A redundant column compensation resistor units 51. In this embodiment, the column compensation resistor units 51 corresponding to the pixel column RS_N in the first active portion are closer to the first redundant portion than the column compensation resistor units 51 corresponding to the pixel column RS_1. Combined with the above description of the front-to-back relationship of the pixel columns 110 in the pixel array 1, it can be seen that the first redundant portion is located behind the first active portion.

[0128] The first selection circuit 52 in the column compensation part 5 is arranged between the pixel array 1 and the N+A column compensation resistor units 51, and is configured to control the N pixel columns 110 in the pixel array 1 and the N column compensation resistor units 51 in the first effective part to be turned on in a one-to-one correspondence, and is configured to be able to control the i-th pixel column 110 and all pixel columns 110 behind the i-th column to be connected to the next column compensation resistor unit 51 when the column compensation resistor unit 51 connected to the i-th pixel column 110 fails to work.

[0129] Exemplarily, in an initial state, the first selection circuit 52 controls the conduction between the nth pixel column 110 and the nth column compensation resistor unit 51, where n=1, 2, 3, ..., N. The N+1th to N+Ath column compensation resistor units 51 in the first redundant portion are not connected to any pixel column 110. When the i-th column compensation resistor unit 51 connected to the i-th pixel column 110 malfunctions and fails to operate, the first selection circuit 52 is controlled to change the selection state so that the connection between the 1st to i-1th pixel columns 110 and the column compensation resistor unit 51 remains unchanged, and the i-th to Nth pixel columns 110 are controlled to be connected to the i+1th to N+1th column compensation resistor units 51, that is, to the next column compensation resistor unit 51; where i is any value between 1 and N.

[0130] With such a design, when a column compensation resistor unit 51 connected to a certain pixel column 110 in the pixel array 1 malfunctions and fails to work, that is, when a "bad column" occurs, the pixel column 110 and all the pixel columns 110 behind it are controlled to be connected to the next column compensation resistor unit 51, thereby achieving "bad column" calibration of the infrared detector 1000 and ensuring the normal operation of the infrared detector 1000.

[0131] In addition, since the number of column compensation resistor units 51 is slightly larger than the number of pixel columns 110, when an abnormality occurs in the column compensation resistor unit 51, that is, when a "bad column" occurs, the bad column in the pixel array 1 can be calibrated to ensure the normal operation of the infrared detector 1000 without significantly increasing the array area and production cost of the infrared detector 1000.

[0132] In some embodiments, the first selection circuit 52 includes a first connection end, a second connection end and a first control end, the first connection end is provided with N connections corresponding one-to-one to N columns of pixel columns 110, and the second connection end is provided with N+A connections corresponding one-to-one to N+A column compensation resistor units 51; the first control end is electrically connected to the controller 2 and is configured to receive a first selection signal sent by the controller 2 to the first selection circuit 52.

[0133] The first gating circuit 52 can be formed by a switching device that can control the conduction state. Exemplarily, the first gating circuit 52 includes N first gating switches, and the N first gating switches have the same structure. Each first gating switch includes a first connection terminal, A+1 second connection terminals and A+1 first switch control terminals.

[0134] In the nth first selection switch, where n=1, 2, 3, ..., N, a first connection terminal is connected to the nth pixel column 110, A+1 second connection terminals are connected to the nth to n+Ath column compensation resistor units 51, respectively, and the A+1 first switch control terminals are configured to receive a conduction signal. The A+1 first switch control terminal corresponds to the A+1 second connection terminals. When a first switch control terminal receives a conduction signal, the first selection switch conducts current between the second connection terminal corresponding to the first switch control terminal and the first connection terminal.

[0135] The first control terminal includes (A+1)×N first switch control terminals of the N first selection switches, and the first selection signal includes a conduction signal corresponding to the (A+1)×N first switch control terminals.

[0136] For example, when A is equal to 1, Figure 3 As shown, the first selection switch 521 includes a first connection terminal 521a, two second connection terminals 521b and two first switch control terminals 521c, wherein the two second connection terminals 521b and the two first switch control terminals 521c have a corresponding relationship. When a first switch control terminal 521c receives a conduction signal, the first selection switch 521 conducts the second connection terminal 521b and the first connection terminal 521a corresponding to the first switch control terminal 521c. For example, Figure 3 When the first switch control terminal 521c on the left side receives the conduction signal, the first selection switch 521 controls Figure 3The second connection end 521b on the left side is connected to the first connection end 521a; Figure 3 When the first switch control terminal 521c on the right side receives the conduction signal, the first selection switch 521 controls Figure 3 The second connection end 521b on the right side is electrically connected to the first connection end 521a.

[0137] In some embodiments, please combine Figure 1 The infrared detector 1000 further includes K virtual pixel columns 410, and when A is less than K, the column compensation part 5 of the readout circuit 3 further includes KA column compensation resistor units 51; wherein the N+1th to N+Kth column compensation resistor units 51 are connected to the 1st to Kth virtual pixel columns 410, respectively.

[0138] Please continue to refer to Figure 2 The arrangement of the column readout circuits 62 is similar to that of the column readout circuit 62. The N+B column readout circuits 62 include a second active portion and a second redundant portion. The second active portion includes N column readout circuits 62 corresponding one-to-one to the N pixel columns 110 in the pixel array 1. The second redundant portion is located to one side of the second active portion and includes B redundant column readout circuits 62. In this embodiment, the column readout circuits 62 corresponding to the pixel column RS_N in the second active portion are closer to the second redundant portion than the column readout circuits 62 corresponding to the pixel column RS_1. Combined with the above description of the contextual relationship of the pixel columns 110 in the pixel array 1, it can be seen that the second redundant portion is located after the second active portion.

[0139] The second selection circuit 61 in the column readout circuit 62 is arranged between the pixel array 1 and the N+B column readout circuits 62, and is configured to control the N pixel columns 110 in the pixel array 1 and the N column readout circuits 62 in the second effective part to be turned on one by one, and is configured to control the i-th pixel column 110 and all pixel columns 110 behind the i-th column to be connected to the next column readout circuit 62 when the column readout circuit 62 connected to the i-th pixel column 110 fails to work.

[0140] Illustratively, in an initial state, the second gating circuit 61 controls the connection between the nth pixel column 110 and the nth column readout circuit 62, where n=1, 2, 3, ..., N. The N+1th to N+Bth column readout circuits 62 in the second redundant portion are not connected to any pixel column 110. When the i-th column readout circuit 62 connected to the i-th pixel column 110 malfunctions and fails to operate, the second gating circuit 61 is controlled to change the gating state so that the connection between the 1st to i-1th pixel columns 110 and the column readout circuit 62 remains unchanged, and the i-th to Nth pixel columns 110 are controlled to connect to the i+1th to N+1th column readout circuits 62, that is, to the next column readout circuit 62. Where i is any value between 1 and N.

[0141] With this design, when a column readout circuit 62 connected to a certain pixel column 110 in the pixel array 1 malfunctions and fails to work, that is, when a "bad column" occurs, the pixel column 110 and all subsequent pixel columns 110 are controlled to be connected to the next column readout circuit 62, thereby achieving "bad column" calibration of the infrared detector 1000 and ensuring the normal operation of the infrared detector 1000.

[0142] In addition, since the number of column readout circuits 62 is slightly larger than the number of pixel columns 110, when an abnormality occurs in the column readout circuit 62, that is, when a "bad column" occurs, calibration of the bad column in the pixel array 1 is completed to ensure the normal operation of the infrared detector 1000 without significantly increasing the array area and production cost of the infrared detector 1000.

[0143] In some embodiments, the second selection circuit 61 includes a third connection terminal, a fourth connection terminal and a second control terminal, the third connection terminal is provided with N connections corresponding one-to-one to N columns of pixel columns 110, and the fourth connection terminal is provided with N+B connections corresponding one-to-one to N+B column readout circuits 62; the second control terminal is electrically connected to the controller 2 and is configured to receive a second selection signal sent by the controller 2 to the second selection circuit 61.

[0144] The second gating circuit 61 can be formed by a switching device that can control the conduction state. Exemplarily, the second gating circuit 61 includes N second gating switches, and the N second gating switches have the same structure. Each second gating switch includes a third connection terminal, B+1 fourth connection terminals and B+1 second switch control terminals.

[0145] In the nth second selection switch, where n=1, 2, 3, ..., N, a third connection terminal is connected to the nth pixel column 110, B+1 fourth connection terminals are connected to the nth to n+Bth column readout circuits 62, respectively, and B+1 second switch control terminals are configured to receive a conduction signal. The B+1 second switch control terminal corresponds to the B+1 fourth connection terminals. When a second switch control terminal receives a conduction signal, the second selection switch conducts the fourth connection terminal corresponding to the second switch control terminal and the third connection terminal.

[0146] The second control terminal includes (A+1)×N second switch control terminals of the N second selection switches, and the second selection signal includes a conduction signal corresponding to the (B+1)×N second switch control terminals.

[0147] For example, when B is equal to 1, Figure 4 As shown, the second selection switch 611 includes a third connection terminal 611a, two fourth connection terminals 611b and two second switch control terminals 611c, wherein the two fourth connection terminals 611b and the two second switch control terminals 611c have a corresponding relationship. When a second switch control terminal 611c receives a conduction signal, the first selection switch 521611 conducts the fourth connection terminal 611b and the third connection terminal 611a corresponding to the second switch control terminal 611c. For example, Figure 4 When the second switch control terminal 611c on the left side receives the conduction signal, the first selection switch 521611 controls Figure 4 The fourth connection terminal 611b on the left side is connected to the third connection terminal 611a; Figure 4 When the second switch control terminal 611c on the right side receives the conduction signal, the first selection switch 521611 controls Figure 4 The fourth connection end 611b on the right side is electrically connected to the third connection end 611a.

[0148] In some embodiments, please combine Figure 1 The infrared detector 1000 further includes K virtual pixel columns 410, and when B is less than K, the readout circuit 3 further includes KB column readout circuits 62; wherein the N+1th to N+Kth column readout circuits 62 are connected to the 1st to Kth virtual pixel columns 410, respectively.

[0149] In some embodiments, A and B are equal, that is, in the readout circuit 3, the number of column compensation resistor units 51 and the number of column readout circuits 62 are the same. For example, A and B are both 1, 2, 3, and so on.

[0150] The following takes A and B both equal to 1 as an example to further illustrate the solution provided in the embodiment of the present application.

[0151] Figure 5 For a circuit diagram of an infrared detector provided in an embodiment of the present application, please also refer to Figures 1 to 5 The infrared detector 1000 includes a pixel array 1 and a virtual pixel array 4. The pixel array 1 includes N pixel columns 110, with the first to Nth pixel columns 110 being represented by RS_1 to RS_N, respectively. The virtual pixel array 4 includes two virtual pixel columns 410, which are represented by RS_D1 to RS_D2, respectively. Virtual pixel column RS_D1 is closer to the pixel array 1 than virtual pixel column RS_D2.

[0152] In the infrared detector 1000, the readout circuit 3 includes a column compensation section 5 and a column readout circuit section 6. The column compensation section 5 includes N+2 column compensation resistor units 51 and a first selection circuit 52. The column readout circuit section 6 includes N+2 column readout circuits 62 and a second selection circuit 61. The N+2 column compensation resistor units 51 are sequentially represented by RD_1 to RD_N+2, and the N+2 column readout circuits 62 are sequentially represented by CH_1 to CH_N+2.

[0153] The first gating circuit 52 includes N first gating switches 521 of the same structure, which are sequentially represented by S1_1 to S1_N. The second gating circuit 61 includes N second gating switches 611 of the same structure, which are sequentially represented by S2_1 to S2_N.

[0154] like Figure 5 As shown, the first first selection switch S1_1 includes a first connection end and two second connection ends, the first connection end is connected to the first pixel column RS_1, and the two second connection ends are respectively connected to the first column compensation resistor unit RD_1 and the second column compensation resistor unit RD_2.

[0155] The second first selection switch S1_1 includes a first connection end and two second connection ends. The first connection end is connected to the second pixel column RS_2, and the two second connection ends are respectively connected to the second column compensation resistor unit RD_2 and the third column compensation resistor unit RD_3.

[0156] Similarly, the Nth first selection switch S1_N includes a first connection end and two second connection ends, one first connection end is connected to the Nth pixel column RS_N, and the two second connection ends are respectively connected to the Nth column compensation resistor unit RD_N and the N+1th column compensation resistor unit RD_N+1.

[0157] In addition, the (N+1)th column compensation resistor unit RD_N+1 is connected to the first dummy pixel column RS_D1 , and the (N+2)th column compensation resistor unit 51 is connected to the second dummy pixel column RS_D2 .

[0158] Please continue to refer to Figure 5 The first second selection switch S2_1 includes a third connection terminal and two fourth connection terminals, one third connection terminal is connected to the first pixel column RS_1, and the two fourth connection terminals are respectively connected to the first column readout circuit CH_1 and the second column readout circuit CH_2.

[0159] The second second selection switch S2_1 includes a third connection terminal and two fourth connection terminals. The third connection terminal is connected to the second pixel column RS_2, and the two fourth connection terminals are respectively connected to the second column readout circuit CH_2 and the third column readout circuit CH_3.

[0160] Similarly, the Nth second selection switch S2_N includes a third connection terminal and two fourth connection terminals. One third connection terminal is connected to the Nth pixel column RS_N, and the two fourth connection terminals are respectively connected to the Nth column readout circuit CH_N and the N+1th column readout circuit CH_N+1.

[0161] Furthermore, the (N+1)th column readout circuit CH_N+1 is connected to the first dummy pixel column RS_D1 , and the (N+2)th column readout circuit CH_N+2 is connected to the second dummy pixel column RS_D2 .

[0162] Figure 6 The circuit diagram of the first selection switch 521 and the second selection switch 611 provided in the embodiment of the present application is as follows: Figure 6 As shown, the first selection switch 521 includes a first transistor M1 and a second transistor M2 , and both the first transistor M1 and the second transistor M2 include a control electrode, a first electrode, and a second electrode.

[0163] In the first transistor M1_n of the n-th first selection switch S1_n, where n=1, 2, 3, ..., N; the first electrode is the first connection terminal connected to the n-th pixel column RS_n, the second electrode is the first second connection terminal connected to the n-th column compensation resistor unit RD_n, and the control electrode is the first first switch control terminal. The first first switch control terminal can be Sel_COL <n>express.

[0164] In the second transistor M2_n of the nth first selection switch S1_n, where n=1, 2, 3, ..., N; the first electrode is the first connection terminal connected to the nth pixel column RS_n, the second electrode is the second second connection terminal connected to the (n+1)th column compensation resistor unit RD_n+1, the control electrode is the second first switch control terminal, and the second first switch control terminal adopts Sel_COL_D <n>express.

[0165] The second gate switch 611 includes a third transistor M3 and a fourth transistor M4 . The third transistor M3 and the fourth transistor M4 each include a control electrode, a first electrode, and a second electrode.

[0166] In the third transistor M3_n of the nth second selection switch S2_n, where n=1, 2, 3, ..., N, the first electrode is the third connection terminal connected to the nth pixel column RS_n, the second electrode is the first fourth connection terminal connected to the nth column readout circuit CH_n, the control electrode is the first second switch control terminal, and the first second switch control terminal adopts Sel_R <n>express.

[0167] In the fourth transistor M4_n of the nth second selection switch S2_n, where n=1, 2, 3, ..., N, the first electrode is the third connection terminal connected to the nth pixel column RS_n, the second electrode is the second fourth connection terminal connected to the n+1th column readout circuit CH_n+1, the control electrode is the second second switch control terminal, and the second second switch control terminal adopts Sel_R_D <n>express.

[0168] Please continue to refer to Figure 5 The readout circuit 3 also includes a data conversion unit 7 connected to the column readout circuit 62. The data conversion unit 7 is used to convert the analog signal output by the column readout circuit 62 into a digital signal and transmit it to the controller 2. The controller 2 realizes infrared imaging based on the received signal.

[0169] For the above infrared detector 1000, its working process is as follows:

[0170] When the infrared detector 1000 has no bad columns, the controller 2 sends a first selection signal to the first selection circuit 52 and sends a second selection signal to the second selection circuit 61. The first selection signal includes the first to Nth first sub-control terminals Sel_COL <1> To Sel_COL <n>The second selection signal includes the first to the Nth third sub-control terminal Sel_R <1> To Sel_R <n>In this case, the first selection circuit 52 controls the 1st to Nth pixel columns 110 to be connected to the 1st to Nth column compensation resistor units 51 respectively, and the second selection circuit 61 controls the 1st to Nth pixel columns 110 to be connected to the 1st to Nth column readout circuits 62 respectively.

[0171] When bad columns occur in the infrared detector 1000 , the controller 2 confirms the number of bad columns and the bad column types, where the bad column types include abnormalities in the column compensation resistor unit 51 and the column readout circuit 62 .

[0172] If the bad column is caused by an abnormality in the column compensation resistor unit 51, when the i-th pixel column 110 has a bad column, the controller 2 sends a first selection signal to the first selection circuit 52 and sends a second selection signal to the second selection circuit 61; the first selection signal includes the 1st to the i-1th first sub-control terminals Sel_COL <1> To Sel_COL <i-1>The conduction signal, and the i-th to N-th second sub-control terminals Sel_COL_D To Sel_COL_D <n>The second selection signal includes the first to the Nth third sub-control terminal Sel_R <1> To Sel_R <n>The conduction signal;

[0173] In this case, the first selection circuit 52 controls the 1st to i-1th pixel columns 110 and the 1st to i-1th column compensation resistor units 51 to be turned on respectively, and the i-th to Nth pixel columns 110 and the i+1th to N+1th column compensation resistor units 51 to be turned on respectively; the second selection circuit 61 controls the 1st to Nth pixel columns 110 and the 1st to Nth column readout circuits 62 to be turned on respectively.

[0174] If the bad column is caused by an abnormality in the column readout circuit 62, when the i-th pixel column 110 has a bad column, the controller 2 sends a first gating signal to the first gating circuit 52 and a second gating signal to the second gating circuit 61; the first gating signal includes the 1st to the Nth first sub-control terminals Sel_COL <1> To Sel_COL <n>The second selection signal includes the first to the i-1 third sub-control terminal Sel_R <1> To Sel_R <i-1>and the ith to the Nth fourth sub-control terminal Sel_R_D To Sel_R_D <n>The conduction signal;

[0175] In this case, the first selection circuit 52 controls the 1st to Nth pixel columns 110 to be connected to the 1st to Nth column compensation resistor units 51 respectively; the second selection circuit 61 controls the 1st to i-1th pixel columns 110 to be connected to the 1st to i-1th column readout circuits 62 respectively, and the i-th to Nth pixel columns 110 to the i+1th to N+1th column readout circuits 62 respectively.

[0176] It can be seen from the above working process that when a bad column appears in the i-th pixel column 110, the i+1-th column readout circuit 62 or column compensation resistor unit 51 is added to the i-th pixel column 110, and the i+2-th column readout circuit 62 or column compensation resistor unit 51 is added to the i+1-th pixel column 110, and so on, to complete the correction of the bad columns in the infrared detector 1000.

[0177] In addition, the inventors found in their research that the bad columns in the imaging of the infrared detector 1000 are not only caused by the column readout circuit 62, but are more likely caused by damage to the column compensation resistor unit 51. Based on this, in some embodiments, the column compensation part 5 of the readout circuit 3 adopts the scheme in the above embodiment, and the column readout circuit part 6 can adopt a scheme different from the above embodiment. For example, the column readout circuit part 6 can adopt a scheme in the prior art or other possible schemes that can realize pixel column data reading.

[0178] However, the embodiments of the present application are not limited to this. In other embodiments, the column readout circuit part 6 of the readout circuit 3 adopts the solution in the above embodiment, and the column compensation part 5 can adopt a solution different from the above embodiment. For example, the column compensation part 5 can adopt a solution in the prior art or other possible solutions that can achieve the same compensation function.

[0179] The embodiment of the present application also provides a control method of the infrared detector 1000, which is applied to the infrared detector 1000 in the above embodiment. Figure 7 As shown, the control method includes:

[0180] Step S100 : controlling a plurality of pixel columns in the pixel array and a plurality of column compensation resistor units in the first active portion to be turned on in a one-to-one correspondence.

[0181] Step S200 : when the column compensation resistor unit connected to the i-th pixel column fails to work, controlling the i-th pixel column and all pixel columns behind the i-th pixel column to be connected to the next column compensation resistor unit.

[0182] The i-th pixel column 110 is any one of the multiple pixel columns 110 .

[0183] Steps S100 to S200 are designed for the column compensation part 5 in the readout circuit 3 of the infrared detector 1000. By using the control method provided in the embodiment of the present application, when a column compensation resistor unit 51 connected to a certain pixel column 110 in the pixel array 1 becomes abnormal and cannot work, that is, when a "bad column" occurs, the pixel column 110 and all the subsequent pixel columns 110 are controlled to be connected to the next column compensation resistor unit 51, thereby realizing the "bad column" calibration of the infrared detector 1000 and ensuring the normal operation of the infrared detector 1000.

[0184] The working process and working principle of this control method can be referred to the above description. It should be noted that the above-mentioned "recursive" control method can rely on the circuit structure provided above, and can also adopt other circuit structures that can achieve the same function. For example, it can be implemented using an integrated circuit having the above-mentioned functions.

[0185] In some embodiments, the infrared detector 1000 includes N columns of pixel columns 110, N+A column compensation resistor units 51 and a first gating circuit 52. The description of the pixel columns 110, column compensation resistor units 51 and the first gating circuit 52 in the infrared detector 1000 can be referred to above and will not be repeated here.

[0186] Correspondingly, in the control method, step S100 may include: controlling the selection states of the 1st to Nth first selection switches 521 to connect the nth pixel column 110 and the nth column compensation resistor unit 51, where n=1, 2, 3, ..., N.

[0187] Step S200 may include: controlling the gating states of the 1st to i-1th first gating switches 521 to remain unchanged, controlling the i-th to N-th first gating switches 521 to change the gating states, so that the i-th to N-th pixel columns 110 are all connected to the next column compensation resistor unit 51.

[0188] The embodiment of the present application also provides another control method of the infrared detector 1000, which is applied to the infrared detector 1000 in the above embodiment. Figure 8 As shown, the control method includes:

[0189] Step S300 : controlling a plurality of pixel columns in the pixel array 1 and a plurality of column readout circuits in the second active portion to be turned on in a one-to-one correspondence.

[0190] Step S400 : When the column readout circuit connected to the i-th pixel column fails to work, control the i-th pixel column and all pixel columns 110 behind the i-th pixel column to be connected to the next column readout circuit.

[0191] The i-th pixel column 110 is any one of the multiple pixel columns 110 .

[0192] Steps S300 to S400 are designed for the column readout circuit portion 6 in the readout circuit 3 of the infrared detector 1000. By adopting the control method provided in the embodiment of the present application, when a column readout circuit 62 connected to a certain pixel column 110 in the pixel array 1 becomes abnormal and cannot work, that is, when a "bad column" occurs, the pixel column 110 and all the subsequent pixel columns 110 are controlled to be connected to the next column readout circuit 62, thereby achieving "bad column" calibration of the infrared detector 1000 and ensuring the normal operation of the infrared detector 1000.

[0193] The working process and working principle of this control method can be referred to above. It should be noted that the above-mentioned "recursive" control method can rely on the circuit structure provided above, and can also adopt other circuit structures that can achieve the same function. For example, it can be implemented by an integrated circuit having the above-mentioned functions.

[0194] In some embodiments, the infrared detector 1000 includes N columns of pixel columns 110, N+B column readout circuits 62 and a second gating circuit 61. The description of the pixel columns 110, the column readout circuits 62 and the second gating circuit 61 in the infrared detector 1000 can be referred to above and will not be repeated here.

[0195] Correspondingly, in the control method, step S300 may include: controlling the selection states of the 1st to Nth second selection switches 611 to connect the nth pixel column 110 and the nth column compensation resistor unit 51, where n=1, 2, 3, ..., N.

[0196] Step S400 may include: controlling the gating states of the 1st to i-1th second gating switches 611 to remain unchanged, and controlling the i-th to N-th second gating switches 611 to change the gating states, so that the i-th to N-th pixel columns 110 are all connected to the next column compensation resistor unit 51.

[0197] Based on the same inventive concept, the embodiment of the present application also provides another infrared detector 1000, such as Figure 9 As shown, the infrared detector 1000 includes a pixel array 1 and a readout circuit 3 coupled to the pixel array 1; wherein the pixel array 1 includes N+C pixel rows 110, and the N+C pixel rows 110 are arranged in a Figure 9 RS_1 to RS_N+C are used in sequence. N+C pixel columns 110 include a third effective part 11 and a third redundant part 12. The third effective part 11 includes N columns of effective pixel columns used for normal imaging. Figure 9 They are successively represented by RS_1 to RS_N; the third redundant portion 12 includes C columns of redundant pixel columns used as redundancy. In Figure 9 they are successively represented by RS_N+1 to RS_N+C; where N is greater than C, that is, the number of columns of redundant pixel columns is less than the number of columns of effective pixel columns.

[0198] In some embodiments, 1≤C<<N, where C<<N means that C is much less than N. Usually, "much less than" means that the difference between the two is at least one order of magnitude. Exemplarily, for pixel arrays 1 of 1280×1024 and 1920×1280, C should be on the order of no more than 100, such as 1, 10, 20, 100, etc. From the above description, it can be seen that in pixel array 1, only a relatively small number of redundant pixel columns are provided.

[0199] Please continue to refer to Figure 9 , the readout circuit 3 includes a circuit sub-part 8 and a third gating circuit 9. The circuit sub-part 8 is provided with N ones corresponding one-to-one to the N columns of pixel columns 110 in the third effective portion 11. Each circuit sub-part 8 includes a column compensation resistance unit 51 and / or a column readout circuit 62 (please refer to Figure 2 ). The third gating circuit 9 is disposed between the pixel array 1 and the N circuit sub-parts 8.

[0200] The third gating circuit 9 is configured to control the one-to-one conduction of the N circuit sub-parts 8 and the N columns of pixel columns 110 in the third effective portion 11, and is configured to be able to control the i-th circuit sub-part 8 and all subsequent circuit sub-parts 8 to be connected to the next column of pixel columns 110 when the pixel column​​​​​With this design, when a pixel column 110 connected to a certain circuit sub-section 8 becomes abnormal and fails to work, that is, when a "bad column" occurs, the circuit sub-section 8 and all subsequent circuit sub-sections 8 are controlled to be connected to the next pixel column 110, thereby achieving "bad column" calibration of the infrared detector 1000 and ensuring the normal operation of the infrared detector 1000.

[0203] In addition, only a small number of pixel columns 110 are provided in the pixel array 1 for redundancy. Therefore, when an abnormality occurs in the pixel column 110, that is, when a "bad column" occurs, the bad column in the pixel array 1 can be calibrated to ensure the normal operation of the infrared detector 1000 without significantly increasing the array area and production cost of the infrared detector 1000.

[0204] In some embodiments, the third selection circuit 9 includes a fifth connection terminal, a sixth connection terminal and a third control terminal, the fifth connection terminal is provided with N connections corresponding one-to-one to the N circuit sub-parts 8, and the sixth connection terminal is provided with N+C connections corresponding one-to-one to the N+C columns of pixel columns 110; the third control terminal is electrically connected to the controller 2 and is configured to receive a third selection signal sent by the controller 2 to the third selection circuit 9.

[0205] The third gating circuit 9 can be formed by a switching device that can control the conduction state. Exemplarily, the third gating circuit 9 includes N third gating switches, and the N third gating switches have the same structure. Each third gating switch includes a fifth connection terminal, C+1 sixth connection terminals and C+1 third switch control terminals.

[0206] In the nth third selection switch, where n=1, 2, 3, ..., N, a fifth connection terminal is connected to the nth circuit sub-section 8, C+1 sixth connection terminals are connected to the nth through n+Cth pixel columns 110, respectively, and the C+1 third switch control terminals are configured to receive a conduction signal. The C+1 third switch control terminal corresponds to the C+1 sixth connection terminals. When a third switch control terminal receives a conduction signal, the third selection switch conducts the sixth connection terminal and the fifth connection terminal corresponding to the third switch control terminal.

[0207] The third control terminal includes (C+1)×N third switch control terminals of the N third selection switches, and the third selection signal includes a conduction signal corresponding to the (C+1)×N third switch control terminals.

[0208] For example, when C is equal to 1, Figure 10 As shown, the third selection switch 91 includes a fifth connection terminal 91a, two sixth connection terminals 91b and two third switch control terminals 91c, wherein the two sixth connection terminals 91b and the two third switch control terminals 91c have a corresponding relationship. When a third switch control terminal 91c receives a conduction signal, the first selection switch 52191 conducts the sixth connection terminal 91b and the fifth connection terminal 91a corresponding to the third switch control terminal 91c. For example, Figure 3 When the third switch control terminal 91c on the left side receives the conduction signal, the first selection switch 52191 controls Figure 3 The sixth connection terminal 91b on the left side is connected to the fifth connection terminal 91a; Figure 3 When the third switch control terminal 91c on the right side receives the conduction signal, the first selection switch 52191 controls Figure 3 The sixth connection end 91b on the right side is electrically connected to the fifth connection end 91a.

[0209] In some embodiments, C is equal to 1, and the third selection switch 91 includes a fifth transistor and a sixth transistor, each of which includes a control electrode, a first electrode, and a second electrode;

[0210] In the fifth transistor of the nth third selection switch 91, the first electrode is the fifth connection terminal connected to the nth circuit sub-section 8, the second electrode is the first sixth connection terminal connected to the nth pixel column 110, and the control electrode is the first third switch control terminal;

[0211] In the sixth transistor of the nth third selection switch 91, the first pole is the fifth connection terminal connected to the nth circuit sub-part 8, the second pole is the second sixth connection terminal connected to the (n+1)th pixel column 110, and the control pole is the second third switch control terminal.

[0212] With respect to the infrared detector 1000 in the above embodiment, the present application also provides a control method of the infrared detector 1000, such as Figure 11 As shown, the control method includes:

[0213] Step S500: controlling the circuit sub-parts in the readout circuit and the pixel columns in the third effective part to be turned on in a one-to-one correspondence.

[0214] Step S600 : When the pixel column connected to the i-th circuit sub-section is unable to work, control the i-th and all subsequent circuit sub-sections to be connected to the next pixel column.

[0215] The i-th circuit sub-section 8 is any one of the multiple circuit sub-sections 8 .

[0216] Steps S500 to S600 are for Figure 9 The infrared detector 1000 shown is designed and adopts the control method provided in the embodiment of the present application. When a pixel column 110 connected to a certain circuit sub-section 8 becomes abnormal and cannot work, that is, when a "bad column" occurs, the circuit sub-section 8 and all subsequent circuit sub-sections 8 are controlled to be connected to the next pixel column 110, thereby realizing the "bad column" calibration of the infrared detector 1000 and ensuring the normal operation of the infrared detector 1000.

[0217] In addition, only a small number of pixel columns 110 are provided in the pixel array 1 for redundancy. Therefore, when an abnormality occurs in the pixel column 110, that is, when a "bad column" occurs, the bad column in the pixel array 1 can be calibrated to ensure the normal operation of the infrared detector 1000 without significantly increasing the array area and production cost of the infrared detector 1000.

[0218] The working process and working principle of this control method can be referred to above. It should be noted that the above-mentioned "recursive" control method can rely on the circuit structure provided above, and can also adopt other circuit structures that can achieve the same function. For example, it can be implemented by an integrated circuit having the above-mentioned functions.

[0219] In some embodiments, the infrared detector 1000 includes N+C columns of pixel columns 110, N circuit sub-parts 8 and a third gating circuit 9. The description of the pixel columns 110, circuit sub-parts 8 and the third gating circuit 9 in the infrared detector 1000 can be referred to above and will not be repeated here.

[0220] Correspondingly, in the control method, step S500 may include: controlling the gating states of the first to Nth third gating switches 91 to connect the nth pixel column 110 to the nth circuit sub-section 8, where n=1, 2, 3, ..., N;

[0221] Step S600 may include: controlling the gating states of the 1st to i-1th third gating switches 91 to remain unchanged, controlling the i-th to N-th third gating switches 91 to change the gating states, so that the i-th to N-th column circuit sub-sections 8 are all connected to the next column of pixel columns 110.

[0222] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some or all of the technical features therein. These modifications or replacements do not deviate the essence of the corresponding technical solutions from the scope of the technical solutions of the embodiments of the present application.< / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n>

Claims

1. An infrared detector, characterized in that: The infrared detector includes a pixel array and a readout circuit; the pixel array includes a plurality of pixel columns; The readout circuit is coupled to the pixel array and includes a column compensation portion and a column readout circuit portion; wherein the column compensation portion includes: a plurality of column compensation resistor units, the plurality of column compensation resistor units including a first active portion and a first redundant portion, the first active portion including column compensation resistor units corresponding one-to-one to a plurality of columns of pixels in the pixel array, the first redundant portion including at least one column compensation resistor unit used as a redundant portion; and a first gating circuit, the first gating circuit being configured to control a plurality of pixel columns in the pixel array to be electrically conductive in a one-to-one correspondence with the column compensation resistor units in the first active portion, and being configured to control the i-th column and all pixel columns subsequent thereto to be connected to the next column compensation resistor unit when the column compensation resistor unit connected to the i-th pixel column fails to operate; and / or The column readout circuit section includes: a plurality of column readout circuits, the plurality of column readout circuits including a second active portion and a second redundant portion located on one side of the second active portion, the second active portion including column readout circuits corresponding one-to-one to a plurality of pixel columns in the pixel array, the second redundant portion including at least one column readout circuit for redundancy; and a second gating circuit, the second gating circuit being configured to control a plurality of pixel columns in the pixel array to be electrically connected to the column readout circuits in the second active portion in a one-to-one correspondence, and being configured to control the i-th column and all pixel columns subsequent thereto to be connected to the next column readout circuit when the column readout circuit connected to the i-th pixel column fails to operate; The i-th pixel column is any one of the multiple pixel columns.

2. The infrared detector according to claim 1, characterized in that: The first gating circuit includes: A plurality of first connection ends connected to the pixel columns in the pixel array in a one-to-one correspondence; a plurality of second connection terminals connected to the column compensation resistor units in a one-to-one correspondence with the column compensation resistor units; and a first control terminal configured to receive a first selection signal; Wherein, when the first control terminal receives the first gating signal, the first gating circuit controls the first connection terminal to be connected to one of the second connection terminals; The infrared detector further includes a controller coupled to a first control terminal in the readout circuit, and the controller is configured to output the first selection signal to the first control terminal.

3. The infrared detector according to claim 2, characterized in that: The pixel array includes N pixel columns, the column compensation resistor units are provided with N+A units, the first effective part includes N column compensation resistor units, and the first redundant part includes A column compensation resistor units; The first gating circuit includes N first gating switches arranged corresponding to N columns of pixel columns, wherein the nth first gating switch includes: One of the first connection ends connected to the n-th column of pixel columns; A+1 second connection terminals respectively connected to the nth to n+Ath column compensation resistor units; and A+1 first switch control terminals corresponding to the A+1 second connection terminals, the first switch control terminals being configured to control the corresponding second connection terminals to be connected to the first connection terminals when a conduction signal is input; Wherein, N, A and n are all positive integers, N is greater than A, n = 1, 2, 3, ..., N; The first control terminal includes the first switch control terminal of the N first gating switches, and the first gating signal includes a conduction signal corresponding to A+1 of the first switch control terminals.

4. The infrared detector according to claim 3, characterized in that: A is equal to 1.

5. The infrared detector according to claim 4, characterized in that: The first gate switch includes a first transistor and a second transistor, and the first transistor and the second transistor each include a control electrode, a first electrode and a second electrode; In the first transistor of the nth first gating switch, the first electrode is the first connection end connected to the nth column of pixel columns, the second electrode is the first second connection end connected to the nth column compensation resistor unit, and the control electrode is the first first switch control end; In the second transistor of the nth first selection switch, the first pole is the first connection end connected to the nth column of the pixel column, the second pole is the second second connection end connected to the (n+1)th column compensation resistor unit, and the control pole is the second first switch control end.

6. The infrared detector according to claim 1, characterized in that: The second gating circuit includes: A plurality of third connection terminals connected to the pixel columns in the pixel array in a one-to-one correspondence; a plurality of fourth connection terminals connected to the column readout circuits in a one-to-one correspondence with the column readout circuits; and a second control terminal configured to receive a second selection signal; Wherein, when the second control terminal receives the second gating signal, the second gating circuit controls the third connection terminal to be connected to one of the fourth connection terminals; The infrared detector further includes a controller coupled to the second control terminal in the readout circuit, and the controller is configured to output the second selection signal to the second control terminal.

7. The infrared detector according to claim 6, characterized in that: The pixel array includes N pixel columns, the column readout circuits are provided with N+B pieces, the second effective part includes N of the column readout circuits, and the second redundant part includes B of the column readout circuits; The second gating circuit includes N second gating switches arranged corresponding to N columns of pixel columns, wherein the nth second gating switch includes: A third connection end connected to the n-th column of pixel columns; B+1 fourth connection terminals respectively connected to the nth to n+Bth column readout circuits; and B+1 second switch control terminals corresponding to the B+1 fourth connection terminals, the second switch control terminals being configured to control the corresponding fourth connection terminals to be conductively connected to the third connection terminal when a conductive signal is input; Wherein, N, B and n are all positive integers, N is greater than B, n = 1, 2, 3, ..., N; The second control terminal includes the second switch control terminals of N second selection switches, and the second selection signal includes conduction signals corresponding to B+1 second switch control terminals.

8. The infrared detector according to claim 7, characterized in that: B is equal to 1.

9. The infrared detector according to claim 8, characterized in that: The second gate switch includes a third transistor and a fourth transistor, and each of the third transistor and the fourth transistor includes a control electrode, a first electrode, and a second electrode; In the third transistor of the nth second selection switch, the first electrode is the third connection terminal connected to the nth column of pixel columns, the second electrode is the first fourth connection terminal connected to the nth column readout circuit, and the control electrode is the first second switch control terminal; In the fourth transistor of the nth second selection switch, the first pole is the third connection terminal connected to the nth column of the pixel column, the second pole is the second fourth connection terminal connected to the (n+1)th column readout circuit, and the control pole is the second second switch control terminal.

10. A method for controlling an infrared detector, characterized in that: Applied to the infrared detector according to any one of claims 1 to 9, the control method comprises: Controlling the plurality of pixel columns in the pixel array and the plurality of column compensation resistor units in the first effective part to be turned on in a one-to-one correspondence; When the column compensation resistor unit connected to the i-th column of pixels fails to work, controlling the i-th column and all the pixel columns behind the i-th column to be connected to the next column compensation resistor unit; and / or Controlling the plurality of pixel columns in the pixel array and the plurality of column readout circuits in the second effective part to be turned on in a one-to-one correspondence; When the column readout circuit connected to the i-th column of pixels fails to work, controlling the i-th column and all the pixel columns behind the i-th column to be connected to the next column readout circuit; The i-th pixel column is any one of the multiple pixel columns.

11. The control method according to claim 10, characterized in that: The infrared detector includes N pixel columns, N+A column compensation resistor units, and a first gating circuit, wherein the first gating circuit includes N first gating switches arranged corresponding to the N pixel columns, the first gating switches being connected to the corresponding pixel columns, and the column compensation resistor units corresponding to the pixel columns and the adjacent A column compensation resistor units near the redundant portion being all connected to the same first gating switch; wherein N and A are both positive integers, and N is greater than A; In the control method, the control method of connecting multiple pixel columns in the pixel array and multiple compensation resistor units in the first effective part in a one-to-one correspondence includes: Controlling the gating states of the 1st to Nth first gating switches to connect the nth column of pixel elements to the nth column compensation resistor unit, where n=1, 2, 3, ..., N; The method of controlling the pixel columns of the i-th column and all the pixel columns after the i-th column to be connected to the next column compensation resistor unit includes: The gating states of the 1st to i-1th first gating switches are controlled to remain unchanged, and the gating states of the ith to Nth first gating switches are controlled to change, so that the ith to Nth pixel columns are all connected to the next column compensation resistor unit.

12. The control method according to claim 10 or 11, characterized in that: The infrared detector includes N pixel columns, N+B column readout circuits, and a second gating circuit. The second gating circuit includes N second gating switches arranged corresponding to the N pixel columns. The second gating switches are connected to the corresponding pixel columns. The column readout circuit corresponding to the pixel column and the adjacent B column readout circuits near the redundant portion are all connected to the same second gating switch. Wherein, N and B are both positive integers, and N is greater than B. In the control method, the control method of connecting multiple pixel columns in the pixel array and multiple compensation resistor units in the first effective part in a one-to-one correspondence includes: Controlling the gating states of the first to Nth second gating switches to connect the nth column of pixel elements to the nth column compensation resistor unit, where n=1, 2, 3, ..., N; The control method of connecting the i-th column and all pixel columns after the i-th column to the next column readout circuit includes: The gating states of the 1st to i-1th second gating switches are controlled to remain unchanged, and the gating states of the ith to Nth second gating switches are controlled to change, so that the ith to Nth pixel columns are all connected to the next column compensation resistor unit.

13. An infrared detector, characterized in that: The infrared detector includes a pixel array and a readout circuit coupled to the pixel array; the pixel array includes a plurality of pixel columns, the plurality of pixel columns include a third effective portion and a third redundant portion located on one side of the third effective portion, the third effective portion includes a plurality of pixel columns used for imaging, and the third redundant portion includes at least one pixel column used as a redundant column; The readout circuit comprises: a plurality of circuit sub-sections, each of the plurality of circuit sub-sections corresponding one-to-one to a pixel column in the third active portion, the circuit sub-sections comprising a column compensation resistor unit and / or a column readout circuit; and a third gating circuit, the third gating circuit being configured to control the circuit sub-sections in the readout circuit to be turned on in a one-to-one correspondence with the pixel columns of the third effective section, and being configured to control the i-th and all subsequent circuit sub-sections to be connected to the next pixel column when the pixel column connected to the i-th circuit sub-section is unable to operate; The i-th circuit sub-part is any one of the multiple circuit sub-parts.

14. The infrared detector according to claim 13, characterized in that: The third gating circuit includes: a plurality of fifth connection terminals connected to the circuit sub-parts in a one-to-one correspondence with the circuit sub-parts of the plurality of circuit sub-parts; a plurality of sixth connection ends connected to the pixel columns in a one-to-one correspondence with the pixel columns; and a third control terminal configured to receive a third selection signal; Wherein, when the third control terminal receives the third gating signal, the third gating circuit controls the fifth connection terminal to be connected to one of the sixth connection terminals; The infrared detector further includes a controller coupled to a third control terminal in the readout circuit, and the controller is configured to output the third selection signal to the third control terminal.

15. The infrared detector according to claim 14, characterized in that: The pixel array includes N+C pixel columns, the third valid portion includes N pixel columns, and the third redundant portion includes C pixel columns; the circuit sub-parts are provided in N numbers; The third gating circuit includes N third gating switches provided corresponding to the N circuit sub-sections, wherein the nth third gating switch includes: a fifth connection terminal connected to the circuit sub-section in the nth column; C+1 sixth connection ends respectively connected to the nth to n+Cth pixel columns; and C+1 third switch control terminals corresponding to the C+1 sixth connection terminals, the third switch control terminals being configured to control the corresponding sixth connection terminals to be conductively connected to the fifth connection terminal when a conductive signal is input; Among them, N, C and n are all positive integers, N is greater than C, and n = 1, 2, 3,…, N.

16. The infrared detector according to claim 15, characterized in that: C is equal to 1.

17. The infrared detector according to claim 16, characterized in that: The third gate switch includes a fifth transistor and a sixth transistor, each of the fifth transistor and the sixth transistor includes a control electrode, a first electrode and a second electrode; In the fifth transistor of the nth third selection switch, the first electrode is the fifth connection terminal connected to the nth circuit sub-portion, the second electrode is the first of the sixth connection terminals connected to the nth pixel column, and the control electrode is the first of the third switch control terminals; In the sixth transistor of the nth third selection switch, the first pole is the fifth connection terminal connected to the nth circuit sub-part, the second pole is the second sixth connection terminal connected to the n+1th pixel column, and the control pole is the second third switch control terminal.

18. A method for controlling an infrared detector, characterized in that: Applied to the infrared detector according to any one of claims 13 to 17, the control method comprises: Controlling the circuit sub-parts in the readout circuit and the pixel columns of the third effective part to be turned on in a one-to-one correspondence; When the pixel column connected to the i-th circuit sub-section is unable to work, control the i-th and all subsequent circuit sub-sections to be connected to the next pixel column; The i-th circuit sub-part is any one of the multiple circuit sub-parts.

19. The control method according to claim 18, characterized in that: The infrared detector includes N+C pixel columns, N circuit sub-sections, and a third gating circuit, wherein the third gating circuit includes N third gating switches arranged corresponding to the N circuit sub-sections, the third gating switches being connected to the corresponding circuit sub-sections, and the pixel columns corresponding to the circuit sub-sections and the adjacent C pixel columns adjacent to the redundant portion are all connected to the same third gating switch; wherein N and C are both positive integers, and N is greater than C; In the control method, the control circuit sub-parts in the readout circuit are turned on in a one-to-one correspondence with the pixel columns of the third effective part, including: Controlling the gating states of the first to Nth third gating switches to connect the nth pixel column to the nth circuit sub-section, where n=1, 2, 3, ..., N; The control circuit sub-parts of the i-th and i-th subsequent ones are connected to the next pixel column, including: The gating states of the 1st to i-1th third gating switches are controlled to remain unchanged, and the gating states of the ith to Nth third gating switches are controlled to change, so that the ith to Nth column circuit sub-parts are all connected to the next column of pixel columns.

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