Power generation for transmitters

Abstract

The present disclosure relates to power generation for a transmitter. In one aspect, a first circuit generates a first signal having a first amplitude based on a first supply voltage. A latch may be coupled to a resistor of a plurality of resistors coupled in series. One end of the resistor may be configured to provide a second supply voltage, which is higher than the first supply voltage, to the latch based on a third supply voltage that is higher than the second supply voltage, and the other end of the resistor may be configured to receive the third supply voltage. The latch may modify the first signal based on the second supply voltage to provide a second signal. An amplifier may amplify the second signal based on a third supply voltage to provide a third signal having a second amplitude greater than the first amplitude.

Description

Technical Field

[0001] The present disclosure generally relates to systems and methods for providing different power supply levels, including but not limited to systems and methods for providing different power supply levels for amplifiers. Background Art

[0002] Recent advances in circuit design have enabled the integration of various circuit components into smaller form factors. In one example, millions of circuit components can be integrated into an integrated circuit (or chip) to perform a variety of operations. Different portions of the circuitry within an integrated circuit can operate in different power domains. For example, digital circuits can be powered and operated according to a first power domain, while analog circuits can be powered and operated according to a second power domain. Summary of the Invention

[0003] Various embodiments disclosed herein relate to a system comprising a first circuit, a second circuit, a third circuit, and a resistor ladder. In some embodiments, the first circuit is configured to generate a first signal having a first voltage amplitude based on a first supply voltage. In some embodiments, the second circuit is electrically coupled to the first circuit. In some embodiments, the second circuit comprises a latch circuit to modify the first signal to generate a second signal based on a second supply voltage higher than the first supply voltage. In some embodiments, the third circuit is electrically coupled to the second circuit. In some embodiments, the third circuit is configured to amplify the second signal based on a third supply voltage higher than the second supply voltage to generate a third signal having a second voltage amplitude greater than the first voltage amplitude. In some embodiments, the resistor ladder circuit comprises at least a first resistor and a second resistor electrically coupled in series. In some embodiments, one end of the first resistor is configured to receive the third supply voltage. In some embodiments, one end of the second resistor is electrically coupled to the latch circuit to provide the second supply voltage to the latch circuit based on the third supply voltage.

[0004] Various embodiments disclosed herein relate to a system comprising circuitry that generates a first signal having a first voltage amplitude based on a first supply voltage. In some embodiments, the circuitry includes a latch electrically coupled to a resistor in a plurality of resistors electrically coupled in series. In some embodiments, one end of the resistor is configured to provide a second supply voltage to the latch based on a third supply voltage. In some embodiments, the other end of the resistor is configured to receive the third supply voltage. In some embodiments, the circuitry is configured to modify the first signal by the latch based on a second supply voltage that is higher than the first supply voltage to provide a second signal. In some embodiments, the circuitry is configured to amplify the second signal based on the third supply voltage that is higher than the second supply voltage to provide a third signal having a second voltage amplitude greater than the first voltage amplitude.

[0005] In some embodiments, the circuitry is configured to generate the first signal that swings between the first supply voltage and a first source voltage. In some embodiments, the latch is configured to generate the second signal that swings between the second supply voltage and a second source voltage. In some embodiments, the second source voltage is higher than the first source voltage. In some embodiments, a terminal of another resistor in the plurality of resistors is electrically coupled to the latch to provide the second source voltage.

[0006] In some embodiments, the circuit system further includes another latch for modifying the first signal to generate a fourth signal. In some embodiments, the circuit system is configured to generate the third signal based on the second signal and the fourth signal. In some embodiments, the circuit system is configured to generate the first signal that swings between the first supply voltage and a first source voltage. In some embodiments, the latch is configured to generate the second signal that swings between the second supply voltage and a second source voltage. In some embodiments, the second source voltage is higher than the first source voltage. In some embodiments, the another latch is configured to generate the fourth signal that swings between a fourth supply voltage and a third source voltage. In some embodiments, the fourth supply voltage is lower than the second supply voltage. In some embodiments, the third source voltage is lower than the fourth source voltage. In some embodiments, one end of another resistor in the plurality of resistors is electrically coupled to the another latch to provide the fourth supply voltage to the another latch based on the third supply voltage. In some embodiments, the system further includes at least a first resistor and a second resistor electrically coupled in series. In some embodiments, one end of the first resistor is configured to receive the third supply voltage. In some embodiments, the other end of the first resistor is electrically coupled to the other latch to provide the fourth power supply voltage to the other latch according to the third power supply voltage.

[0007] In some embodiments, the circuitry includes a capacitor electrically coupled to an input of the latch. In some embodiments, the plurality of resistors is configured to detect a change in the second signal attributable to the capacitor. In some embodiments, the plurality of resistors is configured to adjust the second supply voltage to reduce a difference between i) the change in the second signal attributable to the capacitor and ii) a third voltage amplitude of the second signal.

[0008] In some embodiments, the latch includes a first inverter, a second inverter, a first port electrically coupled to an input of the first inverter and an output of the second inverter, and a second port electrically coupled to an input of the second inverter and an output of the first inverter. In some embodiments, the circuit system includes a first circuit configured to generate the first signal based on the first supply voltage and a second circuit configured to amplify the second signal based on the third supply voltage to generate the third signal. In some embodiments, the first port of the latch is electrically coupled to a first input of the second circuit. In some embodiments, the second port of the latch is electrically coupled to a second input of the second circuit. In some embodiments, the circuit system further includes a capacitor electrically coupled between the first circuit and the first port. In some embodiments, one end of another resistor of the plurality of resistors is electrically coupled to the other end of the resistor. In some embodiments, the system further includes another capacitor electrically coupled between the one end of the other resistor and the other end of the other resistor.

[0009] In some embodiments, one or more of the plurality of resistors is a variable resistor or a programmable resistor.

[0010] Various embodiments disclosed herein relate to a system comprising a first latch, a second latch, an amplifier, and a resistor ladder. In some embodiments, the first latch is configured to receive a first signal and generate a second signal that swings between a first supply voltage and a first source voltage based on the first signal. In some embodiments, the second latch is configured to receive the first signal and generate a third signal that swings between a second supply voltage and a second source voltage based on the first signal. In some embodiments, the amplifier is electrically coupled to the first latch and the second latch. In some embodiments, the amplifier is configured to receive the second signal and the third signal and generate a fourth signal based on a third supply voltage and a third source voltage. In some embodiments, the resistor ladder is electrically coupled to the first latch and the second latch. In some embodiments, the resistor ladder is configured to provide the first supply voltage and the first source voltage to the first latch based on the third supply voltage. In some embodiments, the resistor ladder is configured to provide the second supply voltage and the second source voltage to the second latch based on the third supply voltage.

[0011] In some embodiments, the second signal is a differential signal and the third signal is another differential signal.

[0012] In some embodiments, the amplifier includes a first differential pair circuit including an input electrically coupled to an output of the first latch. In some embodiments, the amplifier includes a second differential pair circuit including an input electrically coupled to an output of the second latch. In some embodiments, the output of the first differential pair circuit is electrically coupled to the output of the second differential pair circuit.

[0013] In some embodiments, the resistor ladder includes a first resistor and a second resistor electrically coupled in series. In some embodiments, one end of the first resistor is configured to receive the third supply voltage. In some embodiments, the other end of the first resistor is electrically coupled to the second latch to provide the second supply voltage to the second latch based on the third supply voltage. In some embodiments, one end of the second resistor is electrically coupled to the second latch to provide the second source voltage to the second latch based on the third supply voltage. In some embodiments, the resistor ladder further includes a third resistor and a fourth resistor electrically coupled in series with the first and second resistors. In some embodiments, one end of the third resistor is electrically coupled to the first latch to provide the first supply voltage to the first latch based on the third supply voltage. In some embodiments, one end of the fourth resistor is electrically coupled to the first latch to provide the first source voltage to the first latch based on the third supply voltage. In some embodiments, the third supply voltage is higher than the second supply voltage. In some embodiments, the second supply voltage is higher than the first supply voltage. In some embodiments, the second source voltage is higher than the first source voltage. In some embodiments, the first source voltage is higher than the third source voltage.

[0014] Various embodiments disclosed herein relate to a method of providing power. In some embodiments, the method includes generating, by circuitry, a first signal having a first voltage amplitude based on a first supply voltage. In some embodiments, the method includes modifying, by a latch of the circuitry, the first signal based on a second supply voltage higher than the first supply voltage to generate a second signal having a second voltage amplitude. In some embodiments, the method includes detecting, by a resistor ladder of the circuitry, a change in the second signal attributable to a capacitor electrically coupled to an input of the latch. In some embodiments, the method includes adjusting, by the resistor ladder of the circuitry, the second supply voltage based on the detected change in the second signal.

[0015] In some embodiments, adjusting the second supply voltage by the resistor ladder based on the detected change in the second signal includes adjusting the second supply voltage through the resistor ladder to reduce a difference between i) the change in the second signal attributable to the capacitor and ii) the second voltage amplitude. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] The various objects, aspects, features and advantages of the present disclosure will become more apparent and better understood by referring to the detailed description taken in conjunction with the accompanying drawings, in which like reference characters identify corresponding elements throughout. In the drawings, like reference numerals generally indicate identical, functionally similar and / or structurally similar elements.

[0017] Figure 1A is a block diagram depicting a network environment including one or more access points in communication with one or more devices or stations in accordance with one or more embodiments.

[0018] Figure 1B and 1C is a block diagram depicting a computing device that may be used in conjunction with the methods and systems described herein, in accordance with one or more embodiments.

[0019] Figure 2 is a block diagram depicting a transmitter in accordance with one or more embodiments.

[0020] Figure 3 is a schematic diagram of a driver circuit according to one or more embodiments.

[0021] Figure 4 is a schematic diagram of a level shifter according to one or more embodiments.

[0022] Figure 5 is a graph showing varying voltages of signals of a level shifter according to one or more embodiments.

[0023] Figure 6A is a schematic diagram of a resistor ladder providing power to a latch according to one or more embodiments.

[0024] Figure 6B is a schematic diagram of a resistor ladder providing power to a latch according to one or more embodiments.

[0025] Figure 7 is a flow chart showing a process of providing power to an amplifier according to one or more embodiments.

[0026] The details of various embodiments of the methods and systems are set forth in the accompanying drawings and the description below. DETAILED DESCRIPTION

[0027] For purposes of reading the description of the various embodiments below, the following description of sections of the specification and their corresponding contents may be useful:

[0028] - Section A describes a network environment and a computing environment that can be used to practice the embodiments described herein; and

[0029] - Section B describes embodiments of systems and methods for providing different supply voltages to amplifiers according to one or more embodiments.

[0030] A. Computing and Network Environment

[0031] Before discussing specific embodiments of the present solution, it is helpful to describe aspects of the operating environment and associated system components (eg, hardware elements) in conjunction with the methods and systems described herein. Figure 1A , depicting an embodiment of a network environment. In brief overview, the network environment includes a wireless communication system that includes one or more access points (APs) 106, one or more wireless communication devices 102, and network hardware components 192. The wireless communication device 102 may, for example, include a laptop computer 102, a tablet computer 102, a personal computer 102, and / or a cellular telephone device 102. Figure 1B and 1C The details of each embodiment of the wireless communication device 102 and / or AP 106 are described in greater detail. In one embodiment, the network environment may be an ad hoc network environment, an infrastructure wireless network environment, a subnet environment, or the like. The AP 106 may be operatively coupled to the network hardware 192 via a local area network connection. The network hardware 192, which may include routers, gateways, switches, bridges, modems, system controllers, devices, and the like, may provide local area network connectivity for the communication system. Each of the APs 106 may have an associated antenna or antenna array to communicate with wireless communication devices in its area. A wireless communication device 102 may register with a particular AP 106 to receive services from the communication system (e.g., via SU-MIMO or MU-MIMO configurations). For direct connections (e.g., point-to-point communication), some wireless communication devices may communicate directly via assigned channels and communication protocols. Some of the wireless communication devices 102 may be mobile or relatively stationary relative to the AP 106.

[0032] In some embodiments, AP 106 comprises a device or module (comprising a combination of hardware and software) that allows wireless communication devices 102 to connect to a wired network using Wireless Fidelity (WiFi) or other standards. AP 106 may sometimes be referred to as a wireless access point (WAP). AP 106 may be implemented (e.g., configured, designed, and / or constructed) to operate in a wireless local area network (WLAN). In some embodiments, AP 106 may be connected to a router (e.g., via a wired network) as a standalone device. In other embodiments, AP 106 may be a component of a router. AP 106 may provide multiple devices with access to a network. For example, AP 106 may connect to a wired Ethernet connection and use a radio frequency link to provide wireless connectivity for other devices 102 to utilize the wired connection. AP 106 may be implemented to support standards for sending and receiving data using one or more radio frequencies. Those standards and the frequencies they use may be defined by IEEE (e.g., IEEE 802.11 standards). AP 106 may be configured and / or used to support public Internet hotspots and / or extend the range of a network's Wi-Fi signal across the network.

[0033] In some embodiments, the access points 106 may be used for a wireless network (e.g., IEEE 802.11, Bluetooth, ZigBee, any other type of radio frequency-based network protocol, and / or variants thereof) (e.g., within a home or building). Each of the wireless communication devices 102 may include a built-in radio and / or be coupled to a radio. Such wireless communication devices 102 and / or access points 106 may operate in accordance with various aspects of the present disclosure presented herein to enhance performance, reduce cost and / or size, and / or enhance broadband applications. Each wireless communication device 102 may have the capability to act as a client node seeking access to resources (e.g., data and connections to networked nodes such as servers) via one or more access points 106.

[0034] The network connection may include any type and / or form of network, and may include any of the following: a point-to-point network, a broadcast network, a telecommunications network, a data communications network, or a computer network. The network topology may be a bus, star, or ring network topology. The network may have any such network topology known to those of ordinary skill in the art that is capable of supporting the operations described herein. In some embodiments, different types of data may be transmitted via different protocols. In other embodiments, the same type of data may be transmitted via different protocols.

[0035] The communication device 102 and the access point 106 may be deployed as and / or executed on any type and form of computing device, such as a computer, network device, or appliance capable of communicating over any type and form of network and performing the operations described herein. Figure 1B and1C A block diagram of a computing device 100 is depicted for practicing an embodiment of a wireless communication device 102 or AP 106. Figure 1B and 1C As shown in FIG, each computing device 100 includes a central processing unit 121 and a main memory unit 122. Figure 1B As shown in FIG, computing device 100 may include storage device 128, installation device 116, network interface 118, I / O controller 123, display devices 124a to 124n, keyboard 126, and pointing device 127 (e.g., mouse). Storage device 128 may include an operating system and / or software. Figure 1C As shown in , each computing device 100 may also include additional optional elements, such as a memory port 103 that communicates with the central processing unit 121, a bridge 170, one or more input / output devices 130a to 130n, and a cache memory 140.

[0036] The central processing unit 121 is any logic circuit that responds to and processes instructions fetched from the main memory unit 122. In many embodiments, the central processing unit 121 is provided by a microprocessor unit, such as those manufactured by Intel Corporation of Santa Clara, California; by International Business Machines of White Plains, New York; or by Advanced Micro Devices of Sunnyvale, California. The computing device 100 may be based on any of these processors or any other processor capable of operating as described herein.

[0037] The main memory unit 122 may be one or more memory chips capable of storing data and allowing any storage location to be directly accessed by the microprocessor 121, such as any type or variation of static random access memory (SRAM), dynamic random access memory (DRAM), ferroelectric RAM (FRAM), NAND flash memory, NOR flash memory, and solid-state drive (SSD). The main memory 122 may be based on any of the above-mentioned memory chips or any other available memory chips capable of operating as described herein. Figure 1B In the embodiment shown in FIG, processor 121 communicates with main memory 122 via system bus 150 (described in more detail below). Figure 1CAn embodiment of the computing device 100 is depicted in which the processor communicates directly with the main memory 122 via the memory port 103. For example, in Figure 1C In the embodiment, the main memory 122 may be DRDRAM.

[0038] Figure 1C An embodiment is depicted in which the main processor 121 communicates directly with the cache memory 140 via a secondary bus (sometimes referred to as a backside bus). In other embodiments, the main processor 121 communicates with the cache memory 140 using the system bus 150. The cache memory 140 typically has a faster response time than the main memory 122 and is provided by, for example, SRAM, BSRAM, or EDRAM. Figure 1C , the processor 121 communicates with the various I / O devices 130 via a local system bus 150. Various buses may be used to connect the central processing unit 121 to any of the I / O devices 130, such as a VESA VL bus, an ISA bus, an EISA bus, a Micro Channel Architecture (MCA) bus, a PCI bus, a PCI-X bus, a PCI Express (PCI-Express) bus, or a NuBus. For embodiments in which the I / O device is a video display 124, the processor 121 may use an Advanced Graphics Port (AGP) to communicate with the display 124. Figure 1C An embodiment of the computer 100 is depicted in which the main processor 121 can communicate directly with the I / O device 130b, for example, via HYPERTRANSPORT, RAPIDIO, or INFINIBAND communication technology. Figure 1C Also depicted are embodiments in which local buses and direct communications are mixed: processor 121 communicates with I / O device 130a using a local interconnect bus while communicating directly with I / O device 130b.

[0039] A variety of I / O devices 130a to 130n may be present in the computing device 100. Input devices include keyboards, mice, trackpads, trackballs, microphones, dials, touchpads, touch screens, and drawing tablets. Output devices include video displays, speakers, inkjet printers, laser printers, projectors, and dye sublimation printers. The I / O devices may be controlled by an I / O controller 123, such as Figure 1B1. The I / O controller may control one or more I / O devices, such as a keyboard 126 and a pointing device 127, such as a mouse or optical pen. In addition, the I / O devices may also provide storage and / or installation media 116 for the computing device 100. In other embodiments, the computing device 100 may provide a USB connection (not shown) to receive a handheld USB storage device, such as a USB flash drive family of devices manufactured by Twintech Industries, Inc. of Los Alamitos, California.

[0040] Reference again Figure 1B , the computing device 100 may support any suitable installation device 116, such as a disk drive, a CD-ROM drive, a CD-R / RW drive, a DVD-ROM drive, a flash memory drive, tape drives of various formats, a USB device, a hard drive, a network interface, or any other device suitable for installing software and programs. The computing device 100 may further include storage devices, such as one or more hard drives or redundant arrays of independent disks, for storing an operating system and other related software and for storing application software programs (e.g., any program or software 120 used to implement (e.g., configured and / or designed for) the systems and methods described herein). Optionally, any of the installation devices 116 may also serve as a storage device. In addition, the operating system and software may be run from bootable media.

[0041] Furthermore, the computing device 100 may include a network interface 118 to interface to the network 104 through various connections, including, but not limited to, a standard telephone line, a LAN or WAN link (e.g., 802.11, T1, T3, 56 kb, X.25, SNA, DECNET), a broadband connection (e.g., ISDN, Frame Relay, ATM, Gigabit Ethernet, Ethernet over SONET), a wireless connection, or some combination of any or all of the above. The connection may be established using various communication protocols (e.g., TCP / IP, IPX, SPX, NetBIOS, Ethernet, ARCNET, SONET, SDH, Fiber Distributed Data Interface (FDDI), RS232, IEEE 802.11, IEEE 802.11a, IEEE 802.11b, IEEE 802.11g, IEEE 802.11n, IEEE 802.11ac, IEEE 802.11ad, CDMA, GSM, WiMax, and direct asynchronous connection). In one embodiment, the computing device 100 communicates with other computing devices 100' via any type and / or form of gateway or tunneling protocol, such as Secure Sockets Layer (SSL) or Transport Layer Security (TLS). The network interface 118 may include a built-in network adapter, a network interface card, a PCMCIA network card, a card bus network adapter, a wireless network adapter, a USB network adapter, a modem, or any other device suitable for interfacing the computing device 100 to any type of network capable of communicating and performing the operations described herein.

[0042] In some embodiments, computing device 100 may include or be connected to one or more display devices 124a-124n. Thus, any of I / O devices 130a-130n and / or I / O controller 123 may include any type and / or form of appropriate hardware, software, or a combination of hardware and software to support, enable, or provide for connection to and use of display devices 124a-124n by computing device 100. For example, computing device 100 may include any type and / or form of video adapter, video card, driver, and / or library to interface, communicate, connect, or otherwise use display devices 124a-124n. In one embodiment, a video adapter may include multiple connectors to interface to display devices 124a-124n. In other embodiments, computing device 100 may include multiple video adapters, each of which is connected to a display device 124a-124n. In some embodiments, any portion of the operating system of computing device 100 may be configured to use multiple displays 124a-124n. In a further embodiment, the I / O device 130 may be a bridge between the system bus 150 and an external communication bus, such as a USB bus, an Apple Desktop bus, an RS-232 serial connection, a SCSI bus, a FireWire bus, a FireWire 800 bus, an Ethernet bus, an AppleTalk bus, a Gigabit Ethernet bus, an Asynchronous Transfer Mode bus, a Fibre Channel bus, a Serial Attached Small Computer System Interface bus, a USB connection, or an HDMI bus.

[0043] Figure 1B and 1CA computing device 100 of the type depicted in the accompanying drawings may operate under the control of an operating system that controls the scheduling of tasks and access to system resources. The computing device 100 may run any operating system, such as any version of the Microsoft WINDOWS operating system, different versions of the Unix and Linux operating systems, any version of the MAC OS for Macintosh computers, any embedded operating system, any real-time operating system, any open source operating system, any proprietary operating system, any operating system for mobile computing devices, or any other operating system capable of running on a computing device and performing the operations described herein. Typical operating systems include (but are not limited to): Android produced by Google Inc.; WINDOWS 7, 8 and 10 produced by Microsoft Corporation of Redmond, Washington; MAC OS produced by Apple Computer of Cupertino, California; WebOS produced by Research In Motion (RIM); OS / 2 produced by International Business Machines of Armonk, New York; and Linux, a freely available operating system released by Caldera Corporation of Salt Lake City, Utah, or any type and / or form of Unix operating system, etc.

[0044] The computer system 100 may be any workstation, phone, desktop computer, laptop or notebook computer, server, handheld computer, mobile phone or other portable telecommunication device, media playback device, gaming system, mobile computing device, or any other type and / or form of computing, telecommunication, or media device capable of communication. In some embodiments, the computing device 100 may have a different processor, operating system, and input device consistent with such a device. For example, in one embodiment, the computing device 100 is a smartphone, mobile device, tablet computer, or personal digital assistant. Furthermore, the computing device 100 may be any workstation, desktop computer, laptop or notebook computer, server, handheld computer, mobile phone, any other computer, or other form of computing or telecommunication device capable of communication and having sufficient processor power and memory capacity to perform the operations described herein.

[0045] Aspects of the operating environment and components described above will become apparent in the context of the systems and methods disclosed herein.

[0046] B. Multi-level Power Generation

[0047] Various embodiments disclosed herein relate to systems and methods for providing different power supply levels or different supply voltages. In one aspect, a system includes a first circuit, a second circuit, and a third circuit that operate according to different supply voltages and / or source voltages. The first circuit can generate a first signal having a first voltage amplitude according to the first supply voltage. The second circuit can include one or more latches (or latch circuits) for amplifying, adjusting, or modifying the first signal to generate a second signal according to the second supply voltage. The third circuit can receive the second signal and generate a third signal having a voltage amplitude greater than the first voltage amplitude according to the third supply voltage. In one aspect, the system includes one or more resistor ladders (or resistor ladder circuits) electrically coupled to the one or more latches. The one or more resistor ladders can receive a third supply voltage and provide a second supply voltage to the one or more latches based on the third supply voltage.

[0048] Advantageously, the disclosed systems and methods can achieve various advantages. In one aspect, the resistor ladder can perform a feedback operation to improve the communication performance or reliability of the system. For example, the resistor ladder can detect a change in the second signal due to a capacitor electrically coupled to the input of the latch and adjust the second supply voltage based on the detected change in the second signal to perform the feedback operation. As a result, the peak values ​​of the second and third signals can be optimized to improve the eye opening of the second and third signals. In addition, inter-symbol interference (ISI) can be reduced, and the linearity of the third circuit can be improved.

[0049] The disclosed systems and methods may also provide additional advantages. In one aspect, the disclosed system implements one or more resistor ladders to provide different supply voltages, so that a low dropout regulator (LDO) can be avoided. By implementing one or more resistor ladders instead of LDOs, the disclosed system can be implemented in an area-efficient manner and a power-efficient manner. For example, implementing one or more resistor ladders without LDOs can reduce area by 80% and save 20% of power. In addition, the simple architecture of the resistor ladder does not require a complex power-on sequence, so that additional circuitry for ensuring stable startup can be omitted. In addition, the resistor ladder can generate the supply voltage and / or source voltage by voltage division, so that the amplitude of the second signal and the random variations in the common-mode voltage can be significantly reduced (for example, compared to implementing an LDO), thereby allowing a well-controlled (stable) peak response of the second circuit and / or the third circuit.

[0050] Figure 2is a block diagram depicting a transmitter 210 according to one or more embodiments. In some embodiments, the transmitter 210 is part of the device 102, node 192, or device 106. In some embodiments, the transmitter 210 is used for wired communication (e.g., Ethernet, USB, FireWire, cable, or optical communication). In some embodiments, the transmitter 210 or a portion of the transmitter 210 may be implemented for wireless communication (e.g., cellular, near field communication, Wi-Fi, etc.). In some embodiments, the transmitter 210 operates as or is implemented as an amplifier. In some embodiments, the transmitter 210 includes a modem 220, a level shifter 230, a driver circuit 240, and a power controller 235. These components can operate together to generate and transmit signals Outp, Outn representing data for communication. In some embodiments, the transmitter 210 includes a Figure 2 For example, transmitter 210 may include one or more additional amplifiers that amplify the signals Outp, Outn output by driver circuit 240.

[0051] In some embodiments, modem 220 is a circuit or component that generates signals d and db representing data for transmission. In some embodiments, modem 220 is implemented as a digital logic circuit. Modem 220 can generate high-speed data at data rates up to, for example, hundreds of Gbps. Modem 220 can receive a supply voltage VDD1 having a first voltage level (e.g., 0.8-1V) and generate signals d and db having a voltage amplitude corresponding to supply voltage VDD1. In some embodiments, signals d and db can be differential signals. In some embodiments, single-ended signal d can be implemented or utilized instead of differential signals d and db.

[0052] In some embodiments, the level shifter 230 is a circuit or component that generates signals In2p, In2n, In1p, In1n based on signals d, db. In some embodiments, the level shifter 230 operates as or is implemented as an amplifier. In one aspect, the level shifter 230 may include a latch that adjusts, modifies, or amplifies the signals d, db to generate the signals In2p, In2n, In1p, In1n. The signals In1p, In1n may be differential signals, and In2p, In2n may be additional differential signals. In one aspect, the common-mode voltage of the differential signals In2p, In2n is higher than the common-mode voltage of the differential signals In1p, In1n. The common-mode voltage of the differential signals In2p, In2n, In1p, In1n may be set to allow correct operation of the driver circuit 240, as described below with respect to Figure 3In some embodiments, the level shifter 230 may receive a supply voltage VDD2H having a second voltage level (e.g., 2.7-3.0V) and a source voltage VSS2H (e.g., 2.45V), and generate signals In2p and In2n having a voltage amplitude corresponding to the difference between the supply voltage VDD2H and the source voltage VSS2H. Similarly, the level shifter 230 may receive a supply voltage VDD2L having a third voltage level (e.g., 0.7-0.9V) and a source voltage VSS2L (e.g., 0.35V), and generate signals In1p and In1n having a voltage amplitude corresponding to the difference between the supply voltage VDD2L and the source voltage VSS2L. In some embodiments, the supply voltage VDD3 may be equal to or lower than the supply voltage VDD1, and the supply voltage VDD2 may be lower than the supply voltage VDD1.

[0053] In some embodiments, the driver circuit 240 is a circuit or component that generates signals Outp and Outn. In some embodiments, the driver circuit 240 operates as or is implemented as an amplifier. In one aspect, the driver circuit 240 can amplify the signals In2p, In2n, In1p, and In1n to generate signals Outp and Outn. The signals Outp and Outn can be differential signals. The driver circuit 240 can receive a supply voltage VDD3 having a fourth voltage level (e.g., 3.0-3.5V) and generate signals Outp and Outn having a voltage amplitude based on the supply voltage VDD3 and the ground voltage GND. In one aspect, the voltage amplitude of the signals Outp and Outn is higher than the voltage amplitude of the signals d and db. In some embodiments, the output of the driver circuit 240 is electrically coupled to a cable or another driver circuit. Therefore, the driver circuit 240 can transmit or provide signals Outp and Outn having a voltage amplitude higher than the voltage amplitude of the signals d and db to another device or another driver circuit. In some embodiments, a single-ended signal Out can be implemented or utilized instead of the differential signals Outp and Outn.

[0054] In some embodiments, the power controller 235 is a circuit or component that generates various supply voltages VDD1, VDD2H, VDD2L, and VDD3. In one aspect, the power controller 235 includes a power supply 270 and one or more resistor ladders 280 electrically coupled to the power supply 270 via conductive traces. The power supply 270 can be any circuit or component that can provide the supply voltage VDD3. For example, the power supply 270 can be a battery, or a circuit that provides a DC voltage. The resistor ladder 280 can include a plurality of resistors connected in series. The resistor ladder 280 can receive the supply voltage VDD3 and generate or provide different supply voltages VDD2H and VDD2L based on the supply voltage VDD3. Although Figure 2The power controller 235 in FIG. 1 is depicted as providing VDD1, VDD2H, VDD2L, and VDD3, but the power controller 235 may provide Figure 2 . For example, power controller 235 may generate or provide a ground voltage GND (or a source voltage) to modem 220 and driver circuit 240. For example, power controller 235 may generate or provide different source voltages VSS2H, VSS2L to level shifter 230. In some embodiments, power controller 235 may lack power supply 270, and power supply 270 may be included in a different portion of device 102, 192, or 106.

[0055] Figure 3 is a schematic diagram of a driver circuit 240 according to one or more embodiments. In some embodiments, the driver circuit 240 includes transistors M1 to M10 and resistors R1 and R2. Transistors M1 to M5 may be N-type transistors (e.g., N-type MOSFETs, N-type FinFETs, N-type BJTs, etc.), and transistors M6 to M10 may be P-type transistors (e.g., P-type MOSFETs, P-type FinFETs, P-type BJTs, etc.). These components may operate together to receive signals In1p, In1n, In2p, In2n, and generate output signals Outp, Outn by amplifying or modifying the signals In1p, In1n, In2p, In2n. In some embodiments, the driver circuit 240 includes more, fewer, or different components, or has the same Figure 3 The different configurations shown in .

[0056] In one configuration, transistor M1 includes a source electrode electrically coupled to a metal rail to receive ground voltage GND, a gate electrode electrically coupled to a bias circuit (not shown) to receive bias voltage Bias1, and a drain electrode electrically coupled to the source electrodes of transistors M2 and M3. Bias voltage Bias1 can be a DC voltage that allows or causes transistor M1 to conduct current. In this configuration, transistor M1 can operate as a current source, allowing current to flow between the drain and source electrodes of transistor M1 according to bias voltage Bias1.

[0057] In one configuration, transistor M2 includes a source electrode electrically coupled to the drain electrode of transistor M1, a gate electrode electrically coupled to the output of level shifter 230 to receive signal In1p, and a drain electrode electrically coupled to the source electrode of transistor M4. In one configuration, transistor M3 includes a source electrode electrically coupled to the drain electrode of transistor M1, a gate electrode electrically coupled to the output of level shifter 230 to receive signal In1n, and a drain electrode electrically coupled to the source electrode of transistor M5. In some embodiments, transistor M4 includes a gate electrode electrically coupled to the gate electrode of transistor M5 and to a bias circuit (not shown). The bias circuit can provide a bias voltage Bias2 to the gate electrodes of transistors M4 and M5. The bias voltage Bias2 can be a DC voltage. In some embodiments, the drain electrode of transistor M4 is electrically coupled to the output of driver circuit 240, at which signal Outp can be generated or provided. In some embodiments, the drain electrode of transistor M5 is electrically coupled to the output of driver circuit 240, at which signal Outn can be generated or provided. In this configuration, transistors M2 and M3 can operate as a differential pair circuit that can pull down one of the voltages of signals Outp and Outn based on differential signals In1p and In1n. In one configuration, transistors M4 and M5 operate as cascode transistors to provide a high output impedance at the output of driver circuit 240. For example, in response to signal In1p having a higher voltage than signal In1n, the current flowing through transistor M2 can be greater than the current flowing through transistor M3. In response to the current flowing through transistor M2 being greater than the current flowing through transistor M3, the voltage of signal Outp can be lower than the voltage of signal Outn.

[0058] In one configuration, transistor M10 includes a source electrode electrically coupled to, for example, power controller 235 via a metal rail to receive supply voltage VDD3, a gate electrode electrically coupled to a bias circuit (not shown) to receive bias voltage Bias4, and a drain electrode electrically coupled to the source electrodes of transistors M8 and M9. Bias voltage Bias4 can be a DC voltage that allows or causes transistor M10 to conduct current. In this configuration, transistor M10 can operate as a current source according to bias voltage Bias4, allowing current to flow between the source and drain electrodes of transistor M10.

[0059] In one configuration, transistor M8 includes a source electrode electrically coupled to the drain electrode of transistor M10, a gate electrode electrically coupled to the output of level shifter 230 to receive signal In2p, and a drain electrode electrically coupled to the source electrode of transistor M6. In one configuration, transistor M9 includes a source electrode electrically coupled to the drain electrode of transistor M10, a gate electrode electrically coupled to the output of level shifter 230 to receive signal In2n, and a drain electrode electrically coupled to the source electrode of transistor M7. In some embodiments, transistor M6 includes a gate electrode electrically coupled to the gate electrode of transistor M7 and to a bias circuit (not shown). The bias circuit can provide a bias voltage Bias3 to the gate electrodes of transistors M6 and M7. Bias voltage Bias3 can be a DC voltage. In some embodiments, the drain electrode of transistor M6 is electrically coupled to the output of driver circuit 240, at which signal Outp can be generated or provided. In some embodiments, the drain electrode of transistor M7 is electrically coupled to the output of driver circuit 240, at which signal Outn can be generated or provided. In this configuration, transistors M8 and M9 can operate as a differential pair circuit that can pull up one of the voltages of signals Outp and Outn based on differential signals In2p and In2n. In one configuration, transistors M6 and M7 operate as cascode transistors to provide a high output impedance at the output of driver circuit 240. For example, in response to signal In2p having a higher voltage than signal In2n, a greater current can flow through transistor M9 than through transistor M8. In response to a greater current flowing through transistor M9 than through transistor M8, the voltage of signal Outn can be higher than the voltage of signal Outp.

[0060] In one configuration, resistors R1 and R2 are electrically coupled in series between the outputs of driver circuit 240. For example, one end of resistor R1 is electrically coupled to the drain electrodes of transistors M4 and M6, and the other end of resistor R1 is electrically coupled to one end of resistor R2. For example, the other end of resistor R2 is electrically coupled to the drain electrodes of transistors M5 and M7.

[0061] In one aspect, the voltages of the differential signals In1p and In1n can swing between a supply voltage VDD2L and a source voltage VSS2L, while the voltages of the differential signals In2p and In2n can swing between a supply voltage VDD2H and a source voltage VSS2H. The common-mode voltage of the differential signals In2p and In2n can be higher than the common-mode voltage of the differential signals In1p and In1p. For example, the common-mode voltage of the differential signals In2p and In2n can allow the differential pair M8 and M9 to compare the voltages of the differential signals In2p and In2n and, based on the comparison, pull up one of the voltages of the signals Outp and Outn. Similarly, for example, the common-mode voltage of the differential signals In1p and In1n can allow the differential pair M2 and M3 to compare the voltages of the differential signals In1p and In1n and, based on the comparison, pull down one of the voltages of the signals Outp and Outn. In one aspect, the signals In1p and In2p are in phase with each other, while the signals In1n and In2n are in phase with each other. Therefore, when transistor M2 pulls down the voltage of signal Outp, transistor M9 can pull up the voltage of signal Outn based on signals In1p, In1n, In2p, and In2n. Conversely, when transistor M3 pulls down the voltage of signal Outn, transistor M8 can pull up the voltage of signal Outp based on signals In1p, In1n, In2p, and In2n. Therefore, driver circuit 240 can generate differential signals Outp and Outn based on differential signals In1p, In1n and differential signals In2p, In2n. Because supply voltage VDD3 is higher than supply voltage VDD1, the voltage amplitudes of output signals Outp and Outn can be greater than the voltage amplitudes of signals d and db. In some embodiments, driver circuit 240 can generate output signals Outp and Outn having voltage amplitudes that are less than the voltage amplitudes of signals d and db.

[0062] Figure 4 is a schematic diagram of a level shifter 230 according to one or more embodiments. In some embodiments, the level shifter 230 includes latch circuit Latch1, latch circuit Latch2, capacitors C3, C3', C4, C4', Cload1 to Cload4, and amplifiers A1 to A4. These components can operate together to receive signals d and db from the modem 220 and amplify or modify the signals d and db to generate signals In1p, In1n, In2p, and In2n. The signals In1p, In1n, In2p, and In2n can be as described above with respect to Figure 3 In some embodiments, the level shifter 230 includes a differential signal Figure 4, or different components than those shown in FIG. For example, capacitors Cload1 through Cload4 may not be implemented as discrete capacitors, but may model the input capacitance at the gate electrodes of transistors M8, M9, M2, and M3, respectively. For example, amplifiers A1 through A4 may be omitted or implemented as part of modem 220.

[0063] In some embodiments, amplifiers A1 to A4 are circuits or components that amplify signals d and db. In one aspect, amplifiers A1 to A4 are embodied as inverters. In one configuration, amplifier A1 includes an input electrically coupled to the input of amplifier A3. In one configuration, amplifier A2 includes an input electrically coupled to the input of amplifier A4. In one configuration, capacitor C3 is electrically coupled between amplifier A1 and the first port of latch Latch1, generating signal In2p at the first port. In one configuration, capacitor C4 is electrically coupled between amplifier A2 and the second port of latch Latch1, generating signal In2n at the second port. In one configuration, capacitor C3' is electrically coupled between amplifier A3 and the first port of latch Latch2, generating signal In1p at the first port. In one configuration, capacitor C4' is electrically coupled between amplifier A4 and the second port of latch Latch2, generating signal In1n at the second port. In one aspect, amplifiers A1 to A4 are powered by a first supply voltage VDD1 and a ground voltage GND. Therefore, amplifiers A1 to A4 can generate signals that swing between the first supply voltage VDD1 and the ground voltage GND based on signals d and db. The signals output by amplifiers A1 and A2 can be provided to latch Latch1 via capacitors C3 and C4, respectively. Similarly, the signals output by amplifiers A3 and A4 can be provided to latch Latch2 via capacitors C3' and C4', respectively.

[0064] In some embodiments, latch Latch1 includes cross-coupled inverters I1 and I2. In one configuration, latch Latch1 includes a first port at which signal In2p is generated, and a second port at which signal In2n is generated. In one approach, latch Latch1 can sense the voltage difference of signals received from amplifiers A1 and A2 via capacitors C3 and C4, and amplify or increase the difference to generate signals In2p and In2n. Inverters I1 and I2 can operate based on a supply voltage VDD2H and a source voltage VSS2H, such that signals In2p and In2n can have a voltage amplitude between the supply voltage VDD2H and the source voltage VSS2H.

[0065] In some embodiments, latch Latch2 includes cross-coupled inverters I3 and I4. In one configuration, latch Latch2 includes a first port at which signal In1p is generated, and a second port at which signal In1n is generated. In one method, latch Latch2 can sense the voltage difference of the signals received from amplifiers A3 and A4 through capacitors C3' and C4', and amplify or increase the difference to generate signals In1p and In1n. Inverters I3 and I4 can operate according to a supply voltage VDD2L and a source voltage VSS2L, so that signals In1p and In1n can have a voltage amplitude between the supply voltage VDD2L and the source voltage VSS2L. In one aspect, the supply voltage VDD2H is higher than the supply voltage VDD2L, and the source voltage VSS2H is higher than the source voltage VSS2L, so that signals In2p and In2n can have a common-mode voltage higher than the common-mode voltage of signals In1p and In1n.

[0066] Figure 5 FIG5 is a graph 500 showing the varying voltage of the output signals (e.g., In2p, In2n, In1p, In1n) of the level shifter 230 according to one or more embodiments. In one aspect, the variation in voltage at the output of the level shifter 230 includes an AC component ΔV AC and DC component ΔV DC AC component ΔV AC It can be attributed to the signal injected through the capacitors (e.g. C3, C3', C4, C4'). For example, the AC component ΔV AC It is attributable to the signal injected through the capacitor, which can be expressed as follows:

[0067]

[0068] Where V in is the output of one of amplifiers A1 to A4, C AC is the capacitance of one of the capacitors C3, C3', C4, and C4'. DC component ΔV DC The DC component ΔV may be the target voltage amplitude of the signal at the output of the level shifter 230. DC ΔV may be set to or correspond to the difference between the supply voltage VDD2 (eg, VDD2H, VDD2L) and the source voltage VSS2 (eg, VSS2H, VSS2L). AC and DC component ΔV DC Deviation from the target difference may reduce the eye opening of the output signals Outp, Outn and cause ISI to degrade communication quality. In one aspect, the power controller 235 may perform a feedback operation so that the DC component ΔV DCA simple architecture can be used to track the AC component ΔV AC , as shown below about Figure 6A 、 6B , 7. In one aspect, the peak value in the output of level shifter 230 can be adjusted or optimized to achieve a specific transmitter bandwidth. Tracking the DC component of the AC component can help stabilize the peak response over process, voltage, and temperature variations and help reduce part-to-part random variations in the peak response, thereby allowing for improved eye opening and reduced ISI at the output of transmitter 210.

[0069] Figure 6A is a schematic diagram of a portion 600A of the power controller 235 according to one or more embodiments, which includes a resistor ladder 280 that provides power to latches Latch1 and Latch2. In some embodiments, portion 600A of the power controller 235 includes a first resistor ladder 280 including resistors R61A, R61B, and R61C coupled in series, a second resistor ladder 280 including resistors R62A, R62B, and R62C coupled in series, and capacitors Cd1A, Cd1B, Cd2A, and Cd2B. These components can operate together to provide different voltages (e.g., supply voltages VDD2H and VDD2L and source voltages VSS2H and VSS2L) to latches Latch1 and Latch2. In some embodiments, portion 600A of the power controller 235 includes a resistor ladder 280 including resistors R61A, R61B, and R61C coupled in series, a second resistor ladder 280 including resistors R62A, R62B, and R62C coupled in series, and capacitors Cd1A, Cd1B, Cd2A, and Cd2B. These components can operate together to provide different voltages (e.g., supply voltages VDD2H and VDD2L and source voltages VSS2H and VSS2L) to latches Latch1 and Latch2. Figure 6A More, fewer or different components than those shown.

[0070] In some embodiments, first resistor ladder 280 includes resistors R61A, R61B, and R61C coupled in series between a metal rail for receiving a third supply voltage VDD3 and a metal rail for receiving a ground voltage GND. In one configuration, one end of resistor R61A is electrically coupled to the metal rail for receiving the supply voltage VDD3, and the other end of resistor R61A is electrically coupled to node n1. In one configuration, one end of resistor R61B is electrically coupled to node n1, and the other end of resistor R61B is electrically coupled to node n2. In one configuration, one end of resistor R61C is electrically coupled to node n2, and the other end of resistor R61C is electrically coupled to the metal rail for receiving the ground voltage GND. In one configuration, capacitor Cd1A is electrically coupled between nodes n1 and n2. In one configuration, capacitor Cd1B is electrically coupled between node n1 and the metal rail for receiving the supply voltage VDD3. Capacitors Cd1A and Cd1B may be implemented as thin-oxide MOS capacitors or other types of capacitors. In one aspect, thin oxide capacitors can help achieve area efficiency. In one configuration, latch Latch1 and capacitor Cd1A are electrically coupled in parallel between node n1 and node n2. In this configuration, the first resistor ladder 280 can generate a supply voltage VDD2H at node n1 and a source voltage VSS2H at node n2 based on voltage division. For example, the supply voltage VDD2H can be lower than the supply voltage VDD3. For example, the source voltage VSS2H can be higher than the ground voltage GND. Capacitors Cd1A and Cd1B can reduce fluctuations in voltages VDD2H and VSS2H. In some embodiments, one or more of resistors R61A, R61B, and R61C can be variable resistors or programmable resistors to allow the voltages at nodes n1 and n2 to be set or adjusted to target voltage levels.

[0071] In one aspect, the second resistor ladder 280 including resistors R62A, R62B, and R62C and capacitors Cd2A and Cd2B are configured and operated in a manner similar to the first resistor ladder 280 including resistors R61A, R61B, and R61C and capacitors Cd1A and Cd1B, except that the second resistor ladder 280 including resistors R62A, R62B, and R62C provides a supply voltage VDD2L and a source voltage VSS2L to the latch Latch2, and capacitor Cd2B is coupled between i) a node providing the source voltage VSS2L and ii) a metal rail for receiving the ground voltage GND. Therefore, for the sake of brevity, a detailed description of the duplicated portion is omitted herein. In one aspect, resistors R62A, R62B, and R62C may have different resistances than resistors R61A, R61B, and R61C, such that supply voltage VDD2L is lower than supply voltage VDD2H and source voltage VSS2L is between ground voltage GND and source voltage VSS2H. In some embodiments, supply voltage VDD2L is lower than source voltage VSS2H.

[0072] In some embodiments, the resistor ladder 280 can perform a feedback operation to adjust or control the supply voltage VDD2 (e.g., VDD2H, VDD2L) and / or the source voltage VSS2 (e.g., VSS2H, VSS2L). In one aspect, the current Idc through the node n1 is proportional to the AC component ΔV AC and DC component ΔV DC Since the amplifiers A1 to A4 may cause or contribute to the AC component ΔV based on the supply voltage VDD1 and the ground voltage GND, AC , and the latches (eg, Latch1, Latch2) may cause or contribute to the remaining variation ΔV based on the supply voltage VDD2 and the source voltage VSS2 DC -ΔV AC At the same time, the DC component ΔV DC It can be expressed as follows:

[0073] ΔV DC =R SW (Ibias-Idc)

[0074] where R SW is the resistance of the resistor (e.g., R61B or R62B) for providing the supply voltage VDD2 and the source voltage VSS2, Ibias is the current through the resistor (e.g., R61A or R62A) electrically coupled to the metal rail for receiving the supply voltage VDD3, and Idc is the current provided by the resistor ladder 280 to the latch (e.g., Latch1, Latch2). In one aspect, the AC component ΔV ACThe increase in can cause the current Idc drawn by the latch to decrease. In addition, the decrease in current Idc can cause the DC component ΔV DC Therefore, the resistor ladder 280 can increase the DC amount ΔV DC Can track or follow the AC component ΔV AC In addition, the resistor ladder 280 can generate a supply voltage by voltage division, so that, for example, the DC component ΔV can be significantly reduced compared to the implementation of LDO. DC By making the DC component ΔV DC Tracking AC component ΔV AC , and reduce the DC component ΔV DC The random changes of the output signal can improve and stabilize the eye opening of the output signals Outp and Outn across processes, voltages and temperatures and from part to part, so that the communication quality can be enhanced.

[0075] Figure 6B is a schematic diagram of a portion 600B of the power controller 235 according to one or more embodiments, which includes a resistor ladder 280 that provides a supply voltage to latches Latch1 and Latch2. In some embodiments, portion 600B of the power controller 235 includes a resistor ladder 280 comprising resistors R63A, R63B, R63C, R63D, and R63E electrically coupled in series, and capacitors Cd3A, Cd3B, Cd3C, and Cd3D. These components can operate together to provide different voltages (e.g., supply voltages VDD2H and VDD2L and source voltages VSS2H and VSS2L) to latches Latch1 and Latch2. In some embodiments, portion 600B of the power controller 235 includes a resistor ladder 280 comprising resistors R63A, R63B, R63C, R63D, and R63E electrically coupled in series. Figure 6B More, fewer or different components than those shown.

[0076] In some embodiments, resistor ladder 280 includes resistors R63A, R63B, R63C, R63D, and R63E, which are electrically coupled in series between a metal rail for receiving a third supply voltage VDD3 and a metal rail for receiving a ground voltage GND. In one configuration, one end of resistor R63A is electrically coupled to the metal rail for receiving the supply voltage VDD3, and the other end of resistor R63A is electrically coupled to one end of resistor R63B. In one configuration, the other end of resistor R63B is electrically coupled to one end of resistor R63C, and the other end of resistor R63C is electrically coupled to one end of resistor R63D. In one configuration, the other end of resistor R63D is electrically coupled to one end of resistor R63E, and the other end of resistor R63E is electrically coupled to the metal rail for receiving the ground voltage GND. In one configuration, capacitor Cd3A is electrically coupled between one end of resistor R63B and the other end of resistor R63B, and capacitor Cd3B is electrically coupled in parallel with resistor R63A. In one configuration, capacitor Cd3C is electrically coupled between one end of resistor R63D and the other end of resistor R63D, and capacitor Cd3D is electrically coupled in parallel with resistor R63E. Latch Latch1 can be electrically coupled in parallel with capacitor Cd3A, and latch Latch2 can be electrically coupled in parallel with capacitor Cd3C. Capacitors Cd3A and Cd3B can be embodied as thin-oxide MOS capacitors or other types of capacitors. In one aspect, thin-oxide capacitors can help achieve area efficiency.

[0077] In this configuration, resistor ladder 280, including resistors R63A, R63B, R63C, R63D, and R63E, can generate supply voltages VDD2H and VDD2L and source voltages VSS2H and VSS2L from supply voltage VDD3 by voltage division. For example, supply voltage VDD2H can be lower than supply voltage VDD3, and source voltage VSS2H can be lower than supply voltage VDD2H. For example, supply voltage VDD2L can be lower than source voltage VSS2H, and source voltage VSS2L can be lower than supply voltage VDD2L. Capacitors Cd3A, Cd3B, Cd3C, and Cd3D can reduce fluctuations in voltages VDD2H, VSS2H, VDD2L, and VSS2L. In some embodiments, one or more of resistors R63A, R63B, R63C, R63D, and R63E can be variable resistors or programmable resistors to allow the voltages at nodes n1 and n2 to be set or adjusted to target voltage levels. In one aspect, as Figure 6BThe single resistor ladder 280 shown in FIG. 2 including resistors R63A, R63B, R63C, R63D, R63E may have lower power consumption than i) a first resistor ladder 280 including resistors R61A, R61B, R61C and ii) a second resistor ladder 280 including resistors R62A, R62B, R62C (e.g., FIG. 2 ). Figure 6A The combined power consumption of the embodiment shown in FIG5 can reduce the power consumption.

[0078] Figure 7 is a flow chart depicting a process 700 for providing power to an amplifier according to one or more embodiments. In some embodiments, the process 700 is performed by the transmitter 210. In other embodiments, the process 700 is performed by other entities. In some embodiments, the process 700 includes Figure 7 More, fewer, or different steps may be shown in .

[0079] In one approach, transmitter 210 generates 710 a first signal based on a first supply voltage (e.g., VDD1). For example, transmitter 210 includes a modem 220 that generates or provides a first signal representing data for communication. In some embodiments, the first signal is embodied as or is one of differential signals d and db. Modem 220 can generate high-speed data at a data rate of up to, for example, hundreds of Gbps. Modem 220 can receive supply voltage VDD1 having a first voltage level (e.g., 0.8-1V) and generate a first signal having a voltage amplitude corresponding to supply voltage VDD1.

[0080] In one approach, transmitter 210 modifies 720 a first signal based on a second supply voltage (e.g., VDD2H or VDD2L) to generate a second signal. In some embodiments, the second signal is embodied as or is one of the differential signals In2p, In2n, In1p, and In1n. In one example, transmitter 210 includes a level shifter 230. Level shifter 230 may include one or more latches that generate the second signal (e.g., signals In2p, In2n, In1p, and In1n). Level shifter 230 may generate the second signal having a different common-mode voltage and / or amplitude than the first signal. In one aspect, the second supply voltage is higher than the first supply voltage. Transmitter 210 may generate or provide the second signal having a different voltage amplitude and / or common-mode voltage than the first signal used to drive driver circuit 240.

[0081] In one approach, transmitter 210 amplifies 730 the second signal based on a third supply voltage (e.g., VDD3) to generate a third signal. In some embodiments, the third signal is embodied as or is one of the differential signals Outp and Outn. For example, transmitter 210 includes a driver circuit 240 that generates or provides the third signal. In one aspect, the third supply voltage (e.g., VDD3) is higher than the second supply voltage (e.g., VDD2). In one aspect, level shifter 230 amplifies or modifies the first signal by adjusting its voltage amplitude and / or common-mode voltage to allow driver circuit 240 to generate the third signal having a greater voltage amplitude than the first signal.

[0082] In one approach, the transmitter 210 detects 740 a change in the second signal due to a capacitor electrically coupled to an input of the latch. The capacitors (e.g., C3, C3', C4, C4') may be electrically coupled between the modem and the latches (e.g., Latch1, Latch2) of the level shifter 230. In one aspect, the first signal applied to the latch through the capacitor may result in a peak or overshoot corresponding to an AC component ΔV AC , as mentioned above about Figure 5 discussed.

[0083] In one approach, the transmitter 210 adjusts 750 the second supply voltage based on the detected change. In one aspect, the resistor ladder 280 can detect the AC component ΔV due to the capacitor. AC , and adjusting the second supply voltage to reduce i) the change in the second signal due to the capacitor (eg, the AC component ΔV AC ) and ii) the voltage amplitude (or DC component ΔV of the second signal DC ). For example, the AC component ΔV AC The increase in ΔV may result in a decrease in the current Idc provided by the resistor ladder 280 to the latches (eg, Latch1, Latch2). The decrease in the current Idc may result in a DC component ΔV DC Therefore, the DC component ΔV DC Can track or follow the AC component ΔV AC By making the DC component ΔV DC Tracking AC component ΔV AC , which can achieve stable peak response and improve the eye opening and linearity of the output signals Outp and Outn, thereby enhancing communication quality.

[0084] The term "coupled" and its variations include two components directly or indirectly joining to each other. The term "electrically coupled" and its variations include two components directly or indirectly joining to each other through a conductive material (e.g., metal or copper traces). Such joining may be fixed (e.g., permanent or fixed) or removable (e.g., removable or releasable). Such joining may be achieved by two components being directly coupled or coupled to each other, two components being coupled to each other using a separate intermediate component and any additional intermediate components, or two components being coupled to each other using an intermediate component that is integrally formed as a single unitary body with one of the two components. If "coupled" or its variations are modified by additional terms (e.g., directly coupled), then the general definition of "coupled" provided above is modified by the plain language meaning of the additional terms (e.g., "directly coupled" means the joining of two components without any separate intermediate components), resulting in a narrower definition than the general definition of "coupled" provided above. Such coupling may be mechanical, electrical, or fluidic.

[0085] It should be noted that certain paragraphs of this disclosure may refer to terms related to circuits, signals, and devices, such as "first" and "second," to identify or distinguish one from another or others. These terms are not intended to relate entities (e.g., a first device and a second device) solely in time or according to sequence, although in some cases, these entities may contain such a relationship. These terms also do not limit the number of possible entities that can operate in a system or environment. It should be understood that the system described above may provide multiple of any or each of these components, and these components may be provided on a standalone machine or, in some embodiments, on multiple machines in a distributed system. In addition, the systems and methods described above may be provided as one or more computer-readable programs or executable instructions embodied on or in one or more articles of manufacture (e.g., a floppy disk, hard disk, CD-ROM, flash memory card, PROM, RAM, ROM, or magnetic tape). The program may be implemented in any programming language (e.g., LISP, PERL, C, C++, C#) or in any bytecode language (e.g., JAVA). The software program or executable instructions may be stored as object code on or in one or more articles of manufacture.

[0086] Although the foregoing written description of the methods and systems enables one of ordinary skill in the art to make and use embodiments thereof, one of ordinary skill in the art will understand and appreciate that variations, combinations, and equivalents exist to the specific embodiments, methods, and examples herein. Therefore, the methods and systems should not be limited to the above-described embodiments, methods, and examples, but rather to all embodiments and methods within the scope and spirit of the present disclosure.

Claims

1. A system comprising: A circuit system for generating a first signal having a first voltage amplitude according to a first supply voltage, wherein the circuit system comprises: a latch electrically coupled to a resistor among a plurality of resistors, the plurality of resistors being coupled in series, one end of the resistor providing a second power supply voltage to the latch according to voltage division according to a third power supply voltage, and the other end of the resistor receiving the third power supply voltage, The circuit system is used to: modifying the first signal by the latch according to the second supply voltage that is higher than the first supply voltage to provide a second signal, and The second signal is amplified according to the third supply voltage that is higher than the second supply voltage to provide a third signal having a second voltage amplitude greater than the first voltage amplitude.

2. The system according to claim 1, wherein the circuit system is configured to generate the first signal that swings between the first supply voltage and a first source voltage, and The latch is configured to generate the second signal swinging between the second supply voltage and a second source voltage, the second source voltage being higher than the first source voltage. 3 . The system of claim 2 , wherein a terminal of another resistor of the plurality of resistors is electrically coupled to the latch to provide the second source voltage.

4. The system of claim 1 , wherein the circuit system further comprises: another latch for modifying the first signal to generate a fourth signal, The circuit system is configured to generate the third signal according to the second signal and the fourth signal.

5. The system according to claim 4, wherein the circuit system is configured to generate the first signal that swings between the first supply voltage and a first source voltage, wherein the latch is configured to generate the second signal swinging between the second supply voltage and a second source voltage, the second source voltage being higher than the first source voltage, and The another latch is configured to generate the fourth signal swinging between a fourth power supply voltage and a third source voltage, the fourth power supply voltage being lower than the second source voltage, and the third source voltage being lower than the fourth power supply voltage. 6 . The system according to claim 5 , wherein one end of another resistor of the plurality of resistors is electrically coupled to the another latch to provide the fourth power supply voltage to the another latch according to the third power supply voltage.

7. The system of claim 5, further comprising: at least a first resistor and a second resistor electrically coupled in series, One end of the first resistor is used to receive the third supply voltage, and The other end of the first resistor is electrically coupled to the other latch to provide the fourth power supply voltage to the other latch according to the third power supply voltage.

8. The system of claim 1 , wherein the circuit system comprises: capacitor, which is electrically coupled to the input of the latch, The plurality of resistors are used to: detecting a change in the second signal attributable to the capacitor, and The second supply voltage is adjusted to reduce a difference between i) the change in the second signal attributable to the capacitor and ii) a third voltage amplitude of the second signal.

9. The system of claim 1 , wherein the latch comprises: The first inverter, The second inverter, a first port electrically coupled to an input of the first inverter and an output of the second inverter, and A second port is electrically coupled to an input of the second inverter and an output of the first inverter.

10. The system of claim 9, wherein the circuit system comprises: a first circuit configured to generate the first signal according to the first supply voltage, and a second circuit for amplifying the second signal according to the third supply voltage to generate the third signal, wherein the first port of the latch is electrically coupled to a first input of the second circuit, wherein the second port of the latch is electrically coupled to a second input of the second circuit, and Wherein the circuitry further includes a capacitor electrically coupled between the first circuit and the first port.

11. The system of claim 10, wherein one end of another resistor of the plurality of resistors is electrically coupled to the other end of the resistor, the system further comprising: Another capacitor is electrically coupled between the one end of the another resistor and the other end of the another resistor.

12. The system of claim 1, wherein one or more of the plurality of resistors is a variable resistor or a programmable resistor.

13. A system comprising: a first latch configured to receive a first signal and generate a second signal swinging between a first supply voltage and a first source voltage based on the first signal; a second latch configured to receive the first signal and generate a third signal swinging between a second supply voltage and a second source voltage according to the first signal; an amplifier electrically coupled to the first latch and the second latch, the amplifier configured to receive the second signal and the third signal and generate a fourth signal based on a third supply voltage and a third source voltage; and a resistor ladder electrically coupled to the first latch and the second latch, wherein: According to the third supply voltage, the resistor ladder provides the first supply voltage to the first latch according to voltage division and provides the first source voltage to the first latch according to voltage division, and According to the third power supply voltage, the resistor ladder provides the second power supply voltage to the second latch according to voltage division and provides the second source voltage to the second latch according to voltage division.

14. The system of claim 13, wherein the second signal is a differential signal, wherein the third signal is another differential signal.

15. The system of claim 13, wherein the amplifier comprises: a first differential pair circuit including an input electrically coupled to an output of the first latch, and A second differential pair circuit includes an input electrically coupled to the output of the second latch, and an output of the first differential pair circuit is electrically coupled to the output of the second differential pair circuit.

16. The system according to claim 13, wherein the resistor ladder comprises a first resistor and a second resistor electrically coupled in series, One end of the first resistor is used to receive the third supply voltage, wherein the other end of the first resistor is electrically coupled to the second latch to provide the second power supply voltage to the second latch according to the third power supply voltage, and One end of the second resistor is electrically coupled to the second latch to provide the second source voltage to the second latch according to the third supply voltage.

17. The system according to claim 16, The resistor ladder further includes a third resistor and a fourth resistor electrically coupled in series with the first resistor and the second resistor, wherein one end of the third resistor is electrically coupled to the first latch to provide the first power supply voltage to the first latch according to the third power supply voltage, and One end of the fourth resistor is electrically coupled to the first latch to provide the first source voltage to the first latch according to the third power supply voltage.

18. The system according to claim 16, wherein the third supply voltage is higher than the second supply voltage, wherein the second supply voltage is higher than the first supply voltage, wherein the second source voltage is higher than the first source voltage, and The first source voltage is higher than the third source voltage.

19. A method comprising: generating, by the circuit system, a first signal having a first voltage amplitude based on the first supply voltage; modifying, by a latch of the circuit system, the first signal according to a second supply voltage higher than the first supply voltage to generate a second signal having a second voltage magnitude; detecting a change in the second signal attributable to a capacitor coupled to an input of the latch by a resistor ladder of the circuitry, wherein the resistor ladder provides the second supply voltage to the latch according to a voltage division; and The second supply voltage is adjusted by the resistor ladder of the circuitry based on the detected change in the second signal.

20. The method of claim 19, wherein adjusting, by the resistor ladder, the second supply voltage based on the detected change in the second signal comprises: The second supply voltage is adjusted by the resistor ladder to reduce a difference between i) the variation in the second signal attributable to the capacitor and ii) the second voltage amplitude.

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