Voltage regulator circuit and corresponding memory device

Abstract

Embodiments of the present disclosure relate to a voltage regulator circuit and a corresponding memory device. The voltage regulator receives an input voltage and generates a regulated output voltage. A first feedback network compares a feedback signal with a reference signal to assert / de-assert a first pulse control signal when the reference signal is higher / lower than the feedback signal. A second feedback network compares an output voltage with a threshold signal to assert / de-assert a second control signal when the threshold signal is higher / lower than the output voltage. If the second control signal is de-asserted and controlled by the first pulse control signal clock to generate a supply voltage higher than the input voltage, a charge pump is enabled. A first transmission element is enabled when the second control signal is asserted, and the first transmission element is selectively activated when the first pulse control signal is asserted. When the second control signal is de-asserted, the second transmission element is selectively activated.

Description

[0001] Priority claim

[0002] This application claims the benefit of Italian Patent Application No. 102021000027458, filed on October 26, 2021, which is incorporated herein by reference. Technical Field

[0003] The present description relates to a voltage regulator circuit that may be applied to, for example, a memory device such as a phase change memory (PCM) device and / or a general purpose microcontroller (GPMCU). Background Art

[0004] Low dropout (LDO) voltage regulator circuits are widely used in industrial and automotive applications, such as general-purpose microcontrollers. An LDO regulator is typically an integrated circuit designed to provide a constant (e.g., fixed) output voltage under varying load conditions with minimal voltage drop and fast response time.

[0005] The growing demand for portable and battery-operated electronic devices requires LDO regulators that can operate in a wide range of supply voltages and / or multi-voltage platforms. For example, the supply voltage VCC of a circuit may be in the range of 1.6V to 3.6V, and the operating voltage VDD of a chip may be in the range of 0.8V to 1.15V. Therefore, standby current and quiescent current are relevant parameters in the design of LDO regulators, also considering that LDO regulators can be expected to operate in a wide temperature range (e.g., from -40°C to 125°C).

[0006] Therefore, there is a need in the art to provide improved voltage regulator circuits (eg, LDO regulators) having fast response time, small silicon area, low standby current and quiescent current consumption, and / or high current efficiency. Summary of the invention

[0007] It is an object of one or more embodiments to help provide such an improved voltage regulator circuit.

[0008] According to one or more embodiments, such an object is achieved by a circuit having the features set out in the appended claims.

[0009] One or more embodiments may be directed to a corresponding memory device.

[0010] The claims are an integral part of the technical teaching provided here regarding the embodiments.

[0011] In one or more embodiments, a circuit includes: an input node configured to receive an input voltage; and an output node configured to generate a regulated output voltage. The circuit includes a first feedback network configured to generate a feedback signal indicating the regulated output voltage, and compare the feedback signal with a reference signal to generate a first pulse control signal. The first pulse control signal is asserted in response to the reference signal being higher than the feedback signal, and is de-asserted in response to the reference signal being lower than the feedback signal. Therefore, the time average value of the first pulse control signal is a function of the difference between the reference signal and the feedback signal (e.g., it linearly depends on the difference between the reference signal and the feedback signal, or is proportional to the difference between the reference signal and the feedback signal). The circuit includes a second feedback network configured to generate a threshold signal indicating the input voltage, and compare the regulated output voltage with the threshold signal to generate a second control signal. The second control signal is asserted in response to the threshold signal being higher than the regulated output voltage, and the second control signal is de-asserted in response to the threshold signal being lower than the regulated output voltage. The circuit includes a charge pump circuit configured to generate a supply voltage higher than the input voltage. The charge pump circuit is enabled in response to the second control signal being de-asserted and is clocked by the first pulse control signal, whereby the value of the power supply voltage is a function of the first pulse control signal (e.g., it depends linearly on or is proportional to the first pulse control signal). The circuit includes a first transmission element arranged between an input node and an output node. The first transmission element is enabled in response to the second control signal being asserted, and the first transmission element is selectively activated in response to the first pulse control signal being asserted to connect the input node to the output node. The circuit includes a second transmission element arranged between the output and the output node of the charge pump circuit. In response to the second control signal being de-asserted, the second transmission element is selectively activated to connect the output of the charge pump circuit to the output node.

[0012] In one or more embodiments, the first feedback network includes a low voltage clocked comparator configured to compare the feedback signal with a reference signal, assert the first pulse control signal in response to the reference signal being higher than the feedback signal, and de-assert the first pulse control signal in response to the reference signal being lower than the feedback signal.

[0013] In one or more embodiments, the low voltage clock controlled comparator includes a plurality of dynamic (e.g., clock controlled) comparators that are clock controlled by corresponding time-shifted clock signals. Each clock signal has the same clock period, and one clock signal is time-shifted by a fraction of the clock period relative to another clock signal. A dynamic comparator in the plurality of dynamic comparators is configured to sequentially compare the feedback signal with the reference signal to assert and de-assert the corresponding output signal in response to the reference signal being higher and lower than the feedback signal, respectively. The low voltage clock controlled comparator includes a monostable circuit that is configured to receive output signals from the plurality of dynamic comparators and assert a first pulse control signal in response to assertion of any output signal received from the plurality of dynamic comparators.

[0014] In one or more embodiments, a low voltage clocked comparator includes a ring oscillator configured to generate a time-shifted clock signal for a plurality of dynamic comparators.

[0015] In one or more embodiments, the circuit includes a first level shifter circuit disposed between the low voltage clock control comparator and the first transmission element. The first level shifter circuit is configured to shift the first pulse control signal from the low voltage domain to the high voltage domain, and propagate the shifted first pulse control signal to the first transmission element in response to the second control signal being asserted.

[0016] In one or more embodiments, the first feedback network includes a first resistor arranged in series with a first current generator between the output node and a ground node. A feedback signal is generated at a node intermediate the first resistor and the first current generator.

[0017] In one or more embodiments, the first current generator comprises a variable current generator configured to generate a variable current depending on a value of a first digital control signal, whereby the feedback signal is shifted depending on the first digital control signal.

[0018] In one or more embodiments, the second feedback network includes a second resistor arranged in series with the second current generator between the input node and the ground node. A threshold signal is generated at a node intermediate the second resistor and the second current generator. The second feedback network includes an additional comparator configured to compare the regulated output voltage with the threshold signal, assert the second control signal in response to the threshold signal being higher than the regulated output voltage, and de-assert the second control signal in response to the threshold signal being lower than the regulated output voltage.

[0019] In one or more embodiments, the second current generator comprises a variable current generator configured to generate a variable current depending on a value of the second digital control signal, whereby the threshold signal is shifted depending on the second digital control signal.

[0020] In one or more embodiments, the circuit includes an inverter circuit and a second level shifter circuit, the second level shifter circuit being arranged between the additional comparator and the second transmission element to generate a complementary signal of the second control signal, shift the complementary signal from a low voltage domain to a high voltage domain, and propagate the shifted complementary signal to the second transmission element. The second transmission element is activated in response to the shifted complementary signal being asserted, and is deactivated in response to the shifted complementary signal being deasserted.

[0021] In one or more embodiments, a memory device includes an array of memory cells arranged in a plurality of bit lines and a plurality of word lines. Each memory cell is arranged in series with a corresponding selection transistor between a ground terminal and a corresponding bit line, and each bit line can be selectively coupled to a power supply voltage rail that provides a regulated voltage. The memory device includes a voltage regulator circuit according to one or more embodiments, which has an output node coupled to the power supply voltage rail to provide a regulated voltage thereto. The voltage regulator circuit is selectively activated in response to the memory device receiving a memory read command to generate a regulated voltage.

[0022] In one or more embodiments, a word line is selectively coupleable to an output node of a voltage regulator circuit. The memory device is configured to couple one or more unselected word lines to the output node of the voltage regulator circuit during a read operation from a selected word line in the memory device.

[0023] In one or more embodiments, a filtered output voltage is generated at one or more unselected word lines coupled to an output node of a voltage regulator circuit. A first feedback network of the voltage regulator circuit may be selectively coupled to the unselected word lines and configured to generate a feedback signal indicative of the filtered output voltage. A second feedback network of the voltage regulator circuit may be selectively coupled to the unselected word lines and configured to compare the filtered output voltage with a threshold signal to generate a second control signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] One or more embodiments will now be described, by way of example only, with reference to the accompanying drawings, in which:

[0025] Figure 1 is an exemplary circuit diagram of a memory architecture according to one or more embodiments of the present specification;

[0026] Figure 2is an exemplary timing diagram of signals during a read operation in a memory;

[0027] Figure 3 is a circuit diagram of an exemplary voltage regulator circuit, particularly a low dropout voltage regulator circuit;

[0028] Figure 4 is an exemplary circuit diagram of a voltage regulator circuit according to one or more embodiments of the present specification, particularly a low dropout voltage regulator circuit; and

[0029] Figure 5A , 5B and 5C are exemplary circuit diagrams of possible implementation details of a voltage regulator circuit according to one or more embodiments of the present specification. DETAILED DESCRIPTION

[0030] In the following description, one or more specific details are shown for the purpose of providing a deeper understanding of the examples of the embodiments of the present description. The embodiments can be obtained without one or more specific details, or with other methods, components, materials, etc. In other cases, well-known structures, materials, or operations are not shown or described in detail so as not to obscure certain aspects of the embodiments.

[0031] References to "an embodiment" or "an embodiment" in the framework of this specification are intended to indicate that a particular configuration, structure, or characteristic described with respect to that embodiment is included in at least one embodiment. Therefore, phrases such as "in an embodiment" or "in an embodiment" that may appear in one or more points of this specification do not necessarily refer to the same embodiment. Furthermore, in one or more embodiments, particular configurations, structures, or characteristics may be combined in any appropriate manner.

[0032] The headings / references used herein are provided for convenience only and do not limit the scope of protection or the scope of the embodiments.

[0033] In the drawings attached hereto, unless the context otherwise indicates, the same parts or elements are denoted by the same reference numerals / numbers, and the corresponding description will not be repeated for the sake of brevity.

[0034] By introducing the detailed description of the exemplary embodiments, reference may first be made to Figure 1 and 2 . Figure 1 is a circuit diagram illustrating a memory read structure in a phase change memory, Figure 2 is an example Figure 1 A timing diagram of the signals during a read operation in a memory.

[0035] like Figure 1, the memory 10 may include an array of memory cells 102 (e.g., phase change memory cells) arranged in bit lines 103B (illustrated here as vertical lines) and word lines 103W1, 103W2, 103W3 (illustrated here as horizontal lines) according to a memory architecture known per se. Specifically, each memory cell 102 may be arranged in series with a corresponding selection transistor 104 (e.g., a pnp BJT transistor) between a ground voltage terminal and the corresponding bit line 103B. The selection transistors 104 of the same word line 103W receive the same control signal at their control (e.g., base) terminals, e.g., Figure 1 and 2 Each bit line 103B can be selectively coupled (eg, via a corresponding p-channel MOS transistor 106 connected in series with the bit line and receiving the control signal Y_SEL) to provide a regulated voltage V REG 108. In addition, each clamp transistor 110 (e.g., a pnp BJT transistor) may be coupled between each bit line 103B (e.g., at the source terminal of transistor 106) and a ground terminal. The clamp transistors 110 may receive the same control signal WL at their control (e.g., base) terminals. CLAMP Due to the capacitance of the memory cell 102 and / or the transistors 106, 110, each bit line 103B has a corresponding capacitive load C BL .

[0036] You can Figure 2 Execute as shown in Figure 1 144:0] to read (and provide as output) the contents of multiple PCM words on the output data bus DATA_OUT[144:0]. Generally speaking, in a phase change memory, information can be stored associating two cells with each bit: a SET cell (with low resistance and high current) and a RESET cell (with high resistance and low current). The memory sensing circuit can read information from the cells in a differential mode. In one or more embodiments, two operations can be used to read the memory contents, namely:

[0037] - Read in 128-bit mode: This operation reads the contents of one word at the specified address (128 bits of data plus 17 bits of ECC, i.e., a total of 145 bits). In this case, the MSB (most significant bit) address is used to select the first memory backup (BANK0) or the second memory backup (BANK1), since the memory may include two banks. The output data bus DATA_OUT[144:0] will provide a word (145 bits), and 145 sense amplifiers can be provided for each memory bank;

[0038] - Read in 256-bit mode: This operation reads the contents of two words stored in two different memory banks. In this case, the LSB (least significant bit) address is used to select the first memory backup (BANK0) or the second memory backup (BANK1). The first word (128 bits of data plus 17 bits of ECC, i.e., a total of 145 bits) will be read after a certain waiting time (T ACC ) is provided at the output data bus DATA_OUT[144:0] and the second word will be available after a very short waiting time (T ACC2 ) is then provided at the output data bus DATA_OUT[144:0].

[0039] It should be noted that the number of bits read in parallel as well as the access time may vary in different embodiments.

[0040] In order to provide fast reading of memory cells, the memory access time (T ACC ) may be particularly demanding (e.g., on the order of 10ns). As previously described, read parallelism (e.g., reading two words in parallel) can be used to increase the throughput of the output data. As previously stated, the sensing of the contents of the memory cells can be performed in differential mode: the readout circuit reads from the bit line BL_SET and the bit line BL_RESET in differential mode, thereby selecting the SET memory cell and the RESET memory cell. The SET memory cell and the RESET memory cell are selected by appropriately driving the control signals (word select signals) WL1, WL2, WL3: for example, Figure 2 As shown, by maintaining signals WL1 and WL3 at high logic values ​​(e.g., equal to power supply voltage VCC) and by driving signal WL2 to a low logic value (e.g., equal to ground voltage), unit 102 S Selected as SET unit, unit 102 R Selected as RESET unit.

[0041] A voltage regulator (eg, an LDO regulator) generates a regulated voltage V at the power rail 108. REG (For example, with an expected voltage value V BL_CHARGE ). Voltage V REG The value of V BL_CHARGE The voltage V at the bit line is selected before sensing (e.g., differentially between BL_SET and BL_RESET). BL Clamped to the value V of the base-emitter voltage of the clamp transistor 110 BE , and then by activating transistor 106 (see Figure 2 In the process, the control signal Y_SEL changes from high value V BL_CHARGE106) to precharge the bit line to the regulated voltage V REG The value of V BL_CHARGE The control signals WL1 and WL3 of the unselected word lines are driven to a high voltage value (eg, the power supply voltage VCC) in order to keep the corresponding selection transistors in a non-conducting state.

[0042] Due to high read parallelism, precharge to V before sensing BL_CHARGE The number of precharged bit lines may be higher. For example, in the case of reading 148 bits (128 words + ECC + redundancy) from two bit lines (SET and RESET) with a word parallelism equal to 2, the number of precharged bit lines is equal to 148*2*2=592. The parasitic capacitance C of each bit line BL It can be in the range of tens of fF (1fF = 10-15F) to hundreds of fF. During the precharge phase, all precharged bit lines are charged from the value V BE (e.g., about 0.5V) is charged to a value V BL_CHARGE (e.g., about 1.55V). When the bit line is connected to the power rail 108 via transistor 106, the associated current flows from the power rail 108 to the bit line, resulting in a voltage V REG The associated drop in voltage V REG The value is adjusted from the value V BL_CHARGE Reduce (see again Figure 2 ). In various applications, the regulated voltage V REG This voltage drop must be recovered within a short recovery time (T REC ) to provide the short access time (T ACC ). Considering the recovery time T with an exemplary value of about 2ns or 3ns REC , the voltage regulator supplying power rail 108 may be required to provide a peak current Ipeak equal to:

[0043]

[0044] Therefore, the (LDO) voltage regulator should be able to provide high current with fast response time.

[0045] Another possible related issue concerns the wide supply voltage range, especially lower supply voltage values ​​that may be below the regulated value. For example, if the supply voltage V CC The minimum value V CC，MIN is about 1.62V, then V BL_CHARGE In typical cases, it may be lower than V CC，MIN , but may be higher than V in some corner cases (e.g., slow silicidation and high temperature) CC，MIN , to compensate for selector and cell variations. Alternatively, the value V BL_CHARGEis set higher to provide higher SET current and reduce read failures. Therefore, even if the supply voltage V CC Lower than expected regulation voltage V BL_CHARGE , a (LDO) voltage regulator may also be needed to provide the correct output voltage.

[0046] Figure 3 is an exemplary circuit diagram of a circuit architecture of an LDO voltage regulator 30 for use in a memory device. Specifically, the regulator includes a circuit configured to receive an input voltage V CC (e.g., in the range of 1.6V to 3.6V) and is configured to provide a regulated output voltage V REG The output node 302 is provided with a voltage V in the range of 1.6V to 1.8V. A transmission element 304 (e.g., a p-channel MOS transistor) provides a current path between the input node 300 and the output node 302, and its conductivity can be modulated depending on a control signal applied to the transmission element 304 (e.g., applied to the gate of the transistor 304). With the help of a selector 306 (e.g., a pair of switches), the terminal of the transmission element 304 opposite to the output node 302 (e.g., the source terminal of the transistor 304) can be directly connected to the input node 300 (when the input voltage V CC Higher than the output voltage V that the regulator 30 is expected to provide REG ), or may be coupled to the output of the charge pump circuit 308 (when the input voltage V CC Lower than the output voltage V REG is also coupled to the input node 300 to receive the input voltage V CC The charge pump circuit 308 may receive an enable signal PMP_EN and a clock signal PMP_CK and may generate a charge pump higher than V depending on the signals PMP_EN and PMP_CK in a manner known per se. CC The output voltage of the large tank capacitor C TANK is coupled between the output node 302 and the ground node 310 and provides a charge storage to reduce the output voltage V REG The undershoot.

[0047] The LDO regulator 30 also includes a feedback network to generate a control signal for the transmission element 304. In particular, the feedback network includes a resistor R1 arranged in series with a variable current generator 312 between the output node 302 and the ground node 310. The amount of current generated by the current generator 312 can depend on the digital control signal VBL_CTL<4:0>. The node between the resistor R1 and the current generator 312 can therefore provide a feedback signal VFB provided at the inverting input of the high-voltage comparator 314. A reference voltage signal VREF is provided at the non-inverting input of the comparator 314. The comparator can receive a power supply voltage from a node between the transmission element 304 and the selector 306, that is, it can receive the power supply voltage V CC or the supply voltage generated by the charge pump 308. The output signal from the comparator 314 is provided to the pass element 304 as a control signal.

[0048] Therefore, in Figure 3 In the LDO architecture illustrated in FIG. 1 , a large selector 306 (e.g., two large switches) is required to connect the input of the pass element 304 and the power supply node of the comparator 314 to either the input node 300 or the output of the charge pump 308 (depending on the state of the selector 306, which depends on V CC With V REG In addition, a voltage detector is required to properly operate the selector 306.

[0049] One or more embodiments may rely on Figure 4 The different LDO voltage regulator architecture 40 illustrated in FIG. 4 , also referred to as an on / off LDO regulator with an integrated charge pump, is also applicable to Figure 1 In the memory device 10 illustrated in .

[0050] Specifically, in one or more embodiments, the voltage regulator 40 includes a circuit configured to receive an input voltage V CC (e.g., in the range of 1.6V to 3.6V) and is configured to provide a regulated output voltage V REG The output node 402 may be electrically connected to a voltage (eg, in the range of 1.6V to 1.8V).

[0051] One or more embodiments may include a first pass element 404a (e.g., an electronic switch, more specifically, an n-channel MOS transistor) disposed between the input node 400 and the output node 402. When enabled, the first pass element 404a may be selectively activated (e.g., in an on-off manner) to provide a low impedance current path between the input node 400 and the output node 402. The first pass element 404a may be responsive to an input voltage V CC Higher than the output voltage V that the regulator 40 is expected to provide REGInstead, there may be a margin ΔV. Purely by way of example, the channel of transistor 404 a may have a width of approximately 200 μm and a length of approximately 0.3 μm.

[0052] One or more embodiments may include a first feedback network configured to generate a control signal COMP_OUT that controls the first transmission element 404a. Specifically, the first feedback network may include a resistor R1 (e.g., a resistor) arranged in series with a variable current generator 412 between the output node 402 and the ground node 410. The amount of current generated by the current generator 412 and the voltage drop across the resistor R1 may depend on the digital control signal VBL_CTL<4:0> (e.g., a 5-bit signal). The node between the resistor R1 and the current generator 412 can therefore provide a feedback signal VFB, which is fed to the inverting input of a low voltage, high speed comparator 414. The reference voltage signal VREF is fed to the non-inverting input of the comparator 414. The comparator 414 may receive a power supply voltage V lower than the power supply voltage V at the node 400 from a node 415. CC The power supply voltage V DD (For example, for a low voltage transistor, V DD The supply voltage can be in the range of 0.81V to 1.15V, and for high voltage transistors, V CC The power supply voltage can be in the range of 1.62V to 3.6V).

[0053] In one or more embodiments, the output signal COMP_OUT from the comparator 414 is provided as a control signal to the first transmission element 404a via the level shifter circuit 416a. The level shifter circuit 416a may receive the positive supply voltage VXR and the control signal VCC_EN generated by the second feedback network of the regulator circuit 40, and may be configured to shift the low voltage level from the output of the comparator 414 to the VXR voltage domain. Specifically, the level shifter 416a may be activated (e.g., turned on) in response to the control signal VCC_EN being asserted (e.g., set to '1'). When turned on, the level shifter 416a shifts the signal COMP_OUT from V DD The level shifter 416a may be disabled (e.g., turned off) in response to the control signal VCC_EN being de-asserted (e.g., set to "0"), thereby forcing the gate of the transistor 404a to a low value (e.g., 0V) to turn it off.

[0054] In response to the control signal VCC_EN being asserted, the control signal COMP_OUT may thus be propagated to the control terminal of the first pass element 404a (eg, to the gate terminal of the transistor 404a) such that when VCC Higher than the expected output voltage V BL_CHARGE Add a voltage margin ΔV (V CC >V BL_CHARGE +ΔV), the first pass element 404a is active, depending on the signal COMP_OUT. The gate of transistor 404a can be clocked to voltage VXR at a very high frequency because comparator 414 operates at high speed. The supply voltage VXR can be regulated to be higher than or equal to V CC The maximum value (for example, VXR = 3.6V ≥ V CC , MAX) value is generated by the charge pump circuit.

[0055] One or more embodiments may include coupling to input node 400 to receive an input voltage V CC The charge pump circuit 408 can receive the enable signal PMP_EN and the control signal COMP_OUT, and can generate a voltage higher than V CC The output voltage V depends on the signal PMP_EN and COMP_OUT BL_SUPPLY , as disclosed below. Specifically, the charge pump 408 may be turned on (respectively, turned off) depending on the enable signal PMP_EN being asserted (respectively, deasserted), while the on / off switching activity of the clock phase of the output stage of the charge pump 408 may be controlled by the signal COMP_OUT. Therefore, in one or more embodiments, the charge pump 408 may not be equipped with a dedicated regulator, as long as it may instead rely on (e.g., use) the (very fast) comparator 414.

[0056] One or more embodiments may include a second pass element 404b (e.g., an electronic switch, more specifically, an n-channel MOS transistor) disposed between the output of the charge pump circuit 408 and the output node 402. The second pass element 404b may be selectively activated (e.g., in a switch manner) to provide a low impedance current path between the output of the charge pump circuit 408 and the output node 402. The second pass element 404b may be selectively activated (e.g., in a switch manner) to provide a low impedance current path between the output of the charge pump circuit 408 and the output node 402. CC is lower than the output voltage V that the regulator 40 is expected to provide REG The second pass element 404b is activated (eg switched to an on state). Purely by way of example, the channel of the transistor 404b may have a width of approximately 200 μm and a length of approximately 0.36 μm.

[0057] Therefore, in one or more embodiments, the output node 402 can be dynamically managed at a voltage V CC (received from node 400 via transmission element 404a) and voltage V BL_SUPPLY (received from circuit 408 via transmission element 404b).

[0058] One or more embodiments may include a second feedback network configured to generate control signals PMP_EN and VCC_EN. Specifically, the second feedback network includes a resistor R2 (e.g., a resistor) arranged in series with a variable current generator 418 between the input node 400 and the ground node 410. The amount of current generated by the current generator 418 and the voltage drop across the resistor R2 may depend on the digital control signal VCC_CTL<2:0> (e.g., a 3-bit signal). The node between the resistor R2 and the current generator 418 can therefore provide a threshold signal VTH, which is fed to the non-inverting input of the comparator 420. The output voltage V REG is fed to the inverting input of comparator 420. Comparator 420 compares VTH and V REG The control signal VCC_EN is generated as an output. The inverter circuit 422 receives the control signal VCC_EN as an input and generates a control signal PMP_EN as the complement of the signal VCC_EN.

[0059] In one or more embodiments, the control signal PMP_EN is provided as a control signal to the second transmission element 404b via the level shifter circuit 416b. The level shifter circuit 416b may receive the positive supply voltage VXR and may be configured to shift the low voltage level from the output of the comparator 420 to the VXR voltage domain. The control signal PMP_EN may thus be propagated to the control terminal of the second transmission element 404b (e.g., to the gate terminal of the transistor 404b) such that when V CC Lower than the expected output voltage V BL_CHARGE Add a voltage margin ΔV (V CC <V BL_CHARGE +ΔV), the second pass element 404b is activated. When the signal PMP_EN is asserted, the gate of the transistor 404b can be forced to reach the voltage VXR, and the output V BL_SUPPLY Directly adjust the output voltage V REG The value of V BL_CHARGE .

[0060] In one or more embodiments, at power-up, the output voltage V REG can be driven to its regulated value V BL_CHARGE , until the control signal VBL_OK is asserted (eg, set to '1'). The output voltage V REG The voltage V CC Or through the voltage V BL_SUPPLY Maintained at its regulated value V BL_CHARGEAs a result of the enable signal PMP_EN being asserted (eg, set to '1'), the charge pump circuit 408 and the driver (ie, the level shifter 416b and the pass element 404b) coupled between the pump 408 and the output node 402 may be turned on. The value of the digital signal VCC_CTL<2:0> may be set to 2 so that when V CC -V REG The charge pump circuit is turned on when ≈80mV.

[0061] In one or more embodiments, the charge pump circuit 408 may not be equipped with an internal voltage regulator. Therefore, the output level may be directly controlled by the output of the comparator 414.

[0062] Additionally, one or more embodiments may not include a dedicated tank capacitor C coupled between the output node 402 and the ground node 410. TANK . All unselected word lines of all memory sectors (e.g., according to Figure 1 and 2 4243) are selectively connected to the output node 402 to provide a large tank capacitance at the output node 402. For example, the switches 4241...4243 may include n-channel MOS transistors. In the case where the select transistors 104 in the memory 10 are pnp BJT transistors (which are turned on when the corresponding control signal WL1, WL2 or WL3 is low), each n-channel MOS transistor 4241...4243 can receive the corresponding control signal WL1, WL2 or WL3 at the gate terminal. Purely by way of example, in a memory architecture including 8 memory sectors, 4 tiles per sector, and 1056 word lines per tile, and considering the capacitance C of each word line WL Approximately equal to 180 fF, the total capacitance that can be coupled to node 402 via switch 424 can be approximately equal to 8*4*1056*180 fF≈6 nF.

[0063] Figure 5A , 5B and 5C are exemplary circuit diagrams of possible implementation details of the voltage regulator circuit 40 according to one or more embodiments.

[0064] Specifically, Figure 5Ais an example of a possible implementation of the comparator 414 in one or more embodiments. The comparator 414 may include a high frequency ring oscillator 500 that provides M different clock signals (or clock phases) CKA, CKB, CKC, CKD, CKE (e.g., five clock signals). Each clock signal may be delayed by 1 / M (e.g., one-fifth) of the ring oscillator period TOSC relative to the previous period. For example, if the frequency of the ring oscillator 500 is approximately 800 MHz, TOSC is approximately 1.25 ns. Each clock signal CKA, CKB, CKC, CKD, CKE may have a period of 1.25 ns, wherein the signal CKB is delayed by 0.25 ns relative to the signal CKA, the signal CKC is delayed by 0.25 ns relative to the signal CKB, and so on, until the signal CKA is delayed by 0.25 ns relative to the signal CKE. Each clock signal generated by the ring oscillator 500 may be used to provide a clock for a corresponding dynamic comparator 502A...502E. Therefore, the comparators 502A...502E can be operated sequentially in a quasi-continuous mode, where each comparator 502A...502E is activated for a period of time equal to T OSC / M(for example, T OSC / 5) time period, and comparators 502A...502E are activated one after another according to a "round-robin" mechanism. Comparators 502A...502E can be equipped with an offset compensation circuit. Each of comparators 502A...502E can receive a reference signal VREF at a corresponding non-inverting input terminal and a feedback signal VFB at a corresponding inverting input terminal. Dynamic comparators 502A...502E and ring oscillator 500 can operate in a low power supply voltage domain (e.g., 0.8V to 1.15V), so that low voltage transistors can be used and very high frequencies can be achieved. Therefore, within the range where the speed of regulator 40 can mainly depend on the speed of comparator 414, using a regulator such as Figure 5A The illustrated ultra high speed comparator 414 is advantageously based on a high frequency ring oscillator 500 with very fast start / stop operation and temperature compensation.

[0065] like Figure 5AAs shown, in one or more embodiments, the output signals from comparators 502A...502E are fed to a monostable circuit 504 that generates a control signal COMP_OUT. The assertion and de-assertion of signal COMP_OUT depend on the values ​​of signals VREF and VFB at the inputs of dynamic comparator 502. In response to VFB being lower than VREF, signal COMP_OUT will be asserted (e.g., set to '1'), and pass element 404a will provide current to output node 402. Specifically, monostable circuit 504 can be configured to generate a pulse in output signal COMP_OUT in response to a pulse received from any one of dynamic comparators 502A...502E. In some cases, generating a pulse in output signal COMP_OUT may be sufficient to restore regulation voltage V REG The desired value of V is thus obtained, so only one pulse passes through the monostable circuit 504 from the comparators 502A…502E. In other cases, two or more pulses may be required to restore the regulated voltage V REG The expected value of COMP_OUT can thus be generated by "combining" the pulses received from the comparator. Therefore, circuit 504 operates as a monostable circuit as long as it generates a stable output pulse, which can be a combination of multiple input pulses (one or more).

[0066] One or more embodiments may include a logic circuit 506 configured to control the switching activities of the ring oscillator 500 and the comparator 502 based on a read command issued to the memory. Specifically, when a read command is issued (e.g., the read signal READSTART is asserted or set to "1"), the ring oscillator 500 and the comparator 502 may be activated. The ring oscillator 500 and the comparator 502 may be refreshed (e.g., periodically) by a low-frequency fine-tunable clock signal. The logic circuit 506 may generate an enable signal COMP_EN for the comparators 502A...502E and a start signal STARTOSC for the oscillator 500 depending on one or more of the signals VBL_EN, READSTART, REFRESH, VBL_OK, and CKA. Specifically, signal COMP_EN may be asserted (e.g., set to '1') in response to signal VBL_EN being asserted (e.g., set to '1'), which indicates that voltage regulator 40 is on after power-on, and signal VBL_OK being asserted (e.g., set to '1'), which indicates that signal VREF is precharged to its stable state by another circuit at power-on. After power-on, it is expected that signals VBL_EN and VBL_OK remain asserted. In addition, signal COMP_EN may be asserted when a pulse is generated in signal READSTART (indicating issuance of a read command). For example, depending on the state of a shift register clocked by one of the clock phases of oscillator 500 (e.g., clock signal CKA), signal COMP_EN may remain asserted for a certain time interval. Thus, voltage regulator 40 may be turned on (only) for the reduced period required to perform a memory read operation. Signal REFRESH may be used to refresh V REG signal (eg, periodically refreshed insofar as it is a clocked structure).

[0067] Figure 5B is an example of a possible implementation of the feedback network that generates the signals VFB, VCC_EN, and PMP_EN.

[0068] like Figure 5B As shown, one or more embodiments may include a reference current generator circuit 508. Circuit 508 may include an operational amplifier 510 that generates gate control signals for transistors 512, 514, and 516 (e.g., p-channel MOS transistors). Transistor 512 may have a specific width of 10*W, a gate terminal coupled to the output of amplifier 510, and a source terminal coupled to power supply node 400 to receive a power supply voltage V CC , and the drain terminal is coupled to a first terminal of a resistor R51 (eg, a 123 kΩ resistor). A second terminal of the resistor R51 may be coupled to the ground node 410. The non-inverting input of the amplifier 510 may receive a bandgap reference voltage VBG , and the inverting input of amplifier 510 can be coupled to node middle transistor 512 and resistor R51. Transistors 514 and 516 can have a certain width W (e.g., one tenth of the width of transistor 512), are coupled to the respective gate terminals of the output of amplifier 510, and are coupled to supply node 400 to receive the power supply voltage V CC , and a corresponding source terminal configured to provide an output current IREF. Due to the size of transistors 512, 514, and 516, the value of current IREF may be equal to:

[0069]

[0070] like Figure 5B As shown, the variable current generator 412 may include an adjustable current mirror device, which includes transistors 518 and 520 and is configured to mirror the current I output from the transistor 516. REF . Specifically, the current mirror may include an n-channel MOS transistor 518 in a cross-diode configuration coupled to a variable n-channel MOS transistor 520 (e.g., a group of selectively activatable transistors 520 arranged in parallel) controlled by a signal VBL_CTL<4:0>. Each bit of the signal VBL_CTL<4:0> may control (e.g., turn on / off) one of the transistors 520 of the current mirror. Specifically, the variable transistor 520 may include (or be composed of) five transistors, one transistor for each bit of the signal VBL_CTL<4:0>. By controlling the value on the bus VBL_CTL<4:0>, the current flowing through the resistor R1 and the voltage drop V1 across the resistor R1 may be controlled. The resistors R1 and R51 may be matched. The voltage V1 across the resistor R1 (e.g., a 40 kΩ resistor) may therefore be calculated as:

[0071]

[0072] By controlling the current I TRIM1 (Using signal VBL_CTL<4:0>), the feedback signal VFB can be controlled and thus the regulation voltage V REG .

[0073] One or more embodiments may include a device coupled in series to receive a voltage V DD Two transistors (e.g., n-channel MOS transistors) 522 and 524 between the low voltage supply node 415 and the ground node. The gate of transistor 522 can be coupled to the node middle transistor 520 and the resistor R1, and a feedback signal VFB can be generated at the node middle transistors 522 and 524. Therefore, transistors 522 and 524 can reduce the voltage at the gate of transistor 522. Signal VREF can also be shifted by the same amount.

[0074] like Figure 5B As shown, the variable current generator 418 may include an adjustable current mirror arrangement including transistors 526, 528 and configured to mirror the current I output from the transistor 514. REF . Specifically, the current mirror may include an n-channel MOS transistor 526 in a cross-diode configuration coupled to a variable n-channel MOS transistor 528 (e.g., a group of selectively activatable transistors 528 arranged in parallel) controlled by a signal VCC_CTL<2:0>. Each bit of the signal VCC_CTL<2:0> may control (e.g., turn on / off) one of the transistors 528 of the current mirror. Specifically, the variable transistor 528 may include (or consist of) three transistors, one for each bit of the signal VCC_CTL<2:0>. By controlling the value on the bus VCC_CTL<2:0>, the current flowing through the resistor R2 and the voltage drop V2 across the resistor R2 may be controlled. The resistors R2 and R51 may be matched. The voltage V2 across the resistor R2 (e.g., a 40 kΩ resistor) may therefore be calculated as:

[0075]

[0076] By controlling the current I TRIM2 The threshold signal VTH, and thus the threshold voltage at which the charge pump 408 turns on, can be controlled (using the signal VCC_CTL<2:0>).

[0077] like Figure 5B and 5C As shown, in one or more embodiments, the first and second feedback networks of the regulator 40 may not be directly coupled to the output node 402 to receive the voltage V REG (like Figure 4 Instead, the feedback network may be coupled to unselected word lines of the memory array (eg, via transistors 5301 . . . 5303) to receive a voltage signal V REG_F , the voltage signal V REG_F corresponds roughly to the supply voltage V filtered by the capacitive load of the unselected word lines. REG Advantageously, this arrangement can also prevent undesired switching.

[0078] Thus, one or more embodiments of an LDO voltage regulator as illustrated herein may have a fast response time, for example, by means of the high speed dynamic comparators 502A . . . 502E in the comparator 414 .

[0079] Additionally, one or more embodiments may provide high accuracy by employing offset compensation for the comparators 502A...502E.

[0080] Additionally, in one or more embodiments, a large capacitor may be selectively coupled to the output node 402 of the voltage regulator by coupling unselected word lines of the memory device to which the voltage regulator is coupled (e.g., via switch 424) to the output node 402 of the voltage regulator. This arrangement facilitates providing fast (e.g., nearly instantaneous) current during the precharge phase without resorting to large dedicated tank capacitors, thereby saving layout area (e.g., silicon area).

[0081] Additionally, one or more embodiments may include a charge pump circuit 408 integrated into the voltage regulator 40. The charge pump circuit 408 may be regulated directly by the output of the dynamic comparator 414, resulting in fast control and response times, as well as reduced layout area when the pump circuit 408 does not require a dedicated comparator, feedback circuitry, and related circuitry.

[0082] In addition, one or more embodiments may provide for a power supply voltage V CC The power supply voltage V generated by the pump 408 BL_SUPPLY The dynamic switching structure also results in reduced current consumption and higher efficiency of the charge pump circuit 408 when there is no need to regulate the charge pump circuit 408 at a high voltage value. The dynamic switching architecture also allows fine-tuning of the supply voltage V CC With the regulated voltage V REG The difference ΔV between ΔV and ΔV is reduced, resulting in a higher degree of flexibility of the architecture and increased adaptability to different specifications (eg, charge / discharge voltage supply ramp rate). In one or more embodiments, hysteresis is introduced to avoid undesired switching.

[0083] Additionally, in one or more embodiments, the on / off architecture facilitates limited and controlled standby current consumption and quiescent current consumption.

[0084] The details and embodiments may vary even significantly with respect to what is described merely by way of example, without violating the essential principles and without departing from the scope of protection.

[0085] The scope of protection is determined by the appended claims.

Claims

1. A circuit comprising: an input node configured to receive an input voltage; an output node configured to generate a regulated output voltage; a first feedback network configured to generate a feedback signal indicative of the regulated output voltage and to compare the feedback signal with a reference signal to generate a first pulse control signal, wherein the first pulse control signal is asserted in response to the reference signal being higher than the feedback signal and the first pulse control signal is de-asserted in response to the reference signal being lower than the feedback signal, whereby a time average of the first pulse control signal depends on a difference between the reference signal and the feedback signal; a second feedback network configured to generate a threshold signal indicative of the input voltage and compare the regulated output voltage to the threshold signal to generate a second control signal, wherein the second control signal is asserted in response to the threshold signal being above the regulated output voltage and the second control signal is de-asserted in response to the threshold signal being below the regulated output voltage; a charge pump circuit configured to generate a supply voltage higher than the input voltage, wherein the charge pump circuit is enabled in response to the second control signal being de-asserted and is clocked by the first pulse control signal, whereby a value of the supply voltage depends on the first pulse control signal; a first transmission element disposed between the input node and the output node, wherein the first transmission element is enabled in response to the second control signal being asserted and is selectively activated to connect the input node to the output node in response to the first pulse control signal being asserted; as well as A second pass element is disposed between the output of the charge pump circuit and the output node, wherein the second pass element is selectively activated to connect the output of the charge pump circuit to the output node in response to the second control signal being de-asserted.

2. The circuit of claim 1 , wherein the first feedback network comprises a low voltage clocked comparator configured to compare the feedback signal with the reference signal, assert the first pulsed control signal in response to the reference signal being higher than the feedback signal, and de-assert the first pulsed control signal in response to the reference signal being lower than the feedback signal.

3. The circuit of claim 2, wherein the low voltage clock controlled comparator comprises: a plurality of dynamic comparators clocked by respective time-shifted clock signals, wherein the respective time-shifted clock signals have a same clock period and one time-shifted clock signal is time-shifted by a portion of the same clock period relative to another time-shifted clock signal, wherein the dynamic comparators of the plurality of dynamic comparators are configured to sequentially compare the feedback signal with the reference signal to assert and de-assert respective output signals in response to the reference signal being respectively higher and lower than the feedback signal; as well as A monostable circuit is configured to receive the output signals from the plurality of dynamic comparators and assert the first pulse control signal in response to assertion of any of the output signals received from the plurality of dynamic comparators. 4 . The circuit of claim 3 , wherein the low voltage clocked comparator comprises a ring oscillator configured to generate the time-shifted clock signal for the plurality of dynamic comparators.

5. The circuit according to claim 2 comprises a first level shifter circuit, which is arranged between the low voltage clock control comparator and the first transmission element, and the first level shifter circuit is configured to shift the first pulse control signal from the low voltage domain to the high voltage domain, and propagate the shifted first pulse control signal to the first transmission element in response to the second control signal being asserted.

6. The circuit of claim 1 , wherein the first feedback network comprises a first resistor arranged in series with a first current generator between the output node and a ground node, wherein the feedback signal is generated at a node intermediate the first resistor and the first current generator.

7. The circuit of claim 6, wherein the first current generator comprises a variable current generator configured to generate a variable current dependent on a value of a first digital control signal, whereby the feedback signal is shifted dependent on the first digital control signal.

8. The circuit of claim 1 , wherein the second feedback network comprises: a second resistor arranged in series with a second current generator between the input node and a ground node, wherein the threshold signal is generated at a node intermediate the second resistor and the second current generator, and an additional comparator configured to compare the regulated output voltage to the threshold signal, assert the second control signal in response to the threshold signal being above the regulated output voltage, and de-assert the second control signal in response to the threshold signal being below the regulated output voltage.

9. The circuit of claim 8, wherein the second current generator comprises a variable current generator configured to generate a variable current dependent on a value of a second digital control signal, whereby the threshold signal is shifted dependent on the second digital control signal.

10. The circuit of claim 8 , comprising an inverter circuit and a second level shifter circuit, the second level shifter circuit being arranged between the additional comparator and the second transmission element to generate a complement signal of the second control signal, shift the complement signal from a low voltage domain to a high voltage domain, and propagate the shifted complement signal to the second transmission element, wherein the second transmission element is activated in response to the shifted complement signal being asserted, and the second transmission element is deactivated in response to the shifted complement signal being deasserted.

11. A memory device comprising: an array of memory cells arranged in a plurality of bit lines and a plurality of word lines, wherein each memory cell is arranged in series with a corresponding select transistor between a ground terminal and a corresponding said bit line, and each bit line is selectively coupleable to a power supply voltage rail; A voltage regulator circuit comprising: an input node configured to receive an input voltage; an output node coupled to the supply voltage rail to provide a regulated output voltage thereto; a first feedback network configured to generate a feedback signal indicative of the regulated output voltage and to compare the feedback signal with a reference signal to generate a first pulse control signal, wherein the first pulse control signal is asserted in response to the reference signal being higher than the feedback signal and the first pulse control signal is de-asserted in response to the reference signal being lower than the feedback signal, whereby a time average of the first pulse control signal depends on a difference between the reference signal and the feedback signal; a second feedback network configured to generate a threshold signal indicative of the input voltage and compare the regulated output voltage to the threshold signal to generate a second control signal, wherein the second control signal is asserted in response to the threshold signal being above the regulated output voltage and the second control signal is de-asserted in response to the threshold signal being below the regulated output voltage; a charge pump circuit configured to generate a supply voltage higher than the input voltage, wherein the charge pump circuit is enabled in response to the second control signal being de-asserted and is clocked by the first pulse control signal, whereby a value of the supply voltage depends on the first pulse control signal; a first transmission element disposed between the input node and the output node, wherein the first transmission element is enabled in response to the second control signal being asserted, and is selectively activated to connect the input node to the output node in response to the first pulse control signal being asserted; and a second pass element disposed between an output of the charge pump circuit and the output node, wherein the second pass element is selectively activated to connect the output of the charge pump circuit to the output node in response to the second control signal being de-asserted; Wherein the voltage regulator circuit is selectively activated to generate the regulated output voltage in response to the memory device receiving a memory read command.

12. The memory device of claim 11 , wherein the word line is capable of selectively coupling to the output node of the voltage regulator circuit, the memory device being configured to couple one or more unselected word lines to the output node of the voltage regulator circuit during a read operation from a selected word line in the memory device.

13. The memory device of claim 12, wherein: generating a filtered output voltage at the one or more unselected word lines coupled to the output node of the voltage regulator circuit; The first feedback network of the voltage regulator circuit is selectively coupleable to the unselected word lines and is configured to generate the feedback signal indicative of the filtered output voltage; as well as The second feedback network of the voltage regulator circuit is selectively coupleable to the unselected word lines and is configured to compare the filtered output voltage to the threshold signal to generate the second control signal.

14. The memory device of claim 11 , wherein the first feedback network comprises a low voltage clock control comparator configured to compare the feedback signal with the reference signal, assert the first pulse control signal in response to the reference signal being higher than the feedback signal, and de-assert the first pulse control signal in response to the reference signal being lower than the feedback signal.

15. The memory device of claim 14, wherein the low voltage clock controlled comparator comprises: a plurality of dynamic comparators clocked by respective time-shifted clock signals, wherein the respective time-shifted clock signals have a same clock period and one time-shifted clock signal is time-shifted by a portion of the same clock period relative to another time-shifted clock signal, wherein the dynamic comparators of the plurality of dynamic comparators are configured to sequentially compare the feedback signal with the reference signal to assert and de-assert respective output signals in response to the reference signal being respectively above and below the feedback signal; as well as A monostable circuit is configured to receive the output signals from the plurality of dynamic comparators and assert the first pulse control signal in response to assertion of any of the output signals received from the plurality of dynamic comparators. 16 . The memory device of claim 15 , wherein the low voltage clocked comparator comprises a ring oscillator configured to generate the time-shifted clock signal for the plurality of dynamic comparators.

17. The memory device of claim 14, wherein the voltage regulator circuit comprises a first level shifter circuit, the first level shifter circuit being arranged between the low voltage clock control comparator and the first transmission element, the first level shifter circuit being configured to shift the first pulse control signal from a low voltage domain to a high voltage domain, and propagate the shifted first pulse control signal to the first transmission element in response to the second control signal being asserted.

18. The memory device of claim 11, wherein the first feedback network comprises a first resistor arranged in series with a first current generator between the output node and a ground node, wherein the feedback signal is generated at a node intermediate the first resistor and the first current generator.

19. The memory device of claim 18, wherein the first current generator comprises a variable current generator configured to generate a variable current dependent on a value of a first digital control signal, whereby the feedback signal is shifted dependent on the first digital control signal.

20. The memory device of claim 11, wherein the second feedback network comprises: a second resistor arranged in series with a second current generator between the input node and a ground node, wherein the threshold signal is generated at a node intermediate the second resistor and the second current generator, and an additional comparator configured to compare the regulated output voltage to the threshold signal, assert the second control signal in response to the threshold signal being above the regulated output voltage, and de-assert the second control signal in response to the threshold signal being below the regulated output voltage.

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