Quadrant Analog Divider Circuit

Abstract

A four-quadrant analog divider circuit designed by the present invention can achieve the four-quadrant voltage division analog operation function, and includes two n-bit multiplication-type D / A chips, an n-bit counter, two current / voltage conversion circuits, a quadrant judgment circuit, a counter UP hysteresis comparator, a counter DOWN hysteresis comparator, two exclusive-OR gate circuits, a sum and difference detection circuit, and a clock unit; where V_DIVIDEND is the dividend voltage signal, V_DIVISOR is the divisor voltage signal, V_REF is the reference voltage source, V_QUO is the divider output voltage signal, and different range division applications can be achieved by configuring the resistance ratio of R1 and R2 in the error detection circuit. Verified by actual use, the present invention can work stably, has high output accuracy, and has a wide application prospect.

Description

Technical Field

[0001] The present invention specifically relates to the technical field of analog divider circuits, and in particular, to a four-quadrant analog divider circuit. Background Art

[0002] In the control system of an aircraft auxiliary power unit, displacement sensors such as LVDT sensors are widely used in the servo control system of an aircraft engine for measuring mechanical linear displacement or rotational shaft angular displacement, such as fuel flow measurement, inlet guide vane position control, and anti-surge control valve control. The LVDT sensor is an important measurement component, directly affecting whether the fuel control, bleed air, and anti-surge functions of the auxiliary power unit can work properly, and directly affecting the operation and safety of the engine.

[0003] The traditional LVDT sensor conditioning circuit is implemented using a certain imported integrated LVDT conditioning subsystem. This integrated chip can convert the displacement information of the LVDT sensor into a DC voltage signal and participate in the negative feedback loop of the servo control system, forming a dual closed-loop structure of hardware closed-loop + software closed-loop, which can effectively shorten the system response time. Currently, there is no similar chip in China. In view of the requirements for the full domestication of aviation equipment and the dual closed-loop structure of the servo control system, the LVDT sensor signal conditioning circuit mainly includes two parts: 1. The AC voltage signal output from the secondary of the LVDT is rectified by full-wave rectification and filtered by a low-pass filter to become DC voltages VA and VB, and VA + VB and VA - VB are obtained through an addition circuit and a subtraction circuit; 2. An analog division operation is performed on (VA - VB) and (VA + VB) to obtain a DC voltage signal proportional to the displacement magnitude of the LVDT sensor. How to design a high-precision analog division circuit plays an important role in giving full play to the accurate and fast response advantages of the dual closed-loop control system, and is also an important prerequisite for the normal and reliable operation of the dual closed-loop control system. Summary of the Invention

[0004] In view of this, this paper proposes a four-quadrant analog division circuit, which is a negative feedback structure. By adjusting the value of the count in the counter, the change of the output current of the multiplication-type D / A is changed. When the circuit reaches a steady state, the output current of the multiplication-type D / A is the output result of the analog divider. Moreover, the division range can be flexibly configured, and when the circuit reaches a steady state, the output signal will not exhibit phenomena such as jitter.

[0005] The technical solution of the present invention is to provide a four-quadrant analog divider circuit, including: an n-bit multiplication-type D / A chip 1, an n-bit multiplication-type D / A chip 2, an n-bit counter, a current / voltage conversion circuit 1, a current / voltage conversion circuit 2, a quadrant judgment circuit, an error detection circuit, a counter UP hysteresis comparator, a counter DOWN hysteresis comparator, an exclusive-OR gate circuit D1, an exclusive-OR gate circuit D2, and a clock unit.

[0006] The dividend voltage signal V_DIVIDEND is simultaneously connected to the voltage reference input terminal of the n-bit multiplicative D / A chip 1 and the input terminal of the quadrant judgment circuit. The current output terminal of the n-bit multiplicative D / A chip 1 is connected to the input terminal of the current / voltage conversion circuit 1. The output terminal of the current / voltage conversion circuit 1 is connected to one input terminal of the error detection circuit. The divisor voltage signal V_DIVISOR is connected to the other input terminal of the error detection circuit. The output terminal of the error detection circuit is simultaneously connected to the input terminal of the counter UP hysteresis comparator and the input terminal of the counter DOWN hysteresis comparator. The output terminal of the counter UP hysteresis comparator is connected to one input terminal of the exclusive-OR gate circuit D2. The output terminal of the counter DOWN hysteresis comparator is connected to one input terminal of the exclusive-OR gate circuit D1. The output terminal of the quadrant judgment circuit is simultaneously connected to the other input terminals of the exclusive-OR gate circuit D1 and the exclusive-OR gate circuit D2. The output terminal of the exclusive-OR gate circuit D1 is connected to the input terminal of the n-bit counter DOWN. The output terminal of the exclusive-OR gate circuit D2 is connected to the input terminal of the n-bit counter UP. The output terminal of the clock unit is connected to the CLK input terminal of the n-bit counter. The counting output terminals of the n-bit counter are simultaneously connected to the data input terminals of the n-bit multiplicative D / A chip 1 and the data input terminals of the n-bit multiplicative D / A chip 2. The reference voltage source V_REF is connected to the voltage reference input terminal of the n-bit multiplicative D / A chip 2. The output terminal of the n-bit multiplicative D / A chip 2 is connected to the current input terminal of the current / voltage conversion circuit 2. The output terminal of the current / voltage conversion circuit 2 is the output voltage signal of the divider.

[0007] The value range of the count value of the above-mentioned n-bit counter is 0 to 2^n - 1. When the value of the counter is 0, the output voltage value of the current / voltage conversion circuit 1 is -V_DIVIDEND, and the output voltage value of the current / voltage conversion circuit 2 is -V_REF. When the value of the counter is 2^n - 1, the output voltage value of the current / voltage conversion circuit 1 is V_DIVIDEND, and the output voltage value of the current / voltage conversion circuit 2 is V_REF.

[0008] The above-mentioned quadrant judgment circuit is a zero-crossing detection circuit. When the voltage value of the dividend voltage signal V_DIVIDEND is greater than 0, the quadrant judgment circuit outputs a logic high level. When the voltage value of the dividend voltage signal V_DIVIDEND is less than 0, the quadrant judgment circuit outputs a logic low level.

[0009] The above-mentioned counter UP hysteresis comparator includes a resistor R3, a resistor R4, a positive feedback resistor R5, a pull-up resistor R6, and a voltage comparator U1. The output terminal of the error detection circuit is connected to one end of the resistor R4, the other end of the resistor R4 is connected to the inverting input terminal of the voltage comparator U1, one end of the resistor R3 is connected to the reference ground GND, the non-inverting input terminal of the voltage comparator U1 is simultaneously connected to the other end of the resistor R3 and one end of the positive feedback resistor R5, the output terminal of the voltage comparator U1 is simultaneously connected to the other end of the positive feedback resistor R5 and the pull-up resistor R6, and the other end of the pull-up resistor R6 is connected to the power supply VCC.

[0010] The above-mentioned counter DOWN hysteresis comparator includes a resistor R7, a resistor R8, a positive feedback resistor R9, a pull-up resistor R10, and a voltage comparator U2. The output terminal of the error detection circuit is connected to one end of the resistor R7, the non-inverting input terminal of the voltage comparator U2 is simultaneously connected to the other end of the resistor R7 and one end of the positive feedback resistor R9, one end of the resistor R8 is connected to the reference ground GND, the other end of the resistor R8 is connected to the inverting input terminal of the voltage comparator U2, the output terminal of the voltage comparator U2 is simultaneously connected to the other end of the positive feedback resistor R9 and the pull-up resistor R10, and the other end of the pull-up resistor R10 is connected to the power supply VCC.

[0011] The above-mentioned counter UP hysteresis comparator is characterized in that when the output voltage of the error detection circuit varies within the range of [0, VCC·R3 / (R3 + R5 + R6)], the output voltage of the voltage comparator U1 remains unchanged. When the output voltage of the error detection circuit is less than the reference ground GND level, the voltage comparator U1 outputs a logic high level. When the output voltage of the error detection circuit is greater than VCC·R3 / (R3 + R5 + R6), the voltage comparator U1 outputs a logic low level.

[0012] The above-mentioned counter DOWN hysteresis comparator is characterized in that when the output voltage of the error detection circuit varies within the range of [-VCC·R7 / (R9 + R10), 0], the output voltage of the voltage comparator U2 remains unchanged. When the output voltage of the error detection circuit is greater than the reference ground GND level, the voltage comparator U2 outputs a logic high level. When the output voltage of the error detection circuit is less than -VCC·R7 / (R9 + R10), the voltage comparator U2 outputs a logic low level.

[0013] The above-mentioned error detection circuit includes a resistor R1 and a resistor R2. The output terminal of the current / voltage conversion circuit 1 is connected to the resistor R1, the divisor voltage signal V_DIVISOR is connected to one end of the resistor R2, and the output terminal of the error detection circuit is simultaneously connected to the other end of the resistor R1 and the other end of the resistor R2.

[0014] The ratio of the resistor R1 and the resistor R2 in the above-mentioned error detection circuit determines the range of the division operation, and the division operation range is expressed as [-R1 / R2, R1 / R2].

[0015] The above-mentioned n-bit counter needs to comply with the following rules:

[0016] Rule 1: When the UP input terminal of the n-bit counter is at a logic high level, the DOWN input terminal of the n-bit counter is at a logic low level, and a rising edge appears at the CLK input terminal of the n-bit counter, the count value of the n-bit counter is incremented by 1;

[0017] Rule 2: When the UP input terminal of the n-bit counter is at a logic low level, the DOWN input terminal of the n-bit counter is at a logic high level, and a rising edge appears at the CLK input terminal of the n-bit counter, the count value of the n-bit counter is decremented by 1;

[0018] Rule 3: When the logic level states of the UP input terminal and the DOWN input terminal of the n-bit counter are the same, the count value of the n-bit counter remains unchanged.

[0019] The working process of the four-quadrant analog divider circuit of the present invention includes the following steps:

[0020] Step 1: When the level of the dividend voltage signal V_DIVIDEND is greater than 0, the quadrant judgment circuit outputs a logic high level. At this time, as the count value of the n-bit counter increases, the output voltage VOUT1 of the current / voltage conversion circuit 1 will increase; when the level of the dividend voltage signal V_DIVIDEND is less than 0, the quadrant judgment circuit outputs a logic low level. At this time, as the count value of the n-bit counter increases, the output voltage VOUT1 of the current / voltage conversion circuit 1 will decrease;

[0021] Step 2: When the output voltage VOUT1 of the current / voltage conversion circuit 1 > -V_DIVISOR·R1 / R2, the output voltage of the error detection circuit is greater than 0, then the counter UP hysteresis comparator is at a logic low level; the counter DOWN hysteresis comparator outputs a logic high level; when the quadrant judgment circuit outputs a logic high level, the exclusive OR gate D2 outputs a logic low level, the exclusive OR gate D1 outputs a logic high level, and the count value of the n-bit counter will decrease, then the voltage of VOUT1 will decrease until it approaches -V_DIVISOR·R1 / R2; when the quadrant judgment circuit outputs a logic low level, the exclusive OR gate D2 outputs a logic high level, the exclusive OR gate D1 outputs a logic low level, and the count value of the n-bit counter will increase, then the voltage of VOUT1 will decrease until it approaches -V_DIVISOR·R1 / R2;

[0022] Step 3: Similarly, when the output voltage VOUT1 of the current / voltage conversion circuit 1 < -V_DIVISOR·R1 / R2, the quadrant determination circuit, the counter UP hysteresis comparator, and the counter DOWN hysteresis comparator control the count value of the n-bit counter to increase or decrease, and VOUT1 will increase until it approaches -V_DIVISOR·R1 / R2;

[0023] Step 4: The functions of the counter UP hysteresis comparator and the counter DOWN hysteresis comparator are to prevent the value of the n-bit counter from continuously jittering during the process when VOUT1 approaches -V_DIVISOR·R1 / R2;

[0024] Step 5: When the voltage of VOUT1 is equal to -V_DIVISOR·R1 / R2, the output voltage of the error detection circuit is 0. At this time, the count value of the n-bit counter is D and remains unchanged. Then VOUT1 = V_DIVIDEND*(D - 2^n - 1) / 2^n - 1. Furthermore, (D - 2^n - 1) / 2^n - 1 = -(V_DIVISOR / V_DIVIDEND)·(R1 / R2). At this time, the voltage V_QUO at the output end of the current / voltage conversion circuit 2 = -V_REF·(V_DIVISOR / V_DIVIDEND)·(R1 / R2), where V_REF, R1, and R2 are all constants. Then V_QUO is proportional to V_DIVISOR / V_DIVIDEND.

[0025] The four-quadrant analog divider circuit of the present invention has the following beneficial effects:

[0026] In view of the current situation in China where there is no integrated chip for realizing analog division operation function, the present invention realizes a four-quadrant analog divider circuit based on an analog multiplication type D / A and a counter, and realizes the four-quadrant analog division function through components such as a multiplication type D / A chip, a counter, conventional gate circuits, and resistors, capacitors, and voltage comparators. The principle is simple, the accuracy is controllable, and it is easy to use; and it can realize a nationalized design, the division range can be set, and the applicable range is wide. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the following will briefly introduce the drawings required to be used in the embodiments. Obviously, the drawings described below are only some embodiments of the present disclosure. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on these drawings.

[0028] Figure 1 It is a functional principle block diagram of a four-quadrant analog divider circuit of the present invention;

[0029] Figure 2Schematic diagram of the counter UP hysteresis comparator circuit;

[0030] Figure 3 Schematic diagram of the counter DOWN hysteresis comparator circuit. Specific implementation mode

[0031] The following describes the embodiments of the present disclosure in detail with reference to the accompanying drawings.

[0032] The following illustrates the implementation mode of the present disclosure through specific specific examples. Those skilled in the art can easily understand other advantages and effects of the present disclosure from the content disclosed in this specification. Obviously, the described embodiments are only a part of the embodiments of the present disclosure, rather than all the embodiments. The present disclosure can also be implemented or applied through other different specific implementation modes. The details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present disclosure. It should be noted that, without conflict, the following embodiments and the features in the embodiments can be combined with each other. All other embodiments obtained by those of ordinary skill in the art based on the embodiments in the present disclosure without creative efforts belong to the scope of protection of the present disclosure.

[0033] It should be noted that the following describes various aspects of the embodiments within the scope of the appended claims. It should be obvious that the aspects described herein can be embodied in a wide variety of forms, and any specific structure and / or function described herein is illustrative only. Based on the present disclosure, those skilled in the art should understand that one aspect described herein can be implemented independently of any other aspect, and two or more of these aspects can be combined in various ways. For example, any number of aspects described herein can be used to implement the device and / or practice the method. In addition, this device and / or this method can be implemented using other structures and / or functions in addition to one or more of the aspects described herein.

[0034] It should also be noted that the diagrams provided in the following embodiments only illustrate the basic concept of the present disclosure in a schematic manner. The diagrams only show the components related to the present disclosure and are not drawn according to the number, shape, and size of the components in actual implementation. The type, quantity, and ratio of each component in its actual implementation can be an arbitrary change, and the component layout type may also be more complex.

[0035] In addition, in the following description, specific details are provided to facilitate a thorough understanding of the examples. However, those skilled in the art will understand that the described aspects can be practiced without these specific details.

[0036] The present invention will be further described below in conjunction with the accompanying drawings and embodiments. The background is as follows: For a certain type of auxiliary power unit inlet guide vane control servo system, a five-wire LVDT sensor is used to collect the inlet guide vane displacement information. The ratio range of this five-wire LVDT sensor is -1 to +1. After conditioning, the dividend voltage range is 3.4V to 3.6V. Now it is necessary to implement analog division operation to output a DC voltage signal that changes proportionally to the ratio of the LVDT sensor. When the ratio of the LVDT sensor is 1, the output voltage is -5V, and when the ratio of the LVDT sensor is -1, the output voltage is +5V.

[0037] Please also refer to Figure 1 , Figure 2 and Figure 3 , where Figure 1 is the functional principle block diagram of a four-quadrant analog divider circuit of the present invention; Figure 2 is the schematic diagram of the counter UP hysteresis comparator circuit; Figure 3 is the schematic diagram of the counter DOWN hysteresis comparator circuit, including:

[0038] A 12-bit multiplicative D / A chip 1, a 12-bit multiplicative D / A chip 2, a 12-bit counter, a current / voltage conversion circuit 1, a current / voltage conversion circuit 2, a quadrant judgment circuit, an error detection circuit, a counter UP hysteresis comparator, a counter DOWN hysteresis comparator, an exclusive-OR gate circuit D1, an exclusive-OR gate circuit D2, and a clock unit. The dividend voltage signal V_DIVIDEND is simultaneously connected to the voltage reference input terminal of the 12-bit multiplicative D / A chip 1 and the input terminal of the quadrant judgment circuit. The current output terminal of the 12-bit multiplicative D / A chip 1 is connected to the input terminal of the current / voltage conversion circuit 1. The output terminal of the current / voltage conversion circuit 1 is connected to one input terminal of the error detection circuit. The divisor voltage signal V_DIVISOR is connected to the other input terminal of the error detection circuit. The output terminal of the error detection circuit is simultaneously connected to the input terminals of the counter UP hysteresis comparator and the counter DOWN hysteresis comparator. The output terminal of the counter UP hysteresis comparator is connected to one input terminal of the exclusive-OR gate circuit D2. The output terminal of the counter DOWN hysteresis comparator is connected to one input terminal of the exclusive-OR gate circuit D1. The output terminal of the quadrant judgment circuit is simultaneously connected to the other input terminals of the exclusive-OR gate circuit D1 and the exclusive-OR gate circuit D2. The output terminal of the exclusive-OR gate circuit D1 is connected to the DOWN input terminal of the 12-bit counter. The output terminal of the exclusive-OR gate circuit D2 is connected to the UP input terminal of the 12-bit counter. The output terminal of the clock unit is connected to the CLK input terminal of the 12-bit counter. The counting output terminal of the 12-bit counter is simultaneously connected to the data input terminals of the 12-bit multiplicative D / A chip 1 and the n-bit multiplicative D / A chip 2.

[0039] The reference voltage source V_REF is connected to the voltage reference input terminal of the 12-bit multiplicative D / A chip 2. The output terminal of the 12-bit multiplicative D / A chip 2 is connected to the current input terminal of the current / voltage conversion circuit 2. The output terminal of the current / voltage conversion circuit 2 is the output voltage signal of the divider. In this embodiment, the multiplicative D / A conversion chip selects the AD7547 of AD Company. This chip integrates two 12-bit multiplicative D / As internally, which can be used for Figure 1 the 12-bit multiplicative D / A chip 1 and the 12-bit multiplicative D / A chip 2 in Figure 1 respectively. The DA output establishment time of the AD7547 does not exceed 1.5 us. The clock frequency output by the clock unit is 500 KHz.

[0040] As a specific implementation manner provided in this case, the counting value range of the 12-bit counter changes from 0 to 4095. When the value of the counter is 0, the output voltage value of the current / voltage conversion circuit 1 is -V_DIVIDEND, and the output voltage value of the current / voltage conversion circuit 2 is -V_REF. When the value of the counter is 4095, the output voltage value of the current / voltage conversion circuit 1 is V_DIVIDEND, and the output voltage value of the current / voltage conversion circuit 2 is V_REF. The relationship between the output voltage value VOUT1 of the current / voltage conversion circuit 1 and the counting value D is: VOUT1 = (D - 2048) / 2048 * V_DIVIDEND. The relationship between the output voltage value V_QUO of the current / voltage conversion circuit 2 and the counting value D is: V_QUO = (D - 2048) / 2048 * V_REF. Then the maximum value of the voltage change of the current / voltage conversion circuit 1 corresponding to 1 LSB of the counter is ΔU = 1 / 2048 * 3.6 V = 1.75 mV.

[0041] The dividend voltage signal cannot be 0. Therefore, the above quadrant judgment circuit is a zero-crossing detection circuit. When the voltage value of the dividend voltage signal V_DIVIDEND is greater than 0, the quadrant judgment circuit outputs a logic high level. When the voltage value of the dividend voltage signal V_DIVIDEND is less than 0, the quadrant judgment circuit outputs a logic low level. In this embodiment, the range of the dividend voltage signal V_DIVIDEND is 3.4 to 3.6, which is often greater than 0. Therefore, this four-quadrant division circuit operates in the 1st and 4th quadrants, and the quadrant detection circuit often outputs a logic high level.

[0042] As a specific implementation manner provided in this case, the schematic diagram of the counter UP hysteresis comparator circuit is as Figure 2As shown in the figure, it includes resistor R3, resistor R4, positive feedback resistor R5, pull-up resistor R6 and voltage comparator U1. The output terminal of the error detection circuit is connected to one end of resistor R4, the other end of resistor R4 is connected to the inverting input terminal of voltage comparator U1, one end of resistor R3 is connected to the reference ground GND, the non-inverting input terminal of voltage comparator U1 is simultaneously connected to the other end of resistor R3 and one end of positive feedback resistor R5, the output terminal of voltage comparator U1 is simultaneously connected to the other end of positive feedback resistor R5 and pull-up resistor R6, and the other end of pull-up resistor R6 is connected to the power supply VCC. According to the working characteristics of voltage comparator U1, it can be theoretically calculated that when the input voltage of this circuit varies within the range of [0, VCC·R3 / (R3 + R5 + R6)], the output voltage of voltage comparator U1 remains unchanged. When the input voltage is lower than the reference ground GND level, the output of voltage comparator U1 is a logic low level. When the input voltage is greater than VCC·R3 / (R3 + R5 + R6), the output of voltage comparator U1 is a logic high level. To ensure that the counter does not continuously jump and ensure the maximum output accuracy when this circuit reaches a steady state, then ΔU < VCC·R3 / (R3 + R5 + R6) < 2·ΔU. In this embodiment, the VCC voltage is +5VDC, so R3 = 499Ω, R5 = 1MΩ, R6 = 2KΩ are selected, then VCC·R3 / (R3 + R5 + R6) = 2.49mV, which meets the requirement of 1.75mV < VCC·R3 / (R3 + R5 + R6) < 3.5mV.

[0043] As a specific implementation manner provided in this case, the schematic diagram of the counter DOWN hysteresis comparator circuit is as Figure 3 shown, including resistor R7, resistor R8, positive feedback resistor R9, pull-up resistor R10 and voltage comparator U2. The output terminal of the error detection circuit is connected to one end of resistor R7, the non-inverting input terminal of voltage comparator U2 is simultaneously connected to the other end of resistor R7 and one end of positive feedback resistor R9, one end of resistor R8 is connected to the reference ground GND, the other end of resistor R8 is connected to the inverting input terminal of voltage comparator U2, the output terminal of voltage comparator U2 is simultaneously connected to the other end of positive feedback resistor R9 and pull-up resistor R10, and the other end of pull-up resistor R10 is connected to the power supply VCC. According to the working characteristics of voltage comparator U2, it can be theoretically calculated that when the input voltage varies within the range of [-VCC·R7 / (R9 + R10), 0], the output voltage of voltage comparator U2 remains unchanged, where:

[0044] When the output voltage of the error detection circuit is greater than the reference ground GND level, the output of voltage comparator U2 is a logic high level;

[0045] When the output voltage of the error detection circuit is less than -VCC·R7 / (R9+R10), the voltage comparator U2 outputs a logic low level. To ensure that the counter does not continuously jump and ensure the maximum output accuracy when the circuit reaches a steady state, then ΔU < VCC·R7 / (R9+R10) < 2·ΔU. In this embodiment, R7 = 499Ω, R9 = 1MΩ, R10 = 2kΩ, then VCC·R7 / (R9+R10) = 2.49mV, meeting the requirement of 1.75mV < VCC·R7 / (R9+R10) < 3.5mV.

[0046] As a specific implementation provided in this case, the error detection circuit includes resistor R1 and resistor R2. The output end of the current / voltage conversion circuit 1 is connected to resistor R1, the divisor voltage signal V_DIVISOR is connected to one end of resistor R2, and the output end of the error detection circuit is simultaneously connected to the other end of resistor R1 and the other end of resistor R2. According to the requirements, the division range to be achieved in this example is [-1, +1], then R1 = R2 = 1kΩ.

[0047] The 12-bit counter needs to follow the following counting rules:

[0048] Rule 1: When the logic of the UP input terminal of the 12-bit counter is high and the logic of the DOWN input terminal of the n-bit counter is low, and a rising edge appears at the CLK input terminal of the 12-bit counter, the count value of the 12-bit counter is incremented by 1;

[0049] Rule 2: When the logic of the UP input terminal of the 12-bit counter is low and the logic of the DOWN input terminal of the 12-bit counter is high, and a rising edge appears at the CLK input terminal of the n-bit counter, the count value of the 12-bit counter is decremented by 1;

[0050] Rule 3: When the logic level states of the UP input terminal and the DOWN input terminal of the 12-bit counter are the same, the count value of the 12-bit counter remains unchanged.

[0051] The functions of the exclusive-OR gates D1 and D2 in this embodiment are to ensure that the divider circuit is always in a negative feedback mode. When the dividend voltage is positive, if the VOUT1 voltage is large, the count value is decreased to reduce VOUT1; when the dividend voltage is negative, if the VOUT1 voltage is large, the count value is increased to reduce VOUT1.

[0052] The working process of the four-quadrant analog divider circuit of the present invention includes the following steps:

[0053] Step 1: In this embodiment, the dividend voltage signal V_DIVIDEND is usually greater than 0, and the quadrant judgment circuit outputs a logic high level. At this time, as the count value of the 12-bit counter increases, the output voltage VOUT1 of the current / voltage conversion circuit 1 will increase; as the count value of the 12-bit counter decreases, the output voltage VOUT1 of the current / voltage conversion circuit 1 will decrease.

[0054] Step 2: When the output voltage VOUT1 of the current / voltage conversion circuit 1 > -V_DIVISOR + 2.49mV, the output voltage of the error detection circuit is greater than 0. Then the counter UP hysteresis comparator outputs a logic low level, the counter DOWN hysteresis comparator outputs a logic high level, the exclusive-OR gate D2 outputs a logic low level, and the exclusive-OR gate D1 outputs a logic high level. As the count value of the n-bit counter gradually decreases with the rising edge of the clock, the voltage of VOUT1 will also decrease until VOUT1 < -V_DIVISOR. Then the counter UP hysteresis comparator outputs a logic high level, the exclusive-OR gate D1 outputs a logic high level. According to the rule of the 12-bit counter, the count value remains unchanged at this time.

[0055] Step 3: Similarly, when the output voltage VOUT1 of the current / voltage conversion circuit 1 < -V_DIVISOR - 2.49mV, the count value of the 12-bit counter will gradually increase, VOUT1 will increase until VOUT1 > -V_DIVISOR. Then the counter UP hysteresis comparator outputs a logic low level, the exclusive-OR gate D1 outputs a logic low level. According to the rule of the 12-bit counter, the count value remains unchanged at this time.

[0056] The functions of the counter UP hysteresis comparator and the counter DOWN hysteresis comparator are to prevent the value of the n-bit counter from continuously jittering during the process when VOUT1 approaches -V_DIVISOR.

[0057] Step 5: When the count value D of the 12-bit counter remains unchanged, the output voltage of the error detection circuit is approximately 0, and it can be considered that VOUT1 = -V_DIVISOR. At this moment, VOUT1 also satisfies:

[0058] VOUT1 = V_DIVIDEND * (D - 2048) / 2048, (D - 2048) / 2048 = -(V_DIVISOR / V_DIVIDEND). Then the output voltage of the current / voltage conversion circuit 2 is:

[0059] V_QUO = -V_REF · (V_DIVISOR / V_DIVIDEND);

[0060] In this embodiment, V_REF is a +5V precision voltage reference, then

[0061] V_QUO = -5·(V_DIVISOR / V_DIVIDEND). When the LVDT ratio is -1, V_QUO = 5V; when the LVDT ratio is 1, V_QUO = -5V.

[0062] As described above, it is only the specific implementation manner of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any changes or substitutions that can be easily thought of by those skilled in the art within the technical scope disclosed by the present disclosure should be covered by the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be subject to the protection scope of the claims.

Claims

1. A four-quadrant analog divider circuit, characterized in that It includes an n-bit multiplicative D / A chip 1, an n-bit multiplicative D / A chip 2, an n-bit counter, a current / voltage conversion circuit 1, a current / voltage conversion circuit 2, a quadrant determination circuit, an error detection circuit, a counter UP hysteresis comparator, a counter DOWN hysteresis comparator, an exclusive-OR gate circuit D1, an exclusive-OR gate circuit D2, and a clock unit, where: The dividend voltage signal V_DIVIDEND is simultaneously connected to the voltage reference input terminal of the n-bit multiplicative D / A chip 1 and the input terminal of the quadrant determination circuit, and the current output terminal of the n-bit multiplicative D / A chip 1 is connected to the input terminal of the current / voltage conversion circuit 1; The output terminal of the current / voltage conversion circuit 1 is connected to one input terminal of the error detection circuit, the divisor voltage signal V_DIVISOR is connected to the other input terminal of the error detection circuit, the output terminal of the error detection circuit is simultaneously connected to the input terminal of the counter UP hysteresis comparator and the input terminal of the counter DOWN hysteresis comparator, the output terminal of the counter UP hysteresis comparator is connected to one input terminal of the exclusive-OR gate circuit D2, the output terminal of the counter DOWN hysteresis comparator is connected to one input terminal of the exclusive-OR gate circuit D1, the output terminal of the quadrant determination circuit is simultaneously connected to the other input terminals of the exclusive-OR gate circuit D1 and the exclusive-OR gate circuit D2, the output terminal of the exclusive-OR gate circuit D1 is connected to the DOWN input terminal of the n-bit counter, the output terminal of the exclusive-OR gate circuit D2 is connected to the UP input terminal of the n-bit counter, and the output terminal of the clock unit is connected to the CLK input terminal of the n-bit counter; The counting output terminal of the n-bit counter is simultaneously connected to the data input terminal of the n-bit multiplicative D / A chip 1 and the data input terminal of the n-bit multiplicative D / A chip 2, the reference voltage source V_REF is connected to the voltage reference input terminal of the n-bit multiplicative D / A chip 2, the output terminal of the n-bit multiplicative D / A chip 2 is connected to the current input terminal of the current / voltage conversion circuit 2, and the output terminal of the current / voltage conversion circuit 2 is the output voltage signal of the divider.

2. The four-quadrant analog divider circuit according to claim 1, wherein The value range of the count value of the n-bit counter is 0 - (2n - 1), where: When the value of the n-bit counter is 0, the output voltage value of the current / voltage conversion circuit 1 is -V_DIVIDEND, and the output voltage value of the current / voltage conversion circuit 2 is -V_REF; When the value of the n-bit counter is 2n - 1, the output voltage value of the current / voltage conversion circuit 1 is V_DIVIDEND, and the output voltage value of the current / voltage conversion circuit 2 is V_REF.

3. The four-quadrant analog divider circuit according to claim 2, wherein The quadrant determination circuit is a zero-crossing detection circuit, where: When the voltage value of the dividend voltage signal V_DIVIDEND is greater than 0, the quadrant determination circuit outputs a logic high level; When the voltage value of the dividend voltage signal V_DIVIDEND is less than 0, the quadrant determination circuit outputs a logic low level.

4. The four-quadrant analog divider circuit according to claim 3, wherein The counter UP hysteresis comparator includes a resistor R3, a resistor R4, a positive feedback resistor R5, a pull-up resistor R6, and a voltage comparator U1, where: The output terminal of the error detection circuit is connected to one end of the resistor R4, the other end of the resistor R4 is connected to the inverting input terminal of the voltage comparator U1, one end of the resistor R3 is connected to the reference ground GND, the non-inverting input terminal of the voltage comparator U1 is simultaneously connected to the other end of the resistor R3 and one end of the positive feedback resistor R5, the output terminal of the voltage comparator U1 is simultaneously connected to the other end of the positive feedback resistor R5 and the pull-up resistor R6, and the other end of the pull-up resistor R6 is connected to the power supply VCC.

5. The four-quadrant analog divider circuit according to claim 4, characterized in that, The counter DOWN hysteresis comparator includes a resistor R7, a resistor R8, a positive feedback resistor R9, a pull-up resistor R10, and a voltage comparator U2, where: The output terminal of the error detection circuit is connected to one end of the resistor R7, the non-inverting input terminal of the voltage comparator U2 is simultaneously connected to the other end of the resistor R7 and one end of the positive feedback resistor R9, one end of the resistor R8 is connected to the reference ground GND, the other end of the resistor R8 is connected to the inverting input terminal of the voltage comparator U2, the output terminal of the voltage comparator U2 is simultaneously connected to the other end of the positive feedback resistor R9 and the pull-up resistor R10, and the other end of the pull-up resistor R10 is connected to the power supply VCC; When the output voltage of the error detection circuit varies within the range of [0, VCC·R3 / (R3 + R5 + R6)], the output voltage of the voltage comparator U1 remains unchanged; When the output voltage of the error detection circuit is lower than the reference ground GND level, the voltage comparator U1 outputs a logic high level. When the output voltage of the error detection circuit is higher than VCC·R3 / (R3 + R5 + R6), the voltage comparator U1 outputs a logic low level.

6. The four-quadrant analog divider circuit according to claim 5, characterized in that, The counter DOWN hysteresis comparator is used such that when the output voltage of the error detection circuit varies within the range of [-VCC·R7 / (R9 + R10), 0], the output voltage of the voltage comparator U2 remains unchanged; When the output voltage of the error detection circuit is higher than the reference ground GND level, the voltage comparator U2 outputs a logic high level; When the output voltage of the error detection circuit is lower than -VCC·R7 / (R9 + R10), the voltage comparator U2 outputs a logic low level.

7. The four-quadrant analog divider circuit according to claim 6, characterized in that, The error detection circuit includes a resistor R1 and a resistor R2, where: The output terminal of the current / voltage conversion circuit 1 is connected to the resistor R1, the divisor voltage signal V_DIVISOR is connected to one end of the resistor R2, and the output terminal of the error detection circuit is simultaneously connected to the other end of the resistor R1 and the other end of the resistor R2; The ratio of the resistor R1 and the resistor R2 in the error detection circuit determines the range for implementing the division operation, and the division operation range is expressed as [-R1 / R2, R1 / R2].

8. The four-quadrant analog divider circuit according to claim 1, wherein The count value of the n-bit counter satisfies: Rule 1: When the UP input terminal of the n-bit counter is at a logic high level and the DOWN input terminal of the n-bit counter is at a logic low level, and a rising edge appears at the CLK input terminal of the n-bit counter, the count value of the n-bit counter is incremented by 1; Rule 2: When the UP input terminal of the n-bit counter is at a logic low level and the DOWN input terminal of the n-bit counter is at a logic high level, and a rising edge appears at the CLK input terminal of the n-bit counter, the count value of the n-bit counter is decremented by 1; Rule 3: When the logic level states of the UP input terminal and the DOWN input terminal of the n-bit counter are the same, the count value of the n-bit counter remains unchanged.

9. The four-quadrant analog divider circuit according to claim 1, characterized in that, It includes the following control steps: Step 1: When the level of the dividend voltage signal V_DIVIDEND is greater than 0, the quadrant determination circuit outputs a logic high level. As the count value of the n-bit counter increases, the output voltage VOUT1 of the current / voltage conversion circuit 1 will increase; when the level of the dividend voltage signal V_DIVIDEND is less than 0, the quadrant determination circuit outputs a logic low level. As the count value of the n-bit counter increases, the output voltage VOUT1 of the current / voltage conversion circuit 1 will decrease; Step 2: When the output voltage VOUT1 of the current / voltage conversion circuit 1 > -V_DIVISOR·R1 / R2, the output voltage of the error detection circuit is greater than 0, then the counter UP hysteresis comparator outputs a logic low level; the counter DOWN hysteresis comparator outputs a logic high level; When the quadrant determination circuit outputs a logic high level, the UP input terminal of the n-bit counter is at a logic low level, the DOWN input terminal of the n-bit counter is at a logic high level, the count value of the n-bit counter will gradually decrease, and then the voltage of VOUT1 will decrease until it is less than -V_DIVISOR·R1 / R2; When the quadrant determination circuit outputs a logic low level, the UP input terminal of the n-bit counter is at a logic high level, the DOWN input terminal of the n-bit counter is at a logic low level, the count value of the n-bit counter will increase, and then the voltage of VOUT1 will decrease until it is less than -V_DIVISOR·R1 / R2; Step 3: Similarly, when the output voltage VOUT1 of the current / voltage conversion circuit 1 < -V_DIVISOR·R1 / R2, the count value of the n-bit counter is controlled to increase or decrease through the quadrant determination circuit, the counter UP hysteresis comparator and the counter DOWN hysteresis comparator, and VOUT1 will increase until it is greater than -V_DIVISOR·R1 / R2; Step 4: The functions of the counter UP hysteresis comparator and the counter DOWN hysteresis comparator are to prevent the value of the n-bit counter from continuously jittering during the process when VOUT1 approaches -V_DIVISOR·R1 / R2; Step 5: When the voltage of VOUT1 is equal to -V_DIVISOR·R1 / R2, the output voltage of the error detection circuit is 0, and the count value of the n-bit counter remains unchanged at D. Then VOUT1 = V_DIVIDEND*(D - 2^n - 1) / (2^n - 1). Furthermore, (D - 2^n - 1) / (2^n - 1) = -(V_DIVISOR / V_DIVIDEND)·(R1 / R2). At this time, the voltage V_QUO at the output end of the current / voltage conversion circuit 2 is V_QUO = -V_REF·(V_DIVISOR / V_DIVIDEND)·(R1 / R2). Since V_REF, R1, and R2 are all constants, V_QUO is proportional to V_DIVISOR / V_DIVIDEND.

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