A method and apparatus for verifying cache coherency of a multi-core processor system

Abstract

Embodiments of the present application disclose a cache coherency verification method and device of a multi-core processor system, and relate to the technical field of multi-core processor function verification, and are invented to improve the cache coherency verification efficiency of the multi-core processor system. The method comprises the following steps: monitoring a first request received or sent by a first cache of a first processor core; monitoring first response information of the first request; determining a state of a first cache line from a preset correspondence between memory addresses and cache line states; predicting the state of the first cache line based on the state of the first cache line, a command type and a preset state transition rule based on a cache coherency protocol; the preset state transition rule based on the cache coherency protocol is consistent with a cache coherency state transition rule used in the multi-core processor system; comparing the current state of the cache line with the predicted state to determine whether the first cache is consistent with the cache coherency. The present application verifies the cache coherency of the multi-core processor.

Description

Technical Field

[0001] This application relates to the field of multi-core processor functional verification technology, and in particular to a method, apparatus, electronic device and readable storage medium for verifying cache coherency of a multi-core processor system. Background Technology

[0002] Computer physical memory typically uses DRAM (Dynamic Random Access Memory), which is generally inexpensive but also relatively slow. The processing speed of the central processing unit (CPU) is limited by the access speed of the computer's physical memory. To improve access speed, cache (high-speed cache memory) is introduced between the two as a bridge for communication.

[0003] Multi-core processors' cache and storage systems interact using fixed-size data blocks called cachelines. A cacheline stores the data cached in memory and records the current state of that data.

[0004] Multi-core processors manage the state of the cacheline through cache coherency protocols to avoid data loss or data inconsistency issues. Cache coherency is a crucial characteristic of on-chip multi-core processor memory systems; it defines the correctness of the results of parallel program execution and defines the relationships between memory access operations in a multi-core processor.

[0005] Cache coherence verification is an important part of on-chip multi-core processor functional verification. However, in the existing technology, there is no relevant scheme for verifying cache coherence, resulting in low verification efficiency of cache coherence in multi-core processor systems. Summary of the Invention

[0006] In view of this, embodiments of this application provide a method, apparatus, electronic device, and readable storage medium for verifying cache coherence in a multi-core processor system, which can improve the verification efficiency of cache coherence in a multi-core processor system.

[0007] In a first aspect, embodiments of this application provide a method for verifying cache coherence in a multi-core processor system. The multi-core processor system includes two or more processor cores, each processor core having a first-level cache and a second-level cache, and all processor cores sharing a third-level cache. The method for verifying cache coherence includes: monitoring a first request received or sent by a first cache of a first processor core; wherein the first request includes the memory address of the data to be operated on by the first request and the command type; monitoring first response information in response to the first request; wherein the first response information includes the current state of a first cache line in the first cache; the first cache line is the cache line containing the data to be operated on by the first request; determining the state of the first cache line based on the memory address from a preset correspondence between memory addresses and cache line states; predicting the state of the first cache line based on the state of the first cache line, the command type, and a preset state transition rule based on a cache coherence protocol, to obtain a predicted state of the first cache line; the preset state transition rule based on the cache coherence protocol is consistent with the cache coherence state transition rule used in the multi-core processor system; and comparing the current state of the cache line with the predicted state to determine whether the first cache conforms to cache coherence.

[0008] According to a specific implementation of an embodiment of this application, the monitoring of the first request received or sent by the first cache of the first processor core includes: monitoring the fetch request, probe request and / or eviction request received or sent by the first cache of the first processor core.

[0009] According to a specific implementation of an embodiment of this application, the first cache is a second-level cache; the monitoring of the first request received or sent by the first cache of the first processor core includes: monitoring the requests between the second-level cache of the first processor core and the access instruction unit, the first-level data cache, or the third-level cache.

[0010] According to a specific implementation of this application, the preset correspondence between memory addresses and cache line states includes: multiple preset correspondences between memory addresses and cache line states; each preset correspondence between memory addresses and cache line states corresponds one-to-one with each processor core; after monitoring the first request received or sent by the first cache of the first processor core, before determining the state of the first cache line from the preset correspondence between memory addresses and cache line states based on the memory address, the method further includes: marking the first request so that the marked first request includes first processor core information; determining the first preset correspondence between memory addresses and cache line states corresponding to the first processor core from the multiple preset correspondences between memory addresses and cache line states based on the first processor core information included in the marked first request; determining the state of the first cache line from the preset correspondence between memory addresses and cache line states based on the memory address includes: determining the state of the first cache line from the first preset correspondence between memory addresses and cache line states based on the memory address.

[0011] According to a specific implementation of an embodiment of this application, the method further includes: when the current state of the cache line is consistent with the predicted state, using the memory address and the current state of the cache line, updating the preset correspondence between the memory address and the cache line state information.

[0012] Secondly, embodiments of this application provide a cache consistency verification device for a multi-core processor system, characterized in that the multi-core processor system includes two or more processor cores, each processor core having its own first-level cache and second-level cache, and all processor cores sharing a third-level cache; wherein the cache consistency verification device includes: a first monitoring module, used to monitor a first request received or sent by the first cache of the first processor core; wherein the first request includes the memory address of the data to be operated on by the first request and the command type; a second monitoring module, used to monitor first response information in response to the first request; wherein the first response information includes the current state of a first cache line in the first cache; the first... The cache line is the cache line containing the data to be operated on by the first request; a first determining module is used to determine the state of the first cache line based on the memory address and from a preset correspondence between memory addresses and cache line states; a prediction module is used to predict the state of the first cache line based on the state of the first cache line, the command type, and a preset state transition rule based on a cache consistency protocol, to obtain the predicted state of the first cache line; the preset state transition rule based on a cache consistency protocol is consistent with the cache consistency state transition rule used in the multi-core processor system; a second determining module is used to compare the current state of the cache line with the predicted state to determine whether the first cache line meets cache consistency requirements.

[0013] According to a specific implementation of an embodiment of this application, the first monitoring module is specifically used to: monitor the fetch requests, probe requests and / or eviction requests received or sent by the first cache of the first processor core.

[0014] According to a specific implementation of an embodiment of this application, the first cache is a second-level cache; the first monitoring module is specifically used to: monitor requests between the second-level cache of the first processor core and the access instruction unit, the first-level data cache, or the third-level cache.

[0015] According to a specific implementation of an embodiment of this application, the preset correspondence between memory addresses and cache line states includes: multiple preset correspondences between memory addresses and cache line states; each preset correspondence between memory addresses and cache line states corresponds one-to-one with each processor core; the device further includes: a marking module, used to mark the first request after the first monitoring module monitors the first cache receiving or sending a first request of the first processor core, and before the first determining module determines the state of the first cache line based on the memory address from the preset correspondence between memory addresses and cache line states, so that the marked first request includes first processor core information; a third determining module, used to determine, based on the first processor core information included in the marked first request, a first preset correspondence between memory addresses and cache line states corresponding to the first processor core from multiple preset correspondences between memory addresses and cache line states; the first determining module is specifically used to: determine the state of the first cache line based on the memory address from the first preset correspondence between memory addresses and cache line states.

[0016] According to a specific implementation of an embodiment of this application, the apparatus further includes: an update module, configured to update a preset correspondence between memory addresses and cache line status information using the memory address and the current state of the cache line when the current state of the cache line is consistent with the predicted state.

[0017] Thirdly, embodiments of this application provide an electronic device, which includes: a housing, a processor, a memory, a circuit board, and a power supply circuit, wherein the circuit board is disposed inside the space enclosed by the housing, and the processor and the memory are disposed on the circuit board; the power supply circuit is used to supply power to various circuits or devices of the above-mentioned electronic device; the memory is used to store executable program code; the processor runs a program corresponding to the executable program code by reading the executable program code stored in the memory, for executing the cache coherence verification method of the multi-core processor system described in any of the foregoing implementations.

[0018] Fourthly, embodiments of this application provide a computer-readable storage medium storing one or more programs, which can be executed by one or more processors to implement the cache consistency verification method for a multi-core processor system as described in any of the foregoing implementations.

[0019] This embodiment of the cache coherence verification method, apparatus, electronic device, and readable storage medium for a multi-core processor system monitors a first request received or sent by the first cache of the first processor core and a first response information to the first request. Based on the memory address in the first request, the state of the first cache line is determined from a preset correspondence between memory addresses and cache line states. Then, based on the state of the first cache line in the first response information, the command type in the first request, and a preset state transition rule based on the cache coherence protocol, the state of the first cache line is predicted to obtain the predicted state of the first cache line. Finally, the current state of the cache line is compared with the predicted state to determine whether the first cache conforms to cache coherence. Since the predicted state of the first cache line is predicted based on the state of the first cache line, the command type, and the preset state transition rule based on the cache coherence protocol, and the preset state transition rule based on the cache coherence protocol is consistent with the cache coherence state transition rule used in the multi-core processor system, the predicted state of the first cache line can be considered as the current standard state of the cacheline. By comparing the current state of the cacheline in the first response information with the predicted state, it can be determined whether the first cache conforms to cache coherence, thereby improving the cache coherence verification efficiency of the multi-core processor system. Attached Figure Description

[0020] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0021] Figure 1 This is a schematic diagram of the structure of a multi-core processor system according to an embodiment of this application;

[0022] Figure 2 This is a schematic diagram of the signal channels between a single processor core and various levels of cache in a specific embodiment of this application;

[0023] Figure 3 A flowchart illustrating a method for verifying cache coherency in a multi-core processor system according to an embodiment of this application;

[0024] Figure 4 A cache coherence transition diagram based on the MOESI protocol is provided as an embodiment of this application;

[0025] Figure 5 This is a schematic diagram illustrating the relationship between the data stored in the first-level cache and the second-level cache in one embodiment of this application;

[0026] Figure 6 This is an architectural diagram of a specific embodiment of this application;

[0027] Figure 7 This application provides a cache consistency verification device according to a specific embodiment.

[0028] Figure 8 This is a schematic diagram of an embodiment of this application;

[0029] Figure 9 A schematic diagram of the structure of a cache coherence verification device for a multi-core processor system provided in an embodiment of this application;

[0030] Figure 10 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application. Detailed Implementation

[0031] The embodiments of this application will now be described in detail with reference to the accompanying drawings. It should be understood that the described embodiments are merely some, not all, of the embodiments of this application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application.

[0032] As mentioned in the background section, to improve the access speed of multi-core processors, a cache is placed between the multi-core processor and the memory system. While cache access is fast, it is also expensive. Limited by processor cost, power consumption, and area, the cache capacity used by the processor is very small. Based on the temporal and spatial locality of memory, if data is accessed now, it is very likely to be accessed again later, and its surrounding data is also likely to be accessed later. The computer places the relevant areas accessed by the CPU into the cache. When the CPU accesses main memory, it first checks the cache; if the data is not found there, it then accesses main memory. This greatly improves the computer's processing speed.

[0033] See Figure 1 and Figure 2 Multi-core processors typically employ a three-level cache architecture. Each core has its own private L1 cache and L2 cache, while the cores share the L3 cache. The L1 cache is further divided into instruction cache and data cache. When the kernel needs to access a program or data, it first checks the L1 cache. If the data is not found in the L1 cache, it checks the L2 cache. If the data is not found in the L2 cache, it checks the L3 cache. If the data is not found in the L3 cache, it checks main memory.

[0034] The cache and storage system interact using fixed-size data blocks called cachelines. A cacheline stores data cached in memory, and records whether the data is currently valid, has been modified, and the address of the corresponding memory block.

[0035] The processor first fetches instructions from the L1 instruction cache using the Instruction Fetch (I-Fetch) unit and stores them in the instruction register. Then, the instruction is decoded, and the source operands are obtained from the register file based on the decoded values. After the Execution Unit (EX) generates valid addresses for load / store operations, the Load Store and Data Cache (LSDC) unit is responsible for completing all memory accesses within the core.

[0036] Multi-core processors typically manage the cacheline state through cache coherency protocols to avoid data loss or data inconsistency issues. Cache coherency is a crucial characteristic of on-chip multi-core processor memory systems; it determines the correctness of the results of parallel program execution and defines the relationships between memory access operations in a multi-processor architecture.

[0037] With the development and increasing scale of modern integrated circuits, verification has gradually become one of the biggest challenges in system-on-chip (SoC) development. Cache coherence verification is an important part of the functional verification of on-chip multi-core processors.

[0038] Based on this, this application provides a method for verifying cache coherence in a multi-core processor system, offering a convenient verification method for technicians and improving the verification efficiency of cache coherence in multi-core processor systems.

[0039] To enable those skilled in the art to better understand the technical concept, implementation scheme and beneficial effects of the embodiments of this application, detailed descriptions are provided below through specific embodiments.

[0040] This application provides an embodiment of a cache consistency verification method for a multi-core processor system. The multi-core processor system includes two or more processor cores, each processor core having its own first-level cache and second-level cache, and all processor cores sharing a third-level cache. The cache consistency verification method includes: monitoring a first request received or sent by the first cache of a first processor core; wherein the first request includes the memory address of the data to be operated on by the first request and the command type; monitoring first response information in response to the first request; wherein the first response information includes the current state of a first cache line in the first cache; the first cache line is the cache line containing the data to be operated on by the first request; determining the state of the first cache line based on the memory address from a preset correspondence between memory addresses and cache line states; predicting the state of the first cache line based on the state of the first cache line and a preset state transition rule based on a cache consistency protocol, obtaining a predicted state of the cache line; comparing the current state of the cache line with the predicted state to determine whether the first cache conforms to cache consistency, thereby improving the cache consistency verification efficiency of the multi-core processor system.

[0041] Figure 3 A flowchart illustrating a method for verifying cache coherence in a multi-core processor system according to an embodiment of this application is shown below. Figure 3 As shown; the multi-core processor system of this embodiment includes two or more processor cores, each processor core has its own first-level cache and second-level cache, and all processor cores share a third-level cache; the cache coherence verification method of the multi-core processor system of this embodiment may include:

[0042] S101, monitor the first request received or sent by the first cache of the first processor core.

[0043] In this embodiment, the first request may include the memory address of the data to be operated on and the command type.

[0044] Command types can include read, write, and probe types.

[0045] The first processor core can be one of two or more processor cores.

[0046] The first cache can be a first-level cache, a second-level cache, or a third-level cache.

[0047] During the operation of a multi-core processor system, this embodiment monitors the cache receiving or sending requests corresponding to one of the processor cores. Taking reading data as an example, the first request includes a read command and the memory address corresponding to the data. This request can be sent to the second-level cache or to the third-level cache.

[0048] S102. Monitor the first response information in response to the first request.

[0049] The first response information can be feedback information in response to the first request.

[0050] In this embodiment, the first response information includes the current state of the first cache line in the first cache; the first cache line is the cache line where the data to be operated on by the first request is located.

[0051] After detecting the first request, the first request can be stored in a predetermined location so that subsequent operations can be performed after receiving the first response information for the first request.

[0052] It is understood that the Cacheline in this embodiment refers to the Cacheline in the first cache. The current state of the first cacheline can be Invalid, Shared, Exclusive, Modified, or Owned.

[0053] S103. Determine the state of the first cache line based on the memory address and the preset correspondence between memory addresses and cache line states.

[0054] Based on the memory address in the first request, the state of the first cache line can be determined from the preset correspondence between memory addresses and cache line states.

[0055] The preset correspondence between memory addresses and cache line states can correspond to the first processor core.

[0056] S104. Based on the state of the first cache line, the command type, and the preset state transition rules based on the cache consistency protocol, predict the state of the first cache line and obtain the predicted state of the first cache line.

[0057] Based on the state of the first cache line determined in S103, the command type included in the first request, and the preset state transition rules based on the cache consistency protocol, the state of the first cache line is predicted to obtain the predicted state of the first cache line.

[0058] See Figure 4 The state transition rules based on the cache coherence protocol can be the state transition rules derived from the cache coherence protocol. These rules can be a state transition diagram, and the corresponding state transition table is shown in Table 1, while the corresponding state interpretation is shown in Table 2.

[0059] Table 1

[0060]

[0061] Table 2

[0062]

[0063] It is understood that the state transition rules based on the cache coherence protocol in this embodiment are consistent with the state transition rules based on the cache coherence protocol used in multi-core processor systems.

[0064] In some examples, the state transition rules based on the cache coherence protocol can be a state transition table based on the MOESI protocol, which includes the correspondence between cacheline state, command type and predicted cacheline state.

[0065] S105. Compare the current state of the cache line with the predicted state to determine whether the first cache meets the cache consistency requirement.

[0066] The current state of the first cache line in the first cache included in the first response information in S102 is compared with the predicted state of the first cache line determined in S104 to determine whether the first cache meets cache consistency. Specifically, if the current state of the cache line is consistent with the predicted state, the first cache meets cache consistency; if the current state of the cache line is inconsistent with the predicted state, the first cache does not meet cache consistency.

[0067] It is understood that consistency can be determined for each request received or sent by the first cache according to the process described in the above embodiments; furthermore, consistency can be determined for each processor core according to the process described in the above embodiments.

[0068] In this embodiment, by monitoring the first request received or sent by the first cache of the first processor core and the first response information for the first request, the state of the first cache line is determined from the correspondence between the memory address and the cache line state in the first request. Then, based on the state of the first cache line in the first response information, the command type in the first request, and the preset state transition rules based on the cache coherence protocol, the state of the first cache line is predicted to obtain the predicted state of the first cache line. Finally, the current state of the cache line is compared with the predicted state to determine whether the first cache meets cache coherence. Since the predicted state of the first cache line is predicted based on the state of the first cache line, the command type, and the preset state transition rules based on the cache coherence protocol, and the preset state transition rules based on the cache coherence protocol are consistent with the cache coherence state transition rules used in multi-core processor systems, the predicted state of the first cache line can be considered as the current standard state of the cacheline. By comparing the current state of the cacheline in the first response information with the predicted state, it can be determined whether the first cache meets cache coherence, thereby improving the verification efficiency of cache coherence in multi-core processor systems.

[0069] In some examples, monitoring the first request received or sent by the first cache of the first processor core (S101) may include:

[0070] S101a, Monitor the instruction fetch request, probe request and / or eviction request received or sent by the first cache of the first processor core.

[0071] A fetch request can be a request to read, write, or modify data at a memory address.

[0072] A probe request can be a request sent to other processor cores to invalidate the data corresponding to that memory address in the cache of other processors in order to satisfy the cache coherency protocol, in response to a change in the data in the first cache of the first processor core.

[0073] A eviction request can be a victim request. A victim request is a request that, after the first cache is full, remove the data that is furthest away from the present in time from the first cache and store the data in the next level cache.

[0074] See Figure 5As shown, in some examples, each processor core's L2 cache contains all the data backup information of the L1 cache, meaning the L2 cache is of the inclusive type. Inclusive caches simplify consistency management. For example, in a multi-core processor, when one processor core modifies data at a memory address (e.g., by executing a store instruction), if the data at that address is also stored in the private caches of other processor cores (typically, in multi-core processors, both the L1 and L2 caches are private), then these caches need to be invalidated to prevent these processors from using incorrect data. For inclusive caches, only the lower-level L2 cache needs to be checked. Furthermore, the L2 cache is connected to the L3 cache, which can monitor all information from the kernel and storage system. Therefore, selecting the L2 cache for consistency monitoring can save computational resources.

[0075] In some examples, the first cache is a second-level cache. Monitoring the first request received or sent by the first cache of the first processor core (S101) may include:

[0076] Monitor requests between the second-level cache and the access instruction unit, the first-level data cache, or the third-level cache of the first processor core.

[0077] It can monitor requests between the second-level cache and the access instruction unit of the first processor core, as well as requests between the second-level cache and the first-level cache of the first processor core, and requests between the second-level cache and the third-level cache of the first processor core.

[0078] The cacheline state of the same data may be different in the cache corresponding to different processor cores. For example, the cacheline state in the cache of one processor core may be S state, while the cacheline state in the cache of another processor core may be O state. To accommodate the above situation, in some examples, the preset correspondence between memory addresses and cache line states may include: multiple preset correspondences between memory addresses and cache line states.

[0079] The correspondence between each preset memory address and cache line state corresponds one-to-one with each processor core. In other words, each processor core corresponds to a preset correspondence between memory address and cache line state.

[0080] Correspondingly, in some examples, after monitoring the first request received or sent by the first cache of the first processor core, and before determining the state of the first cache line based on the memory address and from a preset correspondence between memory addresses and cache line states, the method may further include:

[0081] S106. The first request is marked so that the marked first request includes the first processor core information.

[0082] The first request can be marked with letters, numbers, or core identification information, so that the marked first request also includes the first processor core information.

[0083] S107. Based on the first processor core information included in the marked first request, determine the first preset memory address and cache line state corresponding to the first processor core from multiple preset memory address and cache line state correspondences.

[0084] Based on the memory address, determining the state of the first cache line from a preset correspondence between memory addresses and cache line states (S103) may include:

[0085] Based on the memory address, the state of the first cache line is determined from the correspondence between the first preset memory address and the cache line state.

[0086] To facilitate determining whether the first cache conforms to cache consistency for requests following the first request according to the steps of the above embodiments, in some examples, the method may further include:

[0087] If the current state of the cache line matches the predicted state, the preset correspondence between the memory address and the cache line state information is updated using the memory address and the current state of the cache line.

[0088] The methods described above can be written using hardware description languages ​​such as Verilog. Utilizing hardware accelerators can significantly improve verification speed and support larger-scale verification. Using hardware accelerators such as Zebu and Veloce can achieve simulation speeds in the kHz to MHz range.

[0089] In actual project development, the code written in the aforementioned hardware description language is injected into the hardware platform. Correspondingly, a device that supports the verification of cache consistency of multi-core processors can be obtained, ultimately achieving the verification of CPU RTL cache consistency on the emulator while ensuring running speed.

[0090] The solution of this application will be described in detail below from the perspective of hardware device, with a specific embodiment.

[0091] See Figure 6 and Figure 7 The cache consistency verification device in this embodiment may include:

[0092] 1. Cache coherence model read port uplink: Listens for signals from the I-Fetch unit and the LSDC unit. The specific method is as follows:

[0093] Fetch Bundle Monitor 1 monitors the request and response information between the L2 and LSDC units, such as the request and response generated when the LSDC needs to read data from a certain address.

[0094] Probe Bundle Monitor 1 monitors probe information between the L2 and LSDC units. In a multiprocessor environment, the existence of private caches means that the same memory data may exist in multiple copies; that is, data corresponding to the same memory address may be stored in multiple locations. To ensure data consistency, when a CPU core needs to operate on data at a certain address, it will use a probe operation to obtain the status of that data in other locations (such as the cache of another CPU core).

[0095] The Victim Monitor monitors the Victim information between L2 and LSDC units, mainly referring to the cache address, status, and data written by L1 to L2 during victim operations.

[0096] Fetch Bundle Monitor 2 and Probe Bundle Monitor 2 monitor the request and response information between L2 and I-Fetch, respectively.

[0097] 2. Cache consistency model read port downlink: Listen for signals from L3. The specific method is as follows:

[0098] Fetch Bundle Monitor 0 and Probe Bundle Monitor 0 monitor request and response information between L2 and L3, respectively.

[0099] 3. Cache Coherence Model

[0100] 3.1 Cache the information received by L2 from L1 and L3 into the packet queues.

[0101] 3.2 Upon receiving the response to the request, the response includes the current state of the L2 cacheline and identification information. The corresponding request is searched in the data packet queue using the identification information. The memory address (Cacheline address) is obtained from the request. Based on the memory address (Cacheline address), the state of the Cacheline corresponding to the Cacheline address is searched in the Cache consistency model. The Cache consistency model is similar to a table that records the latest Cacheline state of the private L2 Cache of all cores of the multi-core processor. The index of the table is the Cacheline address (memory address), and the value indexed is the state of that Cacheline.

[0102] The consistency update processor consists of three parts: the Fetch Req / Rsp Handler, the Probe Req / Resp Handler, and the Victim Handler. The consistency update processor processes the request information for caching to the Bundle queue according to the cache consistency protocol such as the MOESI protocol's cache consistency transition table (Figure). This information includes the type of command issued to a cacheline at a certain memory address and the status of the cacheline indexed by the cache consistency model, and can predict the predicted status of the cacheline.

[0103] The predicted state is compared with the state of the Cacheline in the response to determine whether cache consistency is met.

[0104] After comparing the predicted state with the cacheline state in the response, if the predicted state matches the cacheline state in the response, the cache consistency model is updated using the cacheline address and cacheline state.

[0105] When checking the cache consistency model, if the cache is not found, the cacheline status is considered invalid.

[0106] Specifically, in a multi-core processor scenario, each time L2 receives a request / response from L1 and L3, because the target cacheline may exist in multiple copies throughout the storage system, to ensure cache consistency during actual processing by our multi-core processor, we need to look up the cache state of the corresponding cacheline address in the large table of the cache consistency model when the corresponding request is detected, and perform a predictive update, each time we read or write data from a certain L2 cacheline. When the processor receives the response information for this request, we can obtain its actual state after the operation on this cacheline from the response information. Then, we compare the cacheline state obtained from the response with the previously predicted state to verify whether the current multi-core processor meets the cache consistency requirements during operation.

[0107] When using the emulator for verification, the large table of the cache consistency model caches the mapping between cacheline addresses and cacheline states. This step consumes a lot of storage resources. To save hardware resources, the data can be exported to C language via DPI, and the C environment can complete the mapping between cacheline addresses and cacheline states.

[0108] See Figure 8 The Cache Coherence Model table was obtained through the MOESI protocol, which is consistent with the protocol that actual multi-core processors need to follow. Each update of the state of the corresponding address is based on the request of our actual processor, so the predicted state is considered to be a completely correct result.

[0109] This application provides an embodiment of a cache consistency verification device for a multi-core processor system. The multi-core processor system includes two or more processor cores, each processor core having its own first-level cache and second-level cache, and all processor cores sharing a third-level cache. The cache consistency verification device includes: a first monitoring module for monitoring a first request received or sent by the first cache of the first processor core; wherein the first request includes the memory address of the data to be operated on by the first request and the command type; and a second monitoring module for monitoring first response information in response to the first request; wherein the first response information includes the current state of a first cache line in the first cache; the first cache line is the data to be operated on by the first request. The system comprises: a first determining module, configured to determine the state of the first cache line based on the memory address and from a preset correspondence between memory addresses and cache line states; a prediction module, configured to predict the state of the first cache line based on the state of the first cache line, the command type, and a preset state transition rule based on a cache coherence protocol, to obtain the predicted state of the first cache line; the preset state transition rule based on a cache coherence protocol is consistent with the cache coherence state transition rule used in the multi-core processor system; and a second determining module, configured to compare the current state of the cache line with the predicted state to determine whether the first cache line conforms to cache coherence, thereby improving the verification efficiency of cache coherence in the multi-core processor system.

[0110] Figure 9 A schematic diagram of the structure of a cache coherence verification device for a multi-core processor system provided in an embodiment of this application is shown below. Figure 9As shown in this embodiment, the cache consistency verification device for a multi-core processor system includes two or more processor cores. Each processor core has a first-level cache and a second-level cache, and all processor cores share a third-level cache. The cache consistency verification device includes: a first monitoring module 11, used to monitor a first request received or sent by the first cache of the first processor core; wherein the first request includes the memory address of the data to be operated on by the first request and the command type; a second monitoring module 12, used to monitor first response information in response to the first request; wherein the first response information includes the current state of a first cache line in the first cache; the first cache line is the... The first request is for the cache line containing the data to be operated on; the first determining module 13 is used to determine the state of the first cache line based on the memory address and from the preset correspondence between memory addresses and cache line states; the prediction module 14 is used to predict the state of the first cache line based on the state of the first cache line, the command type, and the preset state transition rules based on the cache consistency protocol, to obtain the predicted state of the first cache line; the preset state transition rules based on the cache consistency protocol are consistent with the cache consistency state transition rules used in the multi-core processor system; the second determining module 15 is used to compare the current state of the cache line with the predicted state to determine whether the first cache line meets the cache consistency requirements.

[0111] The apparatus of this embodiment can be used to perform Figure 3 The technical solutions of the method embodiments shown are similar in principle and in effect, and will not be described again here.

[0112] The apparatus of this embodiment monitors the first request received or sent by the first cache of the first processor core and the first response information for the first request. Based on the memory address in the first request, it determines the state of the first cache line from a preset correspondence between memory addresses and cache line states. Then, based on the state of the first cache line in the first response information, the command type in the first request, and a preset state transition rule based on the cache coherence protocol, it predicts the state of the first cache line to obtain the predicted state of the first cache line. Finally, it compares the current state of the cache line with the predicted state to determine whether the first cache meets cache coherence requirements. Since the predicted state of the first cache line is predicted based on the state of the first cache line, the command type, and the preset state transition rule based on the cache coherence protocol, and the preset state transition rule based on the cache coherence protocol is consistent with the cache coherence state transition rule used in multi-core processor systems, the predicted state of the first cache line can be considered as the current standard state of the cacheline. By comparing the current state of the cacheline in the first response information with the predicted state, it can be determined whether the first cache meets cache coherence requirements, thereby improving the verification efficiency of cache coherence in multi-core processor systems.

[0113] As an optional implementation, the first monitoring module is specifically used to: monitor the fetch requests, probe requests and / or eviction requests received or sent by the first cache of the first processor core.

[0114] As an optional implementation, the first cache is a second-level cache; the first monitoring module is specifically used to: monitor requests between the second-level cache of the first processor core and the access instruction unit, the first-level data cache, or the third-level cache.

[0115] As an optional implementation, the preset correspondence between memory addresses and cache line states includes: multiple preset correspondences between memory addresses and cache line states; each preset correspondence between memory addresses and cache line states corresponds one-to-one with each processor core; the device further includes: a marking module, used to mark the first request after the first monitoring module monitors the first cache receiving or sending a first request of the first processor core, and before the first determining module determines the state of the first cache line based on the memory address from the preset correspondence between memory addresses and cache line states, so that the marked first request includes first processor core information; a third determining module, used to determine, based on the first processor core information included in the marked first request, a first preset correspondence between memory addresses and cache line states corresponding to the first processor core from multiple preset correspondences between memory addresses and cache line states; the first determining module is specifically used to: determine the state of the first cache line based on the memory address from the first preset correspondence between memory addresses and cache line states.

[0116] As an optional implementation, the device further includes: an update module, configured to update the preset correspondence between memory address and cache line status information using the memory address and the current state of the cache line when the current state of the cache line is consistent with the predicted state.

[0117] The apparatus described in the above embodiments can be used to execute the technical solutions of the above method embodiments. The implementation principle and technical effects are similar, and will not be repeated here.

[0118] Figure 10 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application, as shown below. Figure 10 As shown, the device may include: a housing 61, a processor 62, a memory 63, a circuit board 64, and a power supply circuit 65. The circuit board 64 is disposed inside the space enclosed by the housing 61, and the processor 62 and the memory 63 are disposed on the circuit board 64. The power supply circuit 65 is used to supply power to the various circuits or devices of the above-mentioned electronic device. The memory 63 is used to store executable program code. The processor 62 runs the program corresponding to the executable program code by reading the executable program code stored in the memory 63, and is used to execute the cache coherence verification method of any of the multi-core processor systems provided in the foregoing embodiments. Therefore, it can also achieve the corresponding beneficial technical effects, which have been described in detail above and will not be repeated here.

[0119] The aforementioned electronic devices exist in various forms, including but not limited to:

[0120] (1) Ultra-mobile personal computer devices: These devices fall under the category of personal computers, have computing and processing capabilities, and generally also have mobile internet access capabilities. These terminals include: PDAs, MIDs, and UMPCs, such as iPads.

[0121] (2) Server: A device that provides computing services. The components of a server include a processor, hard disk, memory, system bus, etc. Servers are similar to general computer architectures, but because they need to provide highly reliable services, they have higher requirements in terms of processing power, stability, reliability, security, scalability, and manageability.

[0122] (3) Other electronic devices with data interaction functions.

[0123] Accordingly, embodiments of this application also provide a computer-readable storage medium storing one or more programs, which can be executed by one or more processors to implement the cache consistency verification method for any of the multi-core processor systems provided in the foregoing embodiments. Therefore, it can also achieve the corresponding technical effects, as has been described in detail above and will not be repeated here.

[0124] It should be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0125] The various embodiments in this specification are described in a related manner. The same or similar parts between the various embodiments can be referred to each other. Each embodiment focuses on describing the differences from other embodiments.

[0126] In particular, the device embodiment is basically similar to the method embodiment, so the description is relatively simple. For relevant details, please refer to the description of the method embodiment.

[0127] For ease of description, the above apparatus is described by dividing it into various functional units / modules. Of course, in implementing this application, the functions of each unit / module can be implemented in one or more software and / or hardware.

[0128] Those skilled in the art will understand that all or part of the processes in the above embodiments can be implemented by a computer program instructing related hardware. The program can be stored in a computer-readable storage medium, and when executed, it can include the processes of the embodiments of the above methods. The storage medium can be a magnetic disk, optical disk, read-only memory (ROM), or random access memory (RAM), etc.

[0129] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A method of verifying cache coherency of a multi-core processor system, the method comprising: The multi-core processor system includes two or more processor cores, each processor core has its own first-level cache and second-level cache, and all processor cores share a third-level cache. The cache consistency verification method includes: Monitor the first request received or sent by the first cache of the first processor core; wherein, the first request includes the memory address of the data to be operated on by the first request and the command type; Monitor the first response information in response to the first request; wherein, the first response information includes the current status of the first cache line in the first cache; the first cache line is the cache line containing the data to be operated on by the first request; Based on the memory address, the state of the first cache line is determined from the preset correspondence between memory addresses and cache line states; Based on the state of the first cache line, the command type, and the preset state transition rules based on the cache coherence protocol, the state of the first cache line is predicted to obtain the predicted state of the first cache line; the preset state transition rules based on the cache coherence protocol are consistent with the cache coherence state transition rules used in the multi-core processor system. The current state of the cache line is compared with the predicted state to determine whether the first cache meets the cache consistency requirement.

2. The method of claim 1, wherein, The monitoring of the first request received or sent by the first cache of the first processor core includes: Monitor the first cache of the first processor core to receive or send fetch requests, probe requests, and / or eviction requests.

3. The method of claim 1, wherein, The first cache is the second-level cache; The monitoring of the first request received or sent by the first cache of the first processor core includes: Monitor requests between the second-level cache and the access instruction unit, the first-level data cache, or the third-level cache of the first processor core.

4. The method of claim 1, wherein, The preset correspondence between memory addresses and cache line states includes: multiple preset correspondences between memory addresses and cache line states; and each preset correspondence between memory addresses and cache line states corresponds one-to-one with each processor core. After monitoring the first request received or sent by the first cache of the first processor core, and before determining the state of the first cache line based on the memory address and from a preset correspondence between memory addresses and cache line states, the method further includes: The first request is marked so that the marked first request includes first processor core information; Based on the first processor core information included in the marked first request, the correspondence between the first preset memory address and cache line state corresponding to the first processor core is determined from multiple preset correspondences between memory addresses and cache line states. Determining the state of the first cache line based on the memory address from a preset correspondence between memory addresses and cache line states includes: Based on the memory address, the state of the first cache line is determined from the correspondence between the first preset memory address and the cache line state.

5. The method of claim 1, wherein, The method further includes: If the current state of the cache line matches the predicted state, the preset correspondence between the memory address and the cache line state information is updated using the memory address and the current state of the cache line.

6. A device for verifying cache coherency in a multi-core processor system, characterized in that, The multi-core processor system includes two or more processor cores, each processor core has its own first-level cache and second-level cache, and all processor cores share a third-level cache. The cache consistency verification device includes: The first monitoring module is used to monitor the first request received or sent by the first cache of the first processor core; wherein, the first request includes the memory address of the data to be operated on by the first request and the command type; The second monitoring module is used to monitor the first response information in response to the first request; wherein, the first response information includes the current status of the first cache line in the first cache; the first cache line is the cache line containing the data to be operated on by the first request; The first determining module is used to determine the state of the first cache line based on the memory address from a preset correspondence between memory addresses and cache line states; The prediction module is used to predict the state of the first cache line based on the state of the first cache line, the command type, and a preset state transition rule based on the cache coherence protocol, and to obtain the predicted state of the first cache line; the preset state transition rule based on the cache coherence protocol is consistent with the cache coherence state transition rule used in the multi-core processor system. The second determining module is used to compare the current state of the cache line with the predicted state to determine whether the first cache meets the cache consistency requirement.

7. The apparatus of claim 6, wherein, The first monitoring module is specifically used for: Monitor the first cache of the first processor core to receive or send fetch requests, probe requests, and / or eviction requests.

8. The apparatus of claim 6, wherein, The first cache is a second-level cache; the first monitoring module is specifically used for: Monitor requests between the second-level cache and the access instruction unit, the first-level data cache, or the third-level cache of the first processor core.

9. The apparatus of claim 6, wherein, The preset correspondence between memory addresses and cache line states includes: multiple preset correspondences between memory addresses and cache line states; and each preset correspondence between memory addresses and cache line states corresponds one-to-one with each processor core. The device further includes: The marking module is used to mark the first request after the first monitoring module monitors the first request received or sent by the first cache of the first processor core and before the first determining module determines the status of the first cache line based on the memory address from the preset correspondence between memory address and cache line status, so that the marked first request includes the first processor core information. The third determining module is used to determine the correspondence between the first preset memory address and cache line state corresponding to the first processor core from multiple preset correspondences between memory addresses and cache line states, based on the first processor core information included in the marked first request. The first determining module is specifically used for: Based on the memory address, the state of the first cache line is determined from the correspondence between the first preset memory address and the cache line state.

10. The apparatus of claim 6, wherein, The device further includes: The update module is used to update the preset correspondence between memory address and cache line status information using the memory address and the current state of the cache line when the current state of the cache line is consistent with the predicted state.

11. An electronic device, comprising: The electronic device includes: a housing, a processor, a memory, a circuit board, and a power supply circuit, wherein the circuit board is disposed inside the space enclosed by the housing, and the processor and the memory are disposed on the circuit board; the power supply circuit is used to supply power to various circuits or devices of the electronic device; the memory is used to store executable program code; the processor runs a program corresponding to the executable program code by reading the executable program code stored in the memory, for executing the cache coherence verification method of the multi-core processor system according to any one of claims 1-5.

12. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores one or more programs, which can be executed by one or more processors to implement the cache coherency verification method for a multi-core processor system as described in any one of claims 1-5.

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