An integrated circuit wafer and method of manufacturing the same

Abstract

The present application relates to the field of wafer manufacturing, in particular to an integrated circuit wafer and a manufacturing method thereof, by performing active area photoetching trimming on the front side of a silicon wafer substrate; setting a pattern mask layer for gate photoetching and trimming to obtain a gate photoetching precursor; setting a gate photoetching layer on the front side of the gate photoetching precursor and trimming; the trimming edge of the gate photoetching layer is located between the trimming edge of the pattern mask layer and the trimming edge of the active area; performing photoetching and etching on the gate photoetching precursor with the gate photoetching layer to obtain a wafer precursor; depositing a filling composite layer; performing planarization polishing on the filling composite layer; etching to remove the pseudo-polysilicon gate and setting a metal gate on the front side of the wafer precursor to obtain the integrated circuit wafer. The present application realizes the consideration of low cost and low metal edge residue.

Description

Technical Field

[0001] This invention relates to the field of wafer manufacturing, and in particular to an integrated circuit wafer and a method for manufacturing the same. Background Technology

[0002] In the semiconductor integrated circuit manufacturing process, various defects are introduced onto the wafer surface and edges, severely impacting subsequent normal processes and reducing the final yield of the chip. In the metal gate process, aluminum (Al) is used as the metal gate and deposited on the wafer surface. The Al in the non-gate areas is then removed by grinding. However, due to positional factors, a large amount of Al residue is often left at the wafer edges. This residual Al is deeply buried in the trenches at the wafer edge and will be exposed in subsequent processes, causing defects such as scratches on the wafer surface.

[0003] To address this issue, existing methods used by semiconductor manufacturers involve adding a wafer edge etching process to remove residual Al at the wafer edges. However, bevel etching significantly increases chip manufacturing costs and is not easily adopted.

[0004] Therefore, how to propose a low-cost method for manufacturing integrated circuit wafers that eliminates metallized gate residues at the crystal edge is a problem that urgently needs to be solved by those skilled in the art. Summary of the Invention

[0005] The purpose of this invention is to provide an integrated circuit wafer and its manufacturing method to solve the problems in the prior art.

[0006] To solve the above-mentioned technical problems, the present invention provides a method for manufacturing an integrated circuit wafer, comprising:

[0007] Active region photolithography is performed on the front side of the silicon wafer substrate, and the active region is then cleaned.

[0008] A patterned mask layer for gate lithography is formed on the surface of the active region, and the edges of the patterned mask layer are washed to obtain a gate lithography precursor.

[0009] A gate lithography layer is formed on the front side of the gate lithography preform, and the edge of the gate lithography layer is washed; the washed edge of the gate lithography layer is located between the washed edge of the pattern mask layer and the washed edge of the active region;

[0010] Photolithography and etching are performed on the gate photolithography precursor with the gate photolithography layer applied, and a patterned pseudo polysilicon gate is obtained on the front side of the gate photolithography precursor to obtain a wafer precursor.

[0011] A filler composite layer is deposited on the front side of the wafer precursor; the filler composite layer includes a filler dielectric layer and a stop layer.

[0012] The filled composite layer is planarized and polished to expose the pseudo-polysilicon gate;

[0013] The pseudo-polysilicon gate is removed by etching, and a metal gate is formed on the front side of the wafer precursor to obtain the integrated circuit wafer.

[0014] Optionally, in the method for manufacturing an integrated circuit wafer, the gate photolithography layer comprises multiple stacked sub-layers, and each sub-layer is washed after it is set.

[0015] Optionally, in the method for manufacturing the integrated circuit wafer, the position of the edge washing of the sub-layer is different.

[0016] Optionally, in the method for manufacturing the integrated circuit wafer, the edge of at least one sublayer in the gate photolithography layer is closer to the edge of the active region than the edge of the innermost sublayer.

[0017] Optionally, in the method for manufacturing the integrated circuit wafer, the gate photolithography layer comprises, from the inside out, an organic carbon layer, a bottom anti-reflective layer, and a photoresist layer.

[0018] Optionally, in the method for manufacturing the integrated circuit wafer, the planarization polishing is chemical mechanical polishing.

[0019] Optionally, in the method for manufacturing the integrated circuit wafer, the filling dielectric layer is a filling dielectric silicon oxide layer.

[0020] Optionally, in the method for manufacturing the integrated circuit wafer, the stop layer is a stop silicon nitride layer.

[0021] Optionally, in the method for manufacturing an integrated circuit wafer, the edge washing process includes at least one of edge photoresist removal and silicon wafer edge exposure.

[0022] An integrated circuit chip, said integrated circuit chip being an integrated circuit chip as described in any of the above.

[0023] The method for manufacturing an integrated circuit wafer provided by this invention involves performing active region photolithography on the front side of a silicon substrate and washing the edges of the active region; depositing a pattern mask layer for gate photolithography on the surface of the active region and washing the edges of the pattern mask layer to obtain a gate photolithography precursor; depositing a gate photolithography layer on the front side of the gate photolithography precursor and washing the edges of the gate photolithography layer; the washed edge of the gate photolithography layer is located between the washed edge of the pattern mask layer and the washed edge of the active region; performing photolithography and etching on the gate photolithography precursor with the gate photolithography layer deposited thereon to obtain a patterned pseudo-polysilicon gate on the front side of the gate photolithography precursor to obtain a wafer precursor; depositing a fill composite layer on the front side of the wafer precursor; the fill composite layer includes a fill dielectric layer and a stop layer; planarizing and polishing the fill composite layer to expose the pseudo-polysilicon gate; etching away the pseudo-polysilicon gate and depositing a metal gate on the front side of the wafer precursor to obtain the integrated circuit wafer.

[0024] In this invention, the edge of the gate lithography layer used in the photolithography process for setting the metal gate is limited to the area between the edge of the pattern mask layer and the edge of the active region. This means that any step-like structures that the gate lithography layer might leave in subsequent etching processes are confined to the active region. This makes the area between the edge of the active region and the wafer edge relatively flat and free of step-like structures. The metal residue caused by the step-like structures formed in the active region is significantly less than that caused by the step-like structures formed in the area between the edge of the active region and the wafer edge in the prior art. This greatly reduces the number of metal edge defects, thereby improving wafer yield. Furthermore, since this invention only changes the edge-washing position of the film layer and hardly alters the wafer manufacturing process, no additional production cost is required, achieving a balance between low cost and low metal edge residue. This invention also provides an integrated circuit wafer with the above-mentioned beneficial effects. Attached Figure Description

[0025] To more clearly illustrate the technical solutions of the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0026] Figure 1 A schematic flowchart illustrating a specific embodiment of the method for manufacturing an integrated circuit wafer provided by the present invention;

[0027] Figure 2 A schematic flowchart illustrating another specific embodiment of the method for manufacturing an integrated circuit wafer provided by the present invention;

[0028] Figure 3-1 This is a process flow diagram of a specific implementation of a method for manufacturing integrated circuit wafers in the prior art.

[0029] Figure 3-2 A process flow diagram of a specific embodiment of the method for manufacturing an integrated circuit wafer provided by the present invention;

[0030] Figure 4-1 This is a process flow diagram of a specific implementation of a method for manufacturing integrated circuit wafers in the prior art.

[0031] Figure 4-2 A process flow diagram of a specific embodiment of the method for manufacturing an integrated circuit wafer provided by the present invention;

[0032] Figure 5-1 This is a process flow diagram of a specific implementation of a method for manufacturing integrated circuit wafers in the prior art.

[0033] Figure 5-2 A process flow diagram of a specific embodiment of the method for manufacturing an integrated circuit wafer provided by the present invention;

[0034] Figure 6-1 This is a process flow diagram of a specific implementation of a method for manufacturing integrated circuit wafers in the prior art.

[0035] Figure 6-2 A process flow diagram of a specific embodiment of the method for manufacturing an integrated circuit wafer provided by the present invention;

[0036] Figure 7-1 This is a process flow diagram of a specific implementation of a method for manufacturing integrated circuit wafers in the prior art.

[0037] Figure 7-2 A process flow diagram of a specific embodiment of the method for manufacturing an integrated circuit wafer provided by the present invention;

[0038] Figure 8-1 This is a process flow diagram of a specific implementation of a method for manufacturing integrated circuit wafers in the prior art.

[0039] Figure 8-2 This is a process flow diagram of a specific embodiment of the method for manufacturing an integrated circuit wafer provided by the present invention. Detailed Implementation

[0040] To enable those skilled in the art to better understand the present invention, the invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. Obviously, the described embodiments are merely some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0041] The core of this invention is to provide a method for manufacturing an integrated circuit wafer, and a flowchart of one specific embodiment is shown below. Figure 1 As shown, this is referred to as Specific Implementation Method One, which includes:

[0042] S101: Perform active area photolithography on the front side of the silicon wafer substrate and clean the edges of the active area.

[0043] After edge washing, the area between the washed edge of the active region and the wafer edge is a thinned flat region.

[0044] In this context, "active region photolithography" refers to the photolithography used to generate the active region. "Edge washing of the active region" refers to the edge washing performed on the active region after exposure and etching to determine the edge position of the active region. The remaining "edge washing of..." in this invention is the same and can be referred to in the preceding text, and will not be repeated hereafter.

[0045] S102: A patterned mask layer for gate lithography is formed on the surface of the active region, and the edges of the patterned mask layer are washed to obtain a gate lithography precursor.

[0046] The pattern mask layer can be a hard mask. After edge washing, the area between the washed edge of the pattern mask layer and the washed edge of the active area is the exposed surface of the active area.

[0047] S103: A gate photolithography layer is formed on the front side of the gate photolithography preform, and the edge of the gate photolithography layer is washed; the washed edge of the gate photolithography layer is located between the washed edge of the pattern mask layer and the washed edge of the active region.

[0048] For reference Figure 3-2 , Figure 3-2 - A schematic diagram of the structure after the gate lithography layer is set on the front side of the gate lithography preform. The PR layer, BARC layer and SOC layer in the figure are all the gate lithography layer. The structure without the above three layers is the gate lithography preform.

[0049] The gate photolithography layer is an auxiliary layer for photolithography of the active region. It can be a single layer or a composite layer of multiple sub-layers stacked together. For example, when using line cut-out (LEC) photolithography, the gate photolithography layer is a composite layer composed of a photoresist layer (PR), a bottom anti-reflective layer (BARC), and an organic carbon layer (SOC), wherein the organic carbon layer is a spin-coated layer.

[0050] S104: Photolithography and etching are performed on the gate photolithography precursor on which the gate photolithography layer has been applied, and a patterned pseudo polysilicon gate is obtained on the front side of the gate photolithography precursor to obtain a wafer precursor.

[0051] Below the pattern mask layer of the active region is the pre-slab layer of the pseudo-polysilicon gate (i.e., the unpatterned polysilicon layer). The pattern mask layer and the gate photolithography layer are used for photolithography of the pre-slab layer of the pseudo-polysilicon gate.

[0052] The wafer precursor is... Figure 4-2 The structure shown.

[0053] S105: Deposit a fill composite layer on the front side of the wafer precursor; the fill composite layer includes a fill dielectric layer and a stop layer.

[0054] In this step, the front side of the wafer precursor is completely covered by the filling dielectric layer and the stop layer. Generally, the front side of the active region and the area between the edge of the active region and the edge of the wafer are covered.

[0055] In one specific embodiment, the filling dielectric layer is a filling dielectric silicon oxide layer, and the stop layer is a stop silicon nitride layer. The filling dielectric layer and stop layer made of the above materials perform best in subsequent polishing steps. Of course, in production, other materials can be selected as the stop layer and the filling dielectric layer according to actual conditions.

[0056] S106: Planarize and polish the filled composite layer to expose the pseudo-polysilicon gate.

[0057] As a preferred embodiment, the planarization polishing is chemical mechanical polishing, which is a processing technology that combines chemical corrosion and mechanical removal, and can achieve surface planarization and polishing on a small scale.

[0058] S107: Etch away the pseudo polysilicon gate and form a metal gate on the front side of the wafer precursor to obtain the integrated circuit wafer.

[0059] Furthermore, the edge washing in each of the above steps is at least one of edge photoresist removal (EBR) and wafer edge exposure (WEE). The two specific edge washing methods mentioned above are highly efficient and have high precision. Of course, other edge washing methods can also be selected according to the actual situation.

[0060] The method for manufacturing an integrated circuit wafer provided by this invention involves performing active region photolithography on the front side of a silicon substrate and washing the edges of the active region; depositing a pattern mask layer for gate photolithography on the surface of the active region and washing the edges of the pattern mask layer to obtain a gate photolithography precursor; depositing a gate photolithography layer on the front side of the gate photolithography precursor and washing the edges of the gate photolithography layer; the washed edge of the gate photolithography layer is located between the washed edge of the pattern mask layer and the washed edge of the active region; performing photolithography and etching on the gate photolithography precursor with the gate photolithography layer deposited thereon to obtain a patterned pseudo-polysilicon gate on the front side of the gate photolithography precursor to obtain a wafer precursor; depositing a fill composite layer on the front side of the wafer precursor; the fill composite layer includes a fill dielectric layer and a stop layer; planarizing and polishing the fill composite layer to expose the pseudo-polysilicon gate; etching away the pseudo-polysilicon gate and depositing a metal gate on the front side of the wafer precursor to obtain the integrated circuit wafer. In this invention, the edge of the gate lithography layer used in the photolithography process for setting the metal gate is limited to the area between the edge of the pattern mask layer and the edge of the active region. This means that any step-like structures that the gate lithography layer might leave in subsequent etching processes are confined to the active region. This makes the area between the edge of the active region and the wafer edge relatively flat and free of step-like structures. The metal residue caused by the step-like structures formed in the active region is far less than that caused by the step-like structures formed in the area between the edge of the active region and the wafer edge in the prior art. This significantly reduces the number of metal edge defects, thereby improving wafer yield. Furthermore, since this invention only changes the edge-washing position of the film layer and hardly alters the wafer manufacturing process, no additional production cost is required, achieving a balance between low cost and low metal edge residue.

[0061] Based on Specific Implementation Method 1, the gate photolithography layer is further improved to obtain Specific Implementation Method 2, the flowchart of which is shown below. Figure 2 As shown, this is referred to as Specific Implementation Method Two, which includes:

[0062] S201: Perform active area photolithography on the front side of the silicon wafer substrate and clean the edges of the active area.

[0063] S202: A patterned mask layer for gate lithography is formed on the surface of the active region, and the edges of the patterned mask layer are washed to obtain a gate lithography precursor.

[0064] S203: A gate lithography layer is formed on the front side of the gate lithography preform, and the edge of the gate lithography layer is washed; the washed edge of the gate lithography layer is located between the washed edge of the pattern mask layer and the washed edge of the active region; the gate lithography layer comprises multiple stacked sub-layers, and each sub-layer is washed after being formed.

[0065] S204: Photolithography and etching are performed on the gate photolithography precursor on which the gate photolithography layer has been applied, and a patterned pseudo polysilicon gate is obtained on the front side of the gate photolithography precursor to obtain a wafer precursor.

[0066] S205: Deposit a fill composite layer on the front side of the wafer precursor; the fill composite layer includes a fill dielectric layer and a stop layer.

[0067] S206: The filled composite layer is planarized and polished to expose the pseudo-polysilicon gate.

[0068] S207: Etch away the pseudo polysilicon gate and form a metal gate on the front side of the wafer precursor to obtain the integrated circuit wafer.

[0069] The difference between this specific embodiment and the above specific embodiment is that the gate photolithography layer in this specific embodiment is limited to a stacked composite layer. The remaining steps are the same as those in the above specific embodiment, and will not be described in detail here.

[0070] In this preferred embodiment, the gate photolithography layer is defined as a composite layer, and edge washing is performed after each sublayer in the composite layer is laid, which can obtain better photolithography effect and increase the versatility of this specific embodiment.

[0071] In one preferred embodiment, the positions of the washing edges of the sub-layers are different.

[0072] Because the different sub-layers are stacked, the actual position of the bottom of the stacked gate lithography layer is determined by the sub-layer whose edge is closest to the edge of the active region, and the actual position of the top is determined by the sub-layer whose edge is furthest from the edge of the active region. This results in a tower-shaped structure with a large bottom and a small top for the actual gate lithography layer, which enhances the structural stability of the gate lithography layer and improves the production yield.

[0073] Furthermore, the edge of at least one sublayer within the gate photolithography layer is closer to the edge of the active region than the edge of the innermost sublayer. (See reference...) Figure 3-2The innermost sublayer is the sublayer closest to the pattern mask layer. In this specific embodiment, the innermost sublayer is defined as not being the sublayer closest to the edge of the active region. This results in a portion of other sublayers falling outside the innermost sublayer (i.e., in the direction close to the edge of the active region). There is surface tension between sublayers of different compositions, causing the extra portion of the upper sublayer to form a wedge that holds the innermost sublayer in place, preventing the innermost sublayer from slipping. This further enhances the structural stability of the gate lithography layer and improves the process yield.

[0074] Specifically, the gate photolithography layer includes an organic carbon layer, a bottom anti-reflection layer, and a photoresist layer from the inside out. The gate photolithography layer with the above three sub-layers is a commonly used enhancement layer in the LEC process. The LEC process is mature, has low cost, and high yield. Of course, other sub-layers can also be selected for the gate photolithography layer according to the actual situation. This invention does not limit it here.

[0075] The following is a detailed explanation of the manufacturing method of the integrated circuit wafer provided by the present invention, along with a corresponding process flow diagram. Please refer to Figures 3 to 8. Each figure in Figures 3 to 8 is divided into X-1 and X-2, where X-1 is a structural schematic diagram of the corresponding structure in other existing technologies, and X-2 represents a structural schematic diagram after using the technical solution provided by the present invention. It should be noted that the edge washing position in the present invention is represented as the distance from the edge washing position to the edge of the wafer. Please refer to the following text and Figures 3 to 8, where the edge position of the lens is marked as 0mm.

[0076] The embodiments of the present invention are described in detail by comparing the undefined and defined edge washing conditions of the specific photolithography process in the preferred metal gate process. The schematic diagrams provided in Figures 3 to 8 are only schematic illustrations of the basic concept of the present invention. Therefore, the figures only show the components related to the present invention and are not drawn according to the number, shape and size of the components in actual implementation. The layout model of each component in actual implementation may be more complex.

[0077] like Figure 3-2As shown, the active region's edge washing position (referred to as the active region lithography in the figure) is 1mm. Therefore, the pattern with shallow trench isolation (STI) oxide will only be retained on the substrate silicon wafer within the 1mm edge washing position. Simultaneously, the substrate silicon wafer thickness within 1mm from the outermost edge to the inner edge of the wafer will be thinner after etching than the substrate silicon wafer thickness within the 1mm edge washing position, forming a noticeable step at the 1mm edge washing position. The edge washing position of the pattern mask layer (referred to as the gate position in the figure) is defined as 1.5mm. Therefore, after etching, the gate hard mask layer will only exist within the 1.5mm edge washing position. The gate hard mask layer is the hard mask for the pseudo-polysilicon gate. (Note: Only the pseudo-polysilicon gate covered by the gate hard mask layer can be retained after the gate LEC etching). At this time, the active region's edge washing position (1mm) is smaller than the pattern mask layer's edge washing position (1.5mm). Before exposing and etching the patterned mask layer of the gate lithography to obtain the patterned pseudo-polysilicon gate, three films need to be grown consecutively: a photoresist layer (PR), a bottom anti-reflective coating (BARC), and a spin-coated organic carbon layer (SOC), from top to bottom: PR, BARC, and SOC. Each film undergoes corresponding edge washing after its setup. The edge washing positions for PR and SOC are defined as 1.4 mm, and for BARC as 1.2 mm. This satisfies the requirement that the edge washing positions of PR / BARC / SOC are located between the edge washing positions of the active area lithography and the patterned mask layer. Simultaneously, it is required that the distance from the edge washing position of any one of these three films to the wafer edge is less than the distance from the edge washing positions of the other two films to the wafer edge. Failure to define the gate lithography edge washing position (i.e., the edge washing position of the gate lithography layer) according to this invention will result in film stacks of varying thicknesses between the active area edge washing position and the wafer edge, such as... Figure 3-1 The edge washing positions of the PC layer and SOC layer are set at 0.7mm, and the edge washing position of the BARC layer is close to the edge of the wafer. The meaning of the edge washing position markings in the following X-1 figures is the same, and will not be repeated hereafter.

[0078] like Figure 4-1 As shown, after the gate LEC is etched, if the gate photolithography wash position is not defined according to this invention, a step of different silicon thickness will be formed in the area from the active region wash position (1 mm in this embodiment) to the wafer edge; as Figure 4-2 As shown, according to the definition of the gate lithography edge washing position in this invention, a step will only be formed between the active area lithography and the edge washing position of the pattern mask layer. In this embodiment, the step positions are at 1.4 mm and 1.2 mm, respectively. After the subsequent deposition of the etch stop layer silicon nitride and the filling dielectric silicon oxide, as... Figure 5-1 and Figure 5-2 As shown, the steps formed by different silicon thicknesses are all filled.

[0079] like Figure 6-1 and Figure 6-2As shown, chemical mechanical polishing (CMP) of the dielectric layer is specifically used for planarization of the etching stop layer silicon nitride and the filling dielectric silicon oxide. Figure 6-2 The process shown in the diagram, following the definition of the gate photolithography edge washing position according to this invention, will not expose the substrate silicon between the active area photolithography edge washing position and the wafer edge. However, in the prior art... Figure 6-1 In the process, due to the presence of steps outside the edge of the active region, a portion of this area is exposed during grinding and polishing. The subsequent dummy polysilicon gate removal process is specifically designed for silicon etching, thus capable of etching both the dummy polysilicon gate and the substrate silicon. Figure 7-1 As shown, in the prior art, a very deep trench is dug in the silicon substrate exposed outside the edge of the active region. This results in a large amount of Al remaining in the deep trench at the crystal edge after subsequent gate Al filling and chemical mechanical polishing. Figure 8-1 As shown; however, in the technical solution provided by this invention, such as Figure 8-2 As shown, because the substrate silicon is not exposed between the active area photolithography edge washing position and the wafer edge, the Al filling in subsequent steps will not remain in this range, thus greatly reducing Al residue.

[0080] According to the definition of this invention, since the gate photolithography edge washing position does not form a deep trench at the crystal edge, the residual Al defect at the crystal edge can be reduced by more than 70%, which can effectively reduce the number of other defects introduced by Al residue in subsequent processes, thereby improving the final yield of the chip.

[0081] The present invention also provides an integrated circuit wafer, wherein the integrated circuit wafer is manufactured by any of the methods described above. The method for manufacturing the integrated circuit wafer provided by the present invention involves performing active region photolithography on the front side of a silicon substrate and edge washing of the active region; forming a pattern mask layer for gate photolithography on the surface of the active region and edge washing of the pattern mask layer to obtain a gate photolithography precursor; forming a gate photolithography layer on the front side of the gate photolithography precursor and edge washing of the gate photolithography layer; the edge washing edge of the gate photolithography layer is located between the edge washing edge of the pattern mask layer and the edge washing edge of the active region; performing photolithography and etching on the gate photolithography precursor with the gate photolithography layer formed thereon to obtain a patterned pseudo-polysilicon gate on the front side of the gate photolithography precursor to obtain a wafer precursor; depositing a fill composite layer on the front side of the wafer precursor; the fill composite layer including a fill dielectric layer and a stop layer; planarizing and polishing the fill composite layer to expose the pseudo-polysilicon gate; etching away the pseudo-polysilicon gate and forming a metal gate on the front side of the wafer precursor to obtain the integrated circuit wafer. In this invention, the edge of the gate lithography layer used in the photolithography process for setting the metal gate is limited to the area between the edge of the pattern mask layer and the edge of the active region. This means that any step-like structures that the gate lithography layer might leave in subsequent etching processes are confined to the active region. This makes the area between the edge of the active region and the wafer edge relatively flat and free of step-like structures. The metal residue caused by the step-like structures formed in the active region is far less than that caused by the step-like structures formed in the area between the edge of the active region and the wafer edge in the prior art. This significantly reduces the number of metal edge defects, thereby improving wafer yield. Furthermore, since this invention only changes the edge-washing position of the film layer and hardly alters the wafer manufacturing process, no additional production cost is required, achieving a balance between low cost and low metal edge residue.

[0082] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on its differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. For the apparatus disclosed in the embodiments, since it corresponds to the method disclosed in the embodiments, the description is relatively simple; relevant parts can be referred to in the method section.

[0083] It should be noted that, in this specification, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0084] The integrated circuit wafer and its manufacturing method provided by this invention have been described in detail above. Specific examples have been used to illustrate the principles and implementation methods of this invention. The descriptions of the embodiments above are only for the purpose of helping to understand the method and core ideas of this invention. It should be noted that those skilled in the art can make several improvements and modifications to this invention without departing from the principles of this invention, and these improvements and modifications also fall within the protection scope of the claims of this invention.

Claims

1. A method for manufacturing an integrated circuit wafer, characterized in that, include: Active region photolithography is performed on the front side of the silicon wafer substrate, and the active region is then cleaned. A patterned mask layer for gate lithography is formed on the surface of the active region, and the edges of the patterned mask layer are washed to obtain a gate lithography precursor. A gate lithography layer is formed on the front side of the gate lithography preform, and the edge of the gate lithography layer is washed; the washed edge of the gate lithography layer is located between the washed edge of the pattern mask layer and the washed edge of the active region; Photolithography and etching are performed on the gate photolithography precursor with the gate photolithography layer applied, and a patterned pseudo polysilicon gate is obtained on the front side of the gate photolithography precursor to obtain a wafer precursor. A filler composite layer is deposited on the front side of the wafer precursor; the filler composite layer includes a filler dielectric layer and a stop layer. The filled composite layer is planarized and polished to expose the pseudo-polysilicon gate; The pseudo-polysilicon gate is removed by etching, and a metal gate is formed on the front side of the wafer precursor to obtain the integrated circuit wafer.

2. The method for manufacturing an integrated circuit wafer as described in claim 1, characterized in that, The gate photolithography layer comprises multiple stacked sub-layers, and each sub-layer is washed after its configuration is completed.

3. The method for manufacturing an integrated circuit wafer as described in claim 2, characterized in that, The positions of the wash edges of the sub-layers are different.

4. The method for manufacturing an integrated circuit wafer as described in claim 3, characterized in that, The edge of at least one sublayer in the gate photolithography layer is closer to the edge of the active region than the edge of the innermost sublayer.

5. The method for manufacturing an integrated circuit wafer as described in claim 2, characterized in that, The gate photolithography layer comprises, from the inside out, an organic carbon layer, a bottom anti-reflective layer, and a photoresist layer.

6. The method for manufacturing an integrated circuit wafer as described in claim 1, characterized in that, The planarization polishing is a chemical mechanical polishing process.

7. The method for manufacturing an integrated circuit wafer as described in claim 1, characterized in that, The filling dielectric layer is a filling dielectric silicon oxide layer.

8. The method for manufacturing an integrated circuit wafer as described in claim 1, characterized in that, The stop layer is a stop silicon nitride layer.

9. The method for manufacturing an integrated circuit wafer as described in any one of claims 1 to 8, characterized in that, The edge washing process in the manufacturing method of the integrated circuit wafer includes at least one of edge photoresist removal and silicon wafer edge exposure.

10. An integrated circuit chip, characterized in that, The integrated circuit wafer is an integrated circuit wafer obtained by the manufacturing method of an integrated circuit wafer as described in any one of claims 1 to 9.

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