Image sensor with configurable pixel circuit and method

Abstract

The present disclosure relates to an image sensor, which includes a plurality of pixel circuits, each of which includes: a photodiode connected between a ground and a floating diffusion (FD) node; a reset transistor (MRST) connected between a first voltage source and a floating diffusion (FD) node; and a source follower transistor (MSF), wherein its drain is connected to a second voltage source, a gate is connected to a floating diffusion (FD) node, and a source is connected to a row select transistor (MSEL). The row select transistor (MSEL) is connected between the source of the source follower transistor (MSF) and a common column output. Each pixel circuit is configured to output an output signal corresponding to light incident on the photodiode. Each pixel circuit includes at least one additional transistor for configuring each pixel circuit to selectively output a linear integral signal or a logarithmic signal.

Description

Technical Field

[0001] The present invention relates to an image sensor integrated circuit comprising a plurality of pixel circuits and a corresponding method. Background Art

[0002] APS (APS: Active Pixel Sensor) is an image sensor integrated circuit comprising a plurality of pixels, usually arranged in rows and columns. Each pixel comprises a photodetector, usually a pinned photodiode, and one or more MOSFET amplifiers (MOSFET: Metal Oxide Semiconductor Field Effect Transistor). CMOS APS (CMOS: Complementary Metal Oxide Semiconductor) is widely used in mobile phone cameras, web cameras, compact cameras, DSLR cameras (DSLR: Digital Single Lens Reflex), mirrorless interchangeable lens cameras, etc.

[0003] APS includes linear APS and logarithmic APS. Linear APS has good sensitivity at low illumination intensities, but the dynamic range is limited by the full well capacity, which defines the amount of charge a pixel can hold before saturation. Logarithmic APS has good response at high illumination, and therefore a high dynamic range, but poor sensitivity at low illumination intensities. Different approaches have been used to combine a linear response at low illumination and a logarithmic response at high illumination.

[0004] Silicon foundries provide image pixel cells with highly optimized process technology and highly optimized layout to create high quality and dense frame image data (standard APS cells). However, the operation is suboptimal for low latency event-based processing. Standard reconfigurations that provide logarithmic outputs are known, but such configurations have disadvantages in performance and do not easily provide signals for pixel local low latency event processing (pixel parallel).

[0005] Factory standard cells are not designed for logarithmic local outputs, and an electrical configuration that provides good performance in such a logarithmic configuration while maintaining good performance in a linear configuration and allowing electrical switching between configurations is not obvious.

[0006] CMOS image sensors (CMOS: Complementary Metal Oxide Silicon) are produced in large quantities in a CIS (CIS: CMOS Image Sensor) fab process that is optimized for high performance (low dark current, low noise, high quantum efficiency). The CIS process is optimized for linear integral response with specific 3T (3T: three transistors) or 4T (4T: four transistors) cells and can be extended for additional functions (such as global shutter operation). Summary of the invention

[0007] The object of the present invention is to provide an image sensor including an improved pixel circuit and a corresponding method, which provide high-quality (especially low-noise at low illumination intensities) image data frames as well as high dynamic range and low-noise continuous data for event generation from the same pixel array.

[0008] This object is achieved by the subject matter of the independent claims. Advantageous embodiments are defined in the dependent claims.

[0009] In accordance with the present invention, a limited set of additional non-critical switching transistors has been discovered that enables reuse of a factory standard linear-integrating APS cell to additionally provide pixel-local high quality continuous logarithmic output.

[0010] There are compatible extensions of the invention that allow additional outputs (frame logarithmic outputs, pixel local linear outputs, etc.) that add additional functionality at the expense of additional surface area and / or power consumption.

[0011] Thus, the present invention provides an extension of the standard APS cell with electrical reconfiguration for high performance logarithmic pixel local low latency output.

[0012] The present invention does increase pixel circuit surface area (cost and / or reduced pixel density) and is therefore preferably suitable for circuits requiring high quality logarithmic output, but also for simple extension of the dynamic image sensor range. The additional area is minimal and provides efficient implementation of the functionality, including significant reuse of transistors in the standard APS structure.

[0013] The present invention discloses adding additional transistors to an optimized fab structure to selectively provide continuously available logarithmic pixel local outputs. The logarithmic outputs extend the operating range of the unit to brighter lighting conditions. The pixel local outputs are suitable for low latency event-based response to changing lighting conditions.

[0014] The addition of additional transistors as disclosed in the present invention is compatible with the standard structure device and its dimensions and does not compromise the functionality of the standard structure linear integration.

[0015] Linear and logarithmic APS have been proposed separately. The present invention discloses an architecture in which these modes are combined with reuse of the same photodiode and optimized readout electronics and pixel-local provision of continuous pixel-local logarithmic outputs suitable for providing low-latency event-based response.

[0016] The present invention relates to an image sensor, the image sensor includes a plurality of pixel circuits, each of which includes a photodiode connected between a ground and a floating diffusion (FD) node, a reset transistor (MRST) configured to be connected between a first voltage source (vrst) and a floating diffusion (FD) node, and a source follower transistor (MSF), wherein its drain is configured to be connected to a second voltage source (vdd), its gate is connected to the floating diffusion (FD) node, and its source is connected to a row selection transistor (MSEL). The drain of the row selection transistor (MSEL) is connected between the source of the source follower transistor (MSF) and a common column output. Each pixel circuit is configured to output an output signal corresponding to light incident on the photodiode. Each pixel circuit includes at least one additional transistor (MS2, MS3, MS4 and MVB) for configuring each pixel circuit to selectively output a linear integral signal or a logarithmic signal.

[0017] Various embodiments may preferably implement the following features:

[0018] Each pixel circuit preferably also includes a transfer gate transistor (MTX) connected between the photodiode and the FD node.

[0019] Each pixel circuit may be configured to generate a logarithmic output signal (vlg out) and further include a first additional bias transistor (MVB) connected between a second voltage source (vdd) and a drain of a source follower transistor (MSF). A second additional transistor (MS2) may connect the drain of the bias transistor (MVB) to the drain of a reset transistor (MRST), and a third additional transistor (MS3) may connect the drain of the reset transistor (MRST) to the first power supply (vrst).

[0020] Preferably, the third additional transistor (MS3) is open. The fourth additional transistor (MS4) may be connected to the drain and gate of the reset transistor (MRST). The row select transistor (MSEL) may be closed and the column output may be connected to ground. Each pixel circuit preferably includes an output (vlg_out) connected between the drain of the bias transistor (MVB) and the drain of the source follower transistor (MSF).

[0021] Preferably, each pixel circuit is configured to generate a logarithmic output signal and further comprises a fourth additional switching transistor (MS4) connecting the drain and gate of the reset transistor (MRST), a first additional biasing transistor (MVB) connected between the second voltage source (vdd) and the source follower transistor (MSF), and a third additional transistor (MS3) connecting the reset transistor (MRST) to the first power supply (vrst). Each pixel circuit preferably further comprises a second additional transistor (MS2) connecting the biasing transistor (MVB) to the reset transistor (MRST). Preferably, the second additional transistor (MS2) is disconnected, and preferably, the row select transistor (MSEL) is closed, and the logarithmic output is available on the column output. In other words, the logarithmic output can be read from the column output.

[0022] According to one aspect of the present invention, an image sensor includes a plurality of pixel circuits, each of which includes: a photodiode connected between a ground and a floating diffusion (FD) node; a reset transistor (MRST) connected between a first voltage source and a floating diffusion (FD) node; a source follower transistor (MSF) wherein its drain is configured to be connected to a second voltage source, its gate is connected to the floating diffusion (FD) node, and its source is connected to a row select transistor (MSEL); and a row select transistor (MSEL) connected between the source of the source follower transistor (MSF) and a common column output, wherein each pixel circuit is configured to output an output signal corresponding to light incident on the photodiode. Each pixel circuit includes at least one additional transistor for configuring each pixel circuit to selectively output a linear integral signal or a logarithmic signal. Each pixel circuit also includes: a first additional bias transistor (MVB), which is connected between the second voltage source and the drain of the source follower transistor (MSF), and a second additional transistor (MS2), which is configured to connect the drain of the bias transistor (MVB) to the drain of the reset transistor (MRST), and a third additional transistor (MS3), which is configured to connect the reset transistor (MRST) to the first power supply, and a fourth additional transistor (MS4), which is configured to connect the drain of the reset transistor (MRST) to the gate. When each pixel circuit is configured to generate a logarithmic output signal, the second additional transistor (MS2) connects the drain of the bias transistor (MVB) to the drain of the reset transistor (MRST), and the third additional transistor (MS3) is disconnected, and the fourth additional transistor (MS4) connects the drain and gate of the reset transistor (MRST), wherein the row select transistor (MSEL) is closed and the column output is connected to ground, and wherein each pixel circuit includes an output (vlg_out) connected between the bias transistor (MVB) and the source follower transistor (MSF).

[0023] According to one aspect of the present invention, an image sensor includes a plurality of pixel circuits, each of which includes: a photodiode connected between a ground and a floating diffusion (FD) node; a reset transistor (MRST) configured to be connected between a first voltage source and a floating diffusion (FD) node; a source follower transistor (MSF) wherein its drain is configured to be connected to a second voltage source, its gate is connected to the floating diffusion (FD) node, and its source is connected to a row select transistor (MSEL); and a row select transistor (MSEL) connected between the source of the source follower transistor (MSF) and a common column output. Each pixel circuit is configured to output an output signal corresponding to light incident on the photodiode. Each pixel circuit includes at least one additional transistor for configuring each pixel circuit to selectively output a linear integral signal or a logarithmic signal. Each pixel circuit further comprises: a bias transistor (MVB) connected between a second voltage source and a drain of a source follower transistor (MSF); a second additional transistor (MS2) configured to connect the drain of the bias transistor (MVB) to the drain of a reset transistor (MRST); and a third additional transistor (MS3) configured to connect the reset transistor (MRST) to a first power supply; and a fourth additional switch transistor (MS4) configured to connect the drain and gate of the reset transistor (MRST). When each pixel circuit is configured to generate a logarithmic output signal, the fourth additional switch transistor (MS4) connects the drain and gate of the reset transistor (MRST), the third additional transistor (MS3) connects the reset transistor (MRST) to the first power supply, and wherein the second additional transistor (MS2) is open, and the row select transistor (MSEL) is closed, and the logarithmic output is available on the column output.

[0024] Preferably, at least one additional diode-connected transistor is connected in series with the second additional transistor (MS2) and is configured to multiply the gain in the logarithmic conversion configuration; or at least one additional diode-connected transistor is connected in parallel with the third additional transistor (MS3) and is configured to multiply the gain in the logarithmic conversion configuration.

[0025] Preferably, during different time intervals, the at least one transistor is configured to sequentially configure the plurality of pixel circuits in an alternate configuration.

[0026] Preferably, at least one transistor is configured to independently configure a standby configuration for each of a plurality of pixel circuits or for a subset of a plurality of pixel circuits, or at least one transistor is configured to independently configure a standby configuration for each of a plurality of pixel circuits or for a subset of a plurality of pixel circuits based on a previous output signal.

[0027] A combined linear logarithmic integration configuration may be implemented as an additional configuration. During the integration phase, optional transistor MTX is closed (ON), MS3 is closed (ON), and the gate of MRST is connected to a common control voltage via the power supply of gate X1. The circuit output is from the source of MSF via transistor MSEL.

[0028] Image sensors are made up of multiple semiconductor layers, where each layer is optimized for the function at that level.

[0029] Preferably, the image sensor is formed of a plurality of semiconductor layers, wherein the second layer contains at least one additional transistor and the first layer includes the photodiode and the remaining transistors.

[0030] Additional reconfiguration switches may connect respective floating diffusion nodes (FD) between subsets of adjacent pixels.

[0031] This may increase the gain from illumination intensity to output at the expense of reduced resolution.The configuration may be electrically reconfigured from time to time in operation, and may optionally depend on the mode of operation or lighting conditions.

[0032] A quasi-continuous pixel local output can be created by repeating short linear integration times. Another transistor MVC can be added, its source connected to ground, its gate connected to a reference voltage vc, and its drain connected to the source of MSF. The MVC provides a local current sink, and the pixel local output vln_out is available at the drain of the MVC. The MVC can also be called a bias transistor.

[0033] High quality logarithmic frame output can additionally be obtained in the electrical reconfiguration.

[0034] In one embodiment, each pixel circuit may further include a row select transistor (MSEL2) connected between the drain of MSF and the column output, and a fifth additional transistor (MS5) connecting the source of the source follower transistor (MSF) to ground.

[0035] Preferably, each pixel circuit also includes a second source follower transistor (MSF2) and a row selection transistor (MSEL2), wherein the gate of MSF2 is connected to the drain of MSF, its drain is connected to the second voltage (vdd), and its source is connected to the drain of the row selection transistor (MSEL2), and the source of the row selection transistor is connected to the column output, and a fifth additional transistor (MS5), which connects the source of the source follower transistor (MSF) to ground.

[0036] Each pixel circuit may also include a second source follower transistor (MSF2) and a row select transistor (MSEL2), wherein the gate of MSF2 is connected to the drain of MSF, its drain is connected to the second voltage (vdd), and its source is connected to the drain of the row select transistor (MSEL2), and the source of the row select transistor is connected to an additional column output.

[0037] In summary, high-quality logarithmic frame output can be additionally obtained in electrical reconfiguration. In one embodiment, the voltage vlg_out is connected to the column line via an additional row select transistor (MSEL2), and the source of MSF is switched to ground via an additional switch MS5. In another embodiment, the voltage vlg_out is connected to the existing column line via a second source follower (MSF2) and a row select transistor (MSEL2), and the source of MSF is switched to ground via an additional switch MS5. In another embodiment, the voltage vlg_out is connected to an additional column line via a second source follower (MSF2) and a row select (MSEL2).

[0038] The invention also comprises a corresponding method. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] The present invention is described with reference to the following drawings.

[0040] Figure 1a shows a linear 3T image sensor circuit according to the prior art,

[0041] Figure 1b shows a logarithmic image sensor circuit according to the prior art,

[0042] Figure 2 shows a reconfigurable linear and logarithmic output circuit according to the prior art,

[0043] Figure 3 shows a logarithmic output circuit according to the prior art,

[0044] Figure 4 shows a combined linear and logarithmic circuit according to the prior art,

[0045] Figure 5 A circuit with a counting method according to the prior art is shown,

[0046] Figure 6 shows a linear 4T image sensor according to the prior art,

[0047] Figure 7a and Figure 7b shows a logarithmic circuit according to an embodiment of the present disclosure,

[0048] Figures 8a to 8c shows a logarithmic circuit according to an embodiment of the present disclosure,

[0049] Fig. 9 shows a circuit according to an embodiment of the present disclosure,

[0050] Figure 9a , Figure 9b and Fig.9c Shows Fig. 9 circuits and configurations corresponding to a linear integration mode, a first logarithmic mode and an alternative logarithmic mode, respectively,

[0051] Figures 10 to 13 Circuits according to various embodiments of the present disclosure are shown. DETAILED DESCRIPTION

[0052] The same reference numerals in the drawings represent the same or similar elements. If not otherwise indicated, the drawings may also show the same circuit with the same or similar elements or parts of the corresponding drawings. Since the switch functions described below can be implemented by transistors, the terms switch and transistor may be used interchangeably.

[0053] Figure 1a and Figure 1b Schematically shows a pixel of a classic Lin-Log image sensor (Lin-Log: linear logarithmic) in a 3T pixel example (3T: three transistors) disclosed in N. Tu et al., "CMOS active pixel sensor with combined linear and logarithmic mode operation" (Proceedings of the Canadian IEEE Conference on Electrical and Computer Engineering, 1998, pp. 754-757). Figure 1aIn the linear integration mode shown, the pixel is reset by turning on the reset transistor MRST. After turning off the reset transistor MRST, and after a certain integration time, the charge on the photodiode is read out by an amplifier including an intra-pixel source follower MSF by turning on the row select transistor MSEL. The readout transistor MSF is configured as a source follower and acts as a buffer that allows the pixel voltage to be observed without removing the accumulated charge. Its power supply vdd is usually the same as the power supply vrst of the reset transistor. The output voltage drop read from the reset value is proportional to the light intensity and the integration time.

[0054] exist Figure 1b In the logarithmic mode shown, the gate of the reset transistor MRST is connected to the supply voltage vrst and operates in the weak inversion region. In this region, the drain-source voltage drop across the transistor has a logarithmic relationship with the current set by the photodiode. As in the linear mode, the voltage across the transistor is transferred to the output via the source follower MSF and the select transistor MSEL.

[0055] Figure 6 A 4T pixel is shown, which includes the same elements as the 3T pixel, but adds a transfer gate MTX between the floating diffusion node FD and the photodiode PD. The reset transistor MRST is closed, and the transfer gate MTX resets the floating diffusion node FD and the photodiode potential to a voltage vrst, which may correspond to the power supply voltage vdd, thereby clearing all integrated charges. Since the reset transistor is n-type, this operation is a soft reset, and the final potential is a threshold voltage lower than vrst.

[0056] Charge integration is performed with MTX off, and the charge is transferred to the floating diffusion (FD) node by turning MTX on after the integration time. Additionally, source follower MSF and select transistor MSEL again select a single row of the pixel array to be read by the readout electronics.

[0057] There are other configurations of pixels, such as 5T and 6T pixels. By adding additional transistors, functions such as a global shutter as opposed to the more common rolling shutter are possible.

[0058] Figure 1b The logarithmic mode shown has the following disadvantages: (i) the signal is related to the power supply, and (ii) the logarithmic output is presented on the column lines and is not directly available for local processing.

[0059] It is known to select a logarithmic configuration which provides an improved response. J. Guo et al. (2008, Sensors, 2008 IEEE) provide electrical reconfiguration between linear and logarithmic modes, but without pixel local output. This is Figure 2As shown in Figure 3 As depicted, P. Lichtsteiner et al. (2008, IEEE Journal of Solid-State Circuits, Vol. 43, No. 2, February 2008) provide pixel local outputs, but without the ability to reconfigure between linear and logarithmic configurations.

[0060] Such a configuration exists (see Figure 4 ), W. Chou et al. (2012, Sensors, 2012 IEEE) provide a combined linear-logarithmic response without reconfiguration, which has a linear response under low illumination intensity conditions and a logarithmic response under high illumination intensity. These image sensors provide high dynamic range response, but do not provide continuous pixel local output for low latency event-based sensing.

[0061] Methods with multiple exposure times (SD Freedman, 2015, 2nd International Conference on Knowledge-Based Engineering and Innovation (KBEI)) and time-based transformation methods (e.g., based on Figure 5 , M. Goto et al., 2016, 2016 IEEE SOI-3D Subthreshold Microelectronics Unified Conference (S3S)) alternatives, the time-based conversion method provides a logarithmic photoresponse and extends the dynamic range of image sensors. These configurations are not suitable for providing continuous pixel local output for low-latency event-based sensing.

[0062] Figure 6 A pixel conceptual circuit configuration of an image sensor according to a 4T configuration is schematically shown. This mode provides a linear integration mode in which transistors MRST, MSF, MSEL, and MTX are used in their standard functional manner. This configuration can be used for both global shutter mode and rolling shutter mode. MTX can be omitted to operate as a 3T circuit.

[0063] Some foundry standard cells provide additional functionality, for example, additional gain ranges, implemented by additional transistors creating 5T, 6T, ... nT structures. The present invention is compatible with these extensions of standard cells.

[0064] The operation of the pixel in this configuration consists of four phases. (i) In the FD reset phase, the reset signal is high and transistor MRST is turned on. The FD node is connected to vrst and any integrated charge from the previous cycle is drained. (ii) In the PD charge accumulation phase, MTX is turned off and when light is incident, photogenerated carriers accumulate in the PD. (iii) In the PD charge transfer phase, MTX is turned on and the accumulated charge is transferred from the PD to the FD and converted into voltage. (iv) In the FD voltage readout phase, MSEL is activated and the transferred charge is held on the FD. When the select (sel) signal is high, the FD voltage is read out to the column line via the buffered source follower transistor MSF.

[0065] Figure 7a A pixel circuit configuration of an image sensor according to the present invention is schematically shown, which enables a logarithmic mode in which readout occurs at the vlg_out output. MRST, MSF, and MSEL are reused components of the 4T circuit described above. The photodiode PD is connected between ground and the node FD. The gate of the source follower transistor MSF is connected to the node FD, its drain is connected to the output line vlg_out, and its source is connected to the ground. The source of the bias transistor MVB is connected to the output line vlg_out, its gate is connected to the bias voltage vb, and its drain is connected to the power supply voltage vdd. Transistor MRST is connected as a diode-connected transistor, its drain is connected to the output line vlg_out, and its source is connected to the node FD.

[0066] The current I through the transistor MRST PD It is given by the current flowing through the photodiode PD. MRST works in a weak inversion mode, and the relationship between its current and voltage is given by:

[0067]

[0068] Therefore, the signal vlg_out is I PD The logarithmic function of plus a constant offset given by the bias:

[0069] vlg_out≈nU T ln(I PD / I D0 )+V FD +V TH

[0070] Among them, I D0 When vlg_out-V FD = V of the MSF transistor TH IPD current, n is the slope factor, U T is the thermal voltage, and V TH is the threshold voltage of MRST. Therefore, the current I through transistor MRST PD This is converted into a well-defined output voltage on the output line vlg_out.

[0071] about Figure 1b The logarithmic mode shown is advantageous because it includes a feedback amplification loop and, in particular, has the following advantages:

[0072] -Pixel local output signals suitable for continuous operation and low-latency event response generation;

[0073] - Reduced noise;

[0074] - Improved output drive speed, especially at low photodiode currents;

[0075] - Improved load and noise independence of the output;

[0076] - a fixed bias voltage of the photodiode given constant operating conditions;

[0077] -Immunity to power supply coupled noise.

[0078] about Figure 3 The logarithmic mode shown is advantageous because it provides:

[0079] - The reduced drain-source voltage on transistor MRST suppresses drain-source and drain-bulk leakage in this transistor, which is reused from a standard 4T structure.

[0080] - Transistor configurations that can be obtained with a standard set of additional switches.

[0081] Figure 3 The logarithmic mode shown can be realized by selectively connecting switch MS4 between the drain of transistor MSF and the gate of transistor MRST.

[0082] In the conceptual circuit, optionally, additional diode-connected transistors can be added in series with transistor MRST. These transistors operate in the same way and provide a multiplied voltage gain. These transistors are not reused from factory standard cells and imply additional cost (area), but are compatible with the present invention.

[0083] Preferably, at least one additional diode-connected transistor is connected in series with the second additional transistor (MS2) and is configured to multiply the gain in the logarithmic conversion configuration, or at least one additional diode-connected transistor is connected in parallel with the third additional transistor (MS3) and is configured to multiply the gain in the logarithmic conversion configuration. Figure 7b Shown in.

[0084] Figure 8a Schematically shows another pixel circuit configuration of an image sensor according to the present invention that can be realized when the pixel circuit is reconfigured. Figure 1b , the third pixel configuration provides a selected logarithmic mode equivalent to the mode reported in the prior art. In this mode, the photocurrent flows through the transistor MRST and the readout of the floating diffusion node FD occurs by closing the row selection transistor MSEL. The photodiode PD is connected between the ground and the floating diffusion node FD. The gate of the source follower transistor MSF is connected to the floating diffusion node FD, its drain is connected to the power supply voltage vdd, and its source is connected to the row selection transistor MSEL. The gate and drain of the transistor MRST are connected to the log power supply voltage vrst, and its source is connected to the floating diffusion node FD.

[0085] The selection of the logarithmic mode is enabled by the current invention without additional transistors in the pixel circuit. In some embodiments, it may also be advantageous to extend the dynamic range of frame image operations without additional cost (ie silicon area).

[0086] like Figure 8c As shown, the logarithmic configuration can be combined with the linear integration configuration. The operation of the pixel in this combined log-lin case consists of three stages. (i) In the FD reset stage, transistor MRST is turned on. The FD node is connected to vrst and any integrated charge from the previous cycle is drained. (ii) In the PD charge accumulation stage, photogenerated carriers accumulate on node FD and are converted into voltage. As shown in FIG. Figure 8c As shown, the gate of MRST is connected to the lower control voltage via the lower power supply of gate X1. When the FD voltage is discharged to a sufficiently low voltage by the photodiode current, MRST starts to conduct. (iv) In the FD voltage readout phase, MRST is turned off, MSEL is activated, and the transferred charge is held on FD. When the signal sel is high, the FD voltage is read out to the column line via MSF.

[0087] The response of the circuit at low illumination intensities is linear because the MRST does not conduct, and the FD voltage changes in proportion to the illumination intensity and the integration time. At high illumination intensities, the MRST provides a logarithmic voltage response, and the FD voltage is a logarithmic function of the intensity.

[0088] This configuration is well known and is compatible with the current invention. This is advantageous because it provides additional dynamic range for the frame image data. Since the isolation provided by the factory standard transfer transistor MTX is not used, the linear response is degraded.

[0089] As in the first logarithmic mode described above, in the conceptual circuit of the standby configuration, additional diode-connected transistors can be added, connected in series with transistor MRST. These transistors operate in the same manner and provide a multiplied voltage gain. These transistors are not reused from factory standard cells and mean additional cost (area), but are compatible with the present invention.

[0090] Fig. 9 The pixel circuit shown has Figure 6 The first pixel configuration of the first linear integration mode has a first pixel configuration according to Figure 7a The second pixel configuration of the optimized integration mode, and the Figure 8a A third pixel configuration of the selected logarithmic mode can be achieved.

[0091] The core is Figure 6 4T pixel and is shown in the lower dashed box in the figure. The photodiode PD and transistors MRST, MSF and MSEL are part of the 4T unit. The upper dashed box shows an additional circuit for providing reconfiguration of the pixel, which consists of four transistors (MS2, MS3, MS4, MVB) and a logic gate X1.

[0092] The photodiode PD is connected to the floating diffusion node FD via the emission transistor MTX.

[0093] Transistor MRST is connected between floating diffusion node FD and second switch MS3, which is also connected to supply voltage vrst. The gate of MRST is connected to the output of tri-state logic gate X1. Operation of X1, MRST and MS3 provides a reset path for node FD.

[0094] The switch MS4 also connects the gate and drain of the transistor MRST. This connection is used to allow the transistor MRST to be reused as a transistor for converting a linear photocurrent into a logarithmic voltage in a logarithmic mode.

[0095] The gate of transistor MSF is connected to floating diffusion node FD, the source is connected to select switch transistor MSEL, and the drain is connected to the drain of transistor MVB, which in turn is connected to power supply vdd. In a configuration using this function, transistor MSF creates a source follower circuit to copy the voltage on node FD to the column line.

[0096] The source of transistor MVB is connected to power supply vdd, the drain is connected to output node vlg_out, and the gate is connected to signal vb. The transistor acts as a switch (on) in configurations where the source follower function of MSF is required, and acts as a current source where the output on vlg_out is required.

[0097] The switch MS2 is connected between the drain of the transistor MRST and vlg_out, and is closed in the first logarithmic mode.

[0098] Reconfigurable circuitry provides high quality (low noise at low light) image data frame output as well as high dynamic range and low noise continuous data for event generation from the same pixel array.

[0099] Reuse of the 4T units provided by the manufacturer is advantageous because:

[0100] - These units are provided in the form of optimized areas, including process technology optimization of the optimized areas;

[0101] - The units are provided in a form factor optimized for performance, including process technology optimization for optimized performance;

[0102] - Characterization information is available for these units;

[0103] -Reliability information is available for these units;

[0104] - Yield information is available for these units;

[0105] -The manufacturer is committed to maintaining the unit's performance specifications over changes in technology;

[0106] - Facilitates migration of designs from one process node to the next through the availability of characterization information.

[0107] In linear integration mode (see Figure 6 ), MS2, MS4, and MS5 are open, while MS3 and MVB are closed. MRST acts as a reset transistor, and MTX, MSF, and MSEL have their usual functions during linear operation. The effective circuit is similar to Figure 6 match. Figure 9a Shows Fig. 9, and shows a linear integration mode, where MS2 and MS4 are in the open position, and MS3 is in the closed position.

[0108] In the first logarithmic mode (see Figure 7a ), MS3 is open, X1 is inactive, and MS2, MS4, and MTX are closed. The bias voltage vb is connected to a configurable bias voltage. The transistor MSEL is short-circuited by connecting the control signal sel to the power supply voltage vdd, and the column line is connected to ground. The effective circuit is Figure 7a Therefore, the photocurrent IPD through MTX and MRST is continuously converted into the output voltage vlg_out, giving a logarithmic response. Figure 9b Shows Fig. 9 , and shows a first logarithmic mode, wherein MS2 and MS4 are in a closed position, and MS3 is in an open position.

[0109] In one embodiment, the voltage vlg_out is used locally for in-pixel processing. In another embodiment, the voltage vlg_out is connected to the column line via an additional row select transistor (MSEL2), and the source of MSF is switched to ground by an additional switch MS5. In another embodiment, the voltage vlg_out is connected to the existing column line via a second source follower (MSF2) and a row select transistor (MSEL2), and the source of MSF is switched to ground by an additional switch MS5. In another embodiment, the voltage vlg_out is connected to an additional column line via a second source follower (MSF2) and a row select (MSEL2).

[0110] In the select log mode, MS2 is open, X1 is inactive, and MS3, MS4, MTX, and MVB are closed. MSEL is used as a row select, and the log voltage is continuously available on the column line when the row is selected. The effective circuit in this configuration is the same as Figure 1b This configuration mode is compatible with existing pixel evaluation on column lines without additional transistors. Fig.9c Shows Fig. 9 , and shows the selection of the logarithmic mode, wherein MS3 and MS4 are in the closed position, and MS2 is in the open position.

[0111] The image sensor can electrically reconfigure the entire pixel arrangement between alternate configurations from time to time. This is advantageous for providing different data qualities from the same image sensor, for example, high-quality low-light frame image data and low-latency dynamic response.

[0112] The image sensor can also electrically reconfigure different regions (subsets of pixels) in different configurations simultaneously, where the subsets can change from time to time. This facilitates obtaining data of different qualities from different regions of the image simultaneously.

[0113] The image sensor can switch the configuration of the entire pixel arrangement or a subset of the pixel arrangement based on the image output over the previous time interval. This is beneficial for providing high quality data under changing lighting conditions.

[0114] In another embodiment, an additional reconfiguration switch connects equivalent FD nodes between subsets of adjacent pixels, which is a logarithmic configuration that enables a single readout MRST transistor. In this way, multiple photodiodes are connected in parallel, increasing the total photodiode current through the active MRST transistor and resulting in a larger voltage and more gain from illumination intensity to output voltage. This is advantageous because it improves the signal-to-noise ratio and improves response speed.

[0115] exist Fig.10 In another embodiment shown, a quasi-continuous pixel local output is created based on a linear integration configuration by implementing repeated short linear integration times. Another transistor MVC is added, with its source connected to ground, its gate connected to a reference voltage vc, and its drain connected to the source of MSF. MVC provides a local current sink, and the pixel local output is available at the drain of MVC.

[0116] This embodiment is advantageous because it reduces noise in the operation of local sequential processing of pixels at lower illumination intensities. Combined with logarithmic processing at higher light levels, this provides an extended dynamic range for local processing and low latency response.

[0117] The response speed is reduced (increased latency) in this operation, but the speed is still higher than full frame output.

[0118] according to Figures 11 to 13 In another configuration depicted, in an electrical reconfiguration, a high quality logarithmic frame output can additionally be obtained. Fig.11 In one example shown, the voltage vlg_out is connected to the column line via an additional row select transistor (MSEL2), and the source of MSF is switched to ground by an additional switch MS5. Fig.12 In another example, the voltage vlg_out is connected to an existing column line via a second source follower (MSF2) and a row select transistor (MSEL2), and the source of MSF is switched to ground by an additional switch MS5. In another embodiment, the voltage vlg_out is connected to an additional column line via a second source follower (MSF2) and a row select (MSEL2).

[0119] In one embodiment, the image sensor integrated circuit is formed from a single semiconductor layer.

[0120] In another embodiment, the image sensor is formed of multiple semiconductor layers, wherein the type of semiconductor process for each layer is optimized for the function of the layer.

[0121] This embodiment is advantageous because the optimization of the function of the semiconductor process allows for (i) improvement in performance, (ii) reduction in silicon area, and, subsequently, reduction in device size and device cost. The altered physical structure improves optical performance in terms of (i) fill factor, (ii) quantum efficiency, and reduces electrical interference between control signal lines and photosensor circuits.

[0122] In particular, a fab standard base cell can be implemented on one semiconductor layer, wherein the semiconductor layer is optimized for optical performance as well as cell density and fill factor. Additional switching transistors are implemented in additional semiconductor layers.

[0123] The proposed structure provides a reconfiguration with a limited number of connections between the semiconductor layers of each pixel. Fig. 9 , three connections are required per pixel to implement all described configurations.

[0124] In summary, the linear integration mode is used for high sensitivity at low light levels and frame mode operation, as in a classic 4T pixel. For frame mode operation, the dynamic range can be extended using the selected logarithmic mode at no additional cost (area) or using the first logarithmic mode to improve performance at an additional cost (area).

[0125] The first logarithmic mode provides a high quality continuous output signal for pixel local processing suitable for generating event responses.

[0126] The operating mode is achieved by low-cost electrical reconfiguration of factory standard 3T or 4T circuits, providing both high quality frame image data and local high quality logarithmic response of consecutive pixels for event processing from the same pixel array.

[0127] The use of the same array for both linear and logarithmic modes of operation is advantageous because:

[0128] - Geographical correlation of frame image data and event data is simple, since the same pixels are used. No precise and time-stable and vibration-stable alignment or calibration of multiple image systems (optics) or compensation of optical aberrations and distortions or chromatic response is required.

[0129] - In some embodiments, the requirement for a second image sensor is removed, reducing camera size, power consumption and cost, and improving reliability.

[0130] Multiple pixels are typically organized in a two-dimensional grid with "rows" and "columns." It should be noted that the definitions of "rows" and "columns" can be interchanged without affecting the present invention. It should also be noted that other geometric configurations mapped to a two-dimensional grid are feasible without affecting the applicability of the present invention.

[0131] The configuration according to the embodiments described above may be electrically reconfigured from time to time in operation, and optionally may depend on the operating mode or lighting conditions.

[0132] Other aspects, features, and advantages will be apparent from the above summary and from the description including the drawings and claims.

[0133] Although the invention has been illustrated and described in detail in the drawings and the foregoing description, such illustration and description are to be considered illustrative or exemplary rather than restrictive. It should be understood that changes and modifications may be made by those of ordinary skill within the scope of the following claims. In particular, the present invention encompasses additional embodiments having any combination of the different embodiments described above and the following features.

[0134] Furthermore, in the claims, the word "comprising" does not exclude other elements or steps, and the indefinite article "a" or "an" does not exclude a plurality. A single unit may fulfill the functions of several features recited in the claims. In particular, the terms "substantially", "about", "approximately" and the like related to an attribute or value also precisely define the attribute or precisely define the value, respectively. Any reference signs in the claims should not be construed as limiting the scope.

Claims

1. An image sensor, comprising a plurality of pixel circuits, each of the plurality of pixel circuits comprising: a photodiode connected between ground and a floating diffusion (FD) node, a reset transistor (MRST) connected between a first voltage source and the floating diffusion (FD) node, a source follower transistor (MSF), wherein the drain of the source follower transistor (MSF) is connected to the second voltage source, the gate is connected to the floating diffusion (FD) node, and the source is connected to the first row select transistor (MSEL), and The first row select transistor (MSEL) is connected between the source of the source follower transistor (MSF) and a common column output, wherein each pixel circuit is configured to output an output signal corresponding to light incident on the photodiode; and wherein each pixel circuit comprises at least one additional transistor for configuring each pixel circuit to selectively output a linear integral signal or a logarithmic signal; wherein each pixel circuit is configured to generate a logarithmic output signal and further comprises a first additional bias transistor (MVB) connected between the second voltage source and the drain of the source follower transistor (MSF), and a second additional transistor (MS2) connecting the drain of the first additional bias transistor (MVB) to the drain of the reset transistor (MRST), and a third additional transistor (MS3) added, the third additional transistor (MS3) connecting the reset transistor (MRST) to the first voltage source, and a fourth additional transistor (MS4) connecting the drain and the gate of the reset transistor (MRST), wherein the first row select transistor (MSEL) is closed and the column output is connected to ground, and Therein, each pixel circuit comprises an output (vlg_out) connected between the first additional bias transistor (MVB) and the source follower transistor (MSF).

2. The image sensor according to claim 1, wherein: Each pixel circuit also includes a transfer gate transistor (MTX) connected between the photodiode and the floating diffusion (FD) node.

3. The image sensor according to claim 1, wherein: The third additional transistor (MS3) is off.

4. The image sensor according to claim 2, wherein: The third additional transistor (MS3) is off.

5. The image sensor according to claim 1, wherein: The second additional transistor (MS2) is off.

6. The image sensor according to claim 2, wherein: The second additional transistor (MS2) is off.

7. An image sensor, comprising a plurality of pixel circuits, each of the plurality of pixel circuits comprising: a photodiode connected between ground and a floating diffusion (FD) node, a reset transistor (MRST) configured to be connected between a first voltage source and the floating diffusion (FD) node, a source follower transistor (MSF), wherein a drain of the source follower transistor (MSF) is configured to be connected to a second voltage source, a gate of the source follower transistor (MSF) is connected to the floating diffusion (FD) node, and a source of the source follower transistor (MSF) is connected to the first row select transistor (MSEL), and The first row select transistor (MSEL) is connected between the source of the source follower transistor (MSF) and a common column output, wherein each pixel circuit is configured to output an output signal corresponding to light incident on the photodiode; and wherein each pixel circuit comprises at least one additional transistor for configuring each pixel circuit to selectively output a linear integral signal or a logarithmic signal, Wherein, each pixel circuit further includes: a first additional biasing transistor (MVB) connected between the second voltage source and the drain of the source follower transistor (MSF), and a second additional transistor (MS2) configured to connect the drain of the first additional bias transistor (MVB) to the drain of the reset transistor (MRST), and a third additional transistor (MS3) configured to connect the reset transistor (MRST) to the first voltage source, and a fourth additional transistor (MS4) configured to connect the drain of the reset transistor (MRST) to the gate, Wherein, when each pixel circuit is configured to generate a logarithmic output signal, The second additional transistor (MS2) connects the drain of the first additional bias transistor (MVB) to the drain of the reset transistor (MRST), and The third additional transistor (MS3) is off, and The fourth additional transistor (MS4) is connected to the drain and gate of the reset transistor (MRST), wherein the first row select transistor (MSEL) is closed and the column output is connected to ground, and Therein, each pixel circuit comprises an output (vlg_out) connected between the first additional bias transistor (MVB) and the source follower transistor (MSF).

8. An image sensor, comprising a plurality of pixel circuits, each of the plurality of pixel circuits comprising: a photodiode connected between ground and a floating diffusion (FD) node, a reset transistor (MRST) configured to be connected between a first voltage source and the floating diffusion (FD) node, a source follower transistor (MSF), wherein a drain of the source follower transistor (MSF) is configured to be connected to a second voltage source, a gate of the source follower transistor (MSF) is connected to the floating diffusion (FD) node, and a source of the source follower transistor (MSF) is connected to the first row select transistor (MSEL), and The first row select transistor (MSEL) is connected between the source of the source follower transistor (MSF) and a common column output, wherein each pixel circuit comprises an output (vlg_out) and is configured to output an output signal corresponding to light incident on the photodiode; and wherein each pixel circuit comprises at least one additional transistor for configuring each pixel circuit to selectively output a linear integral signal or a logarithmic signal, Wherein, each pixel circuit further includes: a bias transistor (MVB) connected between the second voltage source and the drain of the source follower transistor (MSF), a second additional transistor (MS2) configured to connect the drain of the bias transistor (MVB) to the drain of the reset transistor (MRST), and a third additional transistor (MS3) configured to connect the reset transistor (MRST) to the first voltage source, and a fourth additional transistor (MS4) configured to connect the drain and gate of the reset transistor (MRST), wherein when each pixel circuit is configured to generate a logarithmic output signal, The fourth additional transistor (MS4) is connected to the drain and gate of the reset transistor (MRST), The third additional transistor (MS3) connects the reset transistor (MRST) to the first voltage source, and wherein the second additional transistor (MS2) is disconnected, and The first row select transistor (MSEL) is closed and a logarithmic output is available on the column output.

9. The image sensor according to any one of claims 1 to 8, wherein: at least one additional diode-connected transistor connected in series with said second additional transistor (MS2) and configured to multiply the gain in a logarithmic conversion configuration, or Therein, at least one additional diode-connected transistor is connected in parallel with the third additional transistor (MS3) and is configured to multiply the gain in the logarithmic conversion configuration.

10. The image sensor according to any one of claims 1 to 8, wherein: During different time intervals, the at least one additional transistor is configured to sequentially configure the plurality of pixel circuits in an alternate configuration.

11. The image sensor according to claim 10, wherein: The at least one additional transistor is configured to independently configure the alternate configuration for each of the plurality of pixel circuits or for a subset of the plurality of pixel circuits.

12. The image sensor according to claim 11, wherein: The at least one additional transistor is configured to independently configure the alternate configuration for each of the plurality of pixel circuits or for a subset of the plurality of pixel circuits based on a previous output signal.

13. The image sensor according to any one of claims 1 to 8 and 11 to 12, wherein: The image sensor is composed of multiple semiconductor layers, wherein each layer is optimized for the function of that layer.

14. The image sensor according to any one of claims 1 to 8 and 11 to 12, wherein: The image sensor is composed of a plurality of semiconductor layers, wherein the second layer includes at least the at least one additional transistor and the first layer includes the photodiode and the remaining transistors.

15. The image sensor according to any one of claims 1 to 8 and 11 to 12, wherein: Additional reconfiguration switches connect respective floating diffusion nodes (FD) between subsets of adjacent pixels.

16. The image sensor according to any one of claims 1 to 8 and 11 to 12, wherein: Each pixel circuit further comprises a bias transistor (MVC), wherein the bias transistor (MVC) is connected between ground and the source follower transistor (MSF) and a voltage (vc) is connected to a gate of the bias transistor.

17. The image sensor according to any one of claims 1 to 8 and 11 to 12, wherein: Each pixel circuit further comprises a second row select transistor (MSEL2) connected between the output (vlg_out) and the column output, and a fifth additional transistor (MS5) connecting the source follower transistor (MSF) to ground.

18. The image sensor according to any one of claims 1 to 8 and 11 to 12, wherein: Each pixel circuit also includes a second source follower transistor (MSF2) and a second row select transistor (MSEL2) connecting an output (vlg_out) to the column output, and a fifth additional transistor (MS5) connecting the source follower transistor (MSF) to ground.

19. The image sensor according to any one of claims 1 to 8 and 11 to 12, wherein: Each pixel circuit also includes a second source follower transistor (MSF2) and a second row select transistor (MSEL2) connecting the output (vlg_out) to an additional column output.

20. A method for reconfiguring an image sensor comprising a plurality of pixel circuits, the method comprising: Providing a photodiode connected between ground and a floating diffusion (FD) node, providing a reset transistor (MRST) connected between a first voltage source and the floating diffusion (FD) node, providing a source follower transistor (MSF), wherein the drain of the source follower transistor (MSF) is connected to the second voltage source, the gate is connected to the floating diffusion (FD) node, and the source is connected to the first row select transistor (MSEL), and connecting the first row select transistor (MSEL) between the source of the source follower transistor (MSF) and a common column output, outputting an output signal corresponding to light incident on the photodiode; and Configuring each pixel circuit to selectively output a linear integral signal or a logarithmic signal using at least one additional transistor, configuring each pixel circuit to selectively output a linear integral signal or a logarithmic signal using at least one additional transistor further comprises, connecting a first additional bias transistor (MVB) between the second voltage source and the drain of the source follower transistor (MSF); providing a second additional transistor (MS2) configured to connect the drain of the first additional bias transistor (MVB) to the drain of the reset transistor (MRST); providing a third additional transistor (MS3) configured to connect the reset transistor (MRST) to the first voltage source; and providing a fourth additional transistor (MS4) configured to connect the drain of the reset transistor (MRST) to the gate; wherein the first row select transistor (MSEL) is closed and the column output is connected to ground, and Therein, each pixel circuit comprises an output (vlg_out) connected between the first additional bias transistor (MVB) and the source follower transistor (MSF).

21. A method for reconfiguring an image sensor comprising a plurality of pixel circuits, the method comprising: Providing a photodiode connected between ground and a floating diffusion (FD) node, providing a reset transistor (MRST) connected between a first voltage source and the floating diffusion (FD) node, providing a source follower transistor (MSF), wherein the drain of the source follower transistor (MSF) is connected to the second voltage source, the gate is connected to the floating diffusion (FD) node, and the source is connected to the first row select transistor (MSEL), connecting the first row select transistor (MSEL) between the source of the source follower transistor (MSF) and a common column output, outputting an output signal corresponding to light incident on the photodiode; and Configuring each pixel circuit to selectively output a linear integral signal or a logarithmic signal using at least one additional transistor, configuring each pixel circuit to selectively output a linear integral signal or a logarithmic signal using at least one additional transistor further comprises, connecting a first additional bias transistor (MVB) between the second voltage source and the drain of the source follower transistor (MSF), and providing a second additional transistor (MS2) configured to connect the drain of the first additional bias transistor (MVB) to the drain of the reset transistor (MRST), and providing a third additional transistor (MS3) configured to connect the reset transistor (MRST) to the first voltage source, and providing a fourth additional transistor (MS4) configured to connect the drain of the reset transistor (MRST) to the gate, Wherein, when each pixel circuit is configured to generate a logarithmic output signal, The second additional transistor (MS2) connects the drain of the first additional bias transistor (MVB) to the drain of the reset transistor (MRST), The third additional transistor (MS3) is off, and The fourth additional transistor (MS4) is connected to the drain and gate of the reset transistor (MRST), wherein the first row select transistor (MSEL) is closed and the column output is connected to ground, and Therein, each pixel circuit comprises an output (vlg_out) connected between the first additional bias transistor (MVB) and the source follower transistor (MSF).

22. A method for reconfiguring an image sensor comprising a plurality of pixel circuits, the method comprising: Providing a photodiode connected between ground and a floating diffusion (FD) node, providing a reset transistor (MRST) connected between a first voltage source and the floating diffusion (FD) node, providing a source follower transistor (MSF), wherein the drain of the source follower transistor (MSF) is connected to the second voltage source, the gate is connected to the floating diffusion (FD) node, and the source is connected to the first row select transistor (MSEL), and connecting the first row select transistor (MSEL) between the source of the source follower transistor (MSF) and a common column output, outputting an output signal corresponding to light incident on the photodiode; and Configuring each pixel circuit to selectively output a linear integral signal or a logarithmic signal using at least one additional transistor, configuring each pixel circuit to selectively output a linear integral signal or a logarithmic signal using at least one additional transistor further comprises, connecting a bias transistor (MVB) between the second voltage source and the drain of the source follower transistor (MSF), providing a second additional transistor (MS2) configured to connect the drain of the bias transistor (MVB) to the drain of the reset transistor (MRST), and providing a third additional transistor (MS3) configured to connect the reset transistor (MRST) to the first voltage source, and providing a fourth additional transistor (MS4) configured to connect the drain of the reset transistor (MRST) to the gate, Wherein, when each pixel circuit is configured to generate a logarithmic output signal, The fourth additional transistor (MS4) is connected to the drain and gate of the reset transistor (MRST), The third additional transistor (MS3) connects the reset transistor (MRST) to the first voltage source, wherein the second additional transistor (MS2) is disconnected, and The first row select transistor (MSEL) is closed and a logarithmic output is available on the column output.

Images