Methods for improving process compatibility and reliability of embedded medium and high voltage devices

Abstract

The present invention provides a method for improving the process compatibility and reliability of embedded medium- and high-voltage devices. The method comprises providing a substrate, forming a sacrificial oxide layer on the substrate, and then forming a STI to define an active region, wherein first to third device regions are formed on the active region; forming a lightly doped drain on the second device region, and then forming a hard mask layer on the substrate to cover the first to third device regions; forming a photoresist layer on the hard mask layer, photolithographically opening the photoresist layer on the second device region to expose the underlying hard mask layer; etching the hard mask layer to expose the sacrificial oxide layer and a portion of the STI on the second device region; etching the exposed sacrificial oxide layer and STI to a predetermined step height and morphology; and etching back the exposed STI and substrate to a desired etchback depth. The present invention can improve the physical morphology, electrical properties, and reliability of low- and medium-voltage devices.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a method for improving process compatibility and reliability of embedded medium and high voltage devices. Background Art

[0002] At the 28nm technology node, High-K (high dielectric constant) materials and metal gate processes are widely used to meet the high performance and low power consumption requirements of devices. However, the HKMG (high dielectric constant metal gate) platform process requires chemical mechanical polishing (CMP) of the metal gate to remove excess metal, which places high demands on the sag control of large metal gates, especially in the 28HV metal gate platform of embedded medium and high voltage devices, such as Figure 1 As shown, the first to third device areas (A1, A2, A3) are formed on the substrate, and the first to third device areas are low-voltage, medium-voltage, and high-voltage device areas, respectively. The sizes of high-voltage (HV) and medium-voltage (MV) devices are much larger than those of the original HKMG platform devices. The metal gate depression problem has been improved in the industry by adding a slot method, and the height balance problem of the embedded medium- and high-voltage devices and the original low-voltage device metal gate during the CMP process is currently achieved by etching back the active area (AA) of the medium- and high-voltage devices; at the same time, before the formation of the low-voltage device gate oxide, HF solution is needed to remove the thick oxide layer brought about by the growth of the embedded medium-voltage device gate oxide. A large amount of HF solution will seriously deteriorate the physical morphology of the low-voltage device (mainly manifested as deterioration of the step height and morphology), further affecting the electrical properties and reliability of the device.

[0003] The current process solution for improving the step height and morphology degradation of low-voltage devices is to increase the step height as much as possible by compressing the STI-CMP process window and the amount of HF solution. However, this is still worse than the physical morphology of the corresponding devices on the mass production platform. In particular, to meet the customer's demand for an additional low-voltage device, the physical morphology of the platform's original low-voltage devices becomes even worse. At the same time, since the active area etch-back process of medium- and high-voltage devices is directly subject to the physical morphology before etching, the sharp corners of the active area after etch-back will become more serious, which poses a severe challenge to the electrical properties and reliability of the embedded medium- and high-voltage devices.

[0004] In order to solve the above problems, it is necessary to propose a new method to improve the process compatibility and reliability of embedded medium and high voltage devices. Summary of the Invention

[0005] In view of the shortcomings of the prior art described above, the purpose of the present invention is to provide a method for improving the process compatibility and reliability of embedded medium and high voltage devices, which is used to solve the problem of sharp corners in the active area caused by the back etching of the active area of ​​the medium and high voltage devices in the prior art to balance the metal gate height of the embedded medium and high voltage devices with that of the original low voltage devices, and the problem of serious deterioration of the physical morphology of the low voltage devices (mainly manifested as deterioration of step height and morphology) caused by the use of more HF solution to remove the thicker oxide layer before the formation of the gate oxide of the low voltage devices, as well as the problem of further affecting the electrical properties and reliability of the devices.

[0006] To achieve the above-mentioned and other related objectives, the present invention provides a method for improving the process compatibility and reliability of embedded medium and high voltage devices, comprising:

[0007] Step 1: providing a substrate, forming a sacrificial oxide layer on the substrate, and then forming STI to define an active area, wherein the first to third device regions are formed on the active area;

[0008] Step 2: forming a lightly doped source and drain on the second device region, and then forming a hard mask layer covering the first to third device regions on the substrate;

[0009] Step 3: forming a photoresist layer on the hard mask layer, photolithographically opening the photoresist layer on the second device region to expose the hard mask layer thereunder, and etching the hard mask layer to expose the sacrificial oxide layer and a portion of the STI on the second device region;

[0010] Step 4: etching the exposed sacrificial oxide layer and the STI so that the step height and morphology thereof are preset values;

[0011] Step 5: Etching back the exposed STI and the substrate to a desired etch back depth;

[0012] Step 6: Etching to adjust the step height and morphology on the second device region and remove the hard mask layer;

[0013] Step 7: forming a first gate oxide layer on the first and second device regions, and then removing the first gate oxide layer on the first device region;

[0014] Step eight: forming a second gate oxide layer on the first device region.

[0015] Preferably, the substrate in step 1 comprises a bulk semiconductor substrate or a silicon-on-insulator substrate.

[0016] Preferably, the first to third device regions in step one are low voltage, medium voltage and high voltage device regions respectively.

[0017] Preferably, the material of the sacrificial oxide layer in step 1 is silicon dioxide.

[0018] Preferably, the material of the hard mask layer in step 2 is silicon nitride.

[0019] Preferably, the etching method in step three is dry etching.

[0020] Preferably, the method of etching the exposed sacrificial oxide layer and the STI in step 4 includes: removing the byproducts of the dry etching by using a wet etching cleaning method; and then etching the exposed sacrificial oxide layer and the STI using an HF solution so that their step height and morphology are the preset values.

[0021] Preferably, the back etching method in step five is dry etching.

[0022] Preferably, the etching method in step six is ​​to use a mixed solution of HF and phosphoric acid to adjust the step height and morphology on the second device region and remove the hard mask layer.

[0023] Preferably, in step seven, the first gate oxide layer on the first device region is removed using an HF solution.

[0024] As described above, the method of improving the process compatibility and reliability of embedded medium and high voltage devices of the present invention has the following beneficial effects:

[0025] The present invention reduces the amount of HF solution used by skipping the sacrificial oxide layer removal and redeposition process steps before gate oxide formation in medium-voltage devices in the prior art, thereby adjusting the physical morphology of low-voltage devices and increasing the process window. In combination with a multi-step etching solution, the present invention addresses the physical morphology of medium-voltage devices that is deteriorated by skipping the sacrificial oxide layer removal and redeposition process steps before gate oxide formation in medium-voltage devices in the prior art, thereby simultaneously improving the physical morphology and electrical properties / reliability of low-voltage and medium-voltage devices. Furthermore, the present invention also increases the corresponding key process window of the prior art, providing a feasible implementation plan for the development of the next technology node platform for embedded medium- and high-voltage devices. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1 Shown is a schematic diagram of a metal gate structure of an embedded medium- and high-voltage device in the prior art;

[0027] Figure 2 Shown is a schematic diagram of an open portion of the hard mask layer of the present invention;

[0028] Figure 3 Shown is a schematic diagram of adjusting step height by etching for the first time according to the present invention;

[0029] Figure 4 Shown is a schematic diagram of adjusting the step height by etching for the second time according to the present invention;

[0030] Figure 5 Shown is a schematic diagram of the process flow of the present invention. DETAILED DESCRIPTION

[0031] The following describes the embodiments of the present invention through specific examples. Those skilled in the art will readily understand the other advantages and benefits of the present invention from the disclosure herein. The present invention may also be implemented or applied through various other specific embodiments, and the details in this specification may be modified or altered based on different viewpoints and applications without departing from the spirit of the present invention.

[0032] See also Figure 1 The present invention provides a method for improving the process compatibility and reliability of embedded medium and high voltage devices, comprising:

[0033] Step 1: Provide a substrate 102, form a sacrificial oxide layer 103 on the substrate 102, and then form STI 101 to define an active area. First to third device areas (A1, A2, A3) are formed on the active area; the first to third device areas (A1, A2, A3) are formed into wells by doping according to the type of NMOS or PMOS.

[0034] In an embodiment of the present invention, the substrate 102 in step one includes a bulk semiconductor substrate or a silicon-on-insulator (SOI) substrate. The SOI substrate includes an insulator layer located below a thin semiconductor layer serving as an active layer of the SOI substrate. The semiconductor of the active layer and the bulk semiconductor typically include crystalline semiconductor material silicon, but may also include one or more other semiconductor materials, such as germanium, silicon-germanium alloys, compound semiconductors (e.g., GaAs, AlAs, InAs, GaN, AlN, etc.) or their alloys (e.g., GaxAl1-xAs, GaxAl1-xN, InxGa1-xAs, etc.), oxide semiconductors (e.g., ZnO, SnO2, TiO2, Ga2O3, etc.) or combinations thereof. The semiconductor material may be doped or undoped. Other substrates that may be used include multilayer substrates, gradient substrates, or mixed orientation substrates.

[0035] In an embodiment of the present invention, the first to third device regions (A1, A2, A3) in step one are low-voltage, medium-voltage, and high-voltage device regions respectively. The low-voltage, medium-voltage, and high-voltage device regions can be formed by adjusting the type or concentration of ion implantation in the first to third device regions (A1, A2, A3).

[0036] In an embodiment of the present invention, the material of the sacrificial oxide layer 103 in step 1 is silicon dioxide.

[0037] Step 2: forming lightly doped drains and sources on the second device area A2, then skipping the removal and redeposition process of the sacrificial oxide layer, and directly forming a hard mask layer 104 covering the first to third device areas (A1, A2, A3) on the substrate 102;

[0038] In an embodiment of the present invention, the material of the hard mask layer 104 in step 2 is silicon nitride.

[0039] Step 3: Form a photoresist layer on the hard mask layer 104, photolithographically open the photoresist layer on the second device area A2 to expose the hard mask layer 104 thereunder, and etch the hard mask layer 104 to expose the sacrificial oxide layer 103 on the second device area A2 and the portion of the STI 101 near the second device area A2. After that, the remaining photoresist layer and etching byproducts are usually removed. In this step, the sacrificial oxide layer 103 needs to be retained and no hard mask layer 104 remains in the corners, forming a structure as shown in FIG. Figure 2 illustratively, the step height between the STI 101 and the sacrificial oxide layer 103 is 240 angstroms, and the cross width between the STI 101 and the active region is 110 angstroms.

[0040] In an embodiment of the present invention, the etching method in step three is dry etching.

[0041] Step 4: Please refer to Figure 3 The exposed sacrificial oxide layer 103 and the STI 101 are etched, forming a step height between the sacrificial oxide layer 103 and the STI 101, so that the step height and morphology are predetermined values. That is, the entire exposed sacrificial oxide layer 103 and a portion of the STI 101 are removed by etching, thereby reducing the step height between the STI 101 and the substrate 102. Exemplarily, the step height between the STI 101 and the substrate 102 is 100 angstroms.

[0042] In an embodiment of the present invention, the method for etching the exposed sacrificial oxide layer 103 and the STI 101 in step 4 includes: removing byproducts of the dry etching by using a wet etching method; and then etching the exposed sacrificial oxide layer 103 and the STI 101 using an HF solution to achieve a step height and morphology that meets the predetermined values. The amount of HF solution used in this step is determined based on the step height before and after etching.

[0043] Step 5: Please refer to Figure 4 , etching back the exposed STI 101 and the substrate 102 to a required back etching amount;

[0044] In an embodiment of the present invention, the back etching method in step five is dry etching, and the thickness of the hard mask layer 104 and the dry etching process time need to be defined according to the back etching depth of the active area. Cleaning is usually required to remove etching byproducts afterwards.

[0045] Step 6: Etching to adjust the step height and morphology on the second device area A2 and remove the hard mask layer 104;

[0046] In an embodiment of the present invention, the etching method in step six is ​​to use a mixed solution of HF and phosphoric acid to adjust the step height and morphology on the second device region A2 and remove the hard mask layer 104 .

[0047] Step 7: forming a first gate oxide layer on the first and second device regions (A1, A2), and then removing the first gate oxide layer on the first device region A1;

[0048] In an embodiment of the present invention, in step seven, the first gate oxide layer on the first device area A1 is removed using an HF solution.

[0049] Step eight: forming a second gate oxide layer on the first device area A1.

[0050] It should be noted that the illustrations provided in this embodiment are only used to schematically illustrate the basic concept of the present invention. Therefore, the illustrations only show components related to the present invention and are not drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component can be changed at will, and the component layout type may also be more complicated.

[0051] In summary, the present invention reduces HF usage by skipping the sacrificial oxide layer removal and redeposition process steps before gate oxide formation in medium-voltage devices in the prior art, thereby adjusting the physical morphology of low-voltage devices and increasing the process window. Furthermore, a multi-step etching solution is used to address the physical morphology degradation of medium-voltage devices caused by skipping the sacrificial oxide layer removal and redeposition process steps before gate oxide formation in medium-voltage devices in the prior art. This solution simultaneously improves the physical morphology and electrical properties / reliability of both low-voltage and medium-voltage devices. Furthermore, this solution also increases the corresponding key process windows of the prior art, providing a feasible implementation plan for the development of the next technology node platform for embedded medium- and high-voltage devices. Therefore, the present invention effectively overcomes the various shortcomings of the prior art and has high industrial application value.

[0052] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the present invention. Anyone skilled in the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by one of ordinary skill in the art without departing from the spirit and technical principles disclosed herein are intended to be covered by the claims of the present invention.

Claims

1. A method for improving process compatibility and reliability of embedded medium and high voltage devices, characterized in that: At least: Step 1: providing a substrate, forming a sacrificial oxide layer on the substrate, and then forming STI to define an active area, wherein a first device area, a second device area, and a third device area are formed on the active area, wherein the first device area is a low-voltage device area, the second device area is a medium-voltage device area, and the third device area is a high-voltage device area; Step 2: forming a lightly doped source and drain on the second device region, and then forming a hard mask layer on the substrate covering the first device region, the second device region, and the third device region; Step 3: forming a photoresist layer on the hard mask layer, photolithographically opening the photoresist layer on the second device region to expose the hard mask layer thereunder, and etching the hard mask layer to expose the sacrificial oxide layer and a portion of the STI on the second device region; Step 4: etching the exposed sacrificial oxide layer and the STI so that the step height and morphology thereof are preset values; Step 5: Etching back the exposed STI and the substrate to a desired etch back depth; Step 6: Etching to adjust the step height and morphology on the second device region and remove the hard mask layer; Step seven, forming a first gate oxide layer on the first device region and the second device region, and then removing the first gate oxide layer on the first device region; Step eight: forming a second gate oxide layer on the first device region.

2. The method for improving process compatibility and reliability of embedded medium and high voltage devices according to claim 1, characterized in that: The substrate in step 1 includes a bulk semiconductor substrate or a silicon-on-insulator substrate.

3. The method for improving process compatibility and reliability of embedded medium and high voltage devices according to claim 1, characterized in that: The material of the sacrificial oxide layer in step 1 is silicon dioxide.

4. The method for improving process compatibility and reliability of embedded medium and high voltage devices according to claim 1, characterized in that: The material of the hard mask layer in step 2 is silicon nitride.

5. The method for improving process compatibility and reliability of embedded medium and high voltage devices according to claim 1, characterized in that: The etching method in step three is dry etching.

6. The method for improving process compatibility and reliability of embedded medium and high voltage devices according to claim 5, characterized in that: The method of etching the exposed sacrificial oxide layer and the STI in step 4 includes: removing the byproducts of the dry etching by using a wet etching cleaning method; and then etching the exposed sacrificial oxide layer and the STI using an HF solution so that the step height and morphology thereof are the preset values.

7. The method for improving process compatibility and reliability of embedded medium and high voltage devices according to claim 1, characterized in that: The back etching method in step five is dry etching.

8. The method for improving process compatibility and reliability of embedded medium and high voltage devices according to claim 1, characterized in that: The etching method in step six is ​​to use a mixed solution of HF and phosphoric acid to etch and adjust the step height and morphology on the second device region and remove the hard mask layer.

9. The method for improving process compatibility and reliability of embedded medium and high voltage devices according to claim 1, characterized in that: In step seven, the first gate oxide layer on the first device region is removed using an HF solution.

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