Semiconductor structure and manufacturing method thereof, transistor and manufacturing method thereof

Abstract

The present disclosure discloses a semiconductor structure and a method for manufacturing the same, as well as a transistor and a method for manufacturing the same. The semiconductor structure is used to form a gate oxide layer and includes: a metal oxide layer, wherein the dielectric constant of the metal oxide layer is greater than a preset value, the metal oxide layer having a first surface and a second surface disposed opposite each other; and a silicate layer, wherein the silicate layer covers the first surface and / or the second surface, the silicate layer comprises the same metal element as the metal oxide layer, and the silicon content in the silicate layer gradually increases along a first direction, the first direction being from the metal oxide layer to a direction away from the metal oxide layer.

Description

Technical Field

[0001] The present disclosure relates to the technical field, and in particular to a semiconductor structure and a manufacturing method thereof, a transistor and a manufacturing method thereof. Background Art

[0002] Metal-Oxide-Semiconductor (MOS) devices have become the basis of complementary metal-oxide-semiconductor (CMOS) logic used in modern integrated circuits. One or more layers of dielectric material are formed on a semiconductor (typically silicon) substrate, and then a gate is formed on the dielectric. Early devices used silicon oxide (SiO2) as the gate dielectric layer and polysilicon (Poly) as the gate. However, as feature sizes decrease, the thickness of the gate dielectric layer becomes smaller and smaller. The reduction in oxide thickness directly leads to significant gate oxide leakage current caused by tunneling. To alleviate this problem, related technologies have used materials with higher dielectric constants than silicon oxide, namely high-K materials, to replace silicon oxide as the gate dielectric layer. Here, high-K materials generally refer to materials with a dielectric constant greater than 3.9, and are usually significantly higher than this value. For example, K = 5 is considered moderately high, and K = 20 is considered extremely high. High-K materials used for gate dielectric layers are generally metal oxides, such as hafnium oxide (HfO2).

[0003] However, in related art technologies, the introduction of high-K materials in gate dielectric layers brings some new challenges. Summary of the Invention

[0004] To solve related technical problems, the embodiments of the present disclosure provide a semiconductor structure and a manufacturing method thereof, a transistor and a manufacturing method thereof.

[0005] An embodiment of the present disclosure provides a semiconductor structure for forming a gate oxide layer, the semiconductor structure comprising:

[0006] a metal oxide layer, wherein the dielectric constant of the material of the metal oxide layer is greater than a preset value, and the metal oxide layer has a first surface and a second surface disposed opposite to each other;

[0007] A silicate layer covering the first surface and / or the second surface, the silicate layer having the same metal element as the metal oxide layer, the silicon content in the silicate layer gradually increasing along a first direction, and the first direction pointing from the metal oxide layer to a direction away from the metal oxide layer.

[0008] In the above solution, the material of the metal oxide layer includes hafnium oxide or zirconium oxide.

[0009] In the above solution, the silicate layer comprises a continuous silicate layer, and the silicon content in the continuous silicate layer gradually increases along the first direction;

[0010] or,

[0011] The silicate layer includes a plurality of stacked sub-silicate layers, and silicon content in the plurality of stacked sub-silicate layers gradually increases along a first direction.

[0012] In the above scheme, the silicate layer includes a first silicate layer and a second silicate layer, the first silicate layer covers the first surface, the second silicate layer covers the second surface, and the silicon content in the first silicate layer and the silicon content in the second silicate layer both gradually increase along the first direction.

[0013] The present disclosure also provides a transistor, including:

[0014] substrate;

[0015] a source electrode and a drain electrode located in the substrate;

[0016] A gate oxide layer located between the source and the drain; the gate oxide layer comprises the semiconductor structure provided in the embodiment of the present disclosure;

[0017] A gate is located on the gate oxide layer.

[0018] In the above solution, the gate oxide layer further includes a silicon oxide layer located between the substrate and the semiconductor structure.

[0019] The present disclosure further provides a method for manufacturing a semiconductor structure, wherein the semiconductor structure is used to form a gate oxide layer. The method comprises:

[0020] forming a metal oxide layer; wherein the dielectric constant of the material of the metal oxide layer is greater than a preset value; and the metal oxide layer has a first surface and a second surface disposed opposite to each other;

[0021] A silicate layer is formed on the first surface and / or the second surface, wherein the silicate layer has the same metal element as the metal oxide layer; the silicon content in the silicate layer gradually increases along a first direction; and the first direction points from the metal oxide layer to a direction away from the metal oxide layer.

[0022] In the above solution, forming a silicate layer on the first surface and / or the second surface comprises:

[0023] By using deposition parameters that vary gradually over time, a silicate layer having a silicon content that varies gradually along a first direction is formed on the first surface and / or the second surface.

[0024] In the above solution, the deposition parameters include at least one of the following:

[0025] The ratio of silicon source in the deposition reaction gas;

[0026] The rate at which silicon source is introduced into the deposition reaction gas.

[0027] In the above solution, forming a silicate layer on the first surface and / or the second surface comprises:

[0028] forming a continuous silicate layer, wherein the silicon content in the continuous silicate layer gradually increases along a first direction;

[0029] or,

[0030] A plurality of stacked sub-silicate layers is formed, wherein the silicon content in the plurality of stacked sub-silicate layers gradually increases along a first direction.

[0031] In the above solution, forming a silicate layer on the first surface and / or the second surface comprises:

[0032] depositing a material for forming a silicate layer on the first surface and / or the second surface;

[0033] The deposited material for forming the silicate layer is annealed to obtain the silicate layer.

[0034] In the above solution, the step of depositing a material for forming a silicate layer on the first surface and / or the second surface includes:

[0035] A material for forming a silicate layer is deposited on the first surface and / or the second surface by atomic layer deposition, chemical vapor deposition or molecular beam epitaxy.

[0036] In the above solution, during the annealing process, the temperature range adopted is: 500°C to 900°C.

[0037] In the above scheme, during the annealing process, the pressure range used is: 1.2Pa~1.4Pa.

[0038] The present disclosure also provides a method for manufacturing a transistor, including:

[0039] providing a substrate;

[0040] forming a source electrode and a drain electrode in the substrate;

[0041] A gate oxide layer is formed between the source and the drain; the gate oxide layer is formed by using the method for manufacturing a semiconductor structure provided in an embodiment of the present disclosure;

[0042] A gate is formed on the gate oxide layer.

[0043] In the above solution, the gate oxide layer further comprises: a silicon oxide layer; and the gate oxide layer formed between the source and the drain comprises:

[0044] forming a silicon oxide layer between the substrate and the semiconductor structure;

[0045] The semiconductor structure is formed on the silicon oxide layer to obtain the gate oxide layer.

[0046] The embodiments of the present disclosure provide a semiconductor structure and a method for manufacturing the same, as well as a transistor and a method for manufacturing the same. The semiconductor structure is used to form a gate oxide layer, and the semiconductor structure includes: a metal oxide layer; the dielectric constant of the material of the metal oxide layer is greater than a preset value; the metal oxide layer has a first surface and a second surface disposed opposite to each other; a silicate layer; the silicate layer covers the first surface and / or the second surface; the silicate layer has the same metal element as the metal oxide layer; the silicon content in the silicate layer gradually increases along a first direction; the first direction points from the metal oxide layer to a direction away from the metal oxide layer. In the embodiments of the present disclosure, a metal-based silicate with a gradient silicon component is disposed on one side, or two opposite sides, of a metal oxide with a high dielectric constant, wherein the silicon content in the metal-based silicate on each side increases with increasing distance from the metal oxide layer. It is understandable that the metal-based silicon-oxygen bonds formed by metal-based silicates with increased silicon content when in direct contact with silicon have better stability at high temperatures. Therefore, metal-based silicates with higher silicon components are introduced at the interface that may come into contact with silicon. However, too high a silicon component will reduce the dielectric constant, thereby increasing the equivalent oxide layer thickness, which is extremely unfavorable for the further optimization and size reduction of high-K devices. Therefore, by introducing metal-based silicates with a gradient composition, it is possible to ensure that the contact surface has more stable metal-based silicon-oxygen bonds, while also reducing the degradation of device performance caused by the introduction of silicon. BRIEF DESCRIPTION OF THE DRAWINGS

[0047] Figure 1 A schematic diagram of a process flow for implementing a method for manufacturing a semiconductor structure provided by an embodiment of the present disclosure;

[0048] Figure 2a-2c Schematic diagram of the structural relationship between several metal oxide layers and silicate layers provided in the embodiments of the present disclosure;

[0049] Figure 3 A schematic diagram of an implementation flow of a method for manufacturing a transistor provided in an embodiment of the present disclosure;

[0050] Figure 4A schematic structural diagram of a transistor provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0051] Exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although exemplary embodiments of the present disclosure are shown in the accompanying drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the specific embodiments described herein. Instead, these embodiments are provided to enable a more thorough understanding of the present disclosure and to fully convey the scope of the present disclosure to those skilled in the art.

[0052] In the following description, numerous specific details are provided to provide a more thorough understanding of the present disclosure. However, it will be apparent to those skilled in the art that the present disclosure can be practiced without one or more of these details. In other instances, certain technical features known in the art are not described to avoid confusion with the present disclosure; that is, all features of actual embodiments are not described herein, nor are well-known functions and structures described in detail.

[0053] In the drawings, the sizes of layers, regions, elements and their relative sizes may be exaggerated for clarity. Like reference numerals denote like elements throughout.

[0054] It should be understood that spatial relational terms such as "under", "beneath", "below", "under", "above", "above", etc., may be used herein for convenience of description to describe the relationship of one element or feature shown in the figures to other elements or features. It should be understood that in addition to the orientations shown in the figures, the spatial relational terms are intended to also include different orientations of the device in use and operation. For example, if the device in the drawings is turned over, then the elements or features described as "under the other elements" or "beneath" or "beneath" will be oriented as "on" the other elements or features. Thus, the exemplary terms "under" and "under" may include both upper and lower orientations. The device may be oriented otherwise (rotated 90 degrees or in other orientations) and the spatial descriptors used herein are interpreted accordingly.

[0055] The purpose of the terms used herein is only to describe specific embodiments and is not intended to limit the present disclosure. When used herein, the singular forms "a", "an", and "the" are intended to include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "comprising" and / or "comprising", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0056] It should be noted that: "first", "second", etc. are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence.

[0057] In order to enable a more detailed understanding of the features and technical contents of the embodiments of the present disclosure, the implementation of the embodiments of the present disclosure is described in detail below with reference to the accompanying drawings. The accompanying drawings are for reference only and are not intended to limit the embodiments of the present disclosure.

[0058] In semiconductor device manufacturing, as device dimensions continue to shrink, dielectric layers continue to become thinner. Using silicon oxide as the dielectric layer results in significant gate leakage, leading to the introduction of high-k materials in the device dielectric fabrication process. As research deepens, some high-k materials, such as hafnium oxide (HfO2), have emerged as promising candidates due to their wide band gap and high stability at the silicon (Si) interface. However, further research into the dielectric fabrication process has brought with it new challenges.

[0059] In various embodiments of the present disclosure, a metal-based silicate with a graded silicon content is disposed on one side, or on two opposite sides, of a metal oxide having a high dielectric constant, wherein the silicon content of the metal-based silicate on each side increases with increasing distance from the metal oxide layer. It is understood that the provision of the metal oxide can reduce the equivalent oxide thickness (EOT) of the dielectric layer. Furthermore, the metal-based silicon-oxygen bonds formed by the metal-based silicate with an increased silicon content when in direct contact with silicon have greater stability at high temperatures. Therefore, a metal-based silicate with a higher silicon content is introduced at the interface that may contact silicon. However, excessively high silicon content reduces the dielectric constant, thereby increasing the EOT. Therefore, the introduction of the metal-based silicate with a graded composition can ensure more stable metal-based silicon-oxygen bonds in the contact surface layer while also minimizing the increase in EOT caused by the introduction of silicon.

[0060] The present disclosure provides a method for manufacturing a semiconductor structure. Figure 1 The following is a schematic diagram of a method for manufacturing a semiconductor structure according to an embodiment of the present disclosure. Figure 1 As shown, the semiconductor structure is used to form a gate oxide layer, and the manufacturing method of the semiconductor structure includes:

[0061] Step 101: forming a metal oxide layer; the dielectric constant of the material of the metal oxide layer is greater than a preset value; the metal oxide layer has a first surface and a second surface disposed opposite to each other;

[0062] Step 102: forming a silicate layer on the first surface and / or the second surface, wherein the silicate layer has the same metal element as the metal oxide layer; the silicon content in the silicate layer gradually increases along a first direction; the first direction points from the metal oxide layer to a direction away from the metal oxide layer.

[0063] It should be understood that Figure 1 The operations shown in the figure are not exclusive, and other operations may be performed before, after, or between any of the operations shown. There is no clear order in which steps 101 and 102 are performed. In practical applications, the order of execution may be adjusted as needed, and even steps 101 and 102 may be performed alternately.

[0064] It should be noted that the semiconductor structure will be used in subsequent processes to form a gate oxide layer or a gate dielectric layer.

[0065] In step 101, the preset value is greater than 3.9, which means that the dielectric constant of the metal oxide layer in the embodiment of the present disclosure is relatively high. In some embodiments, the material of the metal oxide layer includes hafnium oxide or zirconium oxide (ZrO2).

[0066] Here, the first surface and the second surface are two surfaces of the metal oxide layer disposed opposite each other. In practical applications, one of the first and second surfaces (the lower surface) is close to a substrate, such as a silicon substrate, and the other surface (the upper surface) is close to a gate, such as a polysilicon gate or a metal gate. In the following embodiments, for clarity and simplicity, the first surface is defined as the lower surface of the metal oxide layer, and the second surface is defined as the upper surface of the metal oxide layer.

[0067] In step 102 , the silicate layer includes a metal-based silicate layer, and the metal base is the same as the metal element in the metal oxide layer in step 101 .

[0068] For example, the material of the metal oxide layer is hafnium oxide, and the material of the silicate layer is hafnium-based silicate (HfSiO x ); or, the material of the metal oxide layer is zirconium oxide, and the material of the silicate layer is zirconium-based silicate (ZrSiO x ).

[0069] Here, for the metal oxide, no matter the upper surface or the lower surface, the first direction is from the metal oxide layer to a direction away from the metal oxide layer.

[0070] Figure 2a-2c Schematic diagram of the structural relationship between several metal oxide layers and silicate layers provided in the embodiments of the present disclosure.

[0071] For example, Figure 2a As shown, the silicate layer 202 covers the lower surface of the metal oxide layer 201, and the silicon content in the silicate layer increases along the Figure 2a It is understood that in practical applications, the silicate layer 202 needs to be formed first, and then the metal oxide layer 201 is formed on the silicate layer 202 .

[0072] For example, Figure 2b As shown, the silicate layer 202 covers the upper surface of the metal oxide layer 201, and the silicon content in the silicate layer increases along the Figure 2b It is understood that in practical applications, the metal oxide layer 201 needs to be formed first, and then the silicate layer 202 is formed on the metal oxide layer 201 .

[0073] For example, Figure 2c As shown, the silicate layer includes a first silicate layer 202-1 and a second silicate layer 202-2; wherein the first silicate layer 202-1 covers the lower surface of the metal oxide layer 201, and the second silicate layer 202-2 covers the upper surface of the metal oxide layer, and the silicon content in the first silicate layer 202-1 and the second silicate layer 202-2 is along the Figure 2c It is understood that in practical applications, the first silicate layer 202-1 needs to be formed first, then the metal oxide layer 201 is formed on the first silicate layer 202-1, and then the second silicate layer 202-2 is formed on the metal oxide layer 201.

[0074] It should be noted that the placement of the silicate layer 202 relative to the metal oxide layer 201 may depend on whether the metal oxide layer 201 is close to a substrate material that is easily oxidized in actual applications. In other words, when the silicate layer 202 is close to a substrate material that is easily oxidized, a metal-based silicate layer with a graded silicon composition may be required.

[0075] In some embodiments, forming a silicate layer on the first surface and / or the second surface comprises:

[0076] By using deposition parameters that vary gradually over time, a silicate layer having a silicon content that varies gradually along a first direction is formed on the first surface and / or the second surface.

[0077] In some embodiments, the deposition parameters include at least one of the following:

[0078] The ratio of silicon source in the deposition reaction gas;

[0079] The rate at which silicon source is introduced into the deposition reaction gas.

[0080] That is to say, in practical applications, a silicate layer with a gradient composition can be formed by controlling the proportion of the silicon source in the deposition reaction gas or controlling the introduction rate of the silicon source in the deposition reaction gas. Figure 2c Taking the silicate layer shown in as an example, the portion with a small silicon component of the silicate layer can be formed by controlling the proportion of the silicon source in the deposition reaction gas to become smaller or the introduction rate of the silicon source in the deposition reaction gas to become smaller, so that the deposition reaction is insufficient; the portion with a large silicon component of the silicate layer can be formed by controlling the proportion of the silicon source in the deposition reaction gas to become larger or the introduction rate of the silicon source in the deposition reaction gas to become larger, so that the deposition reaction is sufficient.

[0081] In some embodiments, forming a silicate layer on the first surface and / or the second surface comprises:

[0082] forming a continuous silicate layer, wherein the silicon content in the continuous silicate layer gradually increases along a first direction;

[0083] or,

[0084] A plurality of stacked sub-silicate layers is formed, wherein the silicon content in the plurality of stacked sub-silicate layers gradually increases along a first direction.

[0085] In practical applications, the silicate layer may be a silicate layer with a continuously gradient silicon content, or may be a silicate layer formed by a plurality of sub-silicate layers with an interval gradient silicon content.

[0086] In some embodiments, forming a silicate layer on the first surface and / or the second surface comprises:

[0087] depositing a material for forming a silicate layer on the first surface and / or the second surface;

[0088] The deposited material for forming the silicate layer is annealed to obtain the silicate layer.

[0089] It should be noted here that, in actual applications, when the silicate layer formed is a continuous silicate layer, the annealing treatment is an annealing treatment after the entire gate oxide layer is formed; when the silicate layer formed is a layer having multiple stacked sub-silicate layers, the annealing treatment is an annealing treatment after the formation of each sub-silicate layer.

[0090] In practical applications, in some embodiments, depositing a material for forming a silicate layer on the first surface and / or the second surface includes:

[0091] A material for forming a silicate layer is deposited on the first surface and / or the second surface by atomic layer deposition (ALD), chemical vapor deposition (CVD), or molecular beam epitaxy (MBE). In some embodiments, the temperature used in the annealing process is in the range of 500° C. to 900° C.

[0092] In some embodiments, during the annealing process, the pressure range used is 1.2 Pa to 1.4 Pa. Annealing within this temperature and pressure range can fully activate the silicate layer in the gate oxide layer.

[0093] For example, on a silicon substrate, a high-K dielectric layer is prepared by cycle-by-cycle deposition using processes such as ALD to ensure the formation of a uniform and dense film. Deposition can be performed at a relatively fast growth rate, such as 0.1 nm / cycle. In this process, the reaction temperature in the reactor tube, the silicon source feed rate, the gas pressure in the furnace, and other factors are controlled to control the silicon feed; and a rapid annealing furnace is used to perform rapid annealing (RTA) on the sample: under the condition of a vacuum degree of about 1.3 Pa in the annealing furnace tube, rapid annealing is completed at a temperature of 600°C or 800°C, which can ensure the formation of a uniform and dense silicate layer.

[0094] An embodiment of the present disclosure provides a method for manufacturing a semiconductor structure, wherein the semiconductor structure is used to form a gate oxide layer, the method comprising: forming a metal oxide layer; the dielectric constant of the material of the metal oxide layer is greater than a preset value; the metal oxide layer has a first surface and a second surface disposed opposite each other; forming a silicate layer on the first surface and / or the second surface, the silicate layer having the same metal element as the metal oxide layer; the silicon content in the silicate layer gradually increases along a first direction; the first direction is directed from the metal oxide layer to a direction away from the metal oxide layer. In the embodiment of the present disclosure, a metal-based silicate having a graded silicon component is disposed on one side, or on two opposite sides, of a metal oxide having a high dielectric constant, wherein the silicon content in the metal-based silicate on each side increases with increasing distance from the metal oxide layer. It is understandable that the metal-based silicon-oxygen bonds formed by metal-based silicates with increased silicon content when in direct contact with silicon have better stability at high temperatures. Therefore, metal-based silicates with higher silicon components are introduced at the interface that may come into contact with silicon. However, too high a silicon component will reduce the dielectric constant, thereby increasing the equivalent oxide layer thickness, which is extremely unfavorable for the further optimization and size reduction of high-K devices. Therefore, by introducing metal-based silicates with a gradient composition, it is possible to ensure that the contact surface has more stable metal-based silicon-oxygen bonds, while also reducing the degradation of device performance caused by the introduction of silicon.

[0095] Based on the above-mentioned method for manufacturing a semiconductor structure, the present disclosure also provides a method for manufacturing a transistor, such as Figure 3 As shown, the manufacturing method of the transistor includes:

[0096] Step 301: providing a substrate;

[0097] Step 302: forming a source and a drain in the substrate;

[0098] Step 303: forming a gate oxide layer between the source and the drain; the gate oxide layer is formed by the method for manufacturing a semiconductor structure provided by an embodiment of the present disclosure;

[0099] Step 304: forming a gate on the gate oxide layer.

[0100] In practical applications, the gate material includes polysilicon and / or metal materials. In some embodiments, the metal material may include but is not limited to titanium nitride (TiN) or tantalum nitride (TaN).

[0101] In some embodiments, the gate oxide layer further comprises: a silicon oxide layer; and forming the gate oxide layer between the source and the drain comprises:

[0102] forming a silicon oxide layer between the substrate and the semiconductor structure;

[0103] The semiconductor structure is formed on the silicon oxide layer to obtain the gate oxide layer.

[0104] Figure 4 A schematic diagram of the structure of a transistor provided by an embodiment of the present disclosure. Figure 4 The manufacturing process of the transistor will be described.

[0105] Here, in practical applications, the material of the substrate includes but is not limited to silicon. Ion implantation can be used to form the source and drain in the substrate. Pocket doping (halo implant) or lightly doped drain (LDD) doping can also be performed next to the source and drain to form pocket doped regions and lightly doped regions. Then, the gate oxide layer is formed using the manufacturing method of the semiconductor structure provided by the embodiment of the present disclosure. Figure 4 The figure only shows the case where the silicate layer includes a first silicate layer and a second silicate layer, with the first silicate layer covering the lower surface of the metal oxide layer and the second silicate layer covering the upper surface of the metal oxide layer. In related research and development, to better adapt to high-k dielectric layers, a metal gate has been used instead of a polysilicon gate. Based on this, a metal gate can be formed on the gate oxide layer. In some embodiments, the gate can include polysilicon and / or metal materials. Protective sidewalls can also be formed on both sides of the metal gate.

[0106] Based on the above-mentioned method for manufacturing a semiconductor structure, an embodiment of the present disclosure further provides a semiconductor structure for forming a gate oxide layer, the semiconductor structure comprising:

[0107] a metal oxide layer, wherein the dielectric constant of the material of the metal oxide layer is greater than a preset value, and the metal oxide layer has a first surface and a second surface disposed opposite to each other;

[0108] A silicate layer covering the first surface and / or the second surface, the silicate layer having the same metal element as the metal oxide layer, the silicon content in the silicate layer gradually increasing along a first direction, and the first direction pointing from the metal oxide layer to a direction away from the metal oxide layer.

[0109] In some embodiments, the material of the metal oxide layer includes hafnium oxide or zirconium oxide.

[0110] In some embodiments, the silicate layer comprises a continuous silicate layer, and the silicon content in the continuous silicate layer gradually increases along the first direction;

[0111] or,

[0112] The silicate layer includes a plurality of stacked sub-silicate layers, and silicon content in the plurality of stacked sub-silicate layers gradually increases along a first direction.

[0113] In some embodiments, the silicate layer includes a first silicate layer and a second silicate layer, the first silicate layer covers the first surface, the second silicate layer covers the second surface, and the silicon content in the first silicate layer and the silicon content in the second silicate layer both gradually increase along the first direction.

[0114] In some embodiments, the first silicate layer and the second silicate layer may each include hafnium (zirconium) salt.

[0115] It can be understood that the dielectric layer of graded composition hafnium (zirconium) based silicate / hafnium (zirconium) oxide / graded composition hafnium (zirconium) based silicate is beneficial to reducing the formation of interfacial silicon oxide (low-K material) while improving the high-temperature thermal stability of hafnium (zirconium) based silicate (high-K material).

[0116] Since hafnium (zirconium)-based silicates exhibit better electrical properties and higher thermal stability when in direct contact with silicon, the Hf(Zr)-Si-O bond formed has better stability at high temperatures. Hf-based silicates with a higher Si content are introduced at the contact interface with Si. However, an excessively high Si content will affect the relative dielectric constant of the dielectric layer, thereby increasing the EOT, which is extremely detrimental to the further optimization and size reduction of high-K devices. By introducing hafnium (zirconium)-based silicates with a gradient composition, a more stable Hf(Zr)-Si-O bond can be ensured on the contact surface, while the layered growth controls the Si content, thereby reducing the degradation of device performance caused by the introduction of Si.

[0117] The disclosed embodiments provide a high-K dielectric layer utilizing a hafnium (zirconium)-based silicate with a gradient silicon component / hafnium (zirconium) oxide / hafnium (zirconium)-based silicate with a gradient silicon component. During the growth of the high-K dielectric layer material, the intake of a silicon-based source is controlled to form a silicate layer with a gradient composition. Adjusting the thickness of the hafnium (zirconium) oxide can further adjust the performance of the high-K dielectric layer.

[0118] Based on the above semiconductor structure, an embodiment of the present disclosure further provides a transistor, including:

[0119] substrate;

[0120] a source electrode and a drain electrode located in the substrate;

[0121] A gate oxide layer located between the source and the drain; the gate oxide layer includes the semiconductor structure provided by the embodiment of the present disclosure;

[0122] A gate is located on the gate oxide layer.

[0123] In practical applications, the gate material includes polysilicon and / or a metal material. In some embodiments, the metal material may include but is not limited to titanium nitride (TiN) or tantalum nitride (TaN). In some embodiments, the gate oxide layer further includes a silicon oxide layer located between the substrate and the semiconductor structure.

[0124] It should be noted that the embodiments of the present disclosure propose a new structure and manufacturing method of a high-K dielectric layer, which can be used to form a CMOS based on a high-K dielectric layer.

[0125] It should be understood that the “some embodiments” mentioned in the specification means that specific features, structures or characteristics related to the embodiments are included in at least one embodiment of the present disclosure. Therefore, “in some embodiments” or “in an embodiment” appearing throughout the specification does not necessarily refer to the same embodiment. In addition, these specific features, structures or characteristics may be combined in one or more embodiments in any suitable manner. It should be understood that in the various embodiments of the present disclosure, the size of the serial numbers of the above-mentioned processes does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present disclosure. The serial numbers of the embodiments of the present disclosure are for description only and do not represent the advantages and disadvantages of the embodiments.

[0126] The methods disclosed in the several method embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new method embodiments.

[0127] The above description is merely a specific embodiment of the present disclosure, but the scope of protection of the present disclosure is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this disclosure should be included in the scope of protection of the present disclosure. Therefore, the scope of protection of the present disclosure should be based on the scope of protection of the claims.

Claims

1. A semiconductor structure, characterized in that For forming a gate oxide layer, the semiconductor structure comprises: a metal oxide layer, wherein the dielectric constant of the material of the metal oxide layer is greater than a preset value, and the metal oxide layer has a first surface and a second surface disposed opposite to each other; a silicate layer, the silicate layer covering the first surface and / or the second surface, the silicate layer having the same metal element as the metal oxide layer, the silicon content in the silicate layer gradually increasing along a first direction, the first direction being from the metal oxide layer to a direction away from the metal oxide layer; The silicate layer includes a first silicate layer and a second silicate layer, the first silicate layer covers the first surface, the second silicate layer covers the second surface, and the silicon content in the first silicate layer and the silicon content in the second silicate layer both gradually increase along the first direction.

2. The semiconductor structure according to claim 1, wherein: The material of the metal oxide layer includes hafnium oxide or zirconium oxide.

3. The semiconductor structure according to claim 1, wherein: The silicate layer comprises a continuous silicate layer, wherein the silicon content in the continuous silicate layer gradually increases along a first direction; or, The silicate layer includes a plurality of stacked sub-silicate layers, and silicon content in the plurality of stacked sub-silicate layers gradually increases along a first direction.

4. A transistor, characterized in that: include: substrate; a source electrode and a drain electrode located in the substrate; a gate oxide layer located between the source and the drain; The gate oxide layer comprises the semiconductor structure according to any one of claims 1 to 3; A gate is located on the gate oxide layer.

5. The transistor according to claim 4, wherein: The gate oxide layer further includes a silicon oxide layer located between the substrate and the semiconductor structure.

6. A method for manufacturing a semiconductor structure, characterized in that: The semiconductor structure is used to form a gate oxide layer, and the manufacturing method includes: forming a metal oxide layer; wherein the dielectric constant of the material of the metal oxide layer is greater than a preset value; and the metal oxide layer has a first surface and a second surface disposed opposite to each other; forming a silicate layer on the first surface and / or the second surface, the silicate layer having the same metal element as the metal oxide layer; wherein the silicon content in the silicate layer gradually increases along a first direction; and the first direction is from the metal oxide layer to a direction away from the metal oxide layer; The forming of a silicate layer on the first surface and / or the second surface comprises: A first silicate layer and a second silicate layer are formed, wherein the first silicate layer covers the first surface and the second silicate layer covers the second surface, and the silicon content in the first silicate layer and the silicon content in the second silicate layer both gradually increase along the first direction.

7. The manufacturing method according to claim 6, characterized in that The forming of a silicate layer on the first surface and / or the second surface comprises: By using deposition parameters that vary gradually over time, a silicate layer having a silicon content that varies gradually along a first direction is formed on the first surface and / or the second surface.

8. The manufacturing method according to claim 7, characterized in that The deposition parameters include at least one of the following: The ratio of silicon source in the deposition reaction gas; The rate at which silicon source is introduced into the deposition reaction gas.

9. The manufacturing method according to claim 6, characterized in that The forming of a silicate layer on the first surface and / or the second surface comprises: depositing a material for forming a silicate layer on the first surface and / or the second surface; The deposited material for forming the silicate layer is annealed to obtain the silicate layer.

10. The manufacturing method according to claim 9, characterized in that: The step of depositing a material for forming a silicate layer on the first surface and / or the second surface comprises: A material for forming a silicate layer is deposited on the first surface and / or the second surface by atomic layer deposition, chemical vapor deposition or molecular beam epitaxy.

11. The manufacturing method according to claim 9, characterized in that: During the annealing process, the temperature range used is: 500℃~900℃.

12. The manufacturing method according to claim 9, characterized in that During the annealing process, the pressure range used is: 1.2 Pa ~1.4Pa.

13. A method for manufacturing a semiconductor structure, characterized in that: The semiconductor structure is used to form a gate oxide layer, and the manufacturing method includes: forming a metal oxide layer; wherein the dielectric constant of the material of the metal oxide layer is greater than a preset value; and the metal oxide layer has a first surface and a second surface disposed opposite to each other; forming a silicate layer on the first surface and / or the second surface, the silicate layer having the same metal element as the metal oxide layer; wherein the silicon content in the silicate layer gradually increases along a first direction; and the first direction is from the metal oxide layer to a direction away from the metal oxide layer; The forming of a silicate layer on the first surface and / or the second surface comprises: A plurality of stacked sub-silicate layers are formed on both the first surface and the second surface, and the silicon content in the plurality of stacked sub-silicate layers gradually increases along a first direction.

14. A method for manufacturing a transistor, characterized in that: include: providing a substrate; forming a source electrode and a drain electrode in the substrate; forming a gate oxide layer between the source and the drain; The gate oxide layer is formed by the method for manufacturing a semiconductor structure according to any one of claims 6 to 13; A gate is formed on the gate oxide layer.

15. The manufacturing method according to claim 14, wherein the gate oxide layer further comprises: silicon oxide layer; The forming of a gate oxide layer between the source and the drain comprises: forming a silicon oxide layer between the substrate and the semiconductor structure; The semiconductor structure is formed on the silicon oxide layer to obtain the gate oxide layer.

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