Electronic system and chip

Abstract

An electronic system and a chip are provided. The chip includes first to fifth pads, first and second voltage-controlled current elements, first and second bias elements. The first to third pads are coupled to a drain, a source and a gate of a first gallium nitride transistor, respectively. The third to fifth pads are coupled to a drain, a source and a gate of a second gallium nitride transistor, respectively. The first voltage-controlled current element is coupled to the first and second pads. The second voltage-controlled current element is coupled to the third and fourth pads. The first bias element is coupled to the second and third pads. The second bias element is coupled to the fourth and fifth pads. The first bias element adjusts a bias voltage of the second pad according to the first voltage-controlled current element. The second bias element adjusts a bias voltage of the fourth pad according to the second voltage-controlled current element.

Description

TECHNICAL FIELD

[0001] The present application relates to a system and a chip, and particularly to an electronic system and a chip for coupling with a gallium nitride transistor. BACKGROUND

[0002] Gallium nitride (GaN) transistors are widely used due to some advantages. On the other hand, gallium nitride transistors also have a low threshold voltage, which often causes a large power consumption in a circuit.

[0003] Some enhanced mode (e-mode) gallium nitride transistors are proposed in the prior art to try to reduce the power consumption of gallium nitride transistors. However, these enhanced mode gallium nitride transistors often need special processes to change the structure of the gallium nitride transistor, or are cascode with a transistor, so as to cause a high manufacturing cost, or the current of the gallium nitride transistor is limited by the cascode transistor, thereby affecting the circuit performance of the gallium nitride transistor. SUMMARY

[0004] The present application is directed to an electronic system and a chip, which can improve the manufacturing cost of a gallium nitride transistor without affecting the circuit performance of the gallium nitride transistor itself.

[0005] According to an embodiment of the present application, a chip includes first to fifth pads, first and second voltage-controlled current elements, first and second bias elements. The first to third pads are coupled to a drain, a source and a gate of a first gallium nitride transistor, respectively, and the third to fifth pads are coupled to a drain, a source and a gate of a second gallium nitride transistor, respectively. The first voltage-controlled current element is coupled to the first and second pads. The second voltage-controlled current element is coupled to the third and fourth pads. The first bias element is coupled to the second and third pads. The second bias element is coupled to the fourth and fifth pads. The first bias element adjusts a bias voltage of the second pad according to the first voltage-controlled current element, and the second bias element adjusts a bias voltage of the fourth pad according to the second voltage-controlled current element.

[0006] According to an embodiment of the present application, an electronic system includes a chip, a first and a second gallium nitride transistor. The source of the first gallium nitride transistor is coupled to the drain of the second gallium nitride transistor. The chip includes a first to a fifth pad, a first and a second voltage-controlled current element, a first and a second bias element. The first to the third pad is coupled to the drain, the source and the gate of the first gallium nitride transistor respectively, and the third to the fifth pad is coupled to the drain, the source and the gate of the second gallium nitride transistor respectively. The first voltage-controlled current element is coupled to the first and the second pad. The second voltage-controlled current element is coupled to the third and the fourth pad. The first bias element is coupled to the second and the third pad. The second bias element is coupled to the fourth and the fifth pad. The first bias element is controlled by the first voltage-controlled current element to adjust the bias of the second pad, and the second bias element is controlled by the second voltage-controlled current element to adjust the bias of the fourth pad.

[0007] Based on the above, the electronic system and the chip of the present application control the operation of the gallium nitride transistor to be on and / or off through the coupling relationship of the gallium nitride transistor, the bias element and the voltage-controlled current element.

[0008] The electronic system and the chip of the present application can preferably control the on and / or off of the gallium nitride transistor without the need for additional processes to change the structure of the gallium nitride transistor itself, while retaining the high current and fast switching advantages of the gallium nitride transistor itself, effectively avoiding the leakage current of the gallium nitride transistor, thereby improving the overall power consumption of the electronic system. BRIEF DESCRIPTION OF DRAWINGS

[0009] The accompanying drawings are included to provide a further understanding of the present application, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the present application and, together with the description, serve to explain the principles of the present application.

[0010] Figure 1 FIG. 1 is a block schematic diagram of an electronic system according to an embodiment of the present application;

[0011] Figure 2 FIG. 1 is a block schematic diagram of an electronic system according to an embodiment of the present application;

[0012] Figure 3 FIG. 1 is a block schematic diagram of an electronic system according to an embodiment of the present application;

[0013] DETAILED DESCRIPTION

[0014] 1, 2, 3: electronic system;

[0015] 10, 20, 30: chip;

[0016] 11, 21: driving circuit;

[0017] 12: upper bridge circuit;

[0018] 13: lower bridge circuit;

[0019] 14, 16, 24, 26, 34: voltage-controlled current element;

[0020] 15, 17, 25, 27: bias element;

[0021] 38: bootstrap circuit;

[0022] 210: power supply circuit;

[0023] 211: controller;

[0024] 212: level shifting circuit;

[0025] P1-P5: pad;

[0026] C1, C2: capacitor;

[0027] D1: diode;

[0028] DS1, DS2: drive signal;

[0029] DS1', DS2': control signal;

[0030] GT1, GT2: gallium nitride transistor;

[0031] HVDD, GND: reference voltage;

[0032] MN1, MP1, MP2: transistor;

[0033] R1-R4: resistor;

[0034] T1, T2, T3: power transistor;

[0035] ZD1, ZD2: zener diode. DETAILED DESCRIPTION

[0036] Reference will now be made in detail to the exemplary embodiments of the present application, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers will be used in the different drawings and the description to refer to the same or like parts.

[0037] Figure 1 Fig. 1 is a block diagram of an electronic system 1 according to an embodiment of the present application. The electronic system 1 includes a chip 10, gallium nitride transistors GT1, GT2. The chip 10 is provided with pads P1-P5, and the chip 10 is coupled to the gallium nitride transistors GT1, GT2 through the pads P1-P5. The chip 10 can be used to drive the gallium nitride transistors GT1, GT2.

[0038] In one embodiment, the gallium nitride transistors GT1, GT2 can be gallium nitride transistors of a first conduction type (e.g., n-type) that are turned on when a voltage difference received between a gate and a source thereof is greater than or equal to a threshold voltage. The drain, source and gate of the gallium nitride transistor GT1 can be coupled to the pads P1, P2, P3, respectively. The drain, source and gate of the gallium nitride transistor GT2 can be coupled to the pads P3, P4, P5, respectively. On the other hand, the drain of the gallium nitride transistor GT1 can receive a reference voltage HVDD, and the source of the gallium nitride transistor GT2 can receive a reference voltage GND.

[0039] The chip 10 includes a driving circuit 11, an upper bridge circuit 12, a lower bridge circuit 13, voltage-controlled current elements 14, 16, and bias elements 15, 17. The voltage-controlled current element 14 has a first end and a second end coupled to the pad P1 and the pad P2, respectively. The voltage-controlled current element 16 has a first end and a second end coupled to the pad P3 and the pad P4, respectively. The upper bridge circuit 12 is coupled to a control end of the voltage-controlled current element 14, and the lower bridge circuit 13 is coupled to a control end of the voltage-controlled current element 16. The driving circuit 11 is coupled to operations of the upper bridge circuit 12 and the lower bridge circuit 13.

[0040] In detail, the driving circuit 11 can generate driving signals DS1, DS2 to control operations of the upper bridge circuit 12 and the lower bridge circuit 13. The upper bridge circuit 12 and the lower bridge circuit 13 can generate control signals DS1', DS2' according to the driving signals DS1, DS2, respectively, to control the voltage-controlled current elements 14, 16 to selectively generate bias currents. When the voltage-controlled current element 14 generates a bias current, the bias current is provided to the bias element 15 to raise a voltage of the pad P2, thereby reducing a voltage difference between the gate and the source of the gallium nitride transistor GT1 to be less than a threshold voltage (e.g., -11 V), resulting in the gallium nitride transistor GT1 being turned off and disconnecting a connection between the drain and the source of the gallium nitride transistor GT1. Similarly, when the voltage-controlled current element 16 generates a bias current, the bias current is provided to the bias element 17 to raise a voltage of the pad P4, thereby reducing a voltage difference between the gate and the source of the gallium nitride transistor GT2 to be less than a threshold voltage (e.g., -11 V), resulting in the gallium nitride transistor GT2 being turned off and disconnecting a connection between the drain and the source of the gallium nitride transistor GT2.

[0041] Therefore, the chip 10 can control the turn-on and / or turn-off of the gallium nitride transistor GT1 through the voltage-controlled current element 14 and the bias element 15, and control the turn-on and / or turn-off of the gallium nitride transistor GT2 through the voltage-controlled current element 16 and the bias element 17. Specifically, when the voltage-controlled current element 14 is enabled or turned on, the voltage difference between the gate and the source of the gallium nitride transistor GT1 is reduced to be turned off, the gallium nitride transistor GT1 can be preferably controlled to be disabled, and the leakage current of the gallium nitride transistor GT1 is avoided, thereby improving the power consumption.

[0042] In some embodiments, the voltage-controlled current element 14, the bias element 15, and the gallium nitride transistor GT1 can be collectively regarded as a power transistor T1 for operation, and the power transistor T1 can have a first conduction state or a second conduction state, and the second conduction state (for example, p-type) is taken as an example for description. The first end (for example, the drain of the power transistor T1) of the power transistor T1 can be coupled to the pad P3, the second end (for example, the source of the power transistor T1) of the power transistor T1 can receive the reference voltage HVDD, and the control end (for example, the gate of the power transistor T1) of the power transistor T1 can receive the control of the upper bridge circuit 12. The power transistor T1 can control the conduction between the first end and the second end according to the voltage received by the control end.

[0043] When the control end of the power transistor T1, that is, the voltage-controlled current element 14 receives the enabled control signal DS1', the gallium nitride transistor GT1 is turned off according to the control of the control signal DS1'. In the case that the voltage-controlled current element 14 does not provide a bias current to the bias element 15, the voltage difference between the gate and the source of the gallium nitride transistor GT1 is greater than the threshold voltage, so that the power transistor T1 is turned on. Conversely, when the control end of the power transistor T1 receives the disabled control signal DS1', the gallium nitride transistor GT1 is turned on according to the control of the control signal DS1' to provide a bias current to the bias element 15, causing the source voltage of the gallium nitride transistor GT1 to rise, so that the voltage difference between the gate and the source of the gallium nitride transistor GT1 is less than the threshold voltage, so that the power transistor T1 is turned off.

[0044] Similarly, the voltage-controlled current element 16, the biasing element 17 and the gallium nitride transistor GT2 can be collectively considered as a power transistor T2 for operation, and the power transistor T2 can have a first conduction type or a second conduction type. Hereinafter, the power transistor T2 having the first conduction type (e.g. n-type) is taken as an example for description. The first terminal (e.g. drain) of the power transistor T2 can be coupled to the pad P3, the second terminal (e.g. source) of the power transistor T2 can be coupled to the pad P5, and the control terminal (e.g. gate) of the power transistor T2 can receive the control of the lower bridge circuit 13. The power transistor T2 can control the conduction between the first terminal and the second terminal according to the voltage received at the control terminal.

[0045] When the control terminal of the power transistor T2, i.e. the voltage-controlled current element 16 receives the enabled control signal DS2', the gallium nitride transistor GT2 is turned off according to the control of the control signal DS2'. In the case that the voltage-controlled current element 16 does not provide the biasing current to the biasing element 17, the voltage difference between the gate and the source of the gallium nitride transistor GT2 is greater than the threshold voltage, so that the power transistor T2 is turned on. Conversely, when the control terminal of the power transistor T2 receives the disabled control signal DS2', the gallium nitride transistor GT2 is turned on according to the control of the control signal DS2' to provide the biasing current to the biasing element 17, so that the source voltage of the gallium nitride transistor GT2 rises, and thus the voltage difference between the gate and the source of the gallium nitride transistor GT2 is less than the threshold voltage, so that the power transistor T2 is turned off.

[0046] Therefore, the electronic system 1 and the chip 10 can preferably control the conduction and / or the turn-off of the gallium nitride transistors GT1, GT2 through the coupling relationship between the voltage-controlled current elements 14, 16 and the biasing elements 15, 17 and the gallium nitride transistors GT1, GT2, so as to improve the overall power consumption. On the other hand, since the voltage-controlled current elements 14, 16 are not connected in series with the gallium nitride transistors GT1, GT2, the voltage-controlled current elements 14, 16 do not limit the conduction current of the gallium nitride transistors GT1, GT2, and the advantages of high current and fast switching of the gallium nitride transistors GT1, GT2 can be effectively retained.

[0047] Figure 2 FIG. 1 is a schematic diagram of an electronic system 2 according to an embodiment of the present application. The electronic system 2 includes a chip 20 and gallium nitride transistors GT1, GT2. The chip 20 includes a driving circuit 21, an upper bridge circuit 12, a lower bridge circuit 13, voltage-controlled current elements 24, 26 and biasing elements 25, 27.

[0048] The drain, source and gate of the gallium nitride transistor GT1 can be coupled to the pads P1, P2, P3, respectively. The drain, source and gate of the gallium nitride transistor GT2 can be coupled to the pads P3, P4, P5, respectively. In some embodiments, the gallium nitride transistors GT1, GT2 can be gallium nitride transistors of a first conductivity type (e.g., n-type). When the voltage difference between the gate and the source of the gallium nitride transistors GT1, GT2 is less than a threshold voltage, the gallium nitride transistors GT1, GT2 can be turned off, and the connection between the drain and the source of the gallium nitride transistors GT1, GT2 can be broken. When the voltage difference between the gate and the source of the gallium nitride transistors GT1, GT2 is greater than the threshold voltage, the gallium nitride transistors GT1, GT2 can be turned on, and the drain and the source of the gallium nitride transistors GT1, GT2 can be connected to each other.

[0049] In this embodiment, the driving circuit 21 includes a power supply circuit 210, a controller 211, and a level shifting circuit 212. The power supply circuit 210 is configured to provide a power supply voltage. The controller 211 is configured to control the operation of the upper bridge circuit 12 and the lower bridge circuit 13, thereby controlling the turn-on and / or turn-off of the power transistors T1, T2. The level shifting circuit 212 is coupled to the controller 211 and is configured to shift the voltage level provided by the controller 211 to generate driving signals DS1, DS2 suitable for controlling the voltage-controlled current elements 24, 26. Thus, the upper bridge circuit 12 and the lower bridge circuit 13 can receive the driving signals DS1, DS2, respectively, to generate control signals DS1', DS2', thereby driving the voltage-controlled current elements 24, 26.

[0050] The power transistors T1, T2 are connected in series to each other between a reference voltage HVDD and a reference voltage GND. The power transistor T1 can have, for example, a second conductivity type. A first terminal (e.g., the drain) of the power transistor T1 can be coupled to the pad P3, a second terminal (e.g., the source) of the power transistor T1 can receive the reference voltage HVDD, and a control terminal (e.g., the gate) of the power transistor T1 can be coupled to the upper bridge circuit 12. The power transistor T2 can have, for example, a first conductivity type. A first terminal (e.g., the drain) of the power transistor T2 can be coupled to the pad P3, a second terminal (e.g., the source) of the power transistor T2 can receive the reference voltage GND, and a control terminal (e.g., the gate) of the power transistor T2 can be coupled to the lower bridge circuit 13.

[0051] For the power transistor T1, the power transistor T1 includes the voltage-controlled current element 24, the bias element 25, and the gallium nitride transistor GT1. The voltage-controlled current element 24 is coupled to the upper bridge circuit 12 and the pads P1, P2. The bias element 25 is coupled to the pads P2, P3.

[0052] The voltage-controlled current element 24 includes a resistor Rl and a transistor MNl. The resistor Rl and the transistor MNl are connected in series with each other between the pads P1 and P2. In this embodiment, the transistor MNl can be, for example, a metal oxide semiconductor field effect transistor (MOSFET) of a first conduction type (e.g., n-type) that is turned on when a relatively high voltage is received at the gate of the transistor MNl and turned off when a relatively low voltage is received at the gate. The drain of the transistor MNl receives a reference voltage HVDD through the resistor Rl and the pad P1, the source of the transistor MNl is coupled to the pad P2, and the gate of the transistor MNl is coupled to the upper bridge circuit 12. In some embodiments, the gallium nitride transistor GTl can have a relatively high operating voltage (e.g., about 600 V), and the resistor Rl can step down the voltage received at the drain of the transistor MNl to a voltage suitable for operation of the metal oxide semiconductor transistor (e.g., about 30 V).

[0053] The biasing element 25 includes a resistor R2 and a zener diode ZDl. The resistor R2 and the zener diode ZDl are connected in series with each other between the pads P2 and P3. One end of the resistor R2 is coupled to the pad P2 and the source of the transistor MNl, and the other end of the resistor R2 is coupled to the cathode of the zener diode ZDl. The anode of the zener diode ZDl is coupled to the pad P3. In this way, when a biasing current is provided to the biasing element 25, the biasing element 25 can provide a stable voltage difference through the resistor R2 and the zener diode ZDl.

[0054] In terms of the power transistor Tl as a whole, when the control terminal of the power transistor Tl (i.e., the gate of the transistor MNl) receives a relatively high voltage, the voltage-controlled current element 24 in the power transistor Tl provides a biasing current to the biasing element 25, causing the source voltage of the gallium nitride transistor GTl to rise. Because the rising source voltage causes the voltage difference between the gate and the source of the gallium nitride transistor GTl to be less than the threshold voltage, the gallium nitride transistor GTl is turned off. Thus, the control terminal of the power transistor Tl can be considered to be turned off as a whole when it receives a relatively high voltage. Conversely, when the control terminal of the power transistor Tl (i.e., the gate of the transistor MNl) receives a relatively low voltage, the voltage-controlled current element 24 in the power transistor Tl does not provide a biasing current to the biasing element 25, so the voltage difference between the gate and the source of the gallium nitride transistor GTl can be greater than the threshold voltage, thereby controlling the gallium nitride transistor GTl. Thus, the control terminal of the power transistor Tl can be considered to be turned on as a whole when it receives a relatively low voltage.

[0055] Briefly, since the voltage-controlled current element 24 of the power transistor Tl is provided with the first conduction type transistor MNl, the power transistor Tl can be operated in the second conduction type. That is, when the control terminal of the power transistor Tl receives a relatively high voltage level, the power transistor Tl can be turned off. When the control terminal of the power transistor Tl receives a relatively low voltage level, the power transistor Tl can be turned on.

[0056] As for the power transistor T2, the power transistor T2 includes the voltage-controlled current element 26, the biasing element 27, and the gallium nitride transistor GT2. The voltage-controlled current element 26 is coupled between the lower bridge circuit 13 and the pads P3, P4. The biasing element is coupled between the pads P4, P5.

[0057] The voltage-controlled current element 26 includes the resistor R3 and the transistor MP1. The resistor R3 and the transistor MP1 are connected in series between the pads P3, P4. In this embodiment, the transistor MP1 can be, for example, a metal oxide semiconductor field effect transistor (MOSFET) of the second conduction type (e.g., p-type) that is turned on when the gate thereof receives a relatively low voltage level and turned off when the gate thereof receives a relatively high voltage level. The source of the transistor MP1 is coupled to the pad P3 through the resistor R3, the drain thereof is coupled to the pad P4, and the gate thereof is coupled to the lower bridge circuit 13.

[0058] The biasing element 27 includes the resistor R4 and the zener diode ZD2. The resistor R4 and the zener diode ZD2 are connected in series between the pads P4, P5. One end of the resistor R4 is coupled to the pad P4 and the drain of the transistor MP1, and the other end of the resistor R4 is coupled to the cathode of the zener diode ZD2. The anode of the zener diode ZD2 is coupled to the pad P5 and receives the reference voltage GND through the pad P5. In this way, when a biasing current is provided to the biasing element 27, the biasing element 27 can provide a stable voltage difference through the resistor R4 and the zener diode ZD2.

[0059] When the control terminal of the power transistor T2 (i.e. the gate of the transistor MP1) receives a relatively low voltage level, the voltage-controlled current element 26 in the power transistor T2 provides a bias current to the bias element 27, so that the source voltage of the gallium nitride transistor GT2 rises. Since the rising source voltage causes the voltage difference between the gate and the source of the gallium nitride transistor GT2 to be less than the threshold voltage, the gallium nitride transistor GT2 is turned off. Therefore, the control terminal of the power transistor T2 can be regarded as being turned off when it receives a relatively low voltage level. On the contrary, when the control terminal of the power transistor T2 (i.e. the gate of the transistor MP1) receives a relatively high voltage level, the voltage-controlled current element 26 in the power transistor T2 does not provide a bias current to the bias element 27, so that the voltage difference between the gate and the source of the gallium nitride transistor GT2 can be greater than the threshold voltage, thereby controlling the gallium nitride transistor GT2. Therefore, the control terminal of the power transistor T2 can be regarded as being turned on when it receives a relatively high voltage level.

[0060] In brief, since the voltage-controlled current element 26 in the power transistor T2 is provided with the transistor MP1 of the second conduction mode, the power transistor T2 can be operated in the first conduction mode. That is, when the control terminal of the power transistor T2 receives a relatively low voltage level, the power transistor T2 can be turned off. When the control terminal of the power transistor T2 receives a relatively high voltage level, the power transistor T2 can be turned on.

[0061] Therefore, in general, the coupling relationship between the voltage-controlled current elements 24, 26 and the bias elements 25, 27 and the gallium nitride transistors GT1, GT2 provided inside the chip 20 in the electronic system 2 can make the voltage-controlled current element 24, the bias element 25 and the gallium nitride transistor GT1 form the power transistor T1 having the second conduction mode, and the voltage-controlled current element 26, the bias element 27 and the gallium nitride transistor GT2 form the power transistor T2 having the first conduction mode. The conduction and / or turn-off of the gallium nitride transistors GT1, GT2 are controlled by the voltage-controlled current elements 24, 26 and the bias elements 25, 27 on the chip 20, so as to preferably avoid the leakage current of the gallium nitride transistors GT1, GT2, thereby improving the power consumption of the electronic system 2.

[0062] Figure 3 FIG. 1 shows a schematic diagram of an embodiment one electronic system 3. The chip 30 includes a driving circuit 21, an upper bridge circuit 12, a lower bridge circuit 13, voltage-controlled current elements 34, 26, bias elements 25, 27 and a bootstrap circuit 38. Figure 3 The electronic system 3 shown is similar to the electronic system 2 shown in FIG. 1. Figure 2The electronic system 2 is illustrated, and thus the same elements are labeled with the same reference numerals. The electronic system 3 includes a chip 30 and gallium nitride transistors GT1, GT2. The electronic system 3 differs from the electronic system 2 in that the voltage-controlled current element 24 in the chip 20 of the electronic system 2 is replaced by a voltage-controlled current element 34 in the chip 30 of the electronic system 3. Also, the chip 30 of the electronic system 3 further includes a bootstrap circuit 38 and a capacitor C2. Thus, the operation of the drive circuit 21, the upper bridge circuit 12, the lower bridge circuit 13, the voltage-controlled current element 26, the bias elements 25, 27 are described in the above paragraphs and are not repeated here.

[0063] The voltage-controlled current element 34 includes a resistor R1 and a transistor MP2. The resistor R1 and the transistor MP2 are connected in series with each other between the pads P1, P2. In this embodiment, the transistor MP2 can be, for example, a metal oxide semiconductor field effect transistor (MOSFET) of a second conductivity type (e.g., p-type) that is turned on when a relatively low voltage is received at the gate of the transistor MP2 and turned off when a relatively high voltage is received at the gate of the transistor MP2. The source of the transistor MP2 receives the reference voltage HVDD through the resistor R1 and the pad P1, the drain of the transistor MP2 is coupled to the pad P2, and the gate of the transistor MP2 is coupled to the upper bridge circuit 12. In some embodiments, the gallium nitride transistor GT1 can have a relatively high operating voltage (e.g., about 600 V), and the resistor R1 can step down the voltage received at the drain of the transistor MP2 to a voltage suitable for operation of the metal oxide semiconductor transistor (e.g., about 30 V).

[0064] In some embodiments, the voltage-controlled current element 34, the bias element 25, and the gallium nitride transistor GT1 can be collectively considered as a power transistor T3 for operation, which can be, for example, of a first conductivity type. The first terminal of the power transistor T3 (e.g., the drain of the power transistor T3) can receive the reference voltage HVDD, the second terminal of the power transistor T3 (e.g., the source of the power transistor T3) can be coupled to the pad P3, and the control terminal of the power transistor T3 (e.g., the gate of the power transistor T3) can receive the control of the upper bridge circuit 12. The power transistor T3 can control the conduction between the first terminal and the second terminal in accordance with the voltage received at the control terminal.

[0065] In terms of the power transistor T3 as a whole, when the control terminal of the power transistor T3 (i.e. the gate of the transistor MP2) receives a relatively low voltage level, the voltage-controlled current element 34 in the power transistor T3 provides a bias current to the bias element 25, causing the source voltage of the gallium nitride transistor GT1 to rise. Since the rising source voltage causes the voltage difference between the gate and the source of the gallium nitride transistor GT1 to be less than the threshold voltage, the gallium nitride transistor GT1 is turned off. Thus, the control terminal of the power transistor T3 can be regarded as being turned off when it receives a relatively low voltage level. Conversely, when the control terminal of the power transistor T3 (i.e. the gate of the transistor MP2) receives a relatively high voltage level, the voltage-controlled current element 34 in the power transistor T3 does not provide a bias current to the bias element 25, so the voltage difference between the gate and the source of the gallium nitride transistor GT1 can be greater than the threshold voltage, thereby controlling the gallium nitride transistor GT1. Thus, the control terminal of the power transistor T3 can be regarded as being turned on when it receives a relatively high voltage level.

[0066] Briefly, since the voltage-controlled current element 34 in the power transistor T3 is provided with the second conduction mode transistor MP2, the power transistor T3 can be operated in the first conduction mode. That is, when the control terminal of the power transistor T3 receives a relatively low voltage level, the power transistor T3 can be turned off. When the control terminal of the power transistor T3 receives a relatively high voltage level, the power transistor T3 can be turned on.

[0067] Corresponding to the power transistor T3 in the first conduction mode, the chip 30 is also provided with a bootstrap circuit 38. The bootstrap circuit 38 includes a diode D1 and a capacitor C1, which are connected in series between the driving circuit 21 and the pad P3. The anode of the diode D1 is coupled to the power supply circuit 210 of the driving circuit 21, the cathode of the diode D1 is coupled to one end of the capacitor C1, and the other end of the capacitor C1 is coupled to the pad P3.

[0068] For the operation of the bootstrap circuit 38, when the power transistor T3 is turned off and the power transistor T2 is turned on, the voltage on the pad P3 is correspondingly pulled down. Thus, the upper plate of the capacitor C1 in the bootstrap circuit 38 is charged by the power supply circuit 210. When the power transistor T3 is turned on and the power transistor T2 is turned off, the voltage on the pad P3 is pulled up, and the voltage on the upper plate of the capacitor C1 is correspondingly raised. Thus, the bootstrap circuit 38 can generate a raised power supply voltage to the upper bridge circuit 12 through the operation of the power transistors T3 and T2.

[0069] Further, since the power transistor T3 is a power transistor with a first conduction type, the control signal DS1' generated by the raised power supply voltage can better control the voltage difference between the control terminal and the first terminal of the power transistor T3 to control the power transistor T3 to be cut off.

[0070] In summary, the electronic system and the chip of the present application can better control the conduction and / or cut-off of the gallium nitride transistor without changing the structure of the gallium nitride transistor itself by additional processes, and retain the high current and fast switching advantages of the gallium nitride transistor itself, effectively avoid the leakage current of the gallium nitride transistor, and thus improve the overall power consumption of the electronic system.

[0071] Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present application, and not to limit them; although the present application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand: it can still modify the technical solutions recorded in the foregoing embodiments, or make equivalent replacement for part or all of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A chip, characterized by For controlling a first gallium nitride transistor and a second gallium nitride transistor, a source of the first gallium nitride transistor is coupled to a drain of the second gallium nitride transistor, the chip comprising: a first pad, a second pad, a third pad, a fourth pad and a fifth pad, the first pad, the second pad and the third pad are respectively for coupling to a drain, a source and a gate of the first gallium nitride transistor, the third pad, the fourth pad and the fifth pad are respectively for coupling to a drain, a source and a gate of the second gallium nitride transistor; a first voltage-controlled current element having a first terminal and a second terminal coupled to the first pad and the second pad respectively; a second voltage-controlled current element having a first terminal and a second terminal coupled to the third pad and the fourth pad respectively; a first biasing element coupled between the second pad and the third pad; and a second biasing element coupled between the fourth pad and the fifth pad, wherein the first biasing element adjusts a bias voltage of the second pad according to a control of the first voltage-controlled current element, and the second biasing element adjusts a bias voltage of the fourth pad according to a control of the second voltage-controlled current element.

2. The chip of claim 1, wherein Further comprising: an upper bridge circuit coupled to a control terminal of the first voltage-controlled current element; and a lower bridge circuit coupled to a control terminal of the second voltage-controlled current element, wherein the first voltage-controlled current element provides a first bias current to the first biasing element according to a control of the upper bridge circuit to control the first gallium nitride transistor to be turned on or turned off, wherein the second voltage-controlled current element provides a second bias current to the second biasing element according to a control of the lower bridge circuit to control the second gallium nitride transistor to be turned on or turned off. The first biasing element comprises:

3. The chip of claim 1, wherein a first resistor having a first terminal coupled to the second pad; and a first diode having a cathode coupled to a second terminal of the first resistor and an anode coupled to the third pad, wherein the second biasing element comprises: a second resistor having a first terminal coupled to the fourth pad; and a second diode having a cathode coupled to a second terminal of the second resistor and an anode coupled to the fifth pad. Further comprising:

4. The chip of claim 2, wherein a power supply circuit coupled to the upper bridge circuit and the lower bridge circuit, the power supply circuit is configured to provide a first power supply voltage; a controller coupled to the upper bridge circuit and the lower bridge circuit, the controller is configured to generate a first driving signal and a second driving signal to control operations of the upper bridge circuit and the lower bridge circuit; and a level shifting circuit coupled to the controller, the upper bridge circuit and the lower bridge circuit, the level shifting circuit is configured to adjust voltage levels of the first driving signal and the second driving signal. The first voltage-controlled current element comprises an n-type metal-oxide-semiconductor field effect transistor, when the first voltage-controlled current element receives a high logic level voltage, the first voltage-controlled current element provides the first bias current to the first biasing element to control the first gallium nitride transistor to be turned off, ​ 5. The chip of claim 4, wherein, ​ The second voltage-controlled current element includes a p-type MOSFET, and when the second voltage-controlled current element receives a low logic level voltage, the second voltage-controlled current element provides the second bias current to the second bias element to control the second GaN transistor to be turned off.

6. The chip of claim 4, wherein, The first voltage-controlled current element includes a first p-type MOSFET, and when the first voltage-controlled current element receives a low logic level voltage, the first voltage-controlled current element provides the first bias current to the first bias element to control the first GaN transistor to be turned off, The second voltage-controlled current element includes a second p-type MOSFET, and when the second voltage-controlled current element receives the low logic level voltage, the second voltage-controlled current element provides the second bias current to the second bias element to control the second GaN transistor to be turned off.

7. The chip of claim 6, wherein Further comprising: a bootstrap circuit coupled between the power supply circuit and the third pad, the bootstrap circuit boosting the first power supply voltage to generate a boosted power supply voltage, the bootstrap circuit including: a diode having an anode and a cathode, the anode of the diode coupled to the power supply circuit; and a capacitor coupled between the cathode of the diode and the third pad, wherein the bootstrap circuit generates the boosted first power supply voltage at the cathode of the diode and provides the boosted power supply voltage to the upper bridge circuit. comprising:

8. An electronic system, characterized by a first GaN transistor having a drain, a source, and a gate; a second GaN transistor having a drain, a source, and a gate, the source of the first GaN transistor coupled to the drain of the second GaN transistor; and a chip to control operations of the first GaN transistor and the second GaN transistor, the chip including: a first pad, a second pad, a third pad, a fourth pad, and a fifth pad, the first pad, the second pad, and the third pad coupled to the drain, the source, and the gate of the first GaN transistor, respectively, the third pad, the fourth pad, and the fifth pad coupled to the drain, the source, and the gate of the second GaN transistor, respectively; a first voltage-controlled current element having a first terminal and a second terminal coupled to the first pad and the second pad, respectively; a second voltage-controlled current element having a first terminal and a second terminal coupled to the third pad and the fourth pad, respectively; a first bias element coupled between the second pad and the third pad; and a second bias element coupled between the fourth pad and the fifth pad, wherein the first bias element adjusts a bias voltage of the second pad according to control of the first voltage-controlled current element, and the second bias element adjusts a bias voltage of the fourth pad according to control of the second voltage-controlled current element. The chip further includes: an upper bridge circuit coupled to a control terminal of the first voltage-controlled current element; and 9. The electronic system of claim 8, wherein, a lower bridge circuit coupled to a control terminal of the second voltage-controlled current element, ​ ​ wherein the first voltage-controlled current element provides a first bias current to the first bias element according to a control of the upper bridge circuit to control the first GaN transistor to be turned on or turned off, wherein the second voltage-controlled current element provides a second bias current to the second bias element according to a control of the lower bridge circuit to control the second GaN transistor to be turned on or turned off.

10. The electronic system of claim 8, wherein, The first bias element comprises: a first resistor having a first end coupled to the second pad; and a first diode having a cathode coupled to a second end of the first resistor and an anode coupled to the third pad, wherein the second bias element comprises: a second resistor having a first end coupled to the fourth pad; and a second diode having a cathode coupled to a second end of the second resistor and an anode coupled to the fifth pad.

11. The electronic system of claim 9, wherein, The chip further comprises: a power supply circuit coupled to the upper bridge circuit and the lower bridge circuit, the power supply circuit configured to provide a power supply voltage; a controller coupled to the upper bridge circuit and the lower bridge circuit, the controller configured to generate a first driving signal and a second driving signal to control operations of the upper bridge circuit and the lower bridge circuit; and a level shifter circuit coupled to the controller, the upper bridge circuit and the lower bridge circuit, the level shifter circuit configured to adjust voltage levels of the first driving signal and the second driving signal.

12. The electronic system of claim 11, wherein, The first voltage-controlled current element comprises an n-type MOSFET, when the first voltage-controlled current element receives a high logic level voltage, the first voltage-controlled current element provides the first bias current to the first bias element to control the first GaN transistor to be turned off, wherein the second voltage-controlled current element comprises a p-type MOSFET, when the second voltage-controlled current element receives a low logic level voltage, the second voltage-controlled current element provides the second bias current to the second bias element to control the second GaN transistor to be turned off.

13. The electronic system of claim 11, wherein, The first voltage-controlled current element comprises a first p-type MOSFET, when the first voltage-controlled current element receives a low logic level voltage, the first voltage-controlled current element provides the first bias current to the first bias element to control the first GaN transistor to be turned off, wherein the second voltage-controlled current element comprises a second p-type MOSFET, when the second voltage-controlled current element receives the low logic level voltage, the second voltage-controlled current element provides the second bias current to the second bias element to control the second GaN transistor to be turned off.

14. The electronic system of claim 13, wherein, The chip further comprises: a bootstrap circuit coupled between the power supply circuit and the third pad, the bootstrap circuit configured to boost the power supply voltage to generate a boosted power supply voltage, the bootstrap circuit comprising: a diode having an anode and a cathode, the anode of the diode coupled to the power supply circuit; and a capacitor coupled between the cathode of the diode and the third pad, The bootstrap circuit generates a boosted first power voltage at the cathode of the diode and supplies the boosted first power voltage to the upper bridge circuit.

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