A piva voltage reference system

Abstract

This invention relates to the field of voltage reference setting technology and provides a piv voltage reference system. By setting depletion-type NMOS transistors MN1S and MN2S respectively on the positive temperature coefficient voltage circuit PTAT and the negative temperature coefficient voltage circuit CTAT, respectively forming the current sources of the positive temperature coefficient voltage circuit PTAT and the negative temperature coefficient voltage circuit CTAT, the power supply rejection ratio can be improved. By setting a positive bistable topology of stacked depletion-type NMOS transistors MN1U and MN1D and a negative bistable topology of stacked depletion-type NMOS transistors MN2U and MN2D respectively on the positive temperature coefficient voltage circuit PTAT and the negative temperature coefficient voltage circuit CTAT, the linear sensitivity of the output voltage of the positive temperature coefficient voltage circuit PTAT and the negative temperature coefficient voltage circuit CTAT to the power supply can be suppressed.

Description

Technical Field

[0001] This invention relates to the technical field of voltage reference setting, and more particularly to a piva voltage reference system. Background Technology

[0002] With continuous social development and technological innovation, wearable devices are increasingly being used by humans. Wearable devices are portable devices worn directly on the body or integrated into clothing or accessories. Wearable devices are not merely hardware devices; they achieve powerful functions through software support, data interaction, and cloud interaction, and will bring significant changes to our lives and perceptions. Meanwhile, in the field of Internet of Things (IoT) applications, IoT application chips are frequently used. IoT application chips are more flexible and have more specialized roles; they are more directional and require application in specific environments.

[0003] Because wearable devices and IoT application chips typically require sophisticated designs, the final product area is not large, and power consumption is critical. Furthermore, wearable devices and IoT application chips often need to operate under unstable supply voltages. Therefore, a voltage reference is needed to provide a precise and stable voltage, ensuring that the operation of wearable devices and IoT application chips is not affected by process technology, supply voltage, or temperature.

[0004] A bandgap voltage reference circuit provides accurate and stable voltage, unaffected by process technology, supply voltage, or temperature, making it an important analog module. A traditional bandgap voltage reference consists of two parts: a positive temperature coefficient voltage circuit (PTAT) and a negative temperature coefficient voltage circuit (CTAT). These two circuits cancel each other out with a certain coefficient, forming a near-zero temperature coefficient voltage. However, ordinary bandgap voltage references typically have poor power supply rejection ratio (PSRR) and line sensitivity, resulting in weak noise suppression performance on the supply voltage. A common practice to improve PSRR is to connect a capacitor at the output, but the effect is not ideal. Summary of the Invention

[0005] To address the aforementioned problems, the present invention aims to provide a piva voltage reference system for improving the power supply rejection ratio and linear sensitivity of the voltage reference.

[0006] The above-mentioned objective of this invention is achieved through the following technical solutions:

[0007] A Piva voltage reference system includes: a positive temperature coefficient voltage circuit PTAT, a negative temperature coefficient voltage circuit CTAT, connecting lines for the positive and negative temperature coefficient voltage circuits, and a voltage output terminal VREF;

[0008] The positive temperature coefficient voltage circuit PTAT is used to generate a positive temperature coefficient voltage;

[0009] The negative temperature coefficient voltage circuit CTAT is used to generate a negative temperature coefficient voltage.

[0010] The negative temperature coefficient voltage circuit CTAT is connected in parallel with the positive temperature coefficient voltage circuit PTAT through the positive and negative temperature coefficient voltage circuit connection line, so that the generated negative temperature coefficient voltage is offset by the positive temperature coefficient voltage generated by the positive temperature coefficient voltage circuit PTAT, forming a deducted output voltage;

[0011] The voltage output terminal VREF is connected to the positive temperature coefficient voltage circuit PTAT, and outputs the deducted output voltage.

[0012] Furthermore, the positive temperature coefficient voltage circuit PTAT specifically includes:

[0013] The following transistors are arranged sequentially from the positive temperature coefficient voltage source VDD to the positive temperature coefficient ground point VSS: depletion-type NMOS transistor MN1S, depletion-type NMOS transistor MN1U, depletion-type NMOS transistor MN1D, self-biased current source PMOS transistor MP1, and load MP2.

[0014] Furthermore, the negative temperature coefficient voltage circuit CTAT specifically includes:

[0015] The following transistors are arranged sequentially from the negative temperature coefficient voltage source VDD to the negative temperature coefficient ground point VSS: depletion-type NMOS transistor MN2S, depletion-type NMOS transistor MN2U, depletion-type NMOS transistor MN2D, self-biased current source PMOS transistor MP3, and load Q1.

[0016] Furthermore, the load MP2 is a diode formed by connecting a PMOS transistor through the positive and negative temperature coefficient voltage circuit connection line; the load Q1 is composed of a PNP transistor.

[0017] Furthermore, the depletion-type NMOS transistors MN1S and MN2S are arranged in pairs to form the current sources of the positive temperature coefficient voltage circuit PTAT and the negative temperature coefficient voltage circuit CTAT, respectively, in order to improve the power supply rejection ratio.

[0018] Furthermore, the depletion-type NMOS transistors MN1U and MN1D are stacked to form a positive bistable topology; the depletion-type NMOS transistors MN2U and MN2D are stacked to form a negative bistable topology; the positive and negative bistable topologies are arranged in pairs to suppress the linear sensitivity of the output voltages of the positive temperature coefficient voltage circuit PTAT and the negative temperature coefficient voltage circuit CTAT to the power supply.

[0019] Furthermore, the self-biased current source PMOS transistor MP1 is used to feed back to the load MP2; the self-biased current source PMOS transistor MP3 is used to feed back to the load Q1.

[0020] Furthermore, the load MP2 adopts a substrate bias structure.

[0021] A wearable device powered by a piva voltage reference system as described above.

[0022] An IoT application chip is powered by a piva voltage reference system as described above.

[0023] Compared with the prior art, the present invention has at least one of the following beneficial effects:

[0024] (1) A piva voltage reference system is provided, comprising: a positive temperature coefficient voltage circuit PTA T, a negative temperature coefficient voltage circuit CTAT, a connection line between the positive and negative temperature coefficient voltage circuits, and a voltage output terminal VREF; the positive temperature coefficient voltage circuit PTAT is used to generate a positive temperature coefficient voltage; the negative temperature coefficient voltage circuit CTAT is used to generate a negative temperature coefficient voltage; the negative temperature coefficient voltage circuit CTAT is connected in parallel with the positive temperature coefficient voltage circuit PTA T through the connection line between the positive and negative temperature coefficient voltage circuits, so that the generated negative temperature coefficient voltage is offset against the positive temperature coefficient voltage generated by the positive temperature coefficient voltage circuit PTAT, forming a deducted output voltage; the voltage output terminal VREF is connected to the positive temperature coefficient voltage circuit PTAT, and outputs the deducted output voltage. The above technical solution enables our voltage reference to consist of two parts: a positive temperature coefficient voltage circuit PTAT and a negative temperature coefficient voltage circuit CTAT. The output positive and negative temperature coefficient voltages are offset by a certain coefficient, forming a voltage with an approximate zero temperature coefficient.

[0025] (2) By setting depletion-type NMOS transistors MN1S and MN2S on the positive temperature coefficient voltage circuit PTAT and the negative temperature coefficient voltage circuit CTAT respectively, the current sources of the positive temperature coefficient voltage circuit PTAT and the negative temperature coefficient voltage circuit CTAT can be formed respectively, thereby improving the power supply rejection ratio.

[0026] (3) By setting a positive bistable topology consisting of stacked depletion-type NMOS transistors MN1U and MN1D, and a negative bistable topology consisting of stacked depletion-type NMOS transistors MN2U and MN2D, respectively, on the positive temperature coefficient voltage circuit PTAT and the negative temperature coefficient voltage circuit CTAT, the above technical solutions can suppress the linear sensitivity of the output voltage of the positive temperature coefficient voltage circuit PTAT and the negative temperature coefficient voltage circuit CTAT to the power supply.

[0027] (4) By adopting a substrate bias structure for the load MP2, the impact of process changes can be reduced and the power supply rejection ratio can be improved.

[0028] (5) The lowest operating voltage of the present invention can reach 0.8V; low power consumption; no on-chip capacitor required, and good power supply rejection ratio (PSRR) can be achieved; and only ordinary PMOS, depletion-type NMOS and PNP devices are used. Attached Figure Description

[0029] Figure 1 This is an overall structural diagram of a piva voltage reference system according to the present invention;

[0030] Figure 2 This is a schematic diagram of the positive temperature coefficient voltage circuit PTAT and the negative temperature coefficient voltage circuit CTAT of the present invention canceling each other out to generate the output voltage VREF.

[0031] Figure 3 This is a simulation diagram of the output voltage VREF of the present invention;

[0032] Figure 4 This is a schematic diagram illustrating the simulation effect of the power supply rejection ratio (PSRR) of the present invention. Detailed Implementation

[0033] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0034] Those skilled in the art will understand that, unless specifically stated otherwise, the singular forms “a,” “an,” “the,” and “the” used herein may also include the plural forms. It should be further understood that the term “comprising” as used in this specification means the presence of the stated features, integers, steps, operations, elements, and / or components, but does not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0035] First Embodiment

[0036] like Figure 1 As shown, this embodiment provides a piva voltage reference system, including: a positive temperature coefficient voltage circuit (PTAT). Figure 1 Left side), Negative Temperature Coefficient Voltage Circuit (CTAT) Figure 1 (Right side), positive and negative temperature coefficient voltage circuit connection lines ( Figure 1 (The line marked VB) and the voltage output terminal VREF.

[0037] The positive temperature coefficient voltage circuit PTAT is used to generate a positive temperature coefficient voltage; the negative temperature coefficient voltage circuit CTAT is used to generate a negative temperature coefficient voltage; the negative temperature coefficient voltage circuit CTAT is connected in parallel with the positive temperature coefficient voltage circuit PTAT through the connection line between the positive and negative temperature coefficient voltage circuits, canceling out the generated negative temperature coefficient voltage with the positive temperature coefficient voltage generated by the positive temperature coefficient voltage circuit PTAT, forming a subtracted output voltage; the voltage output terminal VREF is connected to the positive temperature coefficient voltage circuit PTAT, outputting the subtracted output voltage. The subtracted output voltage is approximately a zero temperature coefficient voltage. Figure 2 The diagram shows a positive temperature coefficient voltage circuit PTAT and a negative temperature coefficient voltage circuit CTAT canceling each other out to generate the output voltage VREF.

[0038] Furthermore, for the positive temperature coefficient voltage circuit PTAT, from the positive temperature coefficient voltage source VDD to the positive temperature coefficient ground point VSS, a depletion-type NMOS transistor MN1S, a depletion-type NMOS transistor MN1U, a depletion-type NMOS transistor MN1D, a self-biased current source PMOS transistor MP1, and a load MP2 are sequentially arranged.

[0039] Furthermore, for the negative temperature coefficient voltage circuit CTAT, the depletion-type NMOS transistors MN2S, MN2U, and MN2D, the self-biased current source PMOS transistor MP3, and the load Q1 are sequentially arranged from the negative temperature coefficient voltage source VDD to the negative temperature coefficient ground point VSS.

[0040] Furthermore, the load MP2 is a diode formed by connecting a PMOS transistor through the positive and negative temperature coefficient voltage circuit connection line; the load Q1 is composed of a PNP transistor.

[0041] Furthermore, the depletion-type NMOS transistors MN1S and MN2S are arranged in pairs (MN1S, MN2S), which are two self-adjusting depletion-type NMOS transistors, and respectively constitute the current source of the positive temperature coefficient voltage circuit PTAT and the negative temperature coefficient voltage circuit CTAT, in order to improve the power supply rejection ratio.

[0042] Furthermore, the depletion-type NMOS transistors MN1U and MN1D are stacked to form a positive bistable topology (MN1U & MN1D); the depletion-type NMOS transistors MN2U and MN2D are stacked to form a negative bistable topology (MN2U & MN2D); the positive and negative bistable topologies are arranged in pairs to suppress the linear sensitivity of the output voltages of the positive temperature coefficient voltage circuit PTAT and the negative temperature coefficient voltage circuit CTAT to the power supply.

[0043] Furthermore, the self-biased current source PMOS transistor MP1 is used to feed back to the load MP2;

[0044] The self-biased current source PMOS transistor MP3 is used to feed back current to the load Q1.

[0045] Furthermore, the load MP2 adopts a substrate bias structure, which can reduce the impact of process changes and improve the power supply rejection ratio.

[0046] Furthermore, the principle of generating an output voltage with an approximate zero temperature coefficient by canceling out the negative temperature coefficient voltage and the positive temperature coefficient voltage of the present invention is as follows:

[0047] CTAT negative temperature coefficient voltage generates substrate voltage V B :

[0048]

[0049] Where VBG is the bandgap voltage, Vth3 is the MP3 threshold voltage, η3 is the MP3 subthreshold slope factor, VT is the thermal voltage, α is the scaling factor, and T is the absolute temperature.

[0050] Band gap voltage VBG: It is approximately 0.7V and is the voltage required for a PN junction to transition from an insulating state to a conductive state. The specific voltage depends on the material.

[0051] Thermoelectric voltage VT is defined as the potential difference that occurs between two points in a closed circuit due to a temperature difference. Thermoelectric voltage formula: VT = kT / q, where k and q are constants, k (k = 1.38 × 10⁻²³ J / K) and q (q = 1.6 × 10⁻¹⁹ C). The value of VT can be calculated from the temperature.

[0052] PTAT positive temperature coefficient voltage (threshold voltage of MP2 in the voltage threshold region):

[0053]

[0054] Where Vth2 is the MP2 threshold voltage, η2 is the MP2 subthreshold slope factor, and V BS2 : is the well-source voltage difference of MP2, V B : represents the substrate voltage, V REF : This is the output reference voltage.

[0055] They cancel each other out to form a zero temperature coefficient voltage V REF :

[0056]

[0057] Among them, V th1 η1: is the MP1 threshold voltage, η1: is the MP1 subthreshold slope factor, V th2 η2: MP2 threshold voltage, η2: MP2 subthreshold slope factor, V th3 η3: MP3 subthreshold slope factor; N1: MP1 multiplier coefficient; W1: MP1 width; L1: MP1 length; N2: MP2 multiplier coefficient; W2: MP2 width; L2: MP2 length; V T : represents thermal voltage, α: is the scaling factor, and T: is the absolute temperature.

[0058] like Figure 3 The figure shows a simulation diagram of the output voltage VREF. Minimum operating voltage: 0.8V (normal 1.8V); output voltage VREF range: 123.3mV~156mV; temperature coefficient: 137ppm℃; power consumption: 448.9pW.

[0059] like Figure 4 The image shows a simulation result of the Power Supply Rejection Ratio (PSRR). PSRR = -42dB@100Hz; the power supply rejection performance is good at high frequencies.

[0060] Second Embodiment

[0061] This embodiment provides a wearable device powered by a piva voltage reference system as described in any of the first embodiments.

[0062] Third Embodiment

[0063] This embodiment provides an Internet of Things (IoT) application chip that is powered by a piva voltage reference system as described in any of the first embodiments.

[0064] The above description is merely a preferred embodiment of the present invention. The scope of protection of the present invention is not limited to the above embodiments. All technical solutions falling within the scope of the present invention's concept are within the scope of protection of the present invention. It should be noted that for those skilled in the art, any improvements and modifications made without departing from the principles of the present invention should also be considered within the scope of protection of the present invention.

[0065] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0066] It should be noted that the above embodiments can be freely combined as needed. The above description is only a preferred embodiment of the present invention. It should be pointed out that for those skilled in the art, several improvements and modifications can be made without departing from the principle of the present invention, and these improvements and modifications should also be considered within the scope of protection of the present invention.

Claims

1. A pico-voltage reference system, characterized by, The application relates to a pico-voltage reference system. The application relates to a pico-voltage reference system. The application relates to a pico-voltage reference system. The application relates to a pico-voltage reference system. The application relates to a pico-voltage reference system. The application relates to a pico-voltage reference system. The application relates to a pico-voltage reference system. The application relates to a pico-voltage reference system. The application relates to a pico-voltage reference system. The application relates to a pico-voltage reference system. The application relates to a pico-voltage reference system. The application relates to a pico-voltage reference system. The application relates to a pico-voltage reference system.

2. The pico-voltage reference system of claim 1, wherein, The application relates to a pico-voltage reference system. The application relates to a pico-voltage reference system.

3. The pico-voltage reference system of claim 1, wherein, The application relates to a pico-voltage reference system. The application relates to a pico-voltage reference system.

4. The pico-voltage reference system of claim 1, wherein, The application relates to a pico-voltage reference system. The application relates to a pico-voltage reference system. The application relates to a pico-voltage reference system.

5. The pico-voltage reference system of claim 1, wherein, The application relates to a pico-voltage reference system. The application relates to a pico-voltage reference system.

6. A wearable device, comprising: The application relates to a pico-voltage reference system. The application relates to a pico-voltage reference system.

7. An Internet of Things application chip, characterized by The application relates to a pico-voltage reference system. The application relates to a pico-voltage reference system. The application relates to a pico-voltage reference system. The application relates to a pico-voltage reference system. The application relates to a pico-voltage reference system. The application relates to a pico-voltage reference system. The application relates to a pico-voltage reference system. The application relates to a pico-voltage reference system. The application relates to a pico-voltage reference system. The application relates to a pico-voltage reference system. The application relates to a pico-voltage reference system. The application relates to a pico-voltage reference system. The application relates to a pico-voltage reference system. The application relates to a pico-voltage reference system. The application relates to a pico-voltage reference system. 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