Layout method considering the influence of TAP CELL on single event effect

Abstract

The present invention belongs to the technical field of semiconductors and integrated circuits, and specifically relates to a layout method for considering the influence of TAP CELL on single-event effects; the single-event effect hardening method for integrated circuits of the present invention is applicable to bulk silicon processes that use TAP CELL as a substrate contact. This hardening method mainly utilizes the characteristic that the single-event effect sensitivity of standard cells changes with the change of their distance from TAP CELL. First, through netlist-level analysis, the soft error rate of each standard cell is obtained, and then during circuit layout, by adjusting the positions of different cells, the overall soft error rate of the circuit is reduced. The present invention is compatible with the original integrated circuit process flow, has high flexibility, and can reduce the overall soft error rate of the circuit without increasing the area overhead.

Description

Technical Field

[0001] The present invention belongs to the technical field of integrated circuit anti-single event effect hardening and fault-tolerant design, and particularly relates to a layout method considering the influence of TAP CELL on single event effects. Background Art

[0002] When the electronic devices in a circuit are bombarded by high-energy particles, additional charges will be generated. After the additional charges are collected by circuit nodes, it may cause the state of the logic circuit to flip, and then lead to circuit failures. Especially in radiation environments such as the aerospace field, the hardening design against soft errors of integrated circuits is particularly important. With the continuous development of the aerospace field and the continuous enrichment of application fields, chips with higher integration are gradually applied in related fields, and more flexible design methods for the radiation hardening of circuits are also required.

[0003] Sequential logic units such as flip-flops and latches will generate single event flips after being affected by space radiation, resulting in changes in their operating states. With the continuous development of CMOS technology, the continuous reduction of device feature sizes, the continuous increase of the operating frequency of integrated circuits, and the continuous decrease of the operating voltage, the critical charge (Q critical ) for single event flips (SEU) in sequential logic circuits is continuously decreasing, and the probability of single event flips in sequential logic units is continuously increasing. For combinational logic circuits, the critical charge for single event transients is getting smaller and smaller, and the probability that the single event effects generated by the combinational circuit are finally latched by sequential units into soft errors is also continuously increasing. Combinational circuits are becoming more and more sensitive to single event transients, and the proportion of combinational logic in the overall soft errors of the circuit is getting higher and higher. In advanced integrated circuit processes, soft errors caused by combinational logic are gradually becoming the main factor. This means that in the radiation hardening of integrated circuits, more flexible hardening methods are needed for circuit hardening.

[0004] Existing circuit hardening solutions are mainly achieved by increasing circuit redundancy. In combinational circuits, the triple modular redundancy circuit is a relatively commonly used hardening method, which can better harden single event effects and increase the reliability of the circuit. However, while such hardening methods improve the circuit fault tolerance, they also significantly increase the chip area and power consumption. More flexible hardening methods are needed for the radiation hardening of integrated circuits. Summary of the Invention

[0005] The present invention provides a circuit layout-level radiation hardening method with relatively small additional area overhead and broad applicability, which is applicable to semi-custom integrated circuit designs with TAP CELL as the substrate contact. This method utilizes the property that the SET sensitivities of standard cells at different positions from the TAP CELL in the layout are different to perform layout hardening design. This hardening method does not bring too much additional overhead and has a broad applicable range, and can provide additional radiation resistance performance for the circuit.

[0006] The present invention provides a layout method for radiation hardening, which mainly uses the estimation of the node soft error rate to adjust the layout. The technical solution of the present invention is specifically introduced as follows.

[0007] A layout method considering the influence of TAP CELL on single-event effects, which utilizes the property that the radiation resistances of standard cells at different positions in the layout with Tap Cell as the substrate contact are different, and achieves the function of circuit hardening by adjusting the position arrangement of standard cells in the circuit layout or adding additional TapCell cells; specifically in implementation, it involves three processes: obtaining the sensitivity information of each unit in the circuit, optimizing and adjusting the layout, and trial routing of the layout, where:

[0008] Obtaining the sensitivity of standard cells: By analyzing the target circuit such as a gate-level netlist file, other circuit description files, etc., the probability or soft error rate and other circuit soft error characterization indicators that the single-event effects generated in each standard cell in the circuit finally become soft errors after propagation in the circuit are deduced, and used as the soft error sensitivity reference value in the optimization stage to evaluate the contribution of this unit to the overall soft error rate of the circuit;

[0009] Optimizing and adjusting the layout: According to the obtained standard cell sensitivity information, and utilizing the influence of Tap Cell on the unit sensitivity, adjust the circuit layout, and reduce the sensitivity of the overall circuit to soft errors by adjusting the positions of each standard cell;

[0010] Trial routing of the layout: Hand over the adjusted layout structure to the EDA tool for routing work, and try to give a circuit layout that meets the design requirements.

[0011] In the present invention, before starting the layout, relevant tools are used to analyze the soft error sensitivity indicators of each standard cell in the circuit structure described by standard cells, so as to provide reference indicators for the subsequent adjustment and optimization of the layout. The tools specifically used in implementation can include device-level simulation tools, netlist-level simulation tools, timing-based simulation tools, etc. The reference indicators obtained through analysis can be the probability that the unit finally becomes a soft error after a single-event effect occurs, or the soft error rate of the standard cell or other approximate indicators can be used as a substitute.

[0012] In the present invention, the property that the substrate contact method of Tap Cell affects the sensitivity of standard cells to single-event effects is utilized to complete the hardening of the circuit against single-event irradiation. The standard cells arranged near the Tap Cell in the layout are less sensitive to single-event effects. The farther away from the Tap Cell, the sensitivity of the standard cells to the influence of single-event effects shows a gradually increasing trend.

[0013] In the present invention, when optimizing the layout of the layout, the positions of the respective units in the layout are adjusted according to the different sensitivities of the standard cells in the layout to single-event effects. The standard cells that are more likely to cause final soft errors after being affected by single-event effects are placed near the Tap Cell, or additional Tap Cell units are added near it to reduce the overall soft error rate of the circuit. Since in the layout, the closer the standard cell is to the Tap Cell, the less sensitive it is to single-event effects. When laying out, the standard cells with a higher propagation probability are placed near the Tap Cell, and the other units that are not likely to cause final soft errors are adjusted to a slightly farther distance, which can reduce the total soft error rate of the circuit.

[0014] In the present invention, in order to be compatible with existing EDA tools, ensure high feasibility, and avoid situations such as being unable to be realized and congestion during the placement and routing stage, before adjusting the layout, relevant tools will be used first for component pre-placement, trying to ensure that the units in the same module or with electrical connections in the circuit are adjacent on the layout, reducing the probability of congestion, and obtaining the preliminary circuit layout file after pre-placement. Then, the tools involved in this patent are used to arrange and adjust the positions of specific units to ensure the overall realizability.

[0015] In the present invention, after adjusting the positions of specific standard cells, the units to be fixed and their related settings such as positions are passed to the EDA tool for subsequent routing and adjustment, and an attempt is made to give the final circuit layout.

[0016] Compared with the existing circuit anti-irradiation hardening and optimization methods, the advantages of the present invention are reflected in:

[0017] The standard cell layout hardening method provided by the present invention hardly brings additional area or power consumption overhead. Compared with hardening methods such as triple modular redundancy circuits and guard rings, this method does not require modifying the structure of the standard cells, nor does it require adding additional circuits or components to provide redundancy. It does not bring additional transistors resulting in additional area overhead, nor does it cause an increase in the power consumption of the circuit.

[0018] The standard cell layout reinforcement method provided by the present invention has a certain degree of flexibility. Since this method is a layout-level optimization method that does not modify the gate-level circuit structure but only modifies the circuit layout structure, the impact on the circuit structure and performance is limited. Therefore, this method can be used for a certain degree of adjustment and reinforcement in all integrated circuit designs that use TapCell as the substrate contact.

[0019] The standard cell layout reinforcement method provided by the present invention is compatible with the existing IC design process. It uses relevant commands provided by EDA tools to achieve layout adjustment, can be directly compatible with the existing EDA tool chain, and can be directly integrated into the IC design process without much additional modification. Brief Description of the Drawings

[0020] Figure 1 It is a schematic diagram of the layout structure using TAP CELL as the substrate contact.

[0021] Figure 2 It is a schematic diagram of the SET pulse width at different distances from the TapCell for the inverter unit under the 28nm process.

[0022] Figure 3 It is a process schematic diagram of the layout method of the present invention. Detailed Embodiments

[0023] In order to make the objectives, technical solutions and advantages of the present invention clearer, the present invention will be further described in detail below with reference to the drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention.

[0024] In integrated circuits with advanced processes, in order to increase the component density of the circuit, a dedicated physical unit TapCell replaces the previous power rails to achieve the function of substrate contact. As Figure 1 shown, it is a schematic diagram of the layout structure using TapCell as the substrate contact. When laying out the circuit, the TapCell units are first inserted into the layout according to certain rules, and then the EDA tool performs the layout and wiring of other functional units. Taking Figure 1 shown as an example, in the figure, the TapCells are arranged staggered at a certain interval in the layout, and the rest is used for the placement and wiring of standard cells.

[0025] In a circuit, standard cells implement different combinational logics and timings. For single-event transients in combinational logic, due to effects such as logic masking and electrical masking, the differences in the combinational logics implemented by standard cells and their positions in the netlist will all result in different probabilities (soft error rates) that this cell will be latched by the sequential circuit and form single-event transients after being irradiated. In the layout, the form of substrate contact will affect the radiation resistance characteristics of the device. In the layout using TAP CELL as the substrate contact method, the closer the standard cell is to the TAP CELL, the smaller its device sensitive cross-section, and generally, both the probability of generating single-event transients and the pulse width of the generated single-event transients tend to decrease. For single-event upsets in sequential logic, the closer it is to the TapCell unit, the weaker the sensitivity to single-event effects and the smaller the sensitive cross-section.

[0026] Figure 2 The figure shows the trend graph of the pulse width of single-event transients generated when the inverter unit in the standard cell library is irradiated by heavy ions at different distances from the TapCell in the layout under the process of using TapCell as the substrate contact. As shown in the figure, the NMOS pair in the inverter is not sensitive to the change in spacing, but the PMOS is highly sensitive to the change in spacing. When the inverter unit is farthest from the nearest TapCell unit, the pulse width of the generated single-event transient is larger.

[0027] According to the above properties, in the present invention, based on the circuit description at the netlist level, relevant analysis tools are used to evaluate the gate-level netlist circuit, and then the layout is adjusted.

[0028] Figure 3 The figure shows the specific steps of the optimization process. The optimization mainly starts from (1) the input netlist file.

[0029] When adjusting the layout, a parameter is needed as an index for layout optimization. This parameter should be the probability that the device can propagate to the last stage and finally cause a soft error after being affected by single-event effects, that is, the propagation probability. Parameters such as the soft error rate that can characterize the sensitivity of the circuit to single-event effects can also be used. This probability is obtained for each standard cell through the propagation probability analysis algorithm in (2) based on the analysis of the netlist file, and is used for the selection and analysis of subsequent cells.

[0030] When performing optimization, the circuit needs to be (4) pre-layout first to obtain (5) the pre-layout layout. At this time, the standard cells in the layout are initially arranged in the corresponding areas. On this basis, it is easier to select cells, and at the same time, it can make logically related cells as adjacent as possible, improve the feasibility of the subsequent stage, and avoid congestion in the wiring stage.

[0031] After obtaining the (3) propagation probability and the layout after (5) pre-layout, the layout is adjusted and optimized according to the external input parameters given in (6). The specific (7) layout optimization process (a)~(e) is shown in the figure on the right:

[0032] During optimization, starting from the existing (a) pre-layout layout, collect the propagation probabilities of the standard cells in the region, and select a part of the standard cells with higher propagation probabilities in step (b) according to the externally input metrics. The externally input metrics mainly control the degree of optimization. For example, different degrees of optimization are performed by controlling the number or proportion of selected and rearranged cells. After completing the selection of cells, then (c) sequentially find the TapCell units near each functional unit. Near the TapCell, rearrange the sensitive cells in a certain arrangement pattern (d). During rearrangement, place the selected sensitive cells near the TapCell to reduce the pulse width of SET generated by them. By selectively strengthening the most sensitive cells and arranging the insensitive cells in positions more sensitive to SET, the overall SET sensitivity of the circuit can be reduced. For some circuits, additional TapCell units can also be added near the sensitive cells by utilizing the idle positions for reinforcement. Finally, the rearranged layout (e) is obtained after adjustment.

[0033] After completing the rearrangement and layout optimization of the standard cells, the layout still needs to be further adjusted and routed. In step (8), the adjusted circuit is fed back to the EDA tool for subsequent work. After obtaining the comprehensive results, according to the various reports given by the tool, check whether the obtained circuit meets the various design constraints (9) under the current input metrics. If the constraints are not met, then lower the expected design metrics (10); if the design is satisfied and there is a large design optimization space, then the input design metrics can be appropriately increased (11); if the design constraints are just met, then the final circuit layout (12) is obtained.

[0034] In summary, the present invention proposes a layout method for considering the influence of TAP CELL on single-event effects, which strengthens the circuit by adjusting the positions of the standard cells in the layout. This method has a wide application range and can be used in all integrated circuit designs using TapCell as the substrate contact, without bringing additional area overhead, and can be compatible with the existing design process.

[0035] The above examples are only for illustrating the technical concept and features of the present invention, and the purpose is to more clearly elaborate the purpose, technical solution and advantages of the present invention, and are not used to limit the protection scope of the present invention. Any modifications, equivalent replacements and improvements made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. A layout method considering the influence of TAP CELL on single event effect, characterized in that It utilizes the characteristic that the single-event effect sensitivity of standard cells changes with the variation of their distance from the TAP CELL, and achieves the function of circuit hardening by adjusting the positions of standard cells in the circuit layout. Specifically, when implementing, it involves three processes: obtaining the sensitivity information of standard cells, optimizing and adjusting the layout, and trial routing of the layout. Among them: Obtaining the sensitivity of standard cells: By analyzing the gate-level netlist file and circuit description file in the target circuit, calculate the probability that the single-event effect generated in each standard cell in the circuit finally becomes a soft error after propagation in the circuit, that is, the propagation probability is used as the soft error sensitivity index in the optimization stage; Optimizing and adjusting the layout: According to the obtained sensitivity information of standard cells, utilize the influence of the TapCell substrate on the sensitivity of standard cells to adjust the circuit layout, and reduce the sensitivity of the overall circuit to soft errors by adjusting the positions of each standard cell; Trial routing of the layout: Hand over the adjusted layout structure to the EDA tool for routing work, and try to give a circuit layout that meets the design requirements.

2. The layout method considering the influence of TAP CELL on single event effect according to claim 1, characterized in that In the step of obtaining the sensitivity of standard cells, use relevant tools to analyze the soft error sensitivity index of each standard cell in the circuit structure described by standard cells. The relevant tools include device-level simulation tools, netlist-level simulation tools, and timing-based simulation tools.

3. The layout method considering the influence of TAP CELL on single event effect as described in claim 1, characterized in that, Before the step of optimizing and adjusting the layout, pre-layout the components to ensure that the same module or logically related units with electrical connections in the circuit are adjacent on the layout, reduce the probability of congestion, and obtain the preliminary circuit layout file after pre-layout.

4. The layout method considering the influence of TAP CELL on single event effect as claimed in claim 1, wherein In the step of optimizing and adjusting the layout, the influence of the Tap Cell substrate contact method on the single-event effect sensitivity of standard cells is as follows: The standard cells layout near the TapCell in the layout are less sensitive to the single-event effect. The farther away from the TapCell, the sensitivity of the standard cells affected by the single-event effect has a gradually increasing trend.

5. The layout method considering the influence of TAP CELL on single event effect as claimed in claim 1, wherein In the step of optimizing and adjusting the layout, place the standard cells with a higher probability of finally generating soft errors after being affected by the single-event effect near the TapCell, or add additional TapCell units near it to reduce the overall soft error rate of the circuit.

6. The layout method considering the influence of TAP CELL on single event effect as described in claim 1, wherein In the step of optimizing and adjusting the layout, place the standard cells with a higher probability of finally generating soft errors after being affected by the single-event effect near the TapCell, and adjust other units that are not likely to finally cause soft errors to a slightly longer distance to reduce the total soft error rate of the circuit.

7. The layout method considering the influence of TAP CELL on single event effect as described in claim 1, characterized in that In the step of trial routing of the layout, after adjusting the positions of specific standard cells, transfer the units to be fixed and their position-related settings to the EDA tool for subsequent routing and adjustment, and try to give the final circuit layout.

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