A system and method for detecting the mismatch of sense amplifiers

Abstract

This application relates to the field of semiconductors, particularly to the field of dynamic random access memories, and provides a method and a system for detecting the mismatch of sense amplifiers; the method allows the sense amplifiers to work in a worse environment by delaying the turn-on of NMOS or PMOS transistors in the sense amplifiers and shortening the row pre-charge time, so as to detect the sense amplifiers with mismatch caused by process manufacturing differences.

Description

Technical Field

[0001] This application relates to the field of semiconductors, and particularly to the field of DRAM (Dynamic Random Access Memory). Background Art

[0002] In DRAM, due to the very small size of the memory cells and their weak driving capabilities, the voltage difference between the bit line and the reference bit line is very small. If directly fed into the output buffer, it will be impossible to distinguish between logic 0 and 1. The sense amplifier is used to amplify the weak voltage difference between the bit line and the reference bit line, so that the logical data in the memory cell can be correctly recognized.

[0003] Currently, due to process manufacturing differences, the manufactured sense amplifiers have insufficient anti-interference capabilities, and the MOS transistors do not turn on at the correct time point when the sense amplifier is working, resulting in abnormal flipping of the sense amplifier and read failure. The traditional method for testing the sense amplifier is to perform write and read operations on the memory cell with the precharge time shortened, and judge whether the sense amplifier is mismatched by comparing the output results. Since the precharge time set by the existing traditional method is relatively loose and the working environment of the sense amplifier is not poor enough, some potential failures of the sense amplifier are not easily exposed, and the detection effect fails to meet the expectations. Summary of the Invention

[0004] Based on this, it is necessary to provide a detection method that can effectively detect a sense amplifier that may potentially fail due to process manufacturing differences.

[0005] To achieve the above object, an embodiment of the present application provides a method for detecting sense amplifier mismatch, including:

[0006] Obtain a test data set;

[0007] Convert the test data set into a first voltage difference between the bit line and the reference bit line, and input it into a sense amplifier with a delayed PMOS or NMOS transistor turn-on for precharging for a preset time, where the preset time is less than the standard precharge time;

[0008] Amplify the second voltage difference between the bit line and the reference bit line obtained after precharging through the sense amplifier to obtain a voltage difference to be measured;

[0009] Compare the voltage difference to be measured with a preset voltage difference to be measured. If the voltage difference to be measured is in the same direction as the preset voltage difference to be measured, it is determined that the sense amplifier is mismatched.

[0010] In some embodiments, before obtaining the test data set, it further includes:

[0011] Obtain a preset test data group, convert the preset test data group into a third voltage difference between the bit line and the reference bit line, input it into the sense amplifier with the MOS transistor normally turned on for precharging with a standard precharging time, and amplify the fourth voltage difference between the bit line and the reference bit line obtained after precharging through the sense amplifier to obtain the preset voltage difference to be measured.

[0012] In some embodiments, the data at the corresponding bit line position written by the preset test data group is reversed with respect to the data of the test data group.

[0013] In some embodiments, the converting the test data group into a first voltage difference between the bit line and the reference bit line includes:

[0014] Write the test data group into the storage unit to be tested, and convert the test data group into the first voltage difference between the bit line and the reference bit line through the storage unit to be tested.

[0015] In some embodiments, writing the test data group into the storage unit to be tested and converting the test data group into the first voltage difference between the bit line and the reference bit line through the storage unit to be tested includes:

[0016] After writing the test data group into the storage unit to be tested at preset intervals in sequence, read the first voltage difference between the bit line and the reference bit line from the storage unit to be tested according to the test data group.

[0017] In some embodiments, writing the test data group into the storage unit to be tested at preset intervals in sequence includes:

[0018] Extract first interval data from the test data group at a preset interval, and write the first interval data into all the storage units to be tested in sequence at the preset interval.

[0019] In some embodiments, reading the first voltage difference between the bit line and the reference bit line from the storage unit to be tested according to the test data group includes:

[0020] Perform a read operation along the X direction. Before each execution of the read operation, sequentially turn on all the word lines on the same bit line, turn on one word line and sequentially read the content of the storage units to be tested with a burst length on this word line, turn off this word line, and then repeat the above operations until at least one read operation of the storage units to be tested with a burst length is completed for all the word lines.

[0021] In some embodiments, the converting the preset test data group into a third voltage difference between the bit line and the reference bit line includes:

[0022] Write the preset test data group into the storage unit to be tested, and convert the preset test data group into the third voltage difference between the bit line and the reference bit line through the storage unit to be tested.

[0023] In some embodiments, writing the preset test data group into the storage unit to be tested and converting the preset test data group into the third voltage difference between the bit line and the reference bit line through the storage unit to be tested includes:

[0024] After writing the preset test data group into the storage unit to be tested in sequence according to the preset interval, read the third voltage difference between the bit line and the reference bit line from the storage unit to be tested according to the preset test data group.

[0025] In some embodiments, writing the preset test data group into the storage unit to be tested in sequence according to the preset interval includes:

[0026] Extract the second interval data from the preset test data group according to the preset interval, and write the second interval data into all the storage units to be tested in sequence according to the preset interval.

[0027] In some embodiments, input the first voltage difference into a sense amplifier with a delayed PMOS transistor or NMOS transistor turned on for precharging for a preset time, and amplify the second voltage difference obtained after precharging through the sense amplifier to obtain the voltage difference to be tested. Specifically, it includes:

[0028] Input the first voltage difference into the sense amplifier with a delayed PMOS transistor or NMOS transistor turned on for precharging for a preset time, and amplify the second voltage difference obtained after precharging through the sense amplification circuit of the sense amplifier to obtain the voltage difference to be tested. Among them, the first NMOS transistor and the first PMOS transistor, and the second NMOS transistor and the second PMOS transistor in the sense amplification circuit of the sense amplifier respectively form CMOS inverters.

[0029] The embodiment of the present application further provides a system for detecting the mismatch of a sense amplifier, including:

[0030] A data acquisition module, configured to acquire a test data group;

[0031] A data conversion module, configured to convert the test data group into a first voltage difference between a bit line and a reference bit line, input it into a sense amplifier with a delayed PMOS transistor or NMOS transistor turned on for precharging for a preset time, where the preset time is less than the standard precharging time, and configured to amplify the second voltage difference between the bit line and the reference bit line obtained after precharging through the sense amplifier to obtain the voltage difference to be tested;

[0032] A mismatch detection module is used to compare the measured voltage difference with a preset measured voltage difference. If the measured voltage difference and the preset measured voltage difference are in the same direction, it is determined that the sense amplifier is mismatched.

[0033] Further, the data acquisition module is also used to acquire a preset test data group before acquiring the test data group.

[0034] In the embodiment of the present application, the method for detecting the mismatch of the sense amplifier adopts the method of delaying the turn-on of the PMOS transistor or the NMOS transistor in the sense amplifier to accelerate the testing of the failed memory particles. The Y-Page Write method for performing the write operation is based on the turn-on of the delay transistor. After turning on one word line and sequentially writing the contents of all the corresponding memory cells on this word line, this word line is turned off, and then the next word line is turned on and written sequentially until all the memory cells are written. The X-Fast Read method is when performing the read operation, all the word lines on the same bit line are sequentially turned on. After turning on one word line and sequentially reading the contents of a burst length (8bit) unit on this word line, this word line is turned off, and then the next word line is turned on and read sequentially until the contents of all the memory cells are read. Based on the NMOS transistor or the PMOS transistor of the sense amplifier with delay, a data topology is written in the Y-Page manner, and then this data topology is read in the X-Fast manner on the premise of shortening the tRP time. Thus, the working environment of the sense amplifier that originally had the potential for failure becomes worse, and thus the failed particles of the sense amplifier can be effectively tested more purely. Description of the Drawings

[0035] Figure 1 It is the working circuit diagram of the sense amplifier of an optional embodiment of a method for detecting the mismatch of the sense amplifier provided by the present application;

[0036] Figure 2 It is the flow schematic diagram of an optional embodiment of a method for detecting the mismatch of the sense amplifier provided by the present application;

[0037] Figure 3 It is the test data topology diagram of an optional embodiment of a method for detecting the mismatch of the sense amplifier provided by the present application;

[0038] Figure 4 It is the complete waveform diagram of an optional embodiment of a method for detecting the mismatch of the sense amplifier provided by the present application;

[0039] Figure 5 It is the waveform diagram of the sense amplifier working normally in the amplification stage of an optional embodiment of a method for detecting the mismatch of the sense amplifier provided by the present application;

[0040] Figure 6Waveform diagram of shortening tRP in the sense amplifier and the PMOS transistor operating in the amplification stage when the turn-on is delayed in an alternative embodiment of the method for detecting the mismatch of the sense amplifier provided by this application;

[0041] Figure 7 Flowchart of an alternative embodiment of the method for detecting the mismatch of the sense amplifier provided by this application;

[0042] Figure 8 Structural schematic diagram of an alternative embodiment of the system for detecting the mismatch of the sense amplifier provided by this application.

[0043] Reference numerals:

[0044] 1. First NMOS transistor; 2. Second NMOS transistor; 3. First PMOS transistor; 4. Second PMOS transistor; 5. Sense amplification circuit; 6. Pre-charge circuit; 7. Storage unit; 81. Data acquisition module; 82. Data conversion module; 83. Mismatch detection module. Detailed implementation manners

[0045] Next, the technical solutions in the embodiments of this application will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of this application. Obviously, the described embodiments are only a part of the embodiments disclosed in this application, rather than all of the embodiments. Based on the embodiments disclosed in this application, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of this application.

[0046] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those of ordinary skill in the technical field to which this application belongs. The terms used in the specification of this application herein are only for the purpose of describing specific embodiments and are not intended to limit this application. Additionally, certain terms used throughout the specification and the following claims refer to specific elements. Those skilled in the art will understand that manufacturers may use different names to refer to elements. This document does not intend to distinguish between elements with different names but the same function. In the following description and embodiments, the terms "comprising" and "including" are used in an open-ended manner and should therefore be interpreted as "including, but not limited to...". Similarly, the term "connected" is intended to express an indirect or direct electrical connection. Accordingly, if a device is connected to another device, the connection can be completed through a direct electrical connection or through an indirect electrical connection via other devices and connectors.

[0047] It should be understood that although terms such as "first" and "second" may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, without departing from the scope of the disclosure of the present application, the first element may be referred to as the second element, and similarly, the second element may be referred to as the first element.

[0048] In one embodiment, as Figure 1 shown, it is a working circuit diagram of an induction amplifier of an alternative embodiment of a method for induction amplifier mismatch provided by the present application. The induction amplifier includes an induction amplification circuit 5, a precharge circuit 6, and a storage unit 7.

[0049] The induction amplification circuit 5 is composed of a first NMOS (Negative channel-Metal-Oxide-Semiconductor) transistor 1, a second NMOS transistor 2, a first PMOS (positive channel-Metal Oxide-Semiconductor) transistor 3, a second PMOS transistor 4, a PCS power supply, and an NCS power supply. The drain of the first PMOS transistor 3 and the gate of the second PMOS transistor 4 are both connected to the bit line BL. The gate of the first PMOS transistor 3 and the drain of the second PMOS transistor 4 are both connected to the reference bit line / BL. The sources of the first PMOS transistor 3 and the second PMOS transistor 4 are both connected to the PCS power supply. The gate of the first NMOS transistor 1 and the drain of the second NMOS transistor 2 are both connected to the bit line BL. The drain of the first NMOS transistor 1 and the gate of the second NMOS transistor 2 are both connected to the reference bit line / BL. The sources of the first NMOS transistor 1 and the second NMOS transistor 2 are both connected to the NCS power supply. Thus, it can be seen that the induction amplification circuit 5 is composed of cross-coupling of the first NMOS transistor 1, the second NMOS transistor 2, the first PMOS transistor 3, and the second PMOS transistor 4. Among them, the first NMOS transistor 1 and the first PMOS transistor 3, and the second NMOS transistor 2 and the second PMOS transistor 4 respectively form CMOS inverters.

[0050] In this embodiment, the PCS power supply is used to connect the source of the first PMOS transistor 3 to the power supply voltage VDD in response to the pull-up control signal. The NCS power supply is used to connect the source of the first NMOS transistor 1 to the ground in response to the pull-down control signal.

[0051] In this embodiment, after the voltage difference between the bit line BL and the reference bit line / BL reaches a certain value, the NCS power supply is turned on, the PCS power supply is turned on, and the first NMOS transistor 1, the second NMOS transistor 2, the first PMOS transistor 3, and the second PMOS transistor 4 form two cross-coupled inverter positive feedback circuits, which quickly amplify the voltage difference between the bit line BL and the reference bit line / BL, and complete the amplification of the voltage difference between the bit line BL and the reference bit line / BL by the sense amplifier circuit 5.

[0052] In this embodiment, the PCS power supply may include a pull-up PMOS transistor, and the NCS power supply may include a pull-down NMOS transistor. However, the PCS power supply may also be implemented using NMOS transistors, and the NCS power supply may also be implemented using PMOS transistors. Moreover, the PCS power supply or the NCS power supply may include more than one device, or may include multiple devices controlled to conduct or turn off by different control signals. This application does not limit this.

[0053] The precharge circuit 6 is composed of three NMOS transistors and is connected to the two output terminal lines of the sense amplifier circuit 5. The control terminal of the precharge circuit 6 receives the equalization control signal EQ. The precharge circuit 6 can precharge the bit line BL, the reference bit line / BL, and the two output terminal lines of the sense amplifier circuit 5 under the control of the equalization control signal EQ, and can charge the bit line BL and the reference bit line / BL to a specified precharge voltage VBLP. In the case of implementing the same or similar circuit functions, the precharge circuit 6 provided in this exemplary embodiment may also select any other replacement circuit, and this exemplary embodiment does not make special limitations on this.

[0054] In this embodiment, the YS is a column of bit line selection signals. For example, it may be composed of one NMOS transistor. The gate of the NMOS transistor is connected to the bit line selection signal YS, the source is connected to LIO, and YSW is the gate voltage difference for controlling the NMOS to turn on.

[0055] In this embodiment, the storage unit 7 includes a driving transistor and a storage capacitor. The gate of the driving transistor is connected to the word line WL, the drain is connected to the bit line BL, and the source is connected to the ground wire through the storage capacitor. When the charge on the storage capacitor is emptied (i.e., discharged), the stored data is "0". When the storage capacitor is charged, usually to the operating voltage VDD, the stored data is "1". The word line WL controls the conduction or turn-off of the driving transistor, and thus controls the charge and discharge of the storage capacitor, so as to realize the writing or reading of data.

[0056] In one embodiment, as Figure 2 shown, it is a schematic flowchart of an optional embodiment of a method for detecting the mismatch of a sense amplifier provided by this application. The method includes:

[0057] S11. Obtain a test data set;

[0058] S12. Convert the test data set into a first voltage difference between a bit line and a reference bit line, and input it into a sense amplifier with a delayed PMOS transistor or NMOS transistor turned on for precharging for a preset time, where the preset time is less than the standard precharging time;

[0059] S13. Amplify the second voltage difference between the bit line and the reference bit line obtained after precharging through the sense amplifier to obtain a voltage difference to be measured;

[0060] S14. Compare the voltage difference to be measured with a preset voltage difference to be measured. If the voltage difference to be measured and the preset voltage difference to be measured are in the same direction, it is determined that the sense amplifier is mismatched.

[0061] Specifically, when the sense amplifier with the delayed PMOS transistor or NMOS transistor turned on in step S12 corresponds to Figure 1 the sense amplifier circuit 5 therein, the delayed PMOS transistor simultaneously delays the first PMOS transistor 3 and the second PMOS transistor 4, and the delayed NMOS transistor simultaneously delays the first NMOS transistor 1 and the second NMOS transistor 2.

[0062] After obtaining the preset test data set, convert the preset test data set into a third voltage difference between the bit line BL and the reference bit line / BL, input it into a sense amplifier with a MOS transistor normally turned on for precharging for the standard precharging time, and amplify the fourth voltage difference obtained after precharging through the sense amplifier circuit 5 to obtain a preset voltage difference to be measured; the data at the corresponding bit line positions written by the preset test data set and the test data set are reversed, where the MOS transistors refer to the first NMOS transistor 1, the second NMOS transistor 2, the first PMOS transistor 3, and the second PMOS transistor 4 in the sense amplifier circuit 5 of the sense amplifier.

[0063] As Figure 3 shown, it is the data topology diagram of the test data set written in this embodiment. In the figure, W4C0_RS, W4C1_RS, W4C2_RS, and W4C3_RS can be used as the preset test data set, and W4C0B_RS, W4C1B_RS, W4C2B_RS, and W4C3B_RS can be used as the test data set. The two can be interchanged, but it is necessary to ensure that the data at the written bit line positions of the preset test data set and the test data set are reversed. Here, it is necessary to ensure that the data at the written bit line positions of the preset test data set and the test data set are reversed in order to create a worse test condition for testing the mismatch of the sense amplifier, so that it is easier to detect the failure of the sense amplifier when clamping the precharging time.

[0064] When the sense amplifier is operating, the "0" or "1" stored in the memory cell 7 is represented by the weak voltage difference between the bit line BL and the reference bit line / BL in the memory cell 7, which is the first voltage difference. Since the memory cell 7 is very small in size and has very weak driving ability, the voltage difference between the bit line BL and the reference bit line / BL is very small. If it is directly fed into the output buffer, the "0" or "1" in the memory cell 7 cannot be recognized. Therefore, it is necessary to input the voltage difference between the bit line BL and the reference bit line / BL in the memory cell 7 into the sense amplifier circuit 5 for amplification.

[0065] In this embodiment, as Figure 4 shown, it is a complete waveform diagram of an optional embodiment of a method for detecting the mismatch of a sense amplifier provided by the present application. Taking the previous operation as reading "1" and the current operation as reading "1" as an example, the change of the voltage difference between the bit line BL and the reference bit line / BL during a complete working process of the sense amplifier is described, and the complete working process of the sense amplifier is observed.

[0066] In this embodiment, the tRP (Precharge command period) is the precharge time, also known as the row precharge time. After the precharge command is issued, it takes a period of time to allow the RAS (Row Address Strobe) valid command to open a new working row. Among them, the tRCD is the delay from RAS to CAS (Column address strobe). After the data "1" is read, the working process of the sense amplifier also includes a recovery stage. After the read "1" operation is executed, the equalization control signal EQ is turned off, the word line signal is turned on, and the PCS power supply and the NCS power supply are turned on, so that the reference bit line / BL is restored to a high level and the bit line BL is restored to a low level.

[0067] In this embodiment, since the previous operation was to read "1", the bit line BL is at a high level and the reference bit line / BL is at a low level. The "Pre" indicates the start of the precharge operation. At this time, the word line signal is turned off, the sense amplifier circuit 5 is turned off (SA off, no amplification operation), the equalization control signal EQ is turned on, and both the bit line BL and the reference bit line / BL are charged to the precharge voltage VBLP.

[0068] After the precharge stage ends, the sense amplifier circuit 5 is turned on, the equalization control signal EQ is turned off, and the word line signal is turned on to control the charge operation of the storage capacitor in the corresponding memory cell 7. Charge sharing occurs between the charge in the storage capacitor and the charge on the bit line BL. Since the data with a value of "1" is stored in the corresponding storage capacitor during this process, the voltage of the bit line BL increases by about 15 - 20 millivolts during the charge sharing process.

[0069] During this process, both the NMOS transistor and the PMOS transistor in the sense amplifier circuit 5 are normally turned on. Among them, the first NMOS transistor 1 and the first PMOS transistor 3, as well as the second NMOS transistor 2 and the second PMOS transistor 4 respectively form CMOS inverters. Since this operation performs a read "1" this time, at this time, the CMOS inverter composed of the first NMOS transistor 1 and the first PMOS transistor 3 is mainly relied on to complete the amplification of the voltage difference, so as to complete the reading of the data "1" in the storage unit 1. If this operation performs a read "0" this time, at this time, the CMOS inverter composed of the second NMOS transistor 2 and the second PMOS transistor 4 is mainly relied on to complete the amplification of the voltage difference, so as to complete the reading of the data "0" in the storage unit 1.

[0070] Currently, due to the reasons of process manufacturing differences, the manufactured sense amplifier has insufficient anti-interference ability, and the NMOS transistor or the PMOS transistor in the sense amplifier circuit 5 does not turn on at the correct time point when the sense amplifier is working, resulting in abnormal inversion of the sense amplifier and reading failure. When testing the sense amplifier by the traditional method, the write-read operation is performed on the storage unit 7 under the condition of shortening the pre-charge time, and the output results are compared to judge whether the sense amplifier is mismatched. However, the pre-charge time set by the traditional method is relatively loose, and the working environment of the sense amplifier is not poor enough, so some potential failures of the sense amplifier are not easily exposed, and the detection effect cannot reach the expectation.

[0071] In one embodiment, as Figure 5 shown, it is a waveform diagram of the sense amplifier in a normal working amplification stage of an optional embodiment of a method for detecting sense amplifier mismatch provided by the present application. The last operation performed on the sense amplifier is a read "0" operation, and the current operation performs a read "1" operation.

[0072] In this embodiment, the data written into the storage unit 7 by the provided preset test data group is "0", and the data written into the storage unit 7 by the provided test data group is "1". Reading after writing the preset test data group into the storage unit 7 is a pre-operation for reading after writing the test data group into the storage unit 7.

[0073] When performing the last read "0" operation, the storage unit 7 inputs the sense amplifier with a weak voltage difference between the bit line BL and the reference bit line / BL. At this time, the weak voltage is the third voltage difference. Within the tRP time, the sense amplifier first enters the pre-charge stage, pre-charges the two bit lines (that is, the bit line BL and the reference bit line / BL) for a continuous standard pre-charge time, and pulls the voltages of the two bit lines to the pre-charge voltage VBLP. At this time, the voltage difference between the two bit lines is the fourth voltage difference.

[0074] The standard pre-charge time is based on the factory parameters specified for different products of different companies and will not be specifically defined here. After being amplified by the sense amplifier circuit 5 in which the first NMOS transistor 1, the first PMOS transistor 3, the second NMOS transistor 2, and the second PMOS transistor 4 are normally turned on, a preset voltage difference is obtained. As can be seen from the above embodiments, after the recovery stage of the sense amplifier ends, the reference bit line / BL returns to the high level, and the bit line BL returns to the low level.

[0075] Since the last read "0" operation was performed, before the sense amplifier is turned on, the reference bit line / BL is at the high level, and the bit line BL is at the low level, and the voltage difference between the two bit lines is the first voltage difference. During the tRP time, the sense amplifier first enters the pre-charge stage Pre, pre-charges the two bit lines for a continuous standard pre-charge time, and pulls the voltages of the two bit lines to the pre-charge voltage VBLP. At this time, the voltage difference between the two bit lines is the second voltage difference.

[0076] After the pre-charge operation is completed, the two pre-charged bit lines enter the sense amplifier circuit 5 as inputs and enter the first amplification stage. The word line signal is turned on, and the voltage of the bit line BL rises. At this time, the first PMOS transistor 3 and the first NMOS transistor 1 are turned on according to the preset time, and the second PMOS transistor 4 and the second NMOS transistor 2 are turned off.

[0077] Since the first PMOS transistor 3 and the first NMOS transistor 1 form a CMOS inverter, at this time the bit line BL is at a relatively high level. Due to the function of the inverter, the voltage at the output end of the inverter continuously decreases during the first amplification stage, that is, the voltage of the reference bit line / BL continuously decreases.

[0078] During the first amplification stage of the sense amplifier circuit 5, the voltage difference between the bit line BL and the reference bit line / BL will increase significantly, which helps to further amplify the voltage difference between the two, thereby improving the data reading speed and avoiding incorrect data amplification.

[0079] The sense amplifier circuit 5 then enters the second amplification stage. At this time, the first NMOS transistor 1, the second NMOS transistor 2, the first PMOS transistor 3, and the second PMOS transistor 4 are all turned on to form a cross-coupled amplification structure.

[0080] At this time, the voltage on the bit line BL is higher than the voltage on the reference bit line / BL. At this time, the first NMOS transistor 1 is turned on to discharge the voltage on the reference bit line / BL to the ground. In addition, the second PMOS transistor 4 is turned on to raise the voltage on the bit line BL to the Vary voltage.

[0081] Thus, through this cross-coupled amplification structure, the purpose of amplifying the small voltage read from the storage unit 7 by the bit line BL to 0 or 1 can be achieved. At this time, the voltage difference output between the two bit lines of the sense amplifier circuit 5 is the voltage difference to be measured.

[0082] Then, the bit line selection signal YS is turned on to read the voltage difference to be measured output by the sense amplifier 5, and the data "1" in the storage unit 7 is identified.

[0083] In the embodiment of the present application, by shortening the tRP time and delaying the turn-on of the NMOS transistor or PMOS transistor, the working environment of the sense amplifier is deteriorated, so as to detect that due to process differences, the first NMOS transistor 1, the first PMOS transistor 3, the second NMOS transistor 2, and the second PMOS transistor 4 in the sense amplifier circuit 5 of the sense amplifier cannot be turned on on time when the memory operates at high speed, and there is a potential failure possibility of the sense amplifier.

[0084] As Figure 6 shown, it is a waveform diagram of the sense amplifier working in the amplification stage when shortening tRP and delaying the turn-on of the PMOS transistor in an alternative embodiment of a method for detecting sense amplifier mismatch provided by the present application. The last operation performed on the sense amplifier was a read "0" operation, and the current operation is a read "1" operation.

[0085] Since the last read "0" operation was performed, the reference bit line / BL is at a high level and the bit line BL is at a low level before the sense amplifier is turned on. At this time, the voltage difference between the two bit lines is the first voltage difference. During the shortened tRP time, the sense amplifier first enters the pre-charge stage Pre to perform pre-charge on the two bit lines for a preset time. The preset time is less than the standard pre-charge time. Since the tRP time is shortened, the pre-charge circuit 6 fails to pull the voltages of the two bit lines to the pre-charge voltage VBLP. At this time, the voltage difference between the two bit lines is the second voltage difference. At this time, the reference bit line / BL is at a relatively high level relative to the bit line BL.

[0086] The voltage difference with the reference bit line / BL being at a relatively high level relative to the bit line BL is input into the sense amplifier circuit 5, and it enters the first amplification stage. The word line signal is turned on, the potential of the bit line BL rises, the first NMOS transistor 1 is turned on according to a preset time, the turn-on of the first PMOS transistor 3 is delayed, and the second PMOS transistor 4 and the second NMOS transistor 2 are turned off.

[0087] The working environment of the sense amplifier becomes worse, and it cannot raise the voltage of the bit line BL to a high level relative to the voltage of the reference bit line / BL within a predetermined time.

[0088] The sense amplifier then enters the second amplification stage. At this time, the first NMOS transistor 1, the second NMOS transistor 2, the first PMOS transistor 3, and the second PMOS transistor 4 are all turned on to form a cross-coupled amplification structure.

[0089] At this time, the voltage on the bit line BL is lower than the voltage on the reference bit line / BL. At this time, the second NMOS transistor 2 is turned on, and the voltage on the bit line BL is discharged to the ground through the second NMOS transistor 2. In addition, the first PMOS transistor 3 is turned on, and the voltage on the reference bit line / BL is raised to the Vary voltage. The sense amplifier undergoes an abnormal flip. At this time, the voltage difference output between the two bit lines of the sense amplifier circuit 5 is the voltage difference to be measured.

[0090] Then, the bit line selection signal YS is turned on, and the voltage output by the sense amplifier is read, and the data in the memory cell 7 is misidentified as "0".

[0091] It can be seen that by delaying the turn-on of the PMOS transistor, the working environment of the sense amplifier can be made worse while shortening tRP, so that there is a potential possibility that the sense amplifier that cannot turn on the first NMOS transistor 1, the first PMOS transistor 3, the second NMOS transistor 2, and the second PMOS transistor 4 within the specified time undergoes an abnormal flip, thereby realizing the detection of the mismatched sense amplifier.

[0092] In this embodiment, taking the delay in turning on the PMOS transistor as an example, it can also be changed to delaying the turn-on of the NMOS transistor, or other ways that can similarly make the working environment of the sense amplifier worse. This exemplary embodiment does not make special limitations on this.

[0093] In one embodiment, as Figure 7 shown, it is a flowchart of an optional embodiment of a method for detecting sense amplifier mismatch provided by the present application. Figure 7 The thick arrows in the boxes indicate writing to this word line, and the non-bold arrows indicate not writing to this word line. The specific process is as follows:

[0094] Step 1, the first PMOS transistor 3 and the second PMOS transistor 4 are delayed in turning on.

[0095] Step 2, the preset test data group W4C0_RS is written to the word lines numbered 0 / 4 / 8 / C... in the Y-Page mode, and the word lines 0 / 4 / 8 / C... are read in the X-Fast mode on the premise of shortening tRP.

[0096] Step 3, the preset test data group W4C1_RS is written to the word lines numbered 1 / 5 / 9 / D... in the Y-Page mode, and the word lines 1 / 5 / 9 / D... are read in the X-Fast mode on the premise of shortening tRP.

[0097] Step 4, the preset test data group W4C2_RS is written to the word lines numbered 2 / 6 / A / E... in the Y-Page mode, and the word lines 2 / 6 / A / E... are read in the X-Fast mode on the premise of shortening tRP.

[0098] Step 5: Write the preset test data set W4C3_RS to the word line numbers 3 / 7 / B / F... in the Y-Page mode. On the premise of shortening tRP, read the word lines 3 / 7 / B / F... in the X-Fast mode.

[0099] Step 6: Write the test data set W4C0B_RS to the word line numbers 0 / 4 / 8 / C... in the Y-Page mode. On the premise of shortening tRP, read the word lines 0 / 4 / 8 / C... in the X-Fast mode.

[0100] Step 7: Write the test data set W4C1B_RS to the word line numbers 1 / 5 / 9 / D... in the Y-Page mode. On the premise of shortening tRP, read the word lines 1 / 5 / 9 / D... in the X-Fast mode.

[0101] Step 8: Write the test data set W4C2B_RS to the word line numbers 2 / 6 / A / E... in the Y-Page mode. On the premise of shortening tRP, read the word lines 2 / 6 / A / E... in the X-Fast mode.

[0102] Step 9: Write the test data set W4C3B_RS to the word line numbers 3 / 7 / B / F... in the Y-Page mode. On the premise of shortening tRP, read the word lines 3 / 7 / B / F... in the X-Fast mode.

[0103] Step 10: Exit the test mode, and the first PMOS transistor 3 and the second PMOS transistor 4 return to the normal state.

[0104] Step 11: Switch to the first NMOS transistor 1 and the second NMOS transistor 2 to turn on with a delay, and repeat Steps 2 to 9.

[0105] In this embodiment, the logical arrangement of the storage units 7 is such that the position of a certain storage unit 7 is determined by a given row address and column address. However, under the current storage technology, column operations are performed through the burst length (burst Length, BL), where the burst length is determined by the JEDEC standard or can be freely set, that is, reading and writing of multiple bits (such as 8 or 16 bits) of the column address at a time, and writing or reading data of 0 and 1 in each burst length (for example, if the located address is row 0 and the burst length is 8 bits, then the first 8 values of the storage unit 7 are written simultaneously starting from the position of column 0 in row 0, and the 9 - 16th bits of the storage unit 7 are written in the second burst length, and so on continuously. When all the storage positions in a row are written, the test software relocates the address of the next row and continues the operation of the previous row until all data is written to the entire disk. Reading data is a similar operation), that is, in this embodiment, test data is rewritten for each storage position in a row. For example, if the test data is 1010101010101010, then 10101010 is written in the first row and 10101010 is also written in the second row.

[0106] In addition, the writing at preset intervals is explained as follows: for example, if the preset interval is 1, then when the test data is written to the addresses of column 0, column 2, column 4, etc. in a certain row of the storage unit 7, the test data is not written to the addresses of column 1, column 3, etc. in a certain row of the storage unit 7. The interval between column 0 and column 2 in a certain row of the storage unit 7 is the preset interval, that is, 1; if the preset interval is 2, then when the test data is written to the addresses of column 0, column 3, column 6, etc. in a certain row of the storage unit 7, the test data is not written to the addresses of column 1, column 2, column 4, column 5, etc. in a certain row of the storage unit 7. The interval between column 0 and column 3 in a certain row of the storage unit 7 is the preset interval, that is, 2. Due to storage failures between multiple storage units 7, generally, the failures occur between adjacent storage units 7. Therefore, interval writing, reading, and comparison can identify storage failures between multiple storage units 7. Figure 7 The thick - arrow in the box indicates writing to this word line, and the non - thick arrow indicates not writing to this word line. According to Figure 7 it can be known that when the test data is written to the addresses of column 0, column 4, column 8, etc. in a certain row of the storage unit 7, the test data is not written to the addresses of column 1, column 2, column 3, column 5, column 6, column 7, etc. in a certain row of the storage unit 7. The interval between column 0 and column 4 in a certain row of the storage unit 7 is the preset interval, that is, 3.

[0107] Such as Figure 3As shown, W4CX_RS and W4CXB_RS represent a data group. The two data groups are a test data group and a preset test data group for each other. When W4CX_RS is the preset test data group, W4CXB_RS is the test data group. Similarly, when W4CX_RS is the test data group, W4CXB_RS is the preset test data group. The data of the test data group and the preset test data group are reversed at the same bit line position.

[0108] In this embodiment, the test system first obtains the preset test data group, and then extracts the first interval data from the preset test data group at a preset interval. For example, W4C0_RS is used as the preset test data group, and the data 1010 written at the write bit line BL 0 is extracted. The data 1, 0, 1, 0 are written into the storage units 7 at the positions of row 0 column 0, row 1 column 0, row 2 column 0, row 3 column 0 in sequence from top to bottom according to the word lines WL0, WL1, WL2, WL3, and the first interval data is written into all the storage units 7 to be tested in sequence at the preset interval of 3.

[0109] After the test system reads the data in the storage unit 7 to be tested, a preset voltage difference to be measured is obtained, and the pre-amplification processing of the sense amplifier is completed. The operation mode of writing and reading data in this operation is not specifically specified.

[0110] Then, in the TM (TEST MODE test mode) of the memory, the first PMOS transistor 3 and the second PMOS transistor 4 are set to be delayed to turn on. The test system obtains the test data group, and extracts the second interval data from the test data group at a preset interval. For example, W4C0B_RS is used as the test data group, and the data 0101 written at the write bit line BL 0 is extracted. The data 0, 1, 0, 1... are written into the storage units at the positions of row 0 column 0, row 1 column 0, row 2 column 0, row 3 column 0... in sequence from top to bottom according to the word lines WL0, WL1, WL2, WL3... using the Y-Page Write method, and the first interval data is written into all the storage units 7 to be tested in sequence using the Y-Page method at the preset interval of 3.

[0111] The time threshold for setting the first PMOS transistor 3 and the second PMOS transistor 4 to be delayed to turn on and the shortest threshold for shortening tRP in the TEST MODE are determined according to products of different companies and different models, and are not specifically specified here.

[0112] The Y-Page Write method is a Y-direction write operation method. Before each write operation, one word line WL is turned on. After sequentially writing all the corresponding storage units 7 on this word line WL, this word line WL is turned off. Then the next word line WL is turned on and all the storage units 7 are sequentially written.

[0113] Then, under the condition of shortening tRP, the data in the storage unit 7 to be measured is read by the X-Fast Read method. Since the tRP time is shortened, only by using the X-Fast Read method can the shortened tRP time be captured to complete the reading.

[0114] The X-Fast Read method is a read operation method in the X direction. Before each execution of the read operation, all word lines WL on the same bit line BL are sequentially enabled. After enabling one word line WL and sequentially reading the content of a burst length (8 bit) unit on this word line WL, this word line WL is turned off, and then the next word line WL is enabled and the content of a burst length unit on this word line WL is sequentially read.

[0115] After the test system reads the data in all storage units 7, the preset voltage difference to be measured and the voltage difference to be measured are obtained, and then the first PMOS transistor 3 and the second PMOS transistor 4 are restored to the normal working state. The preset voltage difference to be measured and the voltage difference to be measured are output as data in the form of "0" or "1". The test system browses the outputs of all voltage differences to be measured and preset voltage differences to be measured at the same storage unit 7 position. If they are in the same direction, it is determined that the corresponding sense amplifier is mismatched.

[0116] The above process is to perform one round of sense amplifier mismatch detection. After one round of mismatch detection of the sense amplifiers corresponding to all storage units 7 to be measured, the delay of the first PMOS transistor 3 and the second PMOS transistor opening is switched to the delay of the first NMOS transistor 1 and the second NMOS transistor opening, and then another round of testing is performed until the test requirements are met.

[0117] The present application also provides a system for detecting sense amplifier mismatch, as Figure 8 shown, which is a schematic structural diagram of an optional embodiment of a system for detecting sense amplifier mismatch provided by the present application, including:

[0118] A data acquisition module 81, configured to acquire a test data set;

[0119] A data conversion module 82, configured to convert the test data set into a first voltage difference between a bit line and a reference bit line, input it into a sense amplifier with delayed PMOS or NMOS transistor opening for precharging for a preset time, where the preset time is less than the standard precharging time, and configured to amplify the second voltage difference between the bit line and the reference bit line obtained after precharging through the sense amplifier to obtain a voltage difference to be measured;

[0120] A mismatch detection module 83, configured to compare the voltage difference to be measured with a preset voltage difference to be measured. If the voltage difference to be measured and the preset voltage difference to be measured are in the same direction, it is determined that the sense amplifier is mismatched.

[0121] The data acquisition module 81 is further configured to acquire a preset test data group before acquiring the test data group.

[0122] The data conversion module 82 is further configured to convert the preset test data group into a third voltage difference between the bit line and the reference bit line, input it into a sense amplifier with the MOS transistor normally turned on for precharging with a standard precharging time, amplify the fourth voltage difference between the bit line and the reference bit line obtained after precharging through the sense amplifier to obtain a preset voltage difference to be measured, wherein the data at the corresponding bit line positions written in the preset test data group is opposite to that of the test data group.

[0123] The functions and implementation manners of the modules in the above embodiments of the present application are the same as those of the embodiments of the above method for detecting the mismatch of the sense amplifier. For specific analysis, reference can be made to the embodiments of the above method for detecting the mismatch of the sense amplifier. To avoid repetition, it will not be elaborated here.

[0124] The above is the preferred implementation manner of the present application. It should be noted that for those of ordinary skill in the art, without departing from the principle of the present application, several improvements and refinements can be made, and these improvements and refinements are also regarded as the protection scope of the present application.

Claims

1. A method for detecting the mismatch of a sense amplifier, characterized in that Including: Obtain a test data set; Convert the test data set into a first voltage difference between a bit line and a reference bit line, and input it into a sense amplifier with a delay PMOS transistor or NMOS transistor turned on for precharging for a preset time, where the preset time is less than the standard precharging time; Amplify the second voltage difference between the bit line and the reference bit line obtained after precharging through the sense amplifier to obtain a voltage difference to be measured; Compare the voltage difference to be measured with a preset voltage difference to be measured. If the voltage difference to be measured and the preset voltage difference to be measured are in the same direction, it is determined that the sense amplifier is mismatched.

2. The method for detecting the mismatch of an induction amplifier according to claim 1, characterized in that, Before obtaining the test data set, it further includes: Obtain a preset test data set, convert the preset test data set into a third voltage difference between the bit line and the reference bit line, input it into the sense amplifier with the MOS transistor normally turned on for precharging for the standard precharging time, and amplify the fourth voltage difference between the bit line and the reference bit line obtained after precharging through the sense amplifier to obtain the preset voltage difference to be measured.

3. The method for detecting the mismatch of a sense amplifier according to claim 2, wherein: The data at the corresponding bit line position written by the preset test data set and the test data set is reversed.

4. The method for detecting mismatch of a sense amplifier according to claim 1, characterized in that The conversion of the test data set into a first voltage difference between a bit line and a reference bit line includes: Write the test data set into a storage unit to be tested, and convert the test data set into the first voltage difference between the bit line and the reference bit line through the storage unit to be tested.

5. The method for detecting the mismatch of an induction amplifier according to claim 4, characterized in that, Writing the test data set into the storage unit to be tested and converting the test data set into the first voltage difference between the bit line and the reference bit line through the storage unit to be tested includes: After writing the test data set into the storage unit to be tested at preset intervals in sequence, read the first voltage difference between the bit line and the reference bit line from the storage unit to be tested according to the test data set.

6. The method for detecting the mismatch of an inductive amplifier according to claim 5, wherein Writing the test data set into the storage unit to be tested at preset intervals in sequence includes: Extract first interval data from the test data set at a preset interval, and write the first interval data into all the storage units to be tested in sequence at the preset interval.

7. The method for detecting mismatch of a sense amplifier according to claim 5, wherein Reading the first voltage difference between the bit line and the reference bit line from the storage unit to be tested according to the test data set includes: Perform a read operation along the X direction. Before each execution of the read operation, sequentially turn on all the word lines on the same bit line, turn on one word line and sequentially read the content of the storage units to be tested with a burst length on this word line, turn off this word line, and then repeat the above operations until at least one read operation of the storage units to be tested with a burst length is completed for all the word lines.

8. A method for detecting the mismatch of a sense amplifier as claimed in claim 2, wherein The conversion of the preset test data set into a third voltage difference between the bit line and the reference bit line includes: Write the preset test data set into a storage unit to be tested, and convert the preset test data set into the third voltage difference between the bit line and the reference bit line through the storage unit to be tested.

9. A method for detecting the mismatch of a sense amplifier according to claim 8, characterized in that, Writing the preset test data group into the storage unit under test, and converting the preset test data group into the third voltage difference between the bit line and the reference bit line through the storage unit under test includes: After writing the preset test data group into the storage unit under test at preset intervals in sequence, reading the third voltage difference between the bit line and the reference bit line from the storage unit under test according to the preset test data group.

10. The method for detecting mismatch of a sense amplifier according to claim 9, wherein Writing the preset test data group into the storage unit under test at preset intervals in sequence includes: Extracting second interval data from the preset test data group at the preset interval, and writing the second interval data into all the storage units under test in sequence at the preset interval.

11. The method for detecting the mismatch of an inductive amplifier according to claim 1, wherein Inputting the first voltage difference into an induction amplifier with a delayed PMOS transistor or NMOS transistor turned on for precharging for a preset time, and amplifying the second voltage difference obtained after precharging through the induction amplifier to obtain the voltage difference to be measured, specifically including: Inputting the first voltage difference into the induction amplifier with a delayed PMOS transistor or NMOS transistor turned on for precharging for a preset time, and amplifying the second voltage difference obtained after precharging through the induction amplification circuit of the induction amplifier to obtain the voltage difference to be measured, where the first NMOS transistor and the first PMOS transistor, and the second NMOS transistor and the second PMOS transistor in the induction amplification circuit of the induction amplifier respectively form CMOS inverters.

12. A system for detecting the mismatch of an induction amplifier, characterized in that, Including: A data acquisition module, configured to acquire a test data group; A data conversion module, configured to convert the test data group into a first voltage difference between a bit line and a reference bit line, input the first voltage difference into an induction amplifier with a delayed PMOS transistor or NMOS transistor turned on for precharging for a preset time, where the preset time is less than the standard precharging time, and configured to amplify the second voltage difference between the bit line and the reference bit line obtained after precharging through the induction amplifier to obtain the voltage difference to be measured; A mismatch detection module, configured to compare the voltage difference to be measured with a preset voltage difference to be measured, and if the voltage difference to be measured and the preset voltage difference to be measured are in the same direction, determine that the induction amplifier is mismatched.

13. The system for detecting the mismatch of the sense amplifier according to claim 12, wherein The data acquisition module is further configured to acquire a preset test data group before acquiring the test data group.

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