Insulated gate high electron mobility transistor and method of manufacturing the same

Abstract

The application relates to an insulated gate high electron mobility transistor and a preparation method thereof, and the preparation method comprises the following steps: 1, epitaxial material growth; 2, vertical structure realization; 3, drain electrode manufacturing; 4, source electrode manufacturing; 5, ohmic metal annealing; 6, dielectric layer deposition; 7, gate electrode manufacturing; and 8, manufacturing of an interconnection lead. The application can solve the problems that the threshold voltage of a conventional GaN-based high electron mobility transistor device is less than 0 and the withstand voltage capacity is poor.

Description

Technical Field

[0001] This invention belongs to the field of microelectronic device technology, and relates to a high electron mobility transistor and its fabrication method, particularly an insulated gate high electron mobility transistor and its fabrication method. Background Technology

[0002] As a representative of third-generation wide-bandgap semiconductors, GaN boasts significant advantages such as a large bandgap, high critical breakdown voltage, and high thermal conductivity, making it suitable for various high-temperature, high-pressure, and high-power applications. Furthermore, the large conduction band shift in GaN / AlGaN heterojunctions, due to spontaneous polarization and piezoelectric polarization effects, generates a highly concentrated two-dimensional electron gas (2DEG) at the interface. The separation of charge carriers and scattering centers also enhances electron mobility, resulting in a substantial increase in device saturation current. On-resistance and switching speed are also far superior to traditional power devices. Simultaneously, GaN's high thermal conductivity ensures excellent heat dissipation, improving reliability under high-temperature and high-power environments. With its high breakdown voltage, low on-resistance, high switching speed, and low switching losses, GaN-based HEMTs (High Electron Mobility Transistors) can withstand higher operating voltages, significantly improving efficiency in power conversion processes and reducing energy loss. They have broad application prospects in power management, wind power generation, solar cells, electric vehicles, and other power electronics fields.

[0003] Furthermore, due to the asymmetric lattice structure of GaN, different crystal planes have different polarization properties, resulting in mutually perpendicular polar and non-polar planes. By rationally planning the material structure, the device can generate 2DEG in the material structure direction of the polar plane, while not generating 2DEG in the material structure direction of the non-polar plane perpendicular to it.

[0004] However, GaN-based HENT devices currently have the following drawbacks: 1. Due to the material's inherent polarization characteristics, a high concentration of two-dimensional electron gas exists at the heterojunction interface, causing the device to be in a conducting state under zero gate bias, i.e., a depletion-mode device (normally on). This makes circuit design much more complex than enhancement-mode (normally off) devices, increasing the difficulty and cost of circuit design. 2. From a safety perspective, especially for devices applied in high-voltage fields, the device must be in a turned-off state when no voltage is applied to avoid burning out the entire circuit due to accidental conduction, or even causing unpredictable dangers. 3. For devices used in high-voltage environments, the maximum voltage they can withstand should be 2 to 3 times higher than their operating voltage to ensure stable and efficient operation in complex application environments.

[0005] In view of the above-mentioned technical defects of the prior art, there is a need to provide a novel high electron mobility transistor and its fabrication method to overcome the above defects. Summary of the Invention

[0006] To overcome the shortcomings of existing technologies, this invention proposes an insulated gate high electron mobility transistor and its fabrication method to solve the problems of threshold voltage less than 0 and poor voltage withstand capability of conventional GaN-based high electron mobility transistor devices.

[0007] To achieve the above objectives, the present invention provides the following technical solution:

[0008] A method for fabricating an insulated-gate high electron mobility transistor, characterized by comprising the following steps:

[0009] 1) In self-supporting N + - A C-doped GaN layer with a thickness of 3-30 μm is grown on a GaN substrate;

[0010] 2) An N-type substrate with a thickness of 1-3 μm is grown on the C-doped GaN layer. _ -GaN transition layer;

[0011] 3) Part of the N is removed by dry plasma etching. _ - A GaN transition layer and the C-doped GaN layer below it are arranged to form two steps and a groove between the two steps;

[0012] 4) The two steps are etched by dry plasma etching to remove part of the N in the steps. _ -GaN transition layer and a portion of the C-doped GaN layer below it to form a stepped structure;

[0013] 5) Grow a GaN channel layer with a thickness of 200nm-500nm throughout the entire structure;

[0014] 6) Grow an AlGaN barrier layer with an Al composition of 15-35% and a thickness of 10-30 nm on the GaN channel layer to form an AlGaN / GaN structure;

[0015] 7) In the self-supporting N + - Drain electrode deposited on the back side of the GaN substrate;

[0016] 8) Remove the topmost AlGaN / GaN structure to expose the N. _ -GaN transition layer, thereby forming source window;

[0017] 9) The exposed N is etched using dry plasma etching. _ - The top of the GaN transition layer is etched to form a source trench;

[0018] 10) Deposit a source electrode on the source window and source recess;

[0019] 11) Deposit a medium layer throughout the entire structure;

[0020] 12) Deposit a gate electrode on the dielectric layer located above the stepped platform;

[0021] 13) Make interconnecting leads.

[0022] Preferably, the GaN channel layer has a polar surface in the vertical direction and a non-polar surface in the horizontal direction, and the side surface of the AlGaN barrier layer is a polar c-plane, so that the AlGaN / GaN structure has a two-dimensional electron gas in the vertical direction.

[0023] Preferably, the length of the step is 10μm-15μm, and the distance between two steps is 20μm-30μm.

[0024] Preferably, the length of the stepped steps is 1μm-3μm or 5-8μm.

[0025] Preferably, the drain electrode and the source electrode are formed by stacking a Ti layer, an Al layer, a Ni layer and an Au layer, wherein the thickness of the Ti layer is 20 nm, the thickness of the Al layer is 160 nm, the thickness of the Ni layer is 55 nm, and the thickness of the Au layer is 45 nm.

[0026] Preferably, the depth of the source groove is 0.5 to 0.8 μm.

[0027] Preferably, after completing step 9), metal annealing is performed first, and then step 10) is performed, wherein the metal annealing is a rapid thermal annealing in an N2 atmosphere at 870°C for 30 seconds.

[0028] Preferably, the gate electrode is formed by stacking a Ni layer and an Au layer, wherein the thickness of the Ni layer is 45 nm and the thickness of the Au layer is 200 nm.

[0029] Preferably, the dielectric layer is an HfO2 dielectric layer or a Si3N4 dielectric layer, and its thickness is 30 nm.

[0030] In addition, the present invention provides an insulated gate high electron mobility transistor, characterized in that it is prepared by the above-described preparation method.

[0031] Compared with the prior art, the insulated-gate high electron mobility transistor and its fabrication method of the present invention have one or more of the following beneficial technical effects:

[0032] 1. This invention enables the device current to flow vertically by realizing a vertical structure, which allows the high breakdown characteristics of GaN material to be more fully realized. At the same time, it increases the active area of ​​the device per unit area, thereby achieving a higher current density. Compared with lateral HEMT, the current density per unit area is higher, making it suitable for commercialization.

[0033] 2. This invention utilizes the difference between the polar and non-polar surfaces of GaN material itself, which are perpendicular to each other. The side surface is a polar C-plane, which generates a two-dimensional electron gas (2DEG) in the vertical direction through polarization effect. The upper surface is a non-polar surface, so no 2DEG is generated. In this way, the gate fabricated in the horizontal direction will not directly contact the 2DEG. To open the channel, a corrected gate voltage needs to be applied to achieve enhancement mode operation of the device.

[0034] 3. This invention grows a dielectric layer on the AlGaN barrier layer to form a MIS (metal-insulator-semiconductor) structure, replacing the conventional Schottky gate, effectively reducing gate leakage current and improving gate voltage swing, while also improving N... - - The GaN transition layer is etched to form a grooved gate electrode, which increases the contact area between the source electrode and the two-dimensional electron gas, reduces the source series resistance, and improves the device power performance.

[0035] 4. Compared with the vertical GaN-based MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor), the structure of the present invention realizes the AlGaN / GaN heterostructure through regeneration technology, and generates 2DEG through polarization, so that the device can conduct electricity using 2DEG. Compared with bulk GaN material, 2DEG has higher electron mobility and can obtain higher output current density, while the high-frequency characteristics of the device will not degrade. Attached Figure Description

[0036] Figure 1 It is self-supporting N + -Schematic diagram of the GaN substrate.

[0037] Figure 2 Is Figure 1 The diagram shows the structure after a C-doped GaN layer was grown on top of the existing structure.

[0038] Figure 3 Is Figure 2 N was grown on the basis _ -Schematic diagram of the structure after the GaN transition layer.

[0039] Figure 4 Is Figure 3 A schematic diagram of the structure after steps are formed on the basis above.

[0040] Figure 5 Is Figure 4The diagram shows the structure after the steps are formed.

[0041] Figure 6 Is Figure 5 This is a schematic diagram of the structure after GaN channel layers have been grown on the basis.

[0042] Figure 7 Is Figure 6 This is a schematic diagram of the structure after an AlGaN barrier layer was grown on top of the existing structure.

[0043] Figure 8 Is Figure 7 This is a schematic diagram of the structure after the drain electrode has been deposited.

[0044] Figure 9 Is Figure 8 This is a schematic diagram of the structure after the source window is formed based on the above.

[0045] Figure 10 Is Figure 9 This is a schematic diagram of the structure after the source trench is formed based on the above.

[0046] Figure 11 Is Figure 10 This is a schematic diagram of the structure after the source electrode has been deposited.

[0047] Figure 12 Is Figure 11 This is a schematic diagram of the structure after a dielectric layer has been deposited on top of the above.

[0048] Figure 13 Is Figure 12 This is a schematic diagram of the structure after the gate electrode has been deposited. Detailed Implementation

[0049] The present invention will be further described below with reference to the accompanying drawings and embodiments. The content of the embodiments is not intended to limit the scope of protection of the present invention.

[0050] For power devices, achieving enhancement mode and increasing operating current are crucial. From a safety and energy consumption perspective, it is essential to avoid additional leakage current during power outages. Therefore, fabricating high-performance enhancement-mode devices is a research direction of great value. Combining third-generation semiconductor GaN with enhancement mode research is a significant application-oriented study. Enhancement-mode (E-mode) devices (also known as normally-off devices) are off in a zero-bias state, unlike depletion-mode devices which require an external negative voltage to turn off, thus greatly reducing additional power losses in the circuit. Enhancement-mode AlGaN / GaN HEMTs are used in low-voltage, high-frequency applications. For power switching applications, normally-off characteristics are essential for ensuring safe operation and simple gate drive configuration. Furthermore, the use of enhancement-mode devices can simplify circuit design. Therefore, to achieve GaN power devices with good characteristics, the device must simultaneously be enhancement-mode and able to withstand high voltages. This means realizing an enhancement-mode GaN HEMT device with high breakdown voltage. Furthermore, the vertical structure can more fully utilize the high breakdown characteristics of GaN material, which is more conducive to realizing GaN-based devices with high breakdown voltage. Simultaneously, by combining a heterostructure to generate 2DEG, a vertical structure AlGaN / GaN high electron mobility transistor with high breakdown characteristics can be obtained. Further separating the polar and non-polar surfaces, so that the area below the device gate contacts the non-polar surface that does not generate 2DEG, achieves enhancement-mode operation. Adding a MIS gate structure that can improve gate voltage swing and reduce gate leakage current, a vertical structure AlGaN / GaN enhancement-mode insulated-gate high electron mobility transistor with high breakdown characteristics can be realized.

[0051] This invention provides an insulated gate high electron mobility transistor and its fabrication method. In order to solve the problem that conventional HEMT devices are depletion-type devices with low breakdown voltage, a device structure combining a vertical structure and an AlGaN / GaN heterostructure is introduced to obtain a device that can operate in enhancement mode while having a high breakdown voltage. In addition, the MIS gate structure can improve the gate voltage swing and reduce the gate leakage current, making it a GaN-based power electronic device that can be widely used in switching power supplies, electric vehicles, power electronics and other fields.

[0052] The method for fabricating a high electron mobility transistor with an insulated gate according to the present invention includes the following steps:

[0053] I. For example Figure 1 As shown, self-supporting N is provided. + -GaN substrate 1.

[0054] The self-supporting N + -GaN substrate 1 serves as the substrate layer for high electron mobility transistors. Preferably, the self-supporting N...+ - The thickness of GaN substrate 1 is 1-2 mm.

[0055] II. Figure 2 As shown, in the self-supporting N + A C-doped GaN layer 2 with a thickness of 3-30 μm is grown on a GaN substrate 1. The C doping concentration is 5-8 × 10⁻⁶. 17 / cm 3 .

[0056] Since the GaN layer is a C-doped GaN layer, the introduced C doping will introduce electron trap levels or acceptor levels in the GaN bandgap, causing conduction band electrons to be trapped by electron traps or compensated by acceptors, thereby making the C-doped GaN layer 2 a high-resistivity GaN layer, which in turn enables it to suppress substrate leakage current of the device and improve the device breakdown voltage.

[0057] III. Figure 3 As shown, an N-type layer with a thickness of 1-3 μm is grown on the C-doped GaN layer 2. _ -GaN transition layer 3.

[0058] IV. Figure 4 As shown, some of the N is removed by dry plasma etching. _ - A GaN transition layer 3 and the C-doped GaN layer 2 located below it form two steps a and a groove b between the two steps a.

[0059] Preferably, the length of step a is 10μm-15μm, and the distance between two steps a, that is, the length of the groove b, is 20μm-30μm.

[0060] V. For example Figure 5 As shown, the two steps a are etched using dry plasma etching to remove a portion of the N in step a. _ -GaN transition layer 3 and the portion of the C-doped GaN layer 2 located below it to form a stepped step c.

[0061] Preferably, the thickness of the removed portion of the C-doped GaN layer 2 is 1-2.5 μm.

[0062] More preferably, the length of the step c is 1μm-3μm or 5-8μm.

[0063] VI. For example Figure 6 As shown, a GaN channel layer with a thickness of 200nm-500nm is grown throughout the entire structure.

[0064] Since the polar and non-polar planes of GaN material are perpendicular to each other, when the vertical direction is polar, the horizontal direction is naturally non-polar. Therefore, MOCVD can be used to grow high-quality N-polar GaN epitaxial layers. In this way, an N-polar GaN epitaxial layer will be grown in the vertical direction, and the two-dimensional quantum well formed by it and the AlGaN barrier layer has a lower hole injection barrier and better electron confinement capability. At the same time, the GaN epitaxial layer grown in the horizontal direction is naturally non-polar.

[0065] Therefore, in this invention, the GaN channel layer 4 is made to have a polar surface in the vertical direction and a non-polar surface in the horizontal direction.

[0066] VII. For example Figure 7 As shown, an AlGaN barrier layer 5 with an Al composition of 15-35% and a thickness of 10-30 nm is grown on the GaN channel layer 4 to form an AlGaN / GaN structure.

[0067] In this invention, the AlGaN / GaN structure is a heterostructure. The side of the AlGaN barrier layer 5 is a polar surface (c), which gives the AlGaN / GaN structure a two-dimensional electron gas (d) in the vertical direction. Meanwhile, since the horizontal direction of the GaN channel layer 4 is a non-polar surface, there is no piezoelectric polarization, and therefore, no 2DEG is generated in the horizontal direction.

[0068] 8. For example Figure 8 As shown, in the self-supporting N + - A drain electrode 6 is deposited on the back side of GaN substrate 1.

[0069] In this invention, preferably, the drain electrode 6 is composed of a Ti layer, an Al layer, a Ni layer, and an Au layer stacked together. The thickness of the Ti layer is 20 nm, the thickness of the Al layer is 160 nm, the thickness of the Ni layer is 55 nm, and the thickness of the Au layer is 45 nm.

[0070] IX. For example Figure 9 As shown, the topmost AlGaN / GaN structure is removed to expose the N... _ -GaN transition layer 3, thereby forming the source window.

[0071] 10. For example Figure 10 As shown, the exposed N is etched using dry plasma etching. _ - The top of the GaN transition layer is etched to form the source groove e.

[0072] Preferably, the depth of the source groove 3 is 0.5–0.8 μm. More preferably, the length of the source groove e is 2–8 μm.

[0073] By setting the source groove e and forming the source electrode in the source groove 3, the contact area between the source electrode and the two-dimensional electron gas is increased, the source series resistance is reduced, and the power performance of the device is improved.

[0074] XI. For example Figure 11 As shown, a source electrode 7 is deposited on the source window and the source groove 3.

[0075] Preferably, the source electrode 7 is composed of a Ti layer, an Al layer, a Ni layer, and an Au layer stacked together. The thickness of the Ti layer is 20 nm, the thickness of the Al layer is 160 nm, the thickness of the Ni layer is 55 nm, and the thickness of the Au layer is 45 nm.

[0076] In this invention, after the source electrode 7 is deposited, metal annealing is performed. Specifically, the metal annealing is a rapid thermal annealing at 870°C in a N2 atmosphere for 30 seconds. Through metal annealing, the ohmic contact metal can be alloyed, thereby completing the fabrication of the source and drain electrodes.

[0077] 12. For example Figure 12 As shown, a medium layer 8 is deposited throughout.

[0078] Preferably, the dielectric layer is an HfO2 dielectric layer or a Si3N4 dielectric layer, and its thickness is 30 nm.

[0079] 13. For example Figure 13 As shown, a gate electrode 9 is deposited on the dielectric layer 8 located above the stepped step c.

[0080] Preferably, the gate electrode 9 is formed by stacking a Ni layer and an Au layer. The Ni layer has a thickness of 45 nm, and the Au layer has a thickness of 200 nm.

[0081] In this invention, by growing the dielectric layer 8 on the AlGaN barrier layer, a MIS structure (metal-insulator-semiconductor structure) is formed, replacing the conventional Schottky gate, which effectively reduces the gate leakage current and improves the gate voltage swing.

[0082] 14. Make interconnecting leads.

[0083] After the gate electrode 9 is deposited, interconnect leads are fabricated, thus completing the fabrication of the entire high electron mobility transistor with an insulated gate.

[0084] Preferably, the interconnect leads are formed by stacking a Ti layer and an Au layer. The thickness of the Ti layer is 20 nm, and the thickness of the Au layer is 200 nm.

[0085] The following detailed description of the insulated-gate high electron mobility transistor and its fabrication method, using several specific embodiments, will enable those skilled in the art to implement the invention based on the description provided.

[0086] Example 1

[0087] The fabrication method of the insulated-gate high electron mobility transistor in this embodiment includes the following steps:

[0088] Step 1. Epitaxial material growth

[0089] 1.1) In self-supporting N + - On GaN substrate 1, a 3-30 μm high-resistivity C-doped GaN layer 2 is grown using MOCVD process;

[0090] 1.2) On the high-resistivity C-doped GaN layer 2, 1-3 μm thick N-type ... - -GaN transition layer 3.

[0091] Step 2. Implementation of Vertical Structure

[0092] 2.1) Preliminary Step Treatment

[0093] A photoresist mask was obtained by spinning the photoresist at a speed of 3500 rpm using a spin coater; then, an NSR1755I7A lithography machine was used for exposure to form a mask that retains only a portion of the N-type photoresist. - -Window mask pattern of GaN transition layer 3;

[0094] Then, the substrate with the mask pattern was etched using an ICP98c inductively coupled plasma etching machine in Cl2 plasma at an etching rate of 1 nm / s to remove excess nitrogen. - -GaN transition layer 3 and high-resistivity C-doped GaN layer 2;

[0095] Among them, the retained N - The length of step a in GaN transition layer 3 and high-resistivity C-doped GaN layer 2 is 10μm-15μm, and the spacing between the two initial steps is 20μm-30μm.

[0096] 2.2) Stepped Step Treatment

[0097] A photoresist mask with a thickness of 2.5 μm was obtained by spinning positive photoresist on the surface of the epitaxial material at a speed of 5000 rpm and using the AZ6130 photoresist. The mask was then baked in a high-temperature oven at 80℃ for 10 min and then the window mask pattern of the gate trench was obtained by photolithography using an NSR1755I7A lithography machine.

[0098] Next, after development is complete, the N-type magnets that need to be etched away below the gate are removed. -- The GaN transition layer 3 has a window pattern, and the rest of the area is protected by photoresist as a mask;

[0099] Then, the substrate with the mask pattern was etched using an ICP98c inductively coupled plasma etching machine in Cl2 plasma at an etching rate of 1 nm / s to remove the N2 beneath the gate. - -GaN transition layer 3, and etch away part of the high-resistivity C-doped GaN layer 2;

[0100] Among them, N was etched away - The length of the stepped step c in the GaN transition layer 3 and the partially high-resistivity C-doped GaN layer 2 is 5μm-8μm.

[0101] 2.3) Regeneration to realize AlGaN / GaN heterostructure

[0102] First, a GaN channel layer with a thickness of 200nm-500nm is grown on the substrate after etching to form a stepped structure using MOCVD process.

[0103] Then, an AlGaN barrier layer 5 with an Al composition of 15% and a thickness of 30 nm is grown on the substrate after the GaN channel layer 4 is grown.

[0104] Step 3. Fabrication of the drain electrode

[0105] Ohmic metal was deposited on the back of the material. The drain electrode was fabricated using an Ohmiker-50 electron beam evaporation stage at an evaporation rate of 0.1 nm / s. The drain metals were Ti / Al / Ni / Au in sequence, with Ti thickness of 20 nm, Al thickness of 160 nm, Ni thickness of 55 nm, and Au thickness of 45 nm.

[0106] Step 4. Source Electrode Fabrication

[0107] 4.1) Source Electrode Window Creation

[0108] First, a photoresist mask with a thickness of 0.8 μm was obtained by spinning the photoresist mask at a speed of 5000 rpm.

[0109] Next, it is baked in a high-temperature oven at 80°C for 10 minutes, and then exposed using an NSR1755I7A lithography machine to expose the top AlGaN / GaN heterostructure that is to be realized as the source electrode, while protecting the rest.

[0110] Finally, the substrate with the mask pattern is etched using an ICP98c inductively coupled plasma etching machine in Cl2 plasma at an etching rate of 1 nm / s to remove the AlGaN / GaN heterostructure exposed after photolithography and form the source electrode window.

[0111] 4.2) Fabrication of source electrode recess

[0112] First, a spin coater was used to spin the photoresist onto the front side of the substrate at a speed of 5000 rpm, resulting in a photoresist mask thickness of 0.8 μm.

[0113] Next, it was baked in a high-temperature oven at 80℃ for 10 minutes, and then exposed using an NSR1755I7A lithography machine to expose the N-layer layer to be grooved. - -GaN transition layer 3 is exposed, while the rest is protected;

[0114] Finally, the substrate with the mask pattern was etched using an ICP98c inductively coupled plasma etching machine in Cl2 plasma at an etching rate of 1 nm / s to remove 0.5–0.8 μm of exposed N2. - -GaN transition layer 3, forming a groove structure.

[0115] 4.3) Source electrode deposition

[0116] First, photoresist was spin-coated at 5000 rpm on the front side of the vertical structure substrate with the step-shaped steps of the AlGaN / GaN heterostructure having a drain source window, to obtain a photoresist mask thickness of 0.8 μm.

[0117] Next, it is baked in a high-temperature oven at 80°C for 10 minutes, and then exposed using an NSR1755I7A lithography machine to form a source region mask pattern;

[0118] Then, source and drain electrodes were fabricated using an Ohmiker-50 electron beam evaporation stage at an evaporation rate of 0.1 nm / s. The source metals were Ti / Al / Ni / Au in sequence, with Ti having a thickness of 20 nm, Al having a thickness of 160 nm, Ni having a thickness of 55 nm, and Au having a thickness of 45 nm. After the source ohmic contact metal was evaporated, the metal was stripped to obtain a complete source electrode.

[0119] Step 5. Ohmic metal annealing

[0120] Using an RTP500 rapid thermal annealing furnace, rapid thermal annealing was performed at 870℃ in a N2 atmosphere for 30 seconds to alloy the ohmic contact metal, thus completing the fabrication of the source and drain electrodes.

[0121] Step 6. Dielectric layer deposition

[0122] 6.1) A 30 nm HfO2 dielectric layer was deposited on the substrate using plasma-enhanced atomic layer deposition (PEALD) technology.

[0123] 6.2) A photoresist mask with a thickness of 0.8 μm was obtained by spinning the photoresist mask at a speed of 5000 rpm using a spin coater.

[0124] Next, it is baked in a high-temperature oven at 80°C for 10 minutes, and then exposed using an NSR1755I7A lithography machine to form a gate area mask pattern;

[0125] Next, after development is complete, a window pattern is made in the dielectric layer above the source electrode that needs to be etched away, and the rest is protected by photoresist as a mask.

[0126] Then, the substrate with the mask pattern is etched using an ICP98c inductively coupled plasma etching machine in Cl2 plasma at an etching rate of 1 nm / s to remove the dielectric layer above the source metal and expose the source metal layer.

[0127] Step 7. Grid Electrode Fabrication

[0128] First, a photoresist mask with a thickness of 0.8 μm was obtained by spinning the photoresist mask at a speed of 5000 rpm.

[0129] Next, it is baked in a high-temperature oven at 80°C for 10 minutes, and then exposed using an NSR1755I7A lithography machine to form a gate area mask pattern;

[0130] Finally, the gate metal was evaporated using an Ohmiker-50 electron beam evaporation stage at an evaporation rate of 0.1 nm / s. The gate metal was selected as Ni / Au, with a Ni thickness of 45 nm and an Au thickness of 200 nm. After evaporation, the metal was stripped to obtain a complete gate electrode.

[0131] Step 8. Complete the fabrication of the interconnecting leads.

[0132] First, a spin coater is used to spin positive adhesive at a speed of 5000 rpm. Then, an NSR1755I7A lithography machine is used for exposure to form an electrode lead mask pattern. Next, an Ohmiker-50 electron beam evaporation stage is used to evaporate the lead electrode metal on the substrate with the mask at an evaporation rate of 0.3 nm / s. The metal used is Ti with a thickness of 20 nm and Au with a thickness of 200 nm. Finally, after the lead electrode metal evaporation is completed, it is peeled off to obtain the complete lead electrode.

[0133]

Example 2

[0134] The fabrication method of the insulated-gate high electron mobility transistor in this embodiment includes the following steps:

[0135] Step 1. Epitaxial material growth

[0136] 1.1) In self-support N+- On GaN substrate 1, a 3-30 μm high-resistivity C-doped GaN layer 2 is grown using MOCVD process;

[0137] 1.2) On the high-resistivity C-doped GaN layer 2, 1-3 μm thick N-type nanofibers are grown using MOCVD. - -GaN transition layer 3.

[0138] Step 2. Implementation of Vertical Structure

[0139] 2.1) Preliminary Step Treatment

[0140] A photoresist mask was obtained by spinning the photoresist at a speed of 3500 rpm using a spin coater; then, an NSR1755I7A lithography machine was used for exposure to form a mask that retains only a portion of the N-type photoresist. - -Window mask pattern of GaN transition layer 3;

[0141] Then, the substrate with the mask pattern was etched using an ICP98c inductively coupled plasma etching machine in Cl2 plasma at an etching rate of 1 nm / s to remove excess nitrogen. - -GaN transition layer 3 and high-resistivity C-doped GaN layer 2;

[0142] Among them, the retained N - The step length of GaN transition layer 3 and high-resistivity C-doped GaN layer is 10μm-15μm, and the spacing between the two initial steps is 20μm-30μm.

[0143] 2.2) Stepped Step Treatment

[0144] A photoresist mask with a thickness of 2.5 μm was obtained by spinning positive photoresist on the surface of the epitaxial material at a speed of 5000 rpm and using the AZ6130 photoresist. The mask was then baked in a high-temperature oven at 80℃ for 10 min and then the window mask pattern of the gate trench was obtained by photolithography using an NSR1755I7A lithography machine.

[0145] Next, after development is complete, the N-type magnets that need to be etched away below the gate are removed. - - The GaN transition layer 3 has a window pattern, and the rest of the area is protected by photoresist as a mask;

[0146] Then, the substrate with the mask pattern was etched using an ICP98c inductively coupled plasma etching machine in Cl2 plasma at an etching rate of 1 nm / s to remove the N2 beneath the gate. - -GaN transition layer 3, and etch away part of the high-resistivity C-doped GaN layer 2;

[0147] Among them, N was etched away -The length of the stepped step c in the GaN transition layer 3 and the partially high-resistivity C-doped GaN layer 2 is 5μm-8μm.

[0148] 2.3) Regeneration to realize AlGaN / GaN heterostructure

[0149] First, a GaN channel layer with a thickness of 200nm-500nm is grown on the substrate after etching to form a stepped structure using MOCVD process.

[0150] Then, an AlGaN barrier layer 5 with an Al composition of 15% and a thickness of 30 nm is grown on the substrate after the GaN channel layer 4 is grown.

[0151] Step 3. Fabrication of the drain electrode

[0152] Ohmic metal was deposited on the back of the material. The drain electrode was fabricated using an Ohmiker-50 electron beam evaporation stage at an evaporation rate of 0.1 nm / s. The drain metals were Ti / Al / Ni / Au in sequence, with Ti thickness of 20 nm, Al thickness of 160 nm, Ni thickness of 55 nm, and Au thickness of 45 nm.

[0153] Step 4. Source Electrode Fabrication

[0154] 4.1) Source Electrode Window Creation

[0155] First, a photoresist mask with a thickness of 0.8 μm was obtained by spinning the photoresist mask at a speed of 5000 rpm.

[0156] Next, it is baked in a high-temperature oven at 80°C for 10 minutes, and then exposed using an NSR1755I7A lithography machine to expose the top AlGaN / GaN heterostructure that is to be realized as the source electrode, while protecting the rest.

[0157] Finally, the substrate with the mask pattern is etched using an ICP98c inductively coupled plasma etching machine in Cl2 plasma at an etching rate of 1 nm / s to remove the AlGaN / GaN heterostructure exposed after photolithography and form the source electrode window.

[0158] 4.2) Fabrication of source electrode recess

[0159] First, a spin coater was used to spin the photoresist onto the front side of the substrate at a speed of 5000 rpm, resulting in a photoresist mask thickness of 0.8 μm.

[0160] Next, it was baked in a high-temperature oven at 80℃ for 10 minutes, and then exposed using an NSR1755I7A lithography machine to expose the N-layer layer to be grooved. - -GaN transition layer 3 is exposed, while the rest is protected;

[0161] Finally, the substrate with the mask pattern was etched using an ICP98c inductively coupled plasma etching machine in Cl2 plasma at an etching rate of 1 nm / s to remove 0.5–0.8 μm of exposed N2. - -GaN transition layer 3, forming a groove structure.

[0162] 4.3) Source electrode deposition

[0163] First, photoresist was spin-coated at 5000 rpm on the front side of the vertical structure substrate with the step-shaped steps of the AlGaN / GaN heterostructure having a drain source window, to obtain a photoresist mask thickness of 0.8 μm.

[0164] Next, it is baked in a high-temperature oven at 80°C for 10 minutes, and then exposed using an NSR1755I7A lithography machine to form a source region mask pattern;

[0165] Then, source and drain electrodes were fabricated using an Ohmiker-50 electron beam evaporation stage at an evaporation rate of 0.1 nm / s. The source metals were Ti / Al / Ni / Au in sequence, with Ti having a thickness of 20 nm, Al having a thickness of 160 nm, Ni having a thickness of 55 nm, and Au having a thickness of 45 nm. After the source ohmic contact metal was evaporated, the metal was stripped to obtain a complete source electrode.

[0166] Step 5. Ohmic metal annealing

[0167] Using an RTP500 rapid thermal annealing furnace, rapid thermal annealing was performed at 870℃ in a N2 atmosphere for 30 seconds to alloy the ohmic contact metal, thus completing the fabrication of the source and drain electrodes.

[0168] Step 6. Dielectric layer deposition

[0169] 6.1) A 30 nm Al2O3 dielectric layer 8 was deposited on the substrate using MOCVD process;

[0170] 6.2) A photoresist mask with a thickness of 0.8 μm was obtained by spinning the photoresist mask at a speed of 5000 rpm using a spin coater.

[0171] Next, it is baked in a high-temperature oven at 80°C for 10 minutes, and then exposed using an NSR1755I7A lithography machine to form a gate area mask pattern;

[0172] Next, after development is complete, a window pattern is made in the dielectric layer above the source electrode that needs to be etched away, and the rest is protected by photoresist as a mask.

[0173] Then, the substrate with the mask pattern is etched using an ICP98c inductively coupled plasma etching machine with Cl2 plasma at an etching rate of 1 nm / s to remove the dielectric layer above the source metal and expose the source metal layer.

[0174] Step 7. Grid Electrode Fabrication

[0175] First, a photoresist mask with a thickness of 0.8 μm was obtained by spinning the photoresist mask at a speed of 5000 rpm.

[0176] Next, it is baked in a high-temperature oven at 80°C for 10 minutes, and then exposed using an NSR1755I7A lithography machine to form a gate area mask pattern;

[0177] Finally, the gate metal was evaporated using an Ohmiker-50 electron beam evaporation stage at an evaporation rate of 0.1 nm / s. The gate metal was selected as Ni / Au, with a Ni thickness of 45 nm and an Au thickness of 200 nm. After evaporation, the metal was stripped to obtain a complete gate electrode.

[0178] Step 8. Complete the fabrication of the interconnecting leads.

[0179] First, a spin coater is used to spin positive adhesive at a speed of 5000 rpm. Then, an NSR1755I7A lithography machine is used for exposure to form an electrode lead mask pattern. Next, an Ohmiker-50 electron beam evaporation stage is used to evaporate the lead electrode metal on the substrate with the mask at an evaporation rate of 0.3 nm / s. The metal used is Ti with a thickness of 20 nm and Au with a thickness of 200 nm. Finally, after the lead electrode metal evaporation is completed, it is peeled off to obtain the complete lead electrode.

[0180]

Example 3

[0181] The fabrication method of the high electron mobility transistor with a vertical AlGaN / GaN structure in this embodiment includes the following steps:

[0182] Step 1. Epitaxial material growth

[0183] 1.1) In self-supporting N + - On GaN substrate 1, a 3-30 μm high-resistivity C-doped GaN layer 2 is grown using MOCVD process;

[0184] 1.2) On the high-resistivity C-doped GaN layer 2, 1-3 μm thick N-type ... - -GaN transition layer 3.

[0185] Step 2. Implementation of Vertical Structure

[0186] 2.1) Preliminary Step Treatment

[0187] A photoresist mask was obtained by spinning the photoresist at a speed of 3500 rpm using a spin coater; then, an NSR1755I7A lithography machine was used for exposure to form a mask that retains only a portion of the N-type photoresist. - -Window mask pattern of GaN transition layer 3;

[0188] Then, the substrate with the mask pattern was etched using an ICP98c inductively coupled plasma etching machine in Cl2 plasma at an etching rate of 1 nm / s to remove excess nitrogen. - -GaN transition layer 3 and high-resistivity C-doped GaN C layer 2;

[0189] Among them, the retained N - The step a length of GaN transition layer 3 and high-resistivity C-doped GaN layer 2 is 10μm-15μm, and the spacing between the two initial steps is 20μm-30μm.

[0190] 2.2) Stepped Step Treatment

[0191] A photoresist mask with a thickness of 2.5 μm was obtained by spinning positive photoresist on the surface of the epitaxial material at a speed of 5000 rpm and using the AZ6130 photoresist. The mask was then baked in a high-temperature oven at 80℃ for 10 min and then the window mask pattern of the gate trench was obtained by photolithography using an NSR1755I7A lithography machine.

[0192] Next, after development is complete, the N-type magnets that need to be etched away below the gate are removed. - - The GaN transition layer 3 has a window pattern, and the rest of the area is protected by photoresist as a mask;

[0193] Then, the substrate with the mask pattern was etched using an ICP98c inductively coupled plasma etching machine in Cl2 plasma at an etching rate of 1 nm / s to remove the N2 beneath the gate. - -GaN transition layer 3, and etch away part of the high-resistivity C-doped GaN layer 2;

[0194] Among them, N was etched away - The length of the stepped steps c in the GaN transition layer 3 and the partially high-resistivity C-doped GaN layer is 5μm-8μm.

[0195] 2.3) Regeneration to realize AlGaN / GaN heterostructure

[0196] First, a GaN channel layer with a thickness of 200nm-500nm is grown on the substrate after etching to form a stepped structure using MOCVD process.

[0197] Then, an AlGaN barrier layer with an Al composition of 15% and a thickness of 30 nm is grown on the substrate after the GaN channel layer is grown.

[0198] Step 3. Fabrication of Drain Electrode 6

[0199] Ohmic metal was deposited on the back of the material. The drain electrode was fabricated using an Ohmiker-50 electron beam evaporation stage at an evaporation rate of 0.1 nm / s. The drain metals were Ti / Al / Ni / Au in sequence, with Ti thickness of 20 nm, Al thickness of 160 nm, Ni thickness of 55 nm, and Au thickness of 45 nm.

[0200] Step 4. Fabrication of source electrode 7

[0201] 4.1) Source Electrode Window Creation

[0202] First, a photoresist mask with a thickness of 0.8 μm was obtained by spinning the photoresist mask at a speed of 5000 rpm.

[0203] Next, it is baked in a high-temperature oven at 80°C for 10 minutes, and then exposed using an NSR1755I7A lithography machine to expose the top AlGaN / GaN heterostructure that is to be realized as the source electrode, while protecting the rest.

[0204] Finally, the substrate with the mask pattern is etched using an ICP98c inductively coupled plasma etching machine in Cl2 plasma at an etching rate of 1 nm / s to remove the AlGaN / GaN heterostructure exposed after photolithography and form the source electrode window.

[0205] 4.2) Fabrication of the source electrode groove e

[0206] First, a spin coater was used to spin the photoresist onto the front side of the substrate at a speed of 5000 rpm, resulting in a photoresist mask thickness of 0.8 μm.

[0207] Next, it was baked in a high-temperature oven at 80℃ for 10 minutes, and then exposed using an NSR1755I7A lithography machine to expose the N-layer layer to be grooved. - -GaN transition layer 3 is exposed, while the rest is protected;

[0208] Finally, the substrate with the mask pattern was etched using an ICP98c inductively coupled plasma etching machine in Cl2 plasma at an etching rate of 1 nm / s to remove 0.5–0.8 μm of exposed N2. - -GaN transition layer 3, forming a groove structure.

[0209] 4.3) Source electrode deposition

[0210] First, photoresist was spin-coated at 5000 rpm on the front side of the vertical structure substrate with the step-shaped steps of the AlGaN / GaN heterostructure having a drain source window, to obtain a photoresist mask thickness of 0.8 μm.

[0211] Next, it is baked in a high-temperature oven at 80°C for 10 minutes, and then exposed using an NSR1755I7A lithography machine to form a source region mask pattern;

[0212] Then, source and drain electrodes were fabricated using an Ohmiker-50 electron beam evaporation stage at an evaporation rate of 0.1 nm / s. The source metals were Ti / Al / Ni / Au in sequence, with Ti having a thickness of 20 nm, Al having a thickness of 160 nm, Ni having a thickness of 55 nm, and Au having a thickness of 45 nm. After the source ohmic contact metal was evaporated, the metal was stripped to obtain a complete source electrode.

[0213] Step 5. Ohmic metal annealing

[0214] Using an RTP500 rapid thermal annealing furnace, rapid thermal annealing was performed at 870℃ in a N2 atmosphere for 30 seconds to alloy the ohmic contact metal, thus completing the fabrication of the source and drain electrodes.

[0215] Step 6. Dielectric layer deposition

[0216] 6.1) A 30nm Si3N4 dielectric layer 8 was deposited on the substrate using MOCVD process;

[0217] 6.2) A photoresist mask with a thickness of 0.8 μm was obtained by spinning the photoresist mask at a speed of 5000 rpm using a spin coater.

[0218] Next, it is baked in a high-temperature oven at 80°C for 10 minutes, and then exposed using an NSR1755I7A lithography machine to form a gate area mask pattern;

[0219] Next, after development is complete, a window pattern is made in the dielectric layer above the source electrode that needs to be etched away, and the rest is protected by photoresist as a mask.

[0220] Then, the substrate with the mask pattern is etched using an ICP98c inductively coupled plasma etching machine in Cl2 plasma at an etching rate of 1 nm / s to remove the dielectric layer above the source metal and expose the source metal layer.

[0221] Step 7. Fabrication of the gate electrode 9

[0222] First, a photoresist mask with a thickness of 0.8 μm was obtained by spinning the photoresist mask at a speed of 5000 rpm.

[0223] Next, it is baked in a high-temperature oven at 80°C for 10 minutes, and then exposed using an NSR1755I7A lithography machine to form a gate area mask pattern;

[0224] Finally, the gate metal was evaporated using an Ohmiker-50 electron beam evaporation stage at an evaporation rate of 0.1 nm / s. The gate metal was selected as Ni / Au, with a Ni thickness of 45 nm and an Au thickness of 200 nm. After evaporation, the metal was stripped to obtain a complete gate electrode.

[0225] Step 8. Complete the fabrication of the interconnecting leads.

[0226] First, a spin coater is used to spin positive adhesive at a speed of 5000 rpm. Then, an NSR1755I7A lithography machine is used for exposure to form an electrode lead mask pattern. Next, an Ohmiker-50 electron beam evaporation stage is used to evaporate the lead electrode metal on the substrate with the mask at an evaporation rate of 0.3 nm / s. The metal used is Ti with a thickness of 20 nm and Au with a thickness of 200 nm. Finally, after the lead electrode metal evaporation is completed, it is peeled off to obtain the complete lead electrode.

[0227] The insulated gate high electron mobility transistor and its fabrication method of the present invention can solve the problems of threshold voltage less than 0 and poor withstand voltage capability of conventional GaN-based HEMT devices.

[0228] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit the scope of protection of the present invention. Those skilled in the art can modify or make equivalent substitutions to the technical solutions of the present invention based on the concept of the present invention, without departing from the essence and scope of the technical solutions of the present invention.

Claims

1. A method for fabricating an insulated-gate high electron mobility transistor, characterized in that, Includes the following steps: 1) In self-supporting N + - A C-doped GaN layer (2) with a thickness of 3 μm - 30 μm is grown on a GaN substrate (1); 2) An N-type substrate with a thickness of 1 μm - 3 μm is grown on the C-doped GaN layer (2). - -GaN transition layer (3); 3) Part of the N is removed by dry plasma etching. - -GaN transition layer (3) and the C-doped GaN layer (2) below it to form two steps (a) and a groove (b) between the two steps (a); 4) The two steps (a) are etched by dry plasma etching to remove part of the N in the steps (a). - -GaN transition layer (3) and a portion of the C-doped GaN layer (2) below it to form a stepped step (c); 5) Grow a GaN channel layer with a thickness of 200nm-500nm (4); 6) An AlGaN barrier layer (5) with an Al composition of 15-35% and a thickness of 10nm-30nm is grown on the GaN channel layer (4) to form an AlGaN / GaN structure; 7) In the self-supporting N + - A drain electrode (6) is deposited on the back side of the GaN substrate (1). 8) Remove the topmost AlGaN / GaN structure to expose the N. - -GaN transition layer (3), thereby forming the source window; 9) The exposed N is etched using dry plasma etching. - - The top of the GaN transition layer (3) is etched to form a source groove (e). 10) Deposit source electrode (7) on the source window and source groove (e); 11) Deposit a medium layer as a whole (8); 12) Deposit a gate electrode (9) on the dielectric layer (8) located above the stepped step (c); 13) Make interconnecting leads.

2. The method for fabricating an insulated-gate high electron mobility transistor according to claim 1, characterized in that, The GaN channel layer (4) has a polar surface in the vertical direction and a non-polar surface in the horizontal direction, and the AlGaN barrier layer (5) has a polar c-surface on its side, so that the AlGaN / GaN structure has a two-dimensional electron gas (d) in the vertical direction.

3. The method for fabricating an insulated-gate high electron mobility transistor according to claim 1, characterized in that, The length of the step (a) is 10μm-15μm, and the distance between two steps (a) is 20μm-30μm.

4. The method for fabricating an insulated-gate high electron mobility transistor according to claim 1, characterized in that, The length of the stepped step (c) is 1μm-3μm or 5μm-8μm.

5. The method for fabricating an insulated-gate high electron mobility transistor according to claim 1, characterized in that, The depth of the source groove (e) is 0.5 μm to 0.8 μm.

6. The method for fabricating an insulated-gate high electron mobility transistor according to claim 1, characterized in that, The drain electrode (6) and the source electrode (7) are both made of Ti layer, Al layer, Ni layer and Au layer stacked together, wherein the thickness of the Ti layer is 20nm, the thickness of the Al layer is 160nm, the thickness of the Ni layer is 55nm and the thickness of the Au layer is 45nm.

7. The method for fabricating an insulated-gate high electron mobility transistor according to claim 1, characterized in that, After completing step 10), metal annealing is performed first, followed by step 11), wherein the metal annealing is a rapid thermal annealing at 870°C in a N2 atmosphere for 30 seconds.

8. The method for fabricating an insulated-gate high electron mobility transistor according to claim 1, characterized in that, The gate electrode (9) is formed by stacking a Ni layer and an Au layer, wherein the thickness of the Ni layer is 45 nm and the thickness of the Au layer is 200 nm.

9. The method for fabricating an insulated-gate high electron mobility transistor according to claim 1, characterized in that, The dielectric layer is dielectric layer or The dielectric layer has a thickness of 30 nm.

10. An insulated-gate high electron mobility transistor, characterized in that, It is prepared by any one of the preparation methods according to claims 1-9.

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