VCSEL Chip and Its Manufacturing Method

Abstract

A VCSEL chip and a manufacturing method thereof are disclosed. Among them, the VCSEL chip includes: a base layer, a plurality of VCSEL units formed on the base layer and isolated from each other, and a plurality of optical modulation elements integrally arranged at the wafer level on the plurality of VCSEL light-emitting units. The plurality of VCSEL light-emitting units are divided into a plurality of sub-light source areas through cathode partitioning, and the plurality of optical modulation elements have a preset structural configuration and are distributed in the plurality of sub-light source areas according to a preset distribution manner, so as to control the overall divergence angle of the VCSEL chip by controlling the positions of the lit sub-light source areas in the plurality of sub-light source areas. The VCSEL chip regulates its overall divergence angle through its own structural design to expand the scanning field of the VCSEL chip, and moreover, the VCSEL chip reduces the difficulty of partition wiring through the method of cathode partitioning.

Description

Technical Field

[0001] This application relates to the field of semiconductor lasers, and more specifically to VCSEL chips and their manufacturing methods. Background Art

[0002] A VCSEL (Vertical-Cavity Surface-Emitting Laser) is a semiconductor laser that forms a resonant cavity in the vertical direction of a substrate and emits laser light in the vertical direction. With the development of VCSEL technology, VCSEL lasers are widely used in fields such as intelligent transportation, healthcare, biological detection, and military security.

[0003] In the actual industry, VCSEL lasers are often used as projection light sources to perform depth measurement on a target to be measured for three-dimensional modeling, depth mapping, etc. In some application scenarios, it is also necessary to perform wide-angle scanning on the target to be measured for large-angle modeling of the target. For example, when a VCSEL chip is used as a projection light source of a vehicle lidar, this application scenario requires the VCSEL chip to have a larger scanning range to more comprehensively collect road condition information to assist the vehicle in realizing functions such as route planning and roadblock avoidance. However, the typical scanning range of existing VCSEL chips is within 90°, that is, they can only scan a relatively narrow area of the target to be measured.

[0004] To overcome this technical problem, in a vehicle lidar, a rotating motor is usually configured for the VCSEL chip to drive the VCSEL chip to rotate through the rotating motor, and in this way, the scanning range is expanded. However, this solution has many defects.

[0005] First, the rotation accuracy of the VCSEL chip depends on the structural stability between it and the rotating motor, as well as the control accuracy of the rotating motor. That is, if the control accuracy of the rotating motor is poor, or if the cooperation relationship between the VCSEL chip and the rotating motor changes, this will affect the scanning effect of the VCSEL chip.

[0006] Second, under the action of the rotating motor, the relative position relationship between the VCSEL chip and the target to be measured is adjusted. Although this method can expand the scanning range of the VCSEL chip, because the relative position relationship between the VCSEL chip and the target to be measured is adjusted, this will increase the difficulty of information processing for subsequent three-dimensional modeling.

[0007] Therefore, an optimized solution is needed to expand the scanning range of the VCSEL chip. Summary of the Invention

[0008] One advantage of the present application is to provide a VCSEL chip and a method for manufacturing the same. Among them, the VCSEL chip can adjust its overall divergence angle through its own structural design to expand the scanning area of the VCSEL chip. That is, the VCSEL chip according to the embodiments of the present application can expand its own scanning area (that is, expand the laser projection range) without an external driver.

[0009] Another advantage of the present application is to provide a VCSEL chip and a method for manufacturing the same. Among them, by controlling the illuminated area and the illumination sequence of the VCSEL chip, the scanning area and the scanning mode of the VCSEL chip can be adjusted, so that the VCSEL chip can be applied to a variety of application scenarios.

[0010] Yet another advantage of the present application is to provide a VCSEL chip and a method for manufacturing the same. Among them, the addressing circuit structure of the VCSEL chip cooperates with the semiconductor structure design of the VCSEL chip, so that the VCSEL chip realizes the function of area-by-area illumination with a relatively simplified wiring structure.

[0011] To achieve at least one of the above advantages or other advantages and purposes, according to one aspect of the present application, a VCSEL chip is provided, which includes:

[0012] A base layer;

[0013] A plurality of VCSEL units formed on the base layer and isolated from each other. Among them, each VCSEL light-emitting unit includes a light-emitting body, a positive electrode and a negative electrode electrically connected to the light-emitting body. Among them, the positive electrodes of all the VCSEL light-emitting units are electrically connected to each other to form a top electrical conduction pattern of the plurality of VCSEL light-emitting units, and the negative electrodes in multiple regions among all the negative electrodes of the VCSEL light-emitting units are electrically connected to each other to form a plurality of bottom electrical conduction patterns. The plurality of VCSEL light-emitting units are divided into a plurality of sub-light source regions through the top electrical conduction pattern and the plurality of bottom electrical conduction patterns; and

[0014] A plurality of optical modulation elements integrally arranged at the wafer level on the plurality of VCSEL light-emitting units. Among them, the plurality of optical modulation elements have a preset structural configuration and are distributed in the plurality of sub-light source regions according to a preset distribution method to control the overall divergence angle of the VCSEL chip by controlling the position of the illuminated sub-light source region in the plurality of sub-light source regions.

[0015] In the VCSEL chip of the present application, the VCSEL chip further includes: an addressing circuit structure electrically connected to the plurality of VCSEL units, the addressing circuit structure including a plurality of electrical connection lines, wherein each of the electrical connection lines is electrically connected to at least two of the plurality of bottom electrical conduction patterns. In this way, the addressing circuit structure forms an addressing circuit for the plurality of VCSEL units so that any one of the sub-light source regions is adapted to achieve electrical conduction by simultaneously conducting at least one of the plurality of electrical connection lines and the top electrical conduction pattern.

[0016] In the VCSEL chip of the present application, the laser generated by the light-emitting body exits from the top of the light-emitting body, and the plurality of light modulation elements are disposed on the top surface of the light-emitting body.

[0017] In the VCSEL chip of the present application, the light-emitting body sequentially includes, from bottom to top: an N-type electrical contact layer, an N-DBR layer, an active region, a confinement layer, a P-DBR layer, and a P-type electrical contact layer. Wherein, the confinement layer has a confinement hole corresponding to the active region, and the N-DBR layer and the P-DBR layer are configured such that after the VCSEL light-emitting unit is turned on, the laser generated by the active region is repeatedly reflected in the resonant cavity formed between the N-DBR layer and the P-DBR layer and exits from the P-DBR layer, and the light modulation element is formed on the P-type electrical contact layer.

[0018] In the VCSEL chip of the present application, the positive electrode includes a light-emitting hole structure electrically connected to the light-emitting body and a first electrical conduction layer covering the light-emitting hole structure. Wherein, the light-emitting hole structure forms a light-emitting hole corresponding to the confinement hole, and the first electrical conduction layers of all the VCSEL light-emitting units are integrally connected to form the top electrical conduction pattern.

[0019] In the VCSEL chip of the present application, the first electrical conduction layer has at least one opening, and the opening corresponds to the light-emitting hole.

[0020] In the VCSEL chip of the present application, the first electrical conduction layer is made of a light-transmissive conductive material.

[0021] In the VCSEL chip of the present application, the negative electrode is led out from the N-type electrical contact layer to the bottom of the base layer.

[0022] In the VCSEL chip of the present application, the plurality of light modulation elements include at least one convex lens and at least one concave lens.

[0023] In the VCSEL chip of the present application, at least part of the concave lenses are distributed in the outer sub-light source regions adjacent to the edge of the VCSEL chip among the multiple sub-light source regions.

[0024] In the VCSEL chip of the present application, at least part of the convex lenses are distributed in the inner sub-light source regions at least partially located in the middle region of the VCSEL chip among the multiple sub-light source regions.

[0025] In the VCSEL chip of the present application, the multiple optical modulation elements have a preset structural configuration and cooperate with each other so that the overall divergence angle of the VCSEL chip is greater than or equal to 120°.

[0026] According to another aspect of the present application, there is provided a method for manufacturing a VCSEL chip, which includes:

[0027] Forming a semiconductor structure, which sequentially includes a substrate structure, a bottom conductive layer structure, an N-type electrical contact structure, an N-DBR structure, an active region structure, a P-DBR structure, a P-type electrical contact structure, and a layer to be processed from bottom to top;

[0028] Processing the layer to be processed through an etching process to form multiple optical modulation elements above the P-type electrical contact structure to obtain a chip semi-finished product;

[0029] Forming multiple light-emitting hole structures electrically connected to the P-type electrical contact structure of the semiconductor structure, wherein the multiple light-emitting hole structures define multiple light-emitting holes;

[0030] Removing at least a part of the chip semi-finished product to form multiple sub-structure units that are electrically isolated from each other, and each sub-structure unit includes an N-type electrical contact layer, an N-DBR layer, an active region, a P-DBR layer, and a P-type electrical contact layer from bottom to top;

[0031] Removing at least a part of the bottom conductive layer structure to form multiple bottom electrical conduction patterns that are electrically isolated from each other;

[0032] Processing the multiple sub-structure units forming the bottom electrical conduction patterns to form a confinement layer with confinement holes above the active region, and the confinement holes correspond to the light-emitting holes; and

[0033] Forming a second electrical conduction layer covering all the light-emitting hole structures to form a top electrical conduction pattern.

[0034] In the method for manufacturing a VCSEL chip of the present application, processing a plurality of sub-structure units forming the bottom electrical conduction pattern to form a confinement layer with confinement holes above the active region includes: forming a protective layer covering the light-emitting hole structure and the plurality of bottom electrical conduction patterns; oxidizing the plurality of sub-structure units; and exposing the light-emitting hole structure and the plurality of bottom electrical conduction patterns.

[0035] In the method for manufacturing a VCSEL chip of the present application, the substrate structure is made of a non-conductive material.

[0036] Through the understanding of the subsequent description and the drawings, further objectives and advantages of the present application will be fully embodied.

[0037] These and other objectives, features, and advantages of the present application are fully embodied through the following detailed description, drawings, and claims. Description of the Drawings

[0038] From the following detailed description of the embodiments of the present invention in conjunction with the drawings, these and / or other aspects and advantages of the present application will become clearer and easier to understand, where:

[0039] Figure 1 A partial schematic diagram of a VCSEL chip according to an embodiment of the present application is illustrated.

[0040] Figure 2 A schematic diagram of a VCSEL chip according to an embodiment of the present application is illustrated.

[0041] Figure 3 A schematic diagram of a variant implementation of a VCSEL chip according to an embodiment of the present application is illustrated.

[0042] Figure 4 A flowchart of a method for manufacturing a VCSEL chip according to an embodiment of the present application is illustrated.

[0043] Figure 5A A schematic diagram of one of the manufacturing processes of a VCSEL chip according to an embodiment of the present application is illustrated.

[0044] Figure 5B A schematic diagram of another of the manufacturing processes of a VCSEL chip according to an embodiment of the present application is illustrated.

[0045] Figure 5C A schematic diagram of yet another of the manufacturing processes of a VCSEL chip according to an embodiment of the present application is illustrated. Detailed Embodiments

[0046] The terms and words used in the following specification and claims are not limited to their literal meanings, but are used solely by the present inventor to enable a clear and consistent understanding of the present application. Accordingly, the following description of the various embodiments of the present application is provided to those skilled in the art for illustrative purposes only and not for the purpose of limiting the present application as defined by the appended claims and their equivalents.

[0047] It will be understood that the term "a" should be construed to mean "at least one" or "one or more". That is, in one embodiment, the number of an element may be one, while in other embodiments, the number of the element may be multiple. The term "a" should not be construed as limiting the number.

[0048] Although ordinal numbers such as "first", "second", etc. will be used to describe various components, those components are not limited herein. The term is only used to distinguish one component from another. For example, a first component may be referred to as a second component, and similarly, a second component may also be referred to as a first component, without departing from the teachings of the inventive concept. The term "and / or" used herein includes any and all combinations of one or more of the associated listed items.

[0049] The terms used herein are for the purpose of describing the various embodiments only and are not intended to be limiting. As used herein, the singular forms are also intended to include the plural forms unless the context clearly indicates otherwise. Additionally, it will be understood that the terms "comprises" and / or "has" when used in this specification specify the presence of the stated features, numbers, steps, operations, components, elements, or combinations thereof, without precluding the presence or addition of one or more other features, numbers, steps, operations, components, elements, or groups thereof.

[0050] Application Overview

[0051] As described above, a VCSEL (Vertical-Cavity Surface-Emitting Laser) is a semiconductor laser that forms a resonant cavity in the vertical direction of a substrate and emits laser light in the vertical direction. With the development of VCSEL technology, VCSEL lasers are widely used in fields such as intelligent transportation, health care, biological detection, and military security.

[0052] In the actual industry, VCSEL lasers are often used as projection light sources to measure the depth of the target to be measured for three-dimensional modeling, depth mapping, etc. In some application scenarios, it is also necessary to perform wide-angle scanning on the target to be measured for large-angle modeling. For example, when a VCSEL chip is used as the projection light source of a vehicle lidar, this application scenario requires the VCSEL chip to have a large scanning range to more comprehensively collect road condition information to assist the vehicle in realizing functions such as route planning and roadblock avoidance. However, the scanning range of existing VCSEL chips is usually within 90°, that is, it can only scan a relatively narrow area of the target to be measured.

[0053] To overcome this technical problem, in a vehicle lidar, a rotary motor is usually configured for the VCSEL chip to drive the VCSEL chip to rotate through the rotary motor, and in this way, the scanning range is expanded. However, this solution has many defects.

[0054] First of all, the rotation accuracy of the VCSEL chip depends on the structural stability between it and the rotary motor, and the control accuracy of the rotary motor. That is to say, if the control accuracy of the rotary motor is poor, or the cooperation relationship between the VCSEL chip and the rotary motor changes, this will affect the scanning effect of the VCSEL chip.

[0055] Secondly, under the action of the rotary motor, the relative position relationship between the VCSEL chip and the target to be measured is adjusted. Although this method can expand the scanning range of the VCSEL chip, because the relative position relationship between the VCSEL chip and the target to be measured is adjusted, this will increase the difficulty of information processing for subsequent three-dimensional modeling.

[0056] Moreover, if real-time monitoring of the surrounding environment is to be achieved, the rotating mechanism needs to keep rotating at a high frequency and is prone to wear. On the one hand, this requires a high performance of the rotating mechanism, and on the other hand, it also shows that its working performance is difficult to remain stable.

[0057] In addition, the method of expanding the laser projection range (i.e., the scanning range) of the VCSEL light source by matching the VCSEL light source with the driving device is not conducive to the miniaturization of the overall device. For example, the main reason for the large size of existing lidar devices is that the rotating mechanism occupies a relatively large volume.

[0058] In view of the above technical problems, the technical concept of the present application is as follows: to regulate the overall divergence angle through its own structural design so as to expand the scanning area of the VCSEL chip. That is, the VCSEL chip according to the embodiments of the present application can achieve the expansion of its own scanning area (that is, the expansion of the laser projection range) without an external driver. Specifically, an optical modulation element array with different optical modulation performances is configured on the light-emitting paths of multiple VCSEL light-emitting units of the VCSEL chip, so as to regulate the overall divergence angle of the VCSEL chip through the optical modulation element array and expand its scanning area or laser projection range.

[0059] Based on this, according to one aspect of the present application, a VCSEL chip is proposed, which includes: a base layer, a plurality of VCSEL units formed on the base layer and isolated from each other, and a plurality of optical modulation elements integrally arranged at the wafer level on the plurality of VCSEL light-emitting units. Each of the VCSEL light-emitting units includes a light-emitting body, a positive electrode and a negative electrode electrically connected to the light-emitting body. Among them, the positive electrodes of all the VCSEL light-emitting units are electrically connected to each other to form the top electrical conduction pattern of the plurality of VCSEL light-emitting units, and the negative electrodes in multiple regions among all the negative electrodes of the VCSEL light-emitting units are electrically connected to each other to form a plurality of bottom electrical conduction patterns. The plurality of VCSEL light-emitting units are divided into a plurality of sub-light source regions through the top electrical conduction pattern and the plurality of bottom electrical conduction patterns. The plurality of optical modulation elements have a preset structural configuration and are distributed in the plurality of sub-light source regions according to a preset distribution method, so as to regulate the overall divergence angle of the VCSEL chip by controlling the positions of the illuminated sub-light source regions in the plurality of sub-light source regions.

[0060] According to another aspect of the present application, a method for manufacturing a VCSEL chip is provided, which includes: forming a semiconductor structure, the semiconductor structure sequentially including a substrate structure, a bottom conductive layer structure, an N-type electrical contact structure, an N-DBR structure, an active region structure, a P-DBR structure, a P-type electrical contact structure, and a layer to be processed from bottom to top; processing the layer to be processed through an etching process to form a plurality of optical modulation elements above the P-type electrical contact structure to obtain a chip semi-finished product; forming a plurality of light-emitting hole structures electrically connected to the P-type electrical contact structure of the semiconductor structure, wherein the plurality of light-emitting hole structures define a plurality of light-emitting holes; removing at least a part of the chip semi-finished product to form a plurality of sub-structure units that are electrically isolated from each other, each sub-structure unit including an N-type electrical contact layer, an N-DBR layer, an active region, a P-DBR layer, and a P-type electrical contact layer from bottom to top; removing at least a part of the bottom conductive layer structure to form a plurality of bottom electrical conduction patterns that are electrically isolated from each other; processing the plurality of sub-structure units forming the bottom electrical conduction patterns to form a confinement layer with confinement holes above the active region, the confinement holes corresponding to the light-emitting holes; and forming a second electrical conduction layer covering all the light-emitting hole structures to form a top electrical conduction pattern.

[0061] After introducing the basic principle of the present application, various non-limiting embodiments of the present application will be specifically introduced with reference to the accompanying drawings.

[0062] Schematic VCSEL Chip

[0063] As Figures 1 to 3 shown, a VCSEL chip according to an embodiment of the present application is illustrated, wherein the VCSEL chip includes a base layer 10, a plurality of mutually isolated VCSEL light-emitting units 20 formed on the base layer 10, and a plurality of optical modulation elements 50 integrally provided at the wafer level on the plurality of VCSEL light-emitting units 20. The base layer 10 provides a common growth platform for the plurality of VCSEL light-emitting units 20. The VCSEL light-emitting units 20 can generate and emit laser light. The optical modulation elements 50 can modulate the laser light to adjust the laser performance (for example, the laser emission direction, the wavelength of the laser). With the cooperation of the plurality of optical modulation elements 50, the overall divergence angle of the VCSEL chip can be expanded.

[0064] The base layer 10 can not only provide a common growth platform for the multiple VCSEL light-emitting units 20, enabling the multiple VCSEL light-emitting units 20 to be arranged in a preset arrangement, but also can provide support for the VCSEL light-emitting units 20, enhancing the overall structural strength of the VCSEL chip. In the embodiment of the present application, the base layer 10 is made of a non-conductive material. Therefore, although the base layer 10 provides a common growth platform for the multiple VCSEL light-emitting units 20, electrical isolation can still be achieved between the multiple VCSEL light-emitting units 20. Specifically, the material of the base layer 10 is selected from one of the following materials: InP, GaN, GaAs.

[0065] In a modified embodiment of the present application, the base layer 10 includes a plurality of independent sub-substrates, the multiple VCSEL light-emitting units 20 are formed on the plurality of sub-substrates, and the plurality of sub-substrates and the plurality of VCSEL light-emitting units 20 are in one-to-one correspondence. Each sub-substrate and each VCSEL light-emitting unit 20 form a single independent unit, and the multiple independent units are electrically connected to each other through electrical connection elements.

[0066] The multiple VCSEL light-emitting units 20 are divided into multiple sub-light source areas 201. Different areas of the VCSEL chip can be lit by turning on different sub-light source areas 201 to adapt to different application scenarios. For example, when a wide-angle scan of the target to be measured is required, all areas of the VCSEL chip can be lit by turning on all sub-light source areas 201. When a scan of a specific area of the target to be measured is required, a partial area of the VCSEL chip can be lit by turning on a partial light source area of all sub-light source areas 201. In this way, not only can the requirement for the scan field of the light source (VCSEL chip) in this scenario be met, but also the method of lighting a partial area of the VCSEL chip can reduce energy consumption and reduce the impact on the performance of the VCSEL chip caused by the temperature increase due to high power.

[0067] By controlling the positions of the VCSEL light-emitting units 20 to be lit in the VCSEL light-emitting unit 20, the position and shape of the light-emitting area of the VCSEL chip can be determined to adjust the scanning area of the VCSEL chip, so that the VCSEL chip can be applied to different scenarios. For example, the VCSEL light-emitting units 20 that are turned on (lit) in the VCSEL light-emitting unit 20 as a whole form a light-emitting area with a preset face shape located in the middle of the VCSEL chip, and the VCSEL chip can project laser light onto the face of the object to be detected to confirm whether the object to be detected is a preset target object. Moreover, the sub-light source areas 201 to be lit in the sub-light source area 201 can be lit simultaneously, or the sub-light source areas 201 to be lit in the sub-light source area 201 can be lit sequentially. Further, by controlling the lighting sequence of the sub-light source areas 201 to be lit in the sub-light source area 201, the lighting sequence of the light-emitting area of the VCSEL chip can be determined.

[0068] Specifically, in the embodiment of the present application, the VCSEL light-emitting unit 20 includes a light-emitting body 21, a positive electrode 22 and a negative electrode 23 electrically connected to the light-emitting body 21. The positive electrodes 22 of all the VCSEL light-emitting units 20 are electrically connected to each other to form a top electrical conduction pattern 30 of the plurality of VCSEL light-emitting units 20, and the negative electrodes 23 in a plurality of regions among all the negative electrodes 23 of the VCSEL light-emitting units 20 are electrically connected to each other (the negative electrodes 23 in each region among the plurality of regions are electrically connected to each other) to form a plurality of bottom electrical conduction patterns 40. The VCSEL light-emitting unit 20 is divided into a plurality of sub-light source areas 201 by the top electrical conduction pattern 30 and the plurality of bottom electrical conduction patterns 40. By conducting at least one of the top electrical conduction pattern 30 and the plurality of bottom electrical conduction patterns 40, at least one sub-light source area 201 corresponding to the at least one bottom electrical conduction pattern 40 can be conducted. In other words, the VCSEL light-emitting unit 20 is divided into a plurality of sub-light source areas 201 by means of cathode partitioning.

[0069] It is worth mentioning that preferably, the laser light generated by the light-emitting body 21 exits from the top of the light-emitting body 21. Correspondingly, the plurality of light modulation elements 50 are arranged on the top surface of the light-emitting body 21. During the process of the light-emitting body 21 being lit, the heat generated by the light-emitting body 21 is relatively large. Since the laser light generated by the light-emitting body 21 exits from the top of the light-emitting body 21, the temperature of the top of the light-emitting body 21 is likely to rise, and the performance of the VCSEL chip will also be easily affected. In the embodiment of the present application, partitioning the cathode of the VCSEL light-emitting unit 20 is beneficial to the heat dissipation of the light-emitting body 21 and is also beneficial to reducing the wiring difficulty.

[0070] In the embodiment of the present application, the VCSEL light-emitting unit 20 is partitioned by cathode partitioning, so that the partition wiring structure (for example, the negative electrode, the electrical connection line connected to the negative electrode 23) effectively avoids the laser emission path of the light-emitting body 21. On the one hand, it can avoid the partition wiring structure surrounding the laser generation area and the laser emission area of ​​the light-emitting body 21 as much as possible to affect the heat dissipation of the light-emitting body 21, thereby affecting the performance of the VCSEL chip. On the other hand, it can reduce the difficulty of partition wiring and improve the design flexibility of partition wiring.

[0071] Specifically, in the embodiment of the present application, the light-emitting body 21 includes, from bottom to top, an N-type electrical contact layer 211, an N-DBR layer 212, an active region 213, a limiting layer 214, a P-DBR layer 215, and a P-type electrical contact layer 216, wherein the limiting layer 214 has a limiting hole 202 corresponding to the active region 213, and the N-DBR layer 212 and the P-DBR layer 215 are configured such that after the VCSEL light-emitting unit 20 is turned on, the laser light generated by the active region 213 is reflected multiple times in the resonant cavity formed between the N-DBR layer 212 and the P-DBR layer 215 and then emitted from the P-DBR layer 215. The top surface of the P-type electrical contact layer 216 is the top surface of the light-emitting body 21, and the light modulation element 50 is formed on the P-type electrical contact layer 216. It should be understood that the light modulation element 50 may also be formed at other locations of the light emitting body 21 above the P-DBR layer 215 , for example, formed on the upper surface of the P-DBR layer 215 .

[0072] More specifically, the N-DBR layer 212 is composed of N-type doped Al with a high aluminum content. x Ga 1-x As (x = 1 ~ 0) and N-type doped low aluminum content Al x Ga 1-x The P-DBR layer 215 is formed by alternating layers of As (x=1-0). x Ga 1-x As (x = 1 ~ 0) and P-type doped low aluminum content Al x Ga 1-x As (x = 1 to 0) is formed. In some examples of the present application, the material of the N-DBR layer 212 and the P-DBR layer 215 may not even have an aluminum content, that is, it does not contain aluminum. It is worth mentioning that the material selection of the alternating layer depends on the operating wavelength of the laser emitted by the VCSEL light emitting unit 20, and the optical thickness of the alternating layer is equal to or approximately equal to 1 / 4 of the operating wavelength of the laser.

[0073] The active region 213 is sandwiched between the N-DBR layer 212 and the P-DBR layer 215 to form a resonant cavity. When photons are excited, they reflect back and forth in the resonant cavity and are continuously amplified to form a laser oscillation, thus forming a laser. Those of ordinary skill in the art should know that the emission direction of the laser can be selectively controlled by configuring and designing the N-DBR layer 212 and the P-DBR layer 215. For example, it can be emitted from the N-DBR layer 212, or from the P-DBR layer 215. As mentioned above, in the embodiment of the present application, after the VCSEL light-emitting unit 20 is turned on, the laser generated by the active region 213 is reflected multiple times in the resonant cavity formed between the N-DBR layer 212 and the P-DBR layer 215 and then emitted from the P-DBR layer 215.

[0074] In the embodiment of the present application, the confinement layer 214 has a confinement hole 202 corresponding to the active region 213. After the laser generated by the active region 213 is reflected multiple times in the resonant cavity and passes through the confinement hole 202, it is emitted from the P-DBR layer 215 of the VCSEL light-emitting unit 20.

[0075] In some examples of the present application, the confinement layer 214 can be implemented as an oxidation confinement layer, which is formed above the active region 213 through an oxidation process. In a specific implementation, the oxidation confinement layer can be formed as a separate layer above the active region 213. Of course, in other specific implementation schemes, the oxidation confinement layer can also be formed above the active region 213 by oxidizing at least a part of the region below the P-DBR layer 215. The present application is not limited thereto. In other examples of the present application, the confinement layer 214 can also be implemented in other forms. For example, it can be implemented as an ion confinement layer (not shown in the figure), which is formed above the active region 213 through an ion implantation process. The present application is not limited thereto.

[0076] In the embodiment of the present application, the positive electrode 22 includes a light hole element 221 formed on the light-emitting body 21 and a first electrically conductive layer 222 covering the light hole element 221. The light hole element 221 forms a light-emitting hole 203 corresponding to the confinement hole 202, and the first electrically conductive layers 222 of all the VCSEL light-emitting units 20 are integrally connected to form the top electrically conductive pattern 30.

[0077] When the laser exits from the P-DBR layer 215 of the VCSEL light-emitting unit 20, in order to ensure the performance of the laser emitted by the VCSEL light-emitting unit 20, an opening can be provided on the first electrically conductive layer 222, so that the laser exiting from the P-DBR layer 215 passes through the opening on the first electrically conductive layer 222 and then is emitted. Accordingly, in a specific example of the present application, the first electrically conductive layer 222 has at least one opening, and the opening corresponds to the light-emitting hole 203. Optionally, a light-transmissive material can be used to prepare the first electrically conductive layer 222. Accordingly, in another specific example of the present application, the first electrically conductive layer 222 is made of a light-transmissive conductive material.

[0078] In the embodiment of the present application, the positive electrode 22 is formed on the P-type electrical contact layer 216 of the light-emitting body 21, and the negative electrode 23 is formed on the N-type electrical contact layer 211 of the light-emitting body 21. The specific positions of the positive electrode 22 and the negative electrode 23 are not limited by the present application. In a specific example of the present application, the positive electrode 22 is formed on the upper surface of the N-type electrical contact layer 211, wherein the light hole element 221 is formed on the upper surface of the N-type electrical contact layer 211, and the first electrically conductive layer 222 covers the light hole element 221, as Figure 2 shown. In a specific example of the present application, the negative electrode 23 is formed between the base layer 10 and the light-emitting body 21. In another specific example of the present application, the negative electrode 23 is formed on the side surface of the N-type electrical contact layer 211 of the light-emitting body 21.

[0079] In a modified embodiment of the present application, the negative electrode 23 is led out from the N-type electrical contact layer 211 to the bottom of the base layer 10. Specifically, the negative electrode 23 includes a second electrically conductive layer 232 and a lead-out element 231 electrically connected between the second electrically conductive layer 232 and the N-type electrical contact layer 211, as Figure 3 shown, and in this way, the negative electrode 23 is led out from the N-type electrical contact layer 211.

[0080] It is worth mentioning that leading the negative electrode 23 out from the N-type electrical contact layer 211 to the bottom of the base layer 10 facilitates arranging the second electrical conduction layer 232 and the partitioned wiring structure orderly at the bottom of the base layer 10. By this way, the distribution between the second electrical conduction layer 232 and the partitioned wiring structure is regulated, thereby reducing the probability of mutual stacking, entanglement, and chaos among the partitioned wiring structures, reducing the difficulty of partitioned wiring, and improving the accuracy of partitioned wiring. Moreover, the base layer 10 can serve as a good heat dissipation platform and heat insulation platform, which is beneficial to the heat dissipation of structures such as the negative electrode 23 and the partitioned wiring structure, and at the same time is beneficial to isolating the heat of the laser generation area and the laser generation area from the heat of structures such as the negative electrode 23 and the partitioned wiring structure.

[0081] It is also worth mentioning that in order to achieve electrical isolation between the multiple VCSEL light-emitting units 20, in a specific example of the present application, an isolation groove 205 can be provided between every two of the VCSEL light-emitting units 20. That is to say, the VCSEL chip has a plurality of isolation grooves 205 formed between every two of the VCSEL light-emitting units 20. Specifically, each isolation groove 205 extends downwardly through the P-type electrical contact layer 216 to the N-type electrical contact layer 211, so that the multiple VCSEL light-emitting units 20 are electrically isolated from each other through the plurality of isolation grooves 205.

[0082] In other examples of the present application, electrical isolation between the multiple VCSEL light-emitting units 20 can also be achieved by other means, and this is not limited to the present application. In another specific example of the present application, the VCSEL chip further includes a plurality of isolation dielectric channels located between every two of the VCSEL light-emitting units 20 and doped and formed in the light-emitting body 21 of each of the VCSEL light-emitting units 20, so that the multiple VCSEL light-emitting units 20 are electrically isolated from each other through the plurality of isolation dielectric channels.

[0083] In the embodiment of the present application, not only can different sub-light source areas 201 be turned on to light different areas of the VCSEL chip to adapt to different application scenarios, but also, in cooperation with the optical modulation element 50, the overall divergence angle of the VCSEL chip can be adjusted to adapt to different application scenarios. Specifically, the multiple optical modulation elements 50 have a preset structural configuration and are distributed in a preset distribution manner in the multiple sub-light source areas 201, so as to control the overall divergence angle of the VCSEL chip by regulating the position of the lit sub-light source area 201 in the multiple sub-light source areas 201.

[0084] The multiple optical modulation elements 50 are integrally arranged at the laser emission paths of at least some of the multiple VCSEL light-emitting units 20 at the wafer level. Therefore, the laser emitted by the VCSEL light-emitting units 20 can be modulated by the optical modulation elements 50 to control the laser projection direction of the VCSEL chip, and further regulate the overall divergence angle of the VCSEL chip. When a wide-angle scan of the target to be measured is required, the overall divergence angle of the VCSEL chip can be increased by designing the structure and position of the optical modulation elements 50 located in the illuminated area. Quantitatively, in the embodiments of the present application, the overall divergence angle of the VCSEL chip is greater than or equal to 120°. Here, the overall divergence angle of the VCSEL chip refers to the included angle formed by the outermost lasers among the lasers emitted by the VCSEL chip. In a specific example of the present application, the overall divergence angle of the VCSEL chip can reach 180°. When a scan of a specific area of the target to be measured is required, the overall divergence angle of the VCSEL chip can be reduced by designing the structure and position of the optical modulation elements 50 located in the illuminated area.

[0085] In a specific example of the present application, the multiple optical modulation elements 50 include at least one modulation element for converging light (e.g., convex lens 51) and at least one modulation element for diverging light (e.g., concave lens 52). The convex lens 51 can reduce the beam divergence angle of the laser emitted from the VCSEL light-emitting unit 20, and the concave lens 52 can increase the beam divergence angle of the laser emitted from the VCSEL light-emitting unit 20. It should be understood that in other examples of the present application, the multiple optical modulation elements 50 may only include a modulation element for converging light (e.g., convex lens 51), or only include a modulation element for diverging light (e.g., concave lens 52), and this is not limited to the present application.

[0086] The overall divergence angle or the scanning range of the VCSEL chip can be regulated by adjusting the dimming characteristics of the optical modulation elements 50 (e.g., converging light, diverging light) and the distribution positions of the optical modulation elements 50 with different dimming characteristics.

[0087] When all areas of the VCSEL chip are lit, by disposing the concave lens 52 on at least a part of the VCSEL light-emitting units 20 on the outermost side of the VCSEL chip, the divergence angle of the light beam emitted from the VCSEL light-emitting units 20 can be relatively increased, and further, the overall divergence angle of the VCSEL chip can be increased. By disposing the convex lens 51 on at least a part of the VCSEL light-emitting units 20 on the outermost side of the VCSEL chip, the divergence angle of the light beam emitted from the VCSEL light-emitting units 20 can be relatively reduced, and further, the overall divergence angle of the VCSEL chip can be decreased.

[0088] When a partial area of the VCSEL chip is lit, by disposing the concave lens 52 on at least a part of the VCSEL light-emitting units 20 in this partial area of the VCSEL chip, the divergence angle of the light beam emitted from the VCSEL light-emitting units 20 can be relatively increased, and further, the overall divergence angle of the VCSEL chip can be increased. By disposing the convex lens 51 on at least a part of the VCSEL light-emitting units 20 in this partial area of the VCSEL chip, the divergence angle of the light beam emitted from the VCSEL light-emitting units 20 can be relatively reduced, and further, the overall divergence angle of the VCSEL chip can be decreased to perform concentrated irradiation on a specific area of the target to be measured.

[0089] In a specific example of the present application, the convex lens 51 is disposed on the VCSEL light-emitting units 20 in the middle area of the VCSEL chip, and the concave lens 52 is disposed on the VCSEL light-emitting units 20 in the peripheral area of the VCSEL chip. Correspondingly, in this specific example, at least a part of the concave lens 52 is distributed in the outer sub-light source areas 201 adjacent to the edge of the VCSEL chip among the plurality of sub-light source areas 201, and at least a part of the convex lens 51 is distributed in the inner sub-light source areas 201 at least partially located in the middle area of the VCSEL chip among the plurality of sub-light source areas 201. The scanning domains of the lasers emitted from different areas of the VCSEL chip are different, and the overall divergence angle or scanning domain of the VCSEL chip changes with the change of the scanning domains of the lasers emitted from different areas.

[0090] Furthermore, the divergence angle or scanning domain of the laser emitted from a single VCSEL light-emitting unit 20 can be controlled by adjusting the curvature of the convex lens 51 and / or the concave lens 52, and further, the overall divergence angle or scanning domain of the VCSEL chip can be controlled.

[0091] In the embodiments of the present application, the curvature radii of at least a part of the convex lenses 51 (or the concave lenses 52) are different. The greater the curvature of the convex lens 51, the smaller the curvature radius, and the stronger the ability to converge light. The greater the curvature of the concave lens 52, the smaller the curvature radius, and the stronger the ability to diverge light. The smaller the curvature radius of the convex lens 51 corresponding to the outermost VCSEL light-emitting unit 20 of the VCSEL chip, the smaller the overall divergence angle of the VCSEL chip. The smaller the curvature radius of the concave lens 52 corresponding to the outermost VCSEL light-emitting unit 20 of the VCSEL chip, the greater the overall divergence angle of the VCSEL chip. Of course, the curvature radii of all the convex lenses 51 or concave lenses 52 configured for the multiple VCSEL light-emitting units 20 may be the same, and this is not limited by the present application.

[0092] In a specific example of the present application, in the direction extending outward from the center of the VCSEL chip, the curvature of the concave lenses 52 provided on the multiple VCSEL light-emitting units 20 increases in sequence. Correspondingly, in the direction extending outward from the center of the VCSEL chip, the divergence angles of the multiple VCSEL light-emitting units 20 increase in sequence, not only making the overall divergence angle of the VCSEL chip relatively large, but also making the laser light emitted by the multiple VCSEL light-emitting units 20 form a continuous scanning field.

[0093] Furthermore, the divergence angle of the laser light emitted from a single VCSEL light-emitting unit 20 can be controlled by the relative positional relationship between the optical modulation element 50 and the corresponding light-emitting body 21, and then the overall divergence angle of the VCSEL chip can be controlled.

[0094] In a specific example of the present application, a part of the convex lenses 51 of the multiple optical modulation elements 50 and the corresponding light-emitting bodies 21 are arranged concentrically, and another part of the convex lenses 51 and the corresponding light-emitting bodies 21 are arranged eccentrically. A part of the concave lenses 52 of the multiple optical modulation elements 50 and the corresponding light-emitting bodies 21 are arranged concentrically, and another part of the concave lenses 52 and the corresponding light-emitting bodies 21 are arranged eccentrically.

[0095] Specifically, both the convex lens 51 and the concave lens 52 have optical centers, and the propagation path of the light passing through the optical centers remains unchanged. The extension line of the central axis of the active region 213 forms the optical axis of the light-emitting body 21. When the optical center of the convex lens 51 (or the concave lens 52) lies on the straight line where the optical axis set by the light-emitting body 21 is located, it is regarded that the optical center of the convex lens 51 (or the concave lens 52) is aligned with the center of the light-emitting body 21, that is, the convex lens 51 (or the concave lens 52) is arranged concentrically with the light-emitting body 21. When the optical center of the convex lens 51 (or the concave lens 52) does not lie on the straight line where the optical axis of the light-emitting body 21 is located, it is regarded that the optical center of the convex lens 51 (or the concave lens 52) is not aligned with the center of the light-emitting body 21, that is, the convex lens 51 (or the concave lens 52) is arranged eccentrically with the light-emitting body 21.

[0096] When the convex lens 51 (or the concave lens 52) is arranged eccentrically with the light-emitting body 21, after the laser light emitted from the light-emitting body 21 is modulated by the convex lens 51 (or the concave lens 52), its projection direction deviates in the direction in which the optical center of the convex lens 51 (or the concave lens 52) deviates from the optical axis of the light-emitting body 21.

[0097] Specifically, when the optical center of the convex lens 51 (or the concave lens 52) corresponding to the outermost VCSEL light-emitting unit 20 of the VCSEL chip shifts outward, compared with the case where the convex lens 51 (or the concave lens 52) is arranged concentrically with the light-emitting body 21, the laser projection direction deviates outward, and the overall divergence angle of the VCSEL chip relatively increases.

[0098] It should be understood that in other examples of the present application, all of the convex lenses 51 of the plurality of light modulation elements 50 and the corresponding light-emitting bodies 21 may be arranged concentrically or all arranged eccentrically. All of the concave lenses 52 and the corresponding light-emitting bodies 21 may also be arranged concentrically or all arranged eccentrically. This is not limited to the present application.

[0099] It is worth mentioning that the divergence angle or the scanning range of the VCSEL chip can also be controlled by combining the structure of the light modulation element 50 (for example, lens type, lens curvature) and the relative positional relationship between the light modulation element 50 and the corresponding light-emitting body 21.

[0100] When the optical center of the convex lens 51 corresponding to the outermost VCSEL light-emitting unit 20 of the VCSEL chip shifts outward, the smaller the curvature of the convex lens 51, the more outward the direction of the laser projection deviates, and the larger the overall divergence angle of the VCSEL chip. The overall divergence angle of the VCSEL chip can be adjusted according to the modulation law of the laser by the cooperation of the structure of the dimming element and the relative positional relationship between the optical modulation element 50 and the corresponding light-emitting body 21.

[0101] It should be understood that, compared with controlling the laser projection range of the VCSEL light source by rotating the VCSEL chip through a driving device (such as a rotating motor), the method of setting the optical modulation element 50 on at least part of the VCSEL light-emitting units 20 of the VCSEL chip can control the laser projection range of the VCSEL chip relatively more stably. At the same time, the overall divergence angle increased by the VCSEL chip through its own structure can simplify the solution for expanding the laser projection range of the VCSEL light source and reduce its application cost.

[0102] It is worth mentioning that, in the embodiment of the present application, the VCSEL chip further includes an addressing circuit structure (not shown in the figure) electrically connected to the multiple VCSEL units. The addressing circuit structure forms the addressing circuit of the multiple VCSEL units, and the VCSEL light-emitting units 20 that are lit among the multiple VCSEL light-emitting units 20 can be controlled through the addressing circuit formed by the addressing circuit structure to achieve the zoned lighting of the VCSEL chip.

[0103] Specifically, the addressing circuit structure includes multiple electrical connection lines. Among them, each electrical connection line is electrically connected to at least two bottom electrical conduction patterns 40 among the multiple bottom electrical conduction patterns 40. In this way, the addressing circuit structure forms the addressing circuit of the multiple VCSEL units so that any one of the sub-light source areas 201 is suitable for achieving electrical conduction by simultaneously conducting at least one electrical connection line among the multiple electrical connection lines and the top electrical conduction pattern. The addressing circuit structure of the VCSEL chip cooperates with the semiconductor structure 100 design of the VCSEL chip, so that the VCSEL chip realizes the zoned lighting function with a relatively simplified wiring structure.

[0104] In a specific example of the present application, each electrical connection line is electrically connected to at least two bottom electrical conduction patterns 40 in the same column among the multiple bottom electrical conduction patterns, and there is no need to configure an electrical connection line for each bottom electrical conduction pattern 40. In this way, the wiring structure can be relatively simplified.

[0105] In summary, the VCSEL chip based on the embodiments of the present application is described. The VCSEL chip increases its overall divergence angle through its own structural design to expand the scanning area of the VCSEL chip. Moreover, the VCSEL chip reduces the influence of partition wiring on the light-emitting performance of the multiple VCSEL light-emitting units 20 by means of cathode partitioning. At the same time, it can reduce the difficulty of partition wiring and meet the performance requirements of the VCSEL chip in terms of heat dissipation.

[0106] Preparation Method of Schematic VCSEL Chip

[0107] According to another aspect of the present application, a method for manufacturing a VCSEL chip is also provided, which is used to manufacture the VCSEL chip as described above. Referring to the accompanying drawings of the specification Figures 4 to 5C , the method for manufacturing a VCSEL chip according to the embodiments of the present application is described. As Figure 4 shown, the method for manufacturing the VCSEL chip according to the embodiments of the present application includes: S110, forming a semiconductor structure, which sequentially includes a substrate structure, a bottom conductive layer structure, an N-type electrical contact structure, an N-DBR structure, an active region structure, a P-DBR structure, a P-type electrical contact structure, and a layer to be processed from bottom to top; S120, processing the layer to be processed through an etching process to form multiple light modulation elements above the P-type electrical contact structure to obtain a chip semi-finished product; S130, forming multiple light-emitting hole structures electrically connected to the P-type electrical contact structure of the semiconductor structure, wherein the multiple light-emitting hole structures define multiple light-emitting holes; S140, removing at least a part of the chip semi-finished product to form multiple sub-structure units that are electrically isolated from each other, and each sub-structure unit includes an N-type electrical contact layer, an N-DBR layer, an active region, a P-DBR layer, and a P-type electrical contact layer from bottom to top; S150, removing at least a part of the bottom conductive layer structure to form multiple bottom electrical conduction patterns that are electrically isolated from each other; S160, processing the multiple sub-structure units forming the bottom electrical conduction patterns to form a confinement layer with confinement holes above the active region, and the confinement holes correspond to the light-emitting holes; and S170, forming a second electrical conduction layer covering all the light-emitting hole structures to form a top electrical conduction pattern.

[0108] Figures 5A to 5C Illustrates a schematic diagram of the manufacturing process of the VCSEL chip according to the embodiments of the present application. As Figure 5AAs shown, in step S110, a semiconductor structure 100 is formed. Specifically, the substrate structure 110, the bottom conductive layer structure 120 stacked on the substrate structure 110, the N-type electrical contact structure 130, the N-DBR structure 140, the active region structure 150, the P-DBR structure 160, the P-type electrical contact structure 170, and the layer to be processed 180 are formed by a semiconductor growth process.

[0109] In a specific example of the present application, the substrate structure 110 is made of a non-conductive material, and the substrate structure 110 is non-conductive. The material of the substrate structure 110 is selected from one of the following materials: InP, GaN, GaAs. The material of the layer to be processed 180 is selected from one of the following: GaN, AlN, Al X Ga 1-X As (x = 0 to 1), lnP, Al X Ga 1-X AsSb (x = 0 to 1), AlInAs, InGaAsP.

[0110] In step S120, the layer to be processed 180 is processed by an etching process to form a plurality of optical modulation elements 50 above the P-type electrical contact structure 170 to obtain a chip semi-finished product 200. Specifically, first, an etchable layer 600 is applied on the layer to be processed 180. Among them, the material of the etchable layer 600 can be a photoresist layer. Then, the etchable layer 600 is exposed through a mask 700 with a preset pattern to remove the corresponding part of the etchable layer 600 based on the preset pattern. Among them, the remaining etchable layer 600 forms a template 800 with a preset shape and size, and the preset shape and size of the template 800 are consistent with the shape and size of the optical modulation element 50. Then, at least a part of the template 800 and the layer to be processed 180 is removed by an etching process. Among them, the remaining layer to be processed 180 has the same shape and size as the template 800 to form the plurality of optical modulation elements 50, and the plurality of optical modulation elements 50 include a convex lens 51 and a concave lens 52.

[0111] That is to say, step S120 includes: applying an etchable layer 600 on the layer to be processed 180; shaping the etchable material into a template 800 with a preset shape and size through a mask 700, where the preset shape and size of the template 800 are consistent with the shape and size of the optical modulation element 50; and removing at least a part of the template 800 and the layer to be processed 180 by an etching process, where the remaining layer to be processed 180 has the same shape and size as the template 800 to form the plurality of optical modulation elements 50.

[0112] Specifically, a dry etching process or a wet etching process can be used to remove a part of the template 800 and the layer to be processed 180. Correspondingly, the remaining layer to be processed 180 has the same shape and size as the template 800 to form the optical modulation element 50. During the etching process, in order to ensure that the finally remaining layer to be processed 180 has the same shape and size as the template 800, the etching speed and the etching area should be precisely controlled.

[0113] It is worth mentioning that during the process of removing a part of the layer to be processed 180 by the etching process, at least a part of the P-type electrical contact structure 170 is exposed to form an electrical connection area enabling electrical connection. Correspondingly, the semiconductor structure 100 after being processed by the etching process forms the chip semi-finished product 200, where the chip semi-finished product 200 sequentially includes the substrate structure 110, the bottom conductive layer structure 120, the N-type electrical contact structure 130, the N-DBR structure 140, the active region structure 150, the P-DBR structure 160, the P-type electrical contact structure 170, and the optical modulation element 50 from bottom to top.

[0114] It is worth mentioning that the overall divergence angle of the finally formed VCSEL chip can be regulated by designing the structure and position of the optical modulation element 50. For example, in a specific example of the present application, at least one concave lens 52 is arranged in the region near the outer edge of the semiconductor structure 100 to expand the overall divergence angle of the finally formed VCSEL chip, and at least one convex lens 51 is arranged in a local region of the semiconductor structure 100 to reduce the overall divergence angle of the VCSEL chip when the local region is lit.

[0115] In step S130, a plurality of optical hole elements 221 electrically connected to the P-type electrical contact structure 170 of the semiconductor structure 100 are formed. Specifically, a plurality of optical hole elements 221 electrically connected to the P-type electrical contact structure 170 of the semiconductor structure 100 are formed by an electroplating process, where the plurality of optical hole elements 221 are formed in the electrical connection area of the P-type electrical contact structure 170 of the chip semi-finished product 200. It should be understood that the plurality of optical hole elements 221 can also be formed in the chip semi-finished product 200 by other processes, and this is not limited by the present application. It should also be understood that the plurality of optical hole elements 221 can also be formed at other positions of the chip semi-finished product 200, and this is not limited by the present application.

[0116] Preferably, in order to ensure the light-emitting performance of the VCSEL chip, the shape of the optical aperture element 221 electrically connected to the P-type electrical contact structure 170 is annular, and the plurality of optical aperture elements 221 define a plurality of light-emitting apertures 203. The optical aperture elements 221 are formed around the optical modulation element 50 in a surrounding manner. Correspondingly, the optical modulation element 50 corresponds to the light-emitting apertures 203 of the optical aperture elements 221 to adjust the overall divergence angle of the VCSEL chip and expand the scanning area (i.e., the laser projection range) of the VCSEL chip.

[0117] As Figure 5B shown, in step S140, at least a part of the chip semi-finished product 200 is removed to form a plurality of sub-structure units 300 that are electrically isolated from each other. Each of the sub-structure units 300 includes an N-type electrical contact layer 211, an N-DBR layer 212, an active region 213, a P-DBR layer 215, and a P-type electrical contact layer 216 from bottom to top. Specifically, at least a part of the chip semi-finished product 200 is removed through an etching process to form a plurality of sub-structure units 300 that are separated from each other. An isolation groove 205 is formed in the interval region between every two sub-structure units 300, so that electrical isolation is achieved between the plurality of sub-structure units 300.

[0118] In step S150, at least a part of the bottom conductive layer structure 120 is removed to form a plurality of bottom electrical conduction patterns 40 that are electrically isolated from each other. Specifically, at least a part of the bottom conductive layer structure 120 is removed through an etching process to form a plurality of bottom electrical conduction patterns 40 that are electrically isolated from each other, thereby forming a negative electrode 23. Among them, each of the plurality of bottom electrical conduction patterns 40 is electrically connected to at least one of the sub-structure units 300.

[0119] In the embodiment of the present application, realizing cathode partitioning at the wafer level can reduce the partitioning difficulty. Moreover, the bottom electrical conduction patterns 40 are arranged on the side opposite to the light-emitting side of the VCSEL chip, which can reduce the influence of partitioning wiring on the light-emitting performance of the VCSEL chip and, at the same time, can reduce the difficulty of partitioning wiring.

[0120] As Figure 5CAs shown, in step S160, a plurality of sub-structure units 300 forming the bottom electrical conduction pattern 40 are processed to form a confinement layer 214 having confinement holes 202 above the active region 213. Specifically, the confinement layer 214 can be formed by an oxidation process. First, in order to protect the light hole element 221 and the plurality of bottom electrical conduction patterns 40, a protective layer covering the light hole element 221 and the plurality of bottom electrical conduction patterns 400 needs to be formed before oxidizing the sub-structure units 300. Then, the plurality of sub-structure units 300 are oxidized. After the sub-structure units 300 are oxidized, a part of the P-DBR layer 215 is oxidized to form the confinement layer 214 above the active region 213. Among them, after the confinement layer 214 is formed, the plurality of sub-structure units 300 form a plurality of light-emitting bodies 21, and the confinement holes 202 correspond to the light-emitting holes 203. Then, the light hole element 221 and the plurality of bottom electrical conduction patterns 40 are exposed. Specifically, the light hole element 221 and the plurality of bottom electrical conduction patterns 40 can be exposed by removing at least a part of the protective layer covering the plurality of bottom electrical conduction patterns 40. That is to say, step S160 includes: forming a protective layer covering the light hole element 221 and the plurality of bottom electrical conduction patterns 40; oxidizing the plurality of sub-structure units 300; and exposing the light hole element 221 and the plurality of bottom electrical conduction patterns 40.

[0121] It is worth mentioning that the confinement layer 214 can be formed by other processes. For example, an ion confinement layer above the active region 213 can be formed by an ion implantation process, and this is not limited to the present application.

[0122] Correspondingly, after the confinement layer 214 is formed, the plurality of sub-structure units 300 form a plurality of light-emitting bodies 21, and each light-emitting body 21 includes, from bottom to top, the N-type electrical contact layer 211, the N-DBR layer 212, the active region 213, the confinement layer 214, the P-DBR layer 215, and the P-type electrical contact layer 216.

[0123] In step S170, a second electrically conductive layer 232 covering all the optical hole elements 221 is formed to form a top electrically conductive pattern 30. Specifically, a first electrically conductive layer 222 covering the plurality of optical hole elements 221 is formed, and the first electrically conductive layer 222 and the optical hole elements 221 form a positive electrode 22. The first electrically conductive layer 222 is of an integral structure and is electrically connected to each of the light-emitting bodies 21. The plurality of light-emitting bodies 21, the plurality of positive electrodes 22, and the plurality of negative electrodes 23 together form a plurality of VCSEL light-emitting units 20. Moreover, the plurality of VCSEL light-emitting units 20 are divided into a plurality of sub-light source regions 201 by the top electrically conductive pattern 30 and the plurality of bottom electrically conductive patterns 40. By simultaneously conducting the top electrically conductive pattern 30 and at least one of the bottom electrically conductive patterns 40, the sub-light source region 201 corresponding to the at least one bottom electrically conductive pattern 40 can be conducted.

[0124] When the laser exits from the P-DBR layer 215 of the VCSEL light-emitting unit 20, in order to ensure the performance of the laser emitted by the VCSEL light-emitting unit 20, a light-transmissive material can be selected to prepare the first electrically conductive layer 222. That is, in a specific example of the present application, the first electrically conductive layer 222 electrically connected to the light-emitting body 21 is made of a light-transmissive conductive material. Openings can also be provided in the first electrically conductive layer 222 so that the laser exiting from the P-DBR layer 215 is emitted after passing through the openings. That is, in another specific example of the present application, the first electrically conductive layer 222 has at least one opening corresponding to the light-emitting hole 203.

[0125] In a specific example of the present application, the VCSEL chip realizes the addressing function through a relatively simplified wiring method. Correspondingly, the preparation method of the VCSEL chip further includes: S180, forming an addressing circuit structure electrically connected to the plurality of VCSEL units. The addressing circuit structure includes a plurality of electrical connection lines. Among them, each electrical connection line is electrically connected to at least two of the plurality of bottom electrically conductive patterns 40. In this way, the addressing circuit structure forms an addressing circuit for the plurality of VCSEL units so that any one of the sub-light source regions 201 is adapted to be electrically conducted by simultaneously conducting at least one of the plurality of electrical connection lines and the top electrically conductive pattern 30.

[0126] In summary, the method for manufacturing a VCSEL chip according to the embodiments of the present application is elucidated. The method for manufacturing the VCSEL chip relatively regulates the overall divergence angle thereof by designing the structure of the VCSEL chip, so as to expand the scanning field of the VCSEL chip. Moreover, the method for manufacturing the VCSEL chip reduces the influence of partition wiring on the light-emitting performance of the multiple VCSEL chips by means of cathode partitioning. Meanwhile, the difficulty of partition wiring can be reduced and the performance requirements of the VCSEL chip in terms of heat dissipation can be met.

[0127] Schematic Automotive LiDAR

[0128] According to another aspect of the present application, a vehicle-mounted lidar is further provided. The working principle of the lidar is as follows: using laser as a medium, laser is emitted to the target to be measured, and the laser reflected by the target to be measured is received. Based on the time difference between the emitted laser and the received laser pulse (or the phase difference between the emitted laser and the reflected laser), the relative position and distance between the target to be measured and the lidar are obtained, so as to realize the detection, tracking and identification of the object to be measured in the target area.

[0129] Correspondingly, the vehicle-mounted lidar includes: a laser projection device 510 for projecting laser, wherein the laser projection device is implemented as the VCSEL chip as described above, a laser reception device 520 for receiving laser signals, and a processor 530 communicatively connected to the laser projection device and the laser reception device. The specific structure and function of the VCSEL chip have been described in detail in the description of the VCSEL chip above with reference to Figures 1 to 5C and thus, the repeated description thereof will be omitted.

[0130] The basic principles of the present application have been described above in conjunction with specific embodiments. However, it should be noted that the advantages, benefits, effects, etc. mentioned in the present application are only examples and not limitations, and it cannot be considered that these advantages, benefits, effects, etc. are essential for each embodiment of the present application. In addition, the above-disclosed specific details are only for the purposes of illustration and easy understanding, rather than limitations, and the above details do not limit the present application to necessarily adopt the above specific details for implementation.

Claims

1. A VCSEL chip, characterized in that, Comprising: A base layer; A plurality of VCSEL units formed on the base layer and isolated from each other. Each of the VCSEL light-emitting units includes a light-emitting body, a positive electrode and a negative electrode electrically connected to the light-emitting body. All the positive electrodes of the VCSEL light-emitting units are electrically connected to each other to form a top electrical conduction pattern of the plurality of VCSEL light-emitting units. A plurality of negative electrodes in a plurality of regions among all the negative electrodes of the VCSEL light-emitting units are electrically connected to each other to form a plurality of bottom electrical conduction patterns. The plurality of VCSEL light-emitting units are divided into a plurality of sub-light source regions by the top electrical conduction pattern and the plurality of bottom electrical conduction patterns; and A plurality of optical modulation elements integrally provided at the wafer level on the plurality of VCSEL light-emitting units. The plurality of optical modulation elements have a preset structural configuration and are arranged on the laser projection paths of the plurality of sub-light source regions according to a preset pattern to control the position of the lit sub-light source regions among the plurality of sub-light source regions and regulate the overall divergence angle of the VCSEL chip under the action of the plurality of optical modulation elements.

2. The VCSEL chip according to claim 1, further comprising: An addressing circuit structure electrically connected to the plurality of VCSEL units. The addressing circuit structure includes a plurality of electrical connection lines. Each of the electrical connection lines is electrically connected to at least two of the plurality of bottom electrical conduction patterns. In this way, the addressing circuit structure forms an addressing circuit of the plurality of VCSEL units so that any one of the sub-light source regions is adapted to achieve electrical conduction by simultaneously conducting at least one of the plurality of electrical connection lines and the top electrical conduction pattern.

3. The VCSEL chip according to claim 2, wherein, The laser generated by the light-emitting body exits from the top of the light-emitting body, and the plurality of optical modulation elements are arranged on the top surface of the light-emitting body.

4. The VCSEL chip according to claim 3, wherein, The light-emitting body sequentially includes, from bottom to top: an N-type electrical contact layer, an N-DBR layer, an active region, a confinement layer, a P-DBR layer, and a P-type electrical contact layer. The confinement layer has a confinement hole corresponding to the active region. The N-DBR layer and the P-DBR layer are configured such that after the VCSEL light-emitting unit is turned on, the laser generated by the active region is reflected multiple times in a resonant cavity formed between the N-DBR layer and the P-DBR layer and exits from the P-DBR layer. The optical modulation element is formed on the P-type electrical contact layer.

5. The VCSEL chip according to claim 4, wherein, The positive electrode includes a light-emitting hole structure electrically connected to the light-emitting body and a first electrical conduction layer covering the light-emitting hole structure. The light-emitting hole structure forms a light-emitting hole corresponding to the confinement hole. The first electrical conduction layers of all the VCSEL light-emitting units are integrally connected to form the top electrical conduction pattern.

6. The VCSEL chip according to claim 5, wherein, The first electrical conduction layer has at least one opening corresponding to the light-emitting hole.

7. The VCSEL chip according to claim 5, wherein The first electrical conduction layer is made of a light-transmissive conductive material.

8. The VCSEL chip according to claim 4, wherein, The negative electrode is led out from the N-type electrical contact layer to the bottom of the base layer.

9. The VCSEL chip according to claim 1, wherein, The plurality of optical modulation elements include at least one convex lens and at least one concave lens.

10. The VCSEL chip according to claim 9, wherein, At least part of the concave lens is distributed in the outer sub-light source regions adjacent to the edge of the VCSEL chip among the plurality of sub-light source regions.

11. The VCSEL chip according to claim 10, wherein, At least part of the convex lens is distributed in the inner sub-light source regions at least partially located in the middle region of the VCSEL chip among the plurality of sub-light source regions.

12. The VCSEL chip according to claim 1, wherein, The plurality of optical modulation elements have a preset structural configuration and cooperate with each other to make the overall divergence angle of the VCSEL chip greater than or equal to 120°.

13. A method for preparing a VCSEL chip, characterized in that, Comprising: Forming a semiconductor structure, which sequentially includes a substrate structure, a bottom conductive layer structure, an N-type electrical contact structure, an N-DBR structure, an active region structure, a P-DBR structure, a P-type electrical contact structure, and a layer to be processed from bottom to top; Processing the layer to be processed through an etching process to form a plurality of optical modulation elements above the P-type electrical contact structure to obtain a chip semi-finished product; Forming a plurality of light-emitting hole structures electrically connected to the P-type electrical contact structure of the semiconductor structure, wherein the plurality of light-emitting hole structures define a plurality of light-emitting holes; Removing at least a part of the chip semi-finished product to form a plurality of sub-structure units that are electrically isolated from each other, and each sub-structure unit includes an N-type electrical contact layer, an N-DBR layer, an active region, a P-DBR layer, and a P-type electrical contact layer from bottom to top; Removing at least a part of the bottom conductive layer structure to form a plurality of bottom electrical conduction patterns that are electrically isolated from each other; Processing the plurality of sub-structure units forming the bottom electrical conduction patterns to form a confinement layer with confinement holes above the active region, and the confinement holes correspond to the light-emitting holes; and Forming a second electrical conduction layer covering all the light-emitting hole structures to form a top electrical conduction pattern.

14. The manufacturing method of the VCSEL chip according to claim 13, wherein, Processing the plurality of sub-structure units forming the bottom electrical conduction patterns to form a confinement layer with confinement holes above the active region, including: Forming a protective layer covering the light-emitting hole structures and the plurality of bottom electrical conduction patterns; Oxidizing the plurality of sub-structure units; and Exposing the light-emitting hole structures and the plurality of bottom electrical conduction patterns.

15. The manufacturing method of the VCSEL chip according to claim 13, wherein, The substrate structure is made of a non-conductive material.

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