Word line structure and formation method, semiconductor structure

Abstract

The present disclosure provides a word line structure and a formation method, and a semiconductor structure, relating to the field of memory technology. The word line structure formation method includes: providing a base, the base including a substrate, forming a plurality of spaced word line grooves and active area pillars on the substrate; forming an insulating layer on the active area pillars, and filling a first isolation layer between adjacent insulating layers; processing the insulating layer, and forming a ring gate on the processed insulating layer; etching back the first isolation layer so that the top of the first isolation layer is lower than the bottom of the ring gate; depositing a second isolation layer on the top of the ring gate, and forming an air gap structure between the first isolation layer and the second isolation layer. An air gap structure will be formed between the ring gates in the word line structure formed by the word line structure formation method. The air gap structure can reduce the parasitic capacitance between adjacent ring gates, reduce delay noise, and improve device performance.

Description

Technical Field

[0001] The present disclosure relates to the field of memory technology, and in particular to a word line structure and a forming method thereof, and a semiconductor structure. Background Art

[0002] Memory is a storage component used to store programs and various data, typically found within semiconductor integrated circuits within computers and other electronic devices. Memory includes several types: random access memory (RAM), read-only memory (ROM), dynamic random access memory (DRAM), static random access memory (SRAM), and flash memory. Dynamic random access memory (DRAM) is widely used in mobile devices such as mobile phones and tablets due to its small size, high level of integration, and fast data transmission speeds.

[0003] In the basic storage cell device of dynamic random access memory, in the existing vertical ring gate technology, the word line structure is usually composed of an oxide insulating layer and a metal gate formed by titanium nitride. After the word line structure is formed, the metal ring gate is isolated by a silicon nitride layer. Due to the high density of semiconductors on the substrate, the distance between the metal ring gates on adjacent semiconductors is relatively close. During the use of the device, the parasitic capacitance between the metal ring gates of the word line structure is large, the delay noise is large, and the performance of the device is poor.

[0004] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of the present disclosure, and therefore may include information that does not constitute prior art known to ordinary technicians in the field. Summary of the Invention

[0005] The purpose of the present disclosure is to overcome the deficiencies of the prior art and to provide a word line structure and a formation method thereof, as well as a semiconductor structure.

[0006] Other features and advantages of the present disclosure will become apparent from the following detailed description, or may be learned in part by practice of the present disclosure.

[0007] According to a first aspect of the present disclosure, a method for forming a word line structure is provided, comprising:

[0008] Providing a substrate, the substrate comprising a substrate, on which a plurality of spaced-apart word line trenches and active area pillars are formed;

[0009] forming an insulating layer on the active region pillars and filling a first isolation layer between adjacent insulating layers;

[0010] processing the insulating layer to form a ring-shaped gate on the processed insulating layer;

[0011] Etching back the first isolation layer so that a top of the first isolation layer is lower than a bottom of the annular gate;

[0012] A second isolation layer is deposited on top of the ring-shaped gate, and an air gap structure is formed between the first isolation layer and the second isolation layer.

[0013] In some embodiments of the present disclosure, based on the above solution, forming an insulating layer on the active region pillar includes:

[0014] An insulating layer is deposited on the active region pillar, and the insulating layer is etched to a preset height of the active region pillar to form a first insulating layer.

[0015] In some embodiments of the present disclosure, based on the above solution, etching the first insulating layer to a predetermined height of the active region pillar to form the first insulating layer includes:

[0016] Over-etching the portion of the active area pillar outside the preset height to reduce the cylinder of the active area pillar;

[0017] After cleaning the active area pillars, a second insulating layer is formed on the active area pillars.

[0018] In some embodiments of the present disclosure, based on the above solution, after forming the second insulating layer on the active area pillar, the method includes:

[0019] A titanium nitride layer is deposited on the second insulating layer, and the titanium nitride layer is etched back to form a ring-shaped gate.

[0020] In some embodiments of the present disclosure, based on the aforementioned solution, depositing a second isolation layer on top of the ring gate, and forming an air gap structure between the first isolation layer and the second isolation layer includes:

[0021] A second isolation layer is deposited by a low-step coverage method, and the second isolation layer and the first isolation layer enclose the air gap structure.

[0022] In some embodiments of the present disclosure, based on the aforementioned solution, depositing a second isolation layer on top of the ring gate, and forming an air gap structure between the first isolation layer and the second isolation layer includes:

[0023] A second isolation layer is deposited by physical vapor deposition, and the second isolation layer and the first isolation layer are enclosed to form the air gap structure.

[0024] According to a second aspect of the present disclosure, a word line structure is provided, comprising:

[0025] a plurality of word line trenches;

[0026] A plurality of active area columns are divided by a plurality of word line grooves, an insulating layer is provided on each of the active area columns, a ring gate is provided on the insulating layer, an isolation layer is provided between adjacent ring gates, and an air gap structure is provided in the isolation layer.

[0027] In some embodiments of the present disclosure, based on the aforementioned solution, the bottom of the air gap structure is lower than the bottom of the annular gate, and the top of the air gap structure is higher than the top of the annular gate.

[0028] In some embodiments of the present disclosure, based on the aforementioned scheme, the insulating layer includes a first insulating layer and a second insulating layer, the top of the first insulating layer is connected to the bottom of the second insulating layer, and the width of two adjacent second insulating layers is greater than the width of two adjacent first insulating layers.

[0029] In some embodiments of the present disclosure, based on the aforementioned solution, the isolation layer includes a first isolation layer and a second isolation layer, the first isolation layer is located below the second isolation layer, and the air gap structure is enclosed between the first isolation layer and the second isolation layer.

[0030] In some embodiments of the present disclosure, based on the aforementioned solution, the second insulating layer and the second isolation layer located on the top of the active region pillar form a double-layer covering layer of the word line structure.

[0031] In some embodiments of the present disclosure, based on the aforementioned solution, the second isolation layer is formed by a low-step capping silicon nitride method.

[0032] In some embodiments of the present disclosure, based on the aforementioned solution, the second isolation layer is formed by physical vapor deposition.

[0033] According to a third aspect of the present disclosure, there is provided a semiconductor structure comprising:

[0034] A bit line structure and a word line structure as described above;

[0035] The plurality of bit line structures are arranged perpendicular to the plurality of word line structures.

[0036] In some embodiments of the present disclosure, based on the aforementioned solution, adjacent ring-shaped gates in the word line structure are provided with air gap structures.

[0037] In some embodiments of the present disclosure, based on the aforementioned solution, the size of the air gap structure is greater than or equal to the size of the annular gate.

[0038] In some embodiments of the present disclosure, based on the aforementioned solution, the bit lines in the bit line structure are buried bit lines, and the bit lines are lower than the word lines in the word line structure.

[0039] In some embodiments of the present disclosure, based on the above solution, the bit line is formed by cobalt silicide diffusion deposition.

[0040] The present disclosure provides a method for forming a word line structure. On one hand, an insulating layer is formed on an active region pillar, and a ring gate is formed on the insulating layer. At the same time, a first isolation layer and a second isolation layer are formed between two adjacent active region pillars, and an air gap structure is formed between the first isolation layer and the second isolation layer. The formation of the air gap structure can reduce the parasitic capacitance between adjacent ring gates. Due to the reduction of the parasitic capacitance, the delay noise can be reduced, thereby improving the performance of the device.

[0041] On the other hand, over-etching is performed on the active region pillars in the word line structure, thereby increasing the distance between adjacent active region pillars and improving the margin of the semiconductor integration process;

[0042] Finally, the word line structure provided by the present disclosure can form a double-layer insulating dielectric layer on the top of the active area column, so that the insulation performance of the word line structure is better and the occurrence of short circuit between the word line structure and the surrounding structures is avoided.

[0043] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] The accompanying drawings are incorporated into and constitute a part of the specification, illustrate embodiments consistent with the present disclosure, and together with the specification, are used to explain the principles of the present disclosure. Obviously, the drawings described below are only some embodiments of the present disclosure, and those skilled in the art can derive other drawings based on these drawings without inventive effort.

[0045] Figure 1 The flowchart of a method for forming a word line structure in an exemplary embodiment of the present disclosure is shown.

[0046] Figure 2 The figure is a flowchart of an insulating layer processing method of a word line structure forming method in an exemplary embodiment of the present disclosure.

[0047] Figure 3 FIG. 1 is a top view of a conventional semiconductor structure in an exemplary embodiment of the present disclosure.

[0048] Figure 4 In the exemplary embodiment of the present disclosure Figure 3 A wordline perspective view of a semiconductor structure.

[0049] Figure 5 In the exemplary embodiment of the present disclosure Figure 3 A bit line perspective view of a semiconductor structure.

[0050] Figure 6-Figure 13 Schematic diagram of a method for forming a word line structure in an exemplary embodiment of the present disclosure.

[0051] Figure 14 Schematic diagram of a word line structure from a word line perspective in an exemplary embodiment of the present disclosure.

[0052] Figure 15 Schematic diagram of a word line structure from a bit line perspective in an exemplary embodiment of the present disclosure.

[0053] The description of the accompanying drawings is as follows:

[0054] 1: word line trench; 11: silicon nitride; 12: titanium nitride; 2: active area pillar;

[0055] 3: bit line trench; 4: substrate; 5: insulating layer; 51: first insulating layer;

[0056] 52: second insulating layer; 6: isolation layer; 61: first isolation layer; 61: second isolation layer;

[0057] 7: Titanium nitride layer; 8: Air gap structure; 9: Cobalt silicide diffusion ring. DETAILED DESCRIPTION

[0058] Example embodiments will now be described more fully with reference to the accompanying drawings. However, the example embodiments can be implemented in many forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete and will fully convey the concepts of the example embodiments to those skilled in the art. Like reference numerals in the figures represent identical or similar structures, and thus their detailed descriptions will be omitted. Furthermore, the figures are merely schematic illustrations of the present disclosure and are not necessarily drawn to scale.

[0059] Furthermore, in the following detailed description, for ease of explanation, numerous specific details are set forth in order to provide a thorough understanding of the embodiments of the present disclosure. However, it will be apparent that one or more embodiments can be practiced without these specific details.

[0060] As used herein, “on,” “formed on,” and “disposed on” may mean that one layer is directly formed or disposed on another layer, or may mean that one layer is indirectly formed or disposed on another layer, i.e., there are other layers between the two layers.

[0061] The terms "a," "an," "the," "said," and "at least one" are used to indicate the presence of one or more elements / components / etc.; the terms "comprising" and "having" are used to express an open-ended inclusive meaning and mean that additional elements / components / etc. may be present in addition to the listed elements / components / etc.

[0062] It should be noted that, although the terms "first," "second," etc. may be used herein to describe various parts, components, elements, regions, layers, and / or portions, these parts, components, elements, regions, layers, and / or portions should not be limited by these terms. Rather, these terms are used to distinguish one part, component, element, region, layer, and / or portion from another.

[0063] In this disclosure, unless otherwise specified, the term "same-layer arrangement" is used to mean that two layers, parts, components, elements or parts can be formed by the same composition process, and the two layers, parts, components, elements or parts are generally formed of the same material.

[0064] In the related art, vertical gate all around (VGAA) is a commonly used gate form in the basic storage unit of dynamic random access memory. To ensure the high performance of the memory, as many active areas and vertical gates as possible are usually set on the substrate of the memory. This increases the density of the vertical gates in the limited space of the substrate, increases the interference between adjacent gates, and increases the parasitic capacitance, which affects the performance of the memory.

[0065] Currently, in vertical ring gate technology, e.g. Figures 3 to 5 As shown, Figure 3 is a top view of an existing semiconductor structure. Figure 4 A view of a semiconductor structure from the word line perspective, Figure 5 This is a view of a semiconductor structure from the perspective of the bit line. As can be seen from the figure, the word line trench 1 and the bit line trench 3 are arranged perpendicular to each other. The mainstream word line structure is that the word line trench 1 divides the substrate into multiple active area pillars 2, an insulating layer is formed on the active area 2, and then titanium nitride metal forms titanium nitride 12 on the insulating layer. This titanium nitride 12 is processed to form a ring gate. Adjacent ring gates are isolated by silicon nitride 11. Therefore, there will be a dielectric layer between adjacent ring gates, resulting in large parasitic capacitance between adjacent ring gates, which leads to large delay noise and affects the performance of the memory. Therefore, the present disclosure provides a word line formation method that can improve the defects of the above memory.

[0066] The embodiments disclosed herein are all 4F2 VGAA semiconductor structures, where 4F2 refers to a 2×2 arrangement of the minimum positive-holding unit on the semiconductor structure, and the gate of the semiconductor is a ring-shaped gate perpendicular to the substrate, but the arrangement of the minimum positive-holding unit of the semiconductor disclosed herein is not limited to this.

[0067] The present disclosure provides a method for forming a word line structure. Figure 1 As shown, the word line structure forming method includes:

[0068] Step S10: providing a substrate, the substrate comprising a substrate, and forming a plurality of spaced-apart word line trenches and active area pillars on the substrate;

[0069] Step S20: forming an insulating layer on the active region pillars, and filling a first isolation layer between adjacent insulating layers;

[0070] Step S30: processing the insulating layer, and forming a ring-shaped gate on the processed insulating layer;

[0071] Step S40: etching back the first isolation layer so that the top of the first isolation layer is lower than the bottom of the ring gate;

[0072] Step S50: depositing a second isolation layer on top of the ring-shaped gate, forming an air gap structure between the first isolation layer and the second isolation layer.

[0073] The following is a detailed description of the above steps:

[0074] In step S10, Figure 6 As shown, a substrate 4 may be provided, which includes a substrate in which a plurality of word line trenches 1 are arranged at intervals and a plurality of active region pillars 2 are distributed side by side on the substrate.

[0075] The substrate may be a flat plate structure, and its shape may be rectangular or square, but is not limited thereto. The shape of the substrate may also be circular, elliptical or polygonal. In addition, the material of the substrate may be silicon, but is not limited thereto. The material of the substrate may also be other semiconductor materials. The present disclosure does not specifically limit the shape and material of the substrate, and the shape and material of the substrate may be determined according to actual usage requirements.

[0076] The method for forming multiple word line grooves 1 on the substrate is: the substrate can be etched using a mask to form multiple spaced word line grooves 1, but the method for forming the word line grooves disclosed in the present invention is not limited to this, and other methods can also be used to form word line grooves, which can be determined according to actual usage requirements.

[0077] The present disclosure does not impose any specific limitation on the depth of the word line trench 1. The word line trench can be a shallow trench structure or a trench structure of other different depths. The depth of the word line trench can be set according to actual needs and is not specifically limited in the present disclosure.

[0078] In this step, multiple word line grooves 1 and multiple active area columns 2 are distributed at intervals. The active area columns are semiconductor material columns with active areas isolated by multiple word line grooves on the substrate. The shape of the active area columns 2 can be a cubic column or other cubic shape. The specific shape of the active area columns is determined according to the distribution form of the word line grooves on the substrate, and this disclosure does not make any specific limitations.

[0079] In step S20, Figure 6 and Figure 7 As shown, an insulating layer 5 is formed on the active region pillar 2 , and a first isolation layer 61 is filled between adjacent insulating layers 5 .

[0080] After multiple word line trenches 1 and multiple active area pillars 2 are formed on the substrate 4, a photoresist is formed on the surface of the word line structure to deposit oxide on the substrate using a mask. Oxide is deposited around and on the top of the active area pillars through the mask to form an insulating layer 5. After forming the first isolation layer, the photoresist is stripped off, and silicon nitride layers are filled between adjacent insulating layers and on top of the insulating layer to form a first isolation layer 61.

[0081] Among them, the material of the insulating layer 5 is oxide, which can be silicon oxide, an oxide film in which B2O3 or P2O5 is doped in silicon oxide, or an insulating film layer with a low dielectric constant in which F and CH3 are doped in silicon dioxide. The present disclosure does not specifically limit the specific composition of the insulating layer, as long as the functions and effects of the insulating layer disclosed in the present disclosure are met.

[0082] In step S30, Figures 8 to 11 As shown, the insulating layer is processed and a ring-shaped gate is formed on the processed insulating layer.

[0083] After the insulating layer 5 is formed, the first isolation layer on the top of the word line structure needs to be removed first so that the subsequent insulating layer and the first isolation layer can be processed. The first isolation layer on the top of the word line structure can be removed by chemical mechanical polishing (CMP). After removing the first isolation layer on the top of the word line structure, the top of the active area column and the top of the word line groove can be exposed for subsequent processing steps.

[0084] Chemical mechanical polishing (CMP) is a processing technique that combines chemical etching and mechanical removal. Pure chemical polishing achieves high surface precision and low damage, and is less prone to surface or subsurface damage. However, it also results in a low polishing rate and poor polishing consistency. Pure mechanical polishing offers good consistency and a high polishing rate. Combining the advantages of chemical and mechanical polishing, CMP can achieve surface roughness ranging from nanometers to atomic scales. The present disclosure utilizes CMP to achieve high-precision polished surfaces for semiconductor structures.

[0085] The treatment process of the insulation layer is as follows Figures 8-11 shown, including:

[0086] Step S301: depositing an insulating layer on the active region pillar, and etching the insulating layer to a preset height of the active region pillar to form a first insulating layer;

[0087] Step S302: over-etching the portion of the active region pillar outside the preset height to reduce the cylinder of the active region pillar;

[0088] Step S303: After cleaning the active area pillar, forming a second insulating layer on the active area pillar;

[0089] Step S304: depositing a titanium nitride layer on the second insulating layer, and etching back the titanium nitride layer to form a ring-shaped gate.

[0090] In step S301, an insulating layer 5 and a first isolation layer 61 are formed in step S20. After covering the top of the word line structure with photoresist, the first isolation layer is chemically mechanically polished using a mask to remove the first isolation layer on the top of the word line structure to expose the top of the insulating layer. At the same time, the insulating layer is etched through the mask. After the insulating layer is etched to a preset height, the etching is stopped to form a first insulating layer 51, and the photoresist is removed.

[0091] The first insulating layer 51 is located at the bottom of the word line trench. The first insulating layer 51 and the first isolation layer 61 formed by silicon nitride fill the bottom of the word line trench 1 , leaving a blank space in the middle and upper part of the word line trench 1 .

[0092] Among them, the etching of the insulating layer 5 can adopt a dry etching process or a wet etching process or a combination of dry and wet etching processes. Dry etching can adopt plasma etching, reactive ion etching, sputtering etching or ion milling methods. The present disclosure does not specifically limit the specific type of dry etching and wet etching, and can be selected according to actual use needs.

[0093] In step S302, a first insulating layer 51 is formed in step S301. The first insulating layer 51 has a preset height and is arranged at a circumferential position at the bottom of the active area column 2. At this time, the blank area of ​​the word line groove 1 in step S301 is retained, and the circumferential position of the upper and middle part of the active area column 2 is over-etched, that is, the part outside the preset height of the active area column 2 is over-etched, so that the cylinder of the active area column 2 is reduced.

[0094] Over-etching is performed on the circumferential position and the top of the active area column 2. The over-etching process reduces the circumference of the active area column 2, that is, reduces the radius of the cylinder of the active area column. This can increase the space between adjacent active area columns and leave enough space for the subsequent formation of the ring gate.

[0095] In step S303, after cleaning the active area pillars 2, a second insulating layer 52 is formed on the active area pillars 2. After the active area pillars 2 are etched, contact holes are pre-opened in the word line structure or other conventional process operations are performed, which may cause particles, organic matter, metal contaminants or other contaminants to be present on the substrate surface. At this time, the word line structure needs to be cleaned to ensure the cleanliness of the word line structure and the flatness of the substrate. The next process operation can be performed on the cleaned word line structure.

[0096] After cleaning the wordline structure, an oxide deposition is performed around and on the top of the active area pillars with reduced diameters, forming a second insulating layer 52 around and on the top of the active area pillars. The second insulating layer 52 may be silicon dioxide, silicon oxide, or an oxide formed from other insulating materials, which is not specifically limited in this disclosure. The second insulating layer 52 may be made of the same or different materials as the first insulating layer 51, and may be both silicon oxide or an oxide insulating layer formed from different other oxides. The type of oxide needs to meet the actual needs of this disclosure.

[0097] Among them, the bottom of the first insulating layer 51 is on the same straight line as the bottom of the active area column 2, the top of the first insulating layer 51 is connected to the bottom of the second insulating layer 52, and the second insulating layer 52 is located in the circumferential position other than the coverage of the first insulating layer 51 and the top of the active area column 2.

[0098] In step S304, a titanium nitride layer is deposited on the second insulating layer and etched back to form a ring-shaped gate. The titanium nitride is deposited on the second insulating layer 52 in the blank space of the wordline trench and on the top of the wordline structure, so that the titanium nitride deposited fills the wordline trench and the top of the active area pillar to form a titanium nitride layer 7. The titanium nitride layer 7 is then etched to remove the titanium nitride layer 7 covering the active area pillar and the top of the wordline trench. The remaining titanium nitride layer 7 is then etched back through a mask to form a ring-shaped gate after the titanium nitride layer 7 is etched back to a certain height.

[0099] Among them, the height of the ring gate is determined by the specific use of the ring gate in the semiconductor structure. The bottom of the ring gate is located at the connection between the first insulating layer and the second insulating layer, and the top of the ring gate is lower than the top of the active area column, so that the word line groove area between the second insulating layer and the first isolation layer is left blank. The ring gate is located on the second insulating layer. When the titanium nitride layer is etched back, the shape and structure of the first insulating layer, the second insulating layer and the first isolation layer remain unchanged.

[0100] Among them, the deposition of the titanium nitride layer can be carried out by atomic layer deposition, vacuum evaporation, magnetron sputtering, chemical vapor deposition or physical vapor deposition, and the titanium nitride layer is not limited to a metal conductive layer formed by titanium nitride, but can also be a metal conductive layer formed by metal tungsten or other metals with good conductive properties, which are not listed here one by one.

[0101] After the above steps S301 to S304, a ring gate perpendicular to the substrate can be formed in the word line structure, that is, the vertical ring gate VGAA described in the present disclosure. In addition, over-etching the active area column in step S303 can increase the margin of adjustment of the integrated process of the word line trench.

[0102] In step S40, Figure 12 As shown, the first isolation layer is etched back so that the top of the first isolation layer is lower than the bottom of the annular gate. In the above steps, an annular gate is formed between the second insulating layer and the first isolation layer. A photoresist layer is then applied to the wordline structure, and the first isolation layer is etched back using a mask until the height of the first isolation layer is lower than the bottom of the annular gate. This leaves the wordline trench areas between the annular gates and above the annular gates blank, maintaining the shape and structure of the first insulating layer, the second insulating layer, and the annular gate unchanged.

[0103] Among them, the back etching of the first isolation layer can adopt a dry etching process or a wet etching process or a combination of dry etching and wet etching. The dry etching process can be carried out in a plasma-excited atmosphere to generate active radicals that can react with the substrate and the photoresist. The wet etching process is to immerse in a chemical solution to etch the substrate or strip the photoresist. Therefore, during etching, dry etching can be used for multiple times, and wet etching can be used to remove the photoresist. Alternatively, dry etching or wet etching can be used alone, and a flexible selection can be made according to the actual process requirements of the present disclosure.

[0104] In step S50, Figure 13 As shown, a second isolation layer 62 is deposited on top of the ring gate, and an air gap structure 8 is formed between the first isolation layer 61 and the second isolation layer 62. The second isolation layer is formed using low-step cap silicon nitride or physical vapor deposition silicon nitride. The second isolation layer covers the blank area of ​​the word line trench above the ring gate and the top of the second insulating layer. The second isolation layer is used to cover the top of the word line structure, and an air gap structure 8 is formed between the second isolation layer and the first isolation layer.

[0105] The air gap structure is located between two adjacent annular gates, the top of the air gap structure is higher than the top of the annular gates, and the bottom of the air gap structure is lower than the bottom of the annular gates, that is, the hollow area of ​​the air gap structure needs to be larger than the area between the two adjacent annular gates.

[0106] Among them, the second isolation layer can be formed by a low-step covering silicon nitride method, which controls the diffusion rate of silicon nitride on the substrate so that silicon nitride can quickly cover and form the blank area of ​​the word line groove, so that a hollow area is formed between the second isolation layer and the first isolation layer, that is, an air gap structure is formed between the second isolation layer and the first isolation layer.

[0107] The second isolation layer can also be formed by physical vapor deposition of silicon nitride. Physical vapor deposition is a physical method that vaporizes the surface of silicon nitride into gaseous atoms or molecules, or partially ionizes it into ions under vacuum conditions, and deposits an isolation layer on the surface of the substrate through a low-pressure gas or plasma process. Physical vapor deposition is a method for surface treatment of wordline structures. The physical vapor deposition method used in the present disclosure can be a vacuum evaporation coating method, a vacuum sputtering method, or a vacuum ion plating method, but the present disclosure is not limited to the above methods. The present disclosure uses physical vapor deposition to quickly cover and shape silicon nitride on the top of the wordline structure, so that an air gap structure is formed between the second isolation layer and the first isolation layer.

[0108] The first isolation layer and the second isolation layer of the present disclosure may be made of silicon nitride, silicon oxynitride, or other materials with insulating properties, which are not specifically limited in the present disclosure.

[0109] The word line structure formation method provided by the present disclosure forms vertical annular metal gates on a substrate and forms a word line structure between the annular gates, thereby reducing the parasitic capacitance between adjacent annular gates, thereby reducing delay noise and improving device performance. At the same time, the active area pillars are over-etched, increasing the margin of semiconductor integration. In addition, a double-layer insulating dielectric layer of a second insulating layer and a second isolation layer is formed in the word line structure, which can increase the insulation of the word line structure and prevent the occurrence of short circuit phenomena in the word line structure.

[0110] It should be noted that although the steps of the wordline structure forming method of the present disclosure are described in a specific order in the accompanying drawings, this does not require or imply that the steps must be performed in this specific order, or that all steps must be performed to achieve the desired results. Additionally or alternatively, certain steps may be omitted, multiple steps may be combined into one step, and / or one step may be decomposed into multiple steps.

[0111] Another aspect of the present disclosure provides a word line structure including: a plurality of word line trenches and a plurality of edge region pillars.

[0112] The multiple active area columns are divided by multiple word line trenches. An insulating layer is provided on each active area column. An annular gate is provided on the insulating layer. An isolation layer is provided between adjacent annular gates. An air gap structure is provided in the isolation layer.

[0113] The bottom of the air gap structure is lower than the bottom of the annular gate, and the top of the air gap structure is higher than the top of the annular gate, that is, the hollow space area of ​​the air gap structure covers the area between adjacent annular gates.

[0114] The insulating layer includes a first insulating layer and a second insulating layer, the top of the first insulating layer is connected to the bottom of the second insulating layer, and the width of two adjacent second insulating layers is greater than the width of two adjacent first insulating layers. That is, after the active area column is over-etched, the width of the second insulating layer formed on the surface of the over-etched active area column is greater than the width of the first insulating layer, leaving sufficient margin for subsequent integration processes.

[0115] The first insulating layer and the second insulating layer can be formed by chemical vapor deposition, physical vapor deposition, thermal evaporation or atomic layer deposition. The first insulating layer and the second insulating layer are composed of an oxidized insulating material. The two insulating layers can then be used to insulate and protect two adjacent word line structures, thereby preventing short circuits between the word line structures and other surrounding structures and reducing the short circuit risk of the device.

[0116] The isolation layer includes a first isolation layer and a second isolation layer. The first isolation layer is located below the second isolation layer. An air gap structure is formed between the first isolation layer and the second isolation layer.

[0117] The second insulating layer and the second isolation layer located on the top of the active area column form a double-layer covering layer of the word line structure. The double-layer covering layer is a double-layer insulating dielectric layer, which provides multiple insulation protections for the word line structure and reduces the occurrence of short circuit phenomena in the device.

[0118] The second isolation layer is formed by a low-step capping silicon nitride method or a physical vapor deposition method. The method for forming the second isolation layer has been described above and will not be repeated here.

[0119] The present disclosure provides a word line structure that reduces parasitic capacitance between adjacent metal ring gates and improves device performance by providing an air gap structure within the word line structure. Furthermore, the word line structure has a double cover layer, which reduces the risk of short circuits between word line structures. Furthermore, the volume of active area pillars in the word line structure is reduced, thereby increasing the margin of the integration process.

[0120] The present disclosure also provides a semiconductor structure, such as Figure 14 and Figure 15 As shown, the structure includes: a bit line structure and a word line structure.

[0121] Among them, multiple bit line structures are arranged vertically with multiple word line structures, and the word line structure is a word line structure formed by the word line formation method described above. Adjacent annular gates in the word line structure are provided with an air gap structure 8, and the size of the air gap structure is greater than or equal to the size of the annular gate, that is, the size of the hollow space of the air gap structure is greater than or equal to the size of the area between adjacent annular gates.

[0122] In the present disclosure, a bit line in a bit line structure in a semiconductor junction is a buried bit line, and the bit line is lower than a word line in the word line structure.

[0123] In the process of forming the semiconductor structure disclosed in the present invention, the bit line structure needs to be buried on the substrate first, and the bit line is formed on the substrate by using the cobalt silicide diffusion deposition method. Due to the diffusion effect of cobalt silicide, a cobalt silicide diffusion ring 9 is formed on the substrate, that is, Figure 14 After the bit line structure is formed, a word line structure is provided perpendicularly to the bit line structure. The method for forming the word line structure is as described above and will not be repeated here.

[0124] In some embodiments of the present disclosure, an air gap structure similar to that in a word line structure can also be formed in the bit line structure, allowing the semiconductor structure to simultaneously include a bit line structure with an air gap structure. The semiconductor structure provided by the present disclosure can be vertically constructed with a bit line structure and a word line structure with an air gap structure, or vertically constructed with a word line structure and a bit line structure with an air gap structure. In the present disclosure, the structure can be flexibly adjusted according to actual performance requirements.

[0125] Among them, the semiconductor structure can be a dynamic random access memory or other storage devices, which are not listed here one by one; the semiconductor structure disclosed in the present invention adopts a vertical ring gate (VGAA, Vertical Gate All Around) structure, and the minimum positive unit on the substrate is arranged in a 2×2 form, but the present disclosure is not limited to this.

[0126] The semiconductor structure provided by the present disclosure reduces parasitic capacitance in the semiconductor structure and improves the performance of the semiconductor by providing a word line structure with an air gap structure or a bit line structure with an air gap structure in the semiconductor structure.

[0127] Those skilled in the art will readily appreciate other embodiments of the present disclosure after considering the specification and practicing the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of the present disclosure that follow the general principles of the present disclosure and include common knowledge or customary techniques in the art not disclosed herein. The description and examples are to be considered as exemplary only, with the true scope and spirit of the present disclosure being indicated by the appended claims.

Claims

1. A method for forming a word line structure, characterized in that: include: Providing a substrate, the substrate comprising a substrate, on which a plurality of spaced-apart word line trenches and active area pillars are formed; forming an insulating layer on the active region pillars and filling a first isolation layer between adjacent insulating layers; processing the insulating layer to form a ring-shaped gate on the processed insulating layer; Etching back the first isolation layer so that a top of the first isolation layer is lower than a bottom of the annular gate; A second isolation layer is deposited on top of the ring-shaped gate, and an air gap structure is formed between the first isolation layer and the second isolation layer.

2. The word line structure forming method according to claim 1, wherein: Forming an insulating layer on the active area column includes: An insulating layer is deposited on the active region pillar, and the insulating layer is etched to a preset height of the active region pillar to form a first insulating layer.

3. The word line structure forming method according to claim 2, wherein: Etching the first insulating layer to a predetermined height of the active region pillar to form the first insulating layer comprises: Over-etching the portion of the active area pillar outside the preset height to reduce the cylinder of the active area pillar; After cleaning the active area pillars, a second insulating layer is formed on the active area pillars.

4. The method for forming a word line structure according to claim 3, wherein: After forming the second insulating layer on the active area column, the method includes: A titanium nitride layer is deposited on the second insulating layer, and the titanium nitride layer is etched back to form a ring-shaped gate.

5. The word line structure forming method according to claim 1, wherein: Depositing a second isolation layer on top of the ring gate, and forming an air gap structure between the first isolation layer and the second isolation layer comprises: A second isolation layer is deposited by a low-step coverage method, and the second isolation layer and the first isolation layer enclose the air gap structure.

6. The word line structure forming method according to claim 1, wherein: Depositing a second isolation layer on top of the ring gate, and forming an air gap structure between the first isolation layer and the second isolation layer comprises: A second isolation layer is deposited by physical vapor deposition, and the second isolation layer and the first isolation layer are enclosed to form the air gap structure.

7. A word line structure, characterized in that: The word line structure is formed by the forming method according to any one of claims 1 to 6, include: a plurality of word line trenches; A plurality of active area columns are divided by a plurality of word line grooves, an insulating layer is provided on each of the active area columns, a ring gate is provided on the insulating layer, an isolation layer is provided between adjacent ring gates, and an air gap structure is provided in the isolation layer.

8. The word line structure according to claim 7, wherein: The bottom of the air gap structure is lower than the bottom of the annular gate, and the top of the air gap structure is higher than the top of the annular gate.

9. The word line structure according to claim 7, wherein: The insulating layer includes a first insulating layer and a second insulating layer. The top of the first insulating layer is connected to the bottom of the second insulating layer. The width of two adjacent second insulating layers is greater than the width of two adjacent first insulating layers.

10. The word line structure according to claim 7, wherein: The isolation layer includes a first isolation layer and a second isolation layer. The first isolation layer is located below the second isolation layer. The air gap structure is formed by enclosing the first isolation layer and the second isolation layer.

11. The word line structure according to claim 7, wherein: The second insulating layer and the second isolation layer located on the top of the active region pillar form a double-layer covering layer of the word line structure.

12. The word line structure according to claim 10, wherein: The second isolation layer is formed by using a low-step capping silicon nitride method.

13. The word line structure according to claim 10, wherein: The second isolation layer is formed by physical vapor deposition.

14. A semiconductor structure, characterized in that include: A bit line structure and a word line structure according to any one of claims 7 to 13; The plurality of bit line structures are arranged perpendicular to the plurality of word line structures.

15. The semiconductor structure according to claim 14, wherein: Adjacent annular gates in the word line structure are all provided with air gap structures.

16. The semiconductor structure according to claim 15, wherein: The size of the air gap structure is greater than or equal to the size of the annular gate.

17. The semiconductor structure according to claim 14, wherein: The bit lines in the bit line structure are buried bit lines, and the bit lines are lower than the word lines in the word line structure.

18. The semiconductor structure according to claim 17, wherein: The bit line is formed by cobalt silicide diffusion deposition.

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