Method of manufacturing a fingerprint sensing module

Abstract

A method of manufacturing a fingerprint sensing module includes forming, in sequence, a planarization layer and a photoresist material layer on a substrate, wherein the substrate includes a pixel region including a photosensitive array and a peripheral region surrounding the pixel region; removing a portion of the photoresist material layer on the pixel region to form a photoresist pattern exposing the planarization layer; removing a portion of the planarization layer on the pixel region to form a patterned planarization layer exposing the substrate; forming an infrared cut-off layer on the photoresist pattern and the pixel region of the substrate; removing the photoresist pattern and the infrared cut-off layer on the photoresist pattern to form an infrared cut-off pattern on the pixel region of the substrate; forming a light-shielding layer on the infrared cut-off pattern and the patterned planarization layer; and patterning the light-shielding layer to form a collimating structure layer including a pinhole array on the infrared cut-off pattern and a mark pattern on the patterned planarization layer.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to a method for manufacturing an optical sensing element, and in particular, to a method for manufacturing a fingerprint sensing module. BACKGROUND

[0002] In order to make the display have a narrow frame design, under-display fingerprint sensing technology has become the current trend. The under-display fingerprint sensing technology is to configure a fingerprint sensing module under the display panel of an electronic device. After the electronic device detects that a user contacts the display screen, the electronic device controls the display panel to emit light to illuminate the surface of the user's finger. The sensing light is reflected by the user's finger into the fingerprint sensing module under the display panel, and the reflected light is converged on the photosensitive element through a plurality of microlenses and a collimating structure, so that the optical image signal can be converted into a digital image signal to obtain the fingerprint image of the user. The collimating structure can include a light shielding material layer with pinholes, so that the reflected light can be converged on the photosensitive element through the pinholes and the light shielding material can absorb the reflected light with large angles to avoid interference between different reflected lights.

[0003] However, in the patterning process of forming the light shielding material layer with pinholes, the exposure condition of the light shielding material layer is significantly affected by its thickness. For example, taking an exposure wavelength of about 365 nm as an example, when the thickness of the light shielding material layer is about 1 μm, the light transmittance of the exposure light is about 70%, but when the thickness of the light shielding material layer increases to about 1.5 μm, the light transmittance of the exposure light decreases to about 10%. As can be seen, although the thickness difference between the two is only 0.5 μm, the light transmittance difference between the two is as high as about 7 times. Therefore, in the manufacturing process of the light shielding material layer, some patterns to be formed may not be well exposed to some areas due to the light transmittance difference caused by the thickness difference, so that in the development process, the patterns to be formed may not be well formed on these areas. SUMMARY

[0004] The present disclosure provides a method for manufacturing a fingerprint sensing module, which forms a light shielding layer on an infrared cut-off pattern and a patterned flat layer by design, so that the light shielding layer has approximately the same thickness in different areas of the substrate. In the step of patterning the light shielding layer, the collimating structure layer including an array of pinholes and the marker pattern can be well formed in different areas of the substrate (such as the pixel area and the peripheral area).

[0005] One embodiment of the present disclosure provides a method of manufacturing a fingerprint sensing module. The method includes the following steps. A planarization layer and a photoresist material layer are sequentially formed on a substrate. The substrate includes a pixel region including a photosensitive array and a peripheral region surrounding the pixel region. A portion of the photoresist material layer on the pixel region is removed to form a photoresist pattern exposing the planarization layer. A portion of the planarization layer on the pixel region is removed to form a patterned planarization layer exposing the substrate. An infrared cut-off layer is formed on the photoresist pattern and the pixel region of the substrate. The photoresist pattern and a portion of the infrared cut-off layer on the photoresist pattern are removed to form an infrared cut-off pattern on the pixel region of the substrate. A light-shielding layer is formed on the infrared cut-off pattern and the patterned planarization layer. The light-shielding layer is patterned to form a collimating structure layer including an array of pinholes on the infrared cut-off pattern and a mark pattern on the patterned planarization layer.

[0006] In some embodiments, a thickness of the infrared cut-off pattern is approximately equal to a thickness of the patterned planarization layer on the substrate.

[0007] In some embodiments, the infrared cut-off pattern and the patterned planarization layer are spaced apart by a distance in a direction parallel to the substrate.

[0008] In some embodiments, the photoresist pattern includes a bottom surface in contact with the patterned planarization layer and a top surface opposite to the bottom surface, and an area of the top surface is greater than an area of the bottom surface.

[0009] In some embodiments, the photoresist pattern includes an inclined sidewall, and an angle between the inclined sidewall and the bottom surface is greater than 90 degrees.

[0010] In some embodiments, the infrared cut-off layer is not formed on the inclined sidewall of the photoresist pattern, such that the infrared cut-off layer includes a first portion and a second portion that are discontinuous. The first portion is formed on the pixel region of the substrate. The second portion is formed on the photoresist pattern.

[0011] In some embodiments, the infrared cut-off layer includes a first portion formed on the pixel region of the substrate and a second portion formed on the photoresist pattern. The first portion and the second portion are separated by the photoresist pattern.

[0012] In some embodiments, the photoresist pattern is formed by an exposure fabrication process and a first development fabrication process, and the patterned planarization layer is formed by the exposure fabrication process and a second development fabrication process different from the first development fabrication process.

[0013] In some embodiments, light used in the exposure fabrication process exposes portions of the photoresist material layer and portions of the planarization layer underneath the portions of the photoresist material layer.

[0014] In some embodiments, the method of manufacturing the fingerprint sensing module further comprises forming an additional planar layer on the infrared cut-off pattern and the patterned planar layer before forming the light-shielding layer.

[0015] Based on the above, in the method of manufacturing the fingerprint sensing module, since the light-shielding layer is formed on the infrared cut-off pattern and the patterned planar layer, the thickness of the light-shielding layer in different regions of the substrate (e.g. the pixel region and the peripheral region) is approximately the same. In this way, some patterns to be formed in different regions of the substrate (e.g. the collimating structure layer including the pinhole array in the pixel region and the mark pattern in the peripheral region) can be well formed in the step of patterning the light-shielding layer. BRIEF DESCRIPTION OF DRAWINGS

[0016] Figures 1 to 7 is a cross-sectional schematic view of a method of manufacturing a fingerprint sensing module according to an embodiment of the present disclosure.

[0017] MAIN ELEMENT SYMBOL EXPLANATION

[0018] 10: pixel region

[0019] 20: wiring region

[0020] 30: contact pad region

[0021] 40: scribe region

[0022] 100: substrate

[0023] 102: interconnect structure

[0024] 104: wiring

[0025] 106: contact pad structure

[0026] 108: opening

[0027] 110: planar layer

[0028] 112: patterned planar layer

[0029] 120: infrared cut-off layer

[0030] 120a: first portion

[0031] 120b: second portion

[0032] 122: infrared cut-off pattern

[0033] 130: additional planar layer

[0034] 140: light-shielding layer

[0035] 142: collimating structure layer

[0036] 144: mark pattern

[0037] 146: pinhole array

[0038] A: area

[0039] d: distance

[0040] PR: photoresist pattern

[0041] S1: bottom surface

[0042] S2: top surface

[0043] SW1: slanted sidewall / sidewall

[0044] SW2: sidewall

[0045] θ: angle DETAILED DESCRIPTION

[0046] The present application will be more fully understood from the following detailed description taken in connection with the accompanying drawings, in which:

[0047] It should be understood that when an element such as a layer, region, or substrate is referred to as being "on" or "connected to" another element, it can be directly on or connected to the other element or intervening elements can also be present. In contrast, when an element is referred to as being "directly on" or "directly connected to" another element, there are no intervening elements present. As used herein, the term "connected" can mean physically and / or electrically connected, and the term "electrical connection" or "coupled" can be used to indicate that there is an electrical connection between two elements. As used herein, "electrical connection" can include a physical connection (e.g., a wired connection) and a physical disconnection (e.g., a wireless connection).

[0048] As used herein, "about," "approximately," or "substantially" includes the average value and ranges of acceptable deviations from the specified value that a person of ordinary skill in the art would identify as being within the bounds of acceptable values, taking into account the particular quantity being measured and the particular quantity of error associated with the measurement (i.e., the limitations of the measurement system). For example, "about" can mean within one or more standard deviations of the stated value, or within ±30%, ±20%, ±10%, ±5%. Further, as used herein, "about," "approximately," or "substantially" can select a more acceptable range of deviation or standard deviation for optical properties, etching properties, or other properties, and can not apply one standard deviation to all properties.

[0049] The terminology used herein is for the purpose of describing illustrative embodiments only and is not intended to be limiting of the present application. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.

[0050] Figures 1 to 7 FIG. 1 is a cross-sectional schematic view of a manufacturing method of a fingerprint sensing module according to an embodiment of the present disclosure. Figure 4 (b) of FIG. 1 is Figure 4 (a) of FIG. 1 is an enlarged view of region A. The manufacturing method of the fingerprint sensing module will be exemplified below by Figures 1 to 7 way of FIG. 1.

[0051] First, refer to Figure 1 A planarization layer 110 is formed on a substrate 100. The substrate 100 includes a pixel region 10 including a photosensitive array and a peripheral region surrounding the pixel region 10 and including a wiring region 20, a pad region 30, and a scribe region 40.

[0052] In some embodiments, the substrate 100 can include a plurality of film layers, a plurality of structures, and / or elements formed in a back end of line (BEOL). For example, the substrate 100 can include an intermetal dielectric layer, a via, a wiring layer, an active element (e.g., a transistor), and / or a passive element (e.g., a capacitor). As shown in FIG. 1, the pixel region 10 of the substrate 100 can include an interconnection structure 102 and active elements and / or passive elements (e.g., active elements and / or passive elements included in a CMOS image sensor) connected to the interconnection structure 102, and the peripheral region of the substrate 100 can include a wiring 104 disposed in the wiring region 20 and a pad structure 106 disposed in the pad region 30. Figure 1

[0053] ​In some embodiments, the substrate 100 can include a plurality of film layers, structures, and / or elements formed in a front end of line (FEOL) process. For example, the substrate 100 can include a layer of elements formed on a semiconductor substrate. The layer of elements can include a variety of elements and interlayer dielectric layers covering the elements. In some embodiments, the elements can include active elements, passive elements, or a combination thereof (e.g., active and / or passive elements included in a CMOS image sensor). For example, the elements can include transistors, capacitors, resistors, diodes, photodiodes, or other similar elements. In some embodiments, the layer of elements can include gate structures, source / drain regions, and isolation structures such as shallow trench isolation (STI) structures. In the layer of elements, various N-type metal-oxide semiconductor (NMOS) and / or P-type metal-oxide semiconductor (PMOS) elements such as transistors and memory can be formed and interconnected to each other to perform one or more functions. Other elements such as capacitors, resistors, diodes, photodiodes, etc. can also be formed on the semiconductor substrate. The functions of these elements can include memory, processor, sensor, amplifier, power distribution, or I / O circuitry, etc.

[0054] The semiconductor substrate can be a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, or the like. The semiconductor substrate can be doped (e.g., doped with P-type or N-type dopants) or undoped. The semiconductor substrate can be a wafer, such as a silicon wafer. In general, an SOI substrate is a film layer of semiconductor material formed on an insulating layer. The insulating layer can be, for example, a buried oxide (BOX) layer or a silicon oxide layer, etc. The insulating layer is provided, for example, on a silicon substrate or a glass substrate. In some embodiments, the semiconductor substrate can include an elemental semiconductor such as silicon or germanium, a compound semiconductor such as silicon carbide, gallium arsenic, gallium phosphide, indium phosphide, indium arsenide, and indium antimonide, an alloy semiconductor such as SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, GaInAsP, or a combination thereof.

[0055] The substrate 100 can include an opening 108 exposing the pad structure 106, and a planar layer 110 can be formed on the top surface of the substrate 100 and fill in the opening 108. In some embodiments, the planar layer 110 can be, for example, a photosensitive material. In some embodiments, the planar layer 110 can be formed on the pixel region 10 of the substrate 100 and the peripheral region including the wiring region 20, the pad region 30, and the scribe line region 40.

[0056] Next, referring to Figure 1 and Figure 2 A photoresist pattern PR is formed on the planar layer 110. In some embodiments, the photoresist pattern PR can be formed, for example, via the following steps. First, a photoresist material layer (not shown) is formed on the planar layer 110. In some embodiments, the photoresist material layer is formed over the pixel region 10 of the substrate 100 and over the peripheral region including the wiring region 20, the pad region 30, and the scribe line region 40. In some embodiments, the photoresist material layer can employ a negative photoresist material. Next, portions of the photoresist material layer over the pixel region 10 of the substrate 100 are removed to form the photoresist pattern PR exposing the planar layer 110. That is, the photoresist pattern PR is formed over the peripheral region of the substrate 100.

[0057] The photoresist pattern PR can include a bottom surface SI in contact with the planar layer 110 and a top surface S2 opposite the bottom surface SI. In some embodiments, the area of the top surface S2 of the photoresist pattern PR is greater than the area of the bottom surface SI. In other words, the photoresist pattern PR can include an inclined sidewall SW1, and the angle Θ between the inclined sidewall SW1 and the bottom surface SI is greater than 90 degrees. In some embodiments, where the photoresist material layer employs a negative photoresist material, the photoresist pattern PR formed after the exposure and development fabrication processes can have an inverted trapezoidal pattern such that the area of the top surface S2 of the photoresist pattern PR is greater than the area of the bottom surface SI.

[0058] Then, referring to Figure 2 and Figure 3 , portions of the planar layer 110 over the pixel region 10 are removed to form a patterned planar layer 112 exposing the pixel region 10 of the substrate 100. In some embodiments, the patterned planar layer 112 can be formed, for example, via the following steps. In the exposure fabrication process and the first development fabrication process to form the photoresist pattern PR (illustrated using a negative photoresist material for the photoresist material layer), neither the photoresist material layer nor the portions of the planar layer 110 over the pixel region 10 of the substrate 100 are exposed to the light used in the exposure fabrication process. Therefore, after the portions of the photoresist material layer over the pixel region 10 of the substrate 100 are removed in the first development fabrication process, the portions of the planar layer 110 over the pixel region 10 can be removed via a second development fabrication process different from the first development fabrication process. That is, the photoresist pattern PR can be formed via the exposure fabrication process and the first development fabrication process, and the patterned planar layer 112 can be formed via the exposure fabrication process and a second development fabrication process different from the first development fabrication process. In other embodiments, the portions of the planar layer 110 over the pixel region 10 can also be removed via another exposure fabrication process and development fabrication process (i.e., different from the exposure fabrication process and development fabrication process used in the fabrication processes to form the photoresist pattern PR). In other embodiments, the portions of the planar layer 110 over the pixel region 10 can also be removed as a mask by the photoresist pattern PR and via an etching fabrication process.

[0059] In some embodiments, the sidewall SW1 of the photoresist pattern PR and the sidewall SW2 of the patterned planar layer 112 can be non-coplanar. In other words, the end of the sidewall SW2 of the patterned planar layer 112 in contact with the photoresist pattern PR can be in contact with the bottom surface SI of the photoresist pattern PR.

[0060] Then, referring to Figure 3 and Figure 4An infrared cut-off layer 120 is formed on the photoresist pattern PR and the pixel region 10 of the substrate 100. The infrared cut-off layer 120 can be a film layer having an infrared light filtering function, which can be a single layer or multiple layers. In some embodiments, due to the photoresist pattern PR having a slanted sidewall SW1 with an angle Θ greater than 90 degrees from its bottom surface S1, the infrared cut-off layer 120 is formed only on the top surface S2 of the photoresist pattern PR and the pixel region 10 of the substrate 100, but not on the slanted sidewall SW1 of the photoresist pattern PR. That is, the infrared cut-off layer 120 can include a first portion 120a and a second portion 120b that are discontinuous. The first portion 120a of the infrared cut-off layer 120 can be formed on the pixel region 10 of the substrate 100, and the second portion 120b of the infrared cut-off layer 120 can be formed on the photoresist pattern PR. In other words, the first portion 120a of the infrared cut-off layer 120 and the second portion 120b of the infrared cut-off layer 120 can be separated by the photoresist pattern PR (e.g., in a direction perpendicular to the top surface of the substrate 100). In some embodiments, the thickness of the infrared cut-off layer 120 is approximately equal to the thickness of the patterned planar layer 112 on the substrate 100.

[0061] In some embodiments, due to the photoresist pattern PR having a slanted sidewall SW1 with an angle Θ greater than 90 degrees from its bottom surface S1, that is, the area of the top surface S2 of the photoresist pattern PR is greater than the area of the bottom surface S1, the infrared cut-off layer 120 (e.g., the first portion 120a of the infrared cut-off layer 120) formed on the pixel region 10 of the substrate 100 is spaced apart from the patterned planar layer 112 by a distance (e.g., distance d).

[0062] Next, refer to Figure 4 and Figure 5The photoresist pattern PR and the portion of the infrared cut-off layer 120 (e.g., the second portion 120b of the infrared cut-off layer 120) on the photoresist pattern PR are removed to form an infrared cut-off pattern 122 on the pixel region 10 of the substrate 100. In some embodiments, the infrared cut-off pattern 122 is spaced apart from the patterned planar layer 112 by a distance (e.g., the distance d) in a direction parallel to the substrate 100. In some embodiments, the thickness of the infrared cut-off pattern 122 is approximately equal to the thickness of the patterned planar layer 112 on the substrate 100. That is, the top surface of the infrared cut-off pattern 122 is at approximately the same height as the top surface of the patterned planar layer 112. In other words, the film layer (e.g., the light blocking layer 140 to be mentioned later) formed on the infrared cut-off pattern 122 and the patterned planar layer 112 later has a good planarity with approximately the same thickness over the pixel region 10 and the peripheral region of the substrate 100. In this way, when the light blocking layer 140 is subjected to a subsequent exposure process, the light used in the exposure process can be well exposed to the desired regions of the light blocking layer 140, so that the desired pattern can be well formed in the regions.

[0063] In some embodiments, the second portion 120b of the infrared cut-off layer 120 can be lifted off from the patterned planar layer 112 by removing the photoresist pattern PR. That is, the infrared cut-off pattern 122 can be formed on the pixel region 10 of the substrate 100 by a self-aligned manner without using an additional photomask. In some embodiments, the photoresist pattern PR can be removed, for example, by using an acetone-based photoresist solvent (ACE), but the present application is not limited thereto.

[0064] Thereafter, referring to Figure 5 and Figure 6 a light blocking layer 140 is formed on the infrared cut-off pattern 122 and the patterned planar layer 112. The light blocking layer 140 has a good planarity with approximately the same thickness over the pixel region 10 and the peripheral region of the substrate 100. In some embodiments, before forming the light blocking layer 140, an additional planar layer 130 can be formed on the infrared cut-off pattern 122 and the patterned planar layer 112, so as to further improve the planarity of the light blocking layer 140 formed on the additional planar layer 130. The light blocking layer 140 can be, for example, a material capable of blocking and / or absorbing visible light (e.g., black photoresist). The additional planar layer 130 can be, for example, an organic material or an inorganic material.

[0065] Then, referring to Figure 6 and Figure 7The patterned light-shielding layer 140 forms a collimating structure layer 142 including a pinhole array 146 over the infrared cut-off pattern 122 and a mark pattern 144 over the patterned planar layer 112. The light-shielding layer 140 has a good planarity and a substantially same thickness (e.g., the thickness difference of the light-shielding layer 140 over the different regions of the substrate 100 is less than 0.5 μm or less than 0.4 μm) over the pixel region 10 and over the wiring region 20, the contact pad region 30 and the scribe region 40 in the peripheral region. In this way, in the process of patterning the light-shielding layer 140, some of the patterns to be formed, such as the collimating structure layer 142 formed over the pixel region 10 and the mark pattern 144 formed over the scribe region 40, will not be exposed to the exposure light due to the difference in the light transmittance caused by the thickness difference, and thus, the patterns to be formed, such as the collimating structure layer 142 and the mark pattern 144, can be formed over the regions, such as the pixel region 10 and the scribe region 40, respectively, without being removed in the subsequent development process. The mark pattern 144 can include an alignment mark, an overlay mark or a combination thereof.

[0066] In summary, in the manufacturing method of the above-described fingerprint sensing module, since the light-shielding layer is formed over the infrared cut-off pattern and the patterned planar layer, the thickness of the light-shielding layer over the different regions of the substrate, such as the pixel region and the peripheral region, is substantially the same. In this way, some of the patterns to be formed over the different regions of the substrate, such as the collimating structure layer including the pinhole array in the pixel region and the mark pattern in the peripheral region, can be well formed in the step of patterning the light-shielding layer.

Claims

1. A method for manufacturing a fingerprint sensing module, comprising: A planarization layer and a photoresist material layer are sequentially formed on a substrate, the substrate including a pixel region containing a photosensitive array and a peripheral region surrounding the pixel region; Remove a portion of the photoresist material layer on the pixel area to form a photoresist pattern that exposes the planarization layer; Remove the portion of the planarization layer on the pixel area to form a patterned planarization layer that exposes the substrate; An infrared cutoff layer is formed on the photoresist pattern and on the pixel area of ​​the substrate; Remove the photoresist pattern and the portion of the infrared cut-off layer on the photoresist pattern to form an infrared cut-off pattern on the pixel area of ​​the substrate; A light-shielding layer is formed on the infrared cutoff pattern and on the patterned planarization layer; as well as The light-shielding layer is patterned to form a collimation structure layer including a pinhole array on the infrared cutoff pattern, and a marking pattern is formed on the patterned planarization layer.

2. The method for manufacturing a fingerprint sensing module as claimed in claim 1, wherein the thickness of the infrared cutoff pattern is equal to the thickness of the patterned planarization layer on the substrate.

3. The method for manufacturing a fingerprint sensing module as claimed in claim 1, wherein the infrared cutoff pattern and the patterned planarization layer are spaced apart by a distance in a direction parallel to the substrate.

4. The method for manufacturing a fingerprint sensing module as claimed in claim 1, wherein the photoresist pattern includes a bottom surface in contact with the patterned planarization layer and a top surface opposite to the bottom surface, the area of ​​the top surface being larger than the area of ​​the bottom surface.

5. The method for manufacturing a fingerprint sensing module as claimed in claim 4, wherein the photoresist pattern includes inclined sidewalls, and the angle between the inclined sidewalls and the bottom surface is greater than 90 degrees.

6. The method of manufacturing a fingerprint sensing module as claimed in claim 5, wherein the infrared cut-off layer is not formed on the inclined sidewall of the photoresist pattern, such that the infrared cut-off layer includes a discontinuous first portion and a second portion, the first portion being formed on the pixel region of the substrate, and the second portion being formed on the photoresist pattern.

7. The method of manufacturing a fingerprint sensing module as claimed in claim 1, wherein the infrared cutoff layer includes a first portion formed on the pixel region of the substrate and a second portion formed on the photoresist pattern, the first portion and the second portion being separated by the photoresist pattern.

8. The method for manufacturing the fingerprint sensing module as described in claim 1, wherein: The photoresist pattern is formed through an exposure process and a first development process. The patterned planarization layer is removed by the exposure process and a second development process different from the first development process.

9. The method of manufacturing a fingerprint sensing module as claimed in claim 8, wherein the light used in the exposure process does not expose the portion of the photoresist material layer and the portion of the planarization layer below the portion of the photoresist material layer.

10. The method for manufacturing the fingerprint sensing module as described in claim 1, further comprising: Before forming the light-shielding layer, an additional planarization layer is formed on the infrared cutoff pattern and the patterned planarization layer.

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