High-efficiency gate drive circuit

Abstract

The present invention discloses a high-efficiency gate drive circuit for driving a power switch SiC MOSFET. The circuit includes: an input receiving circuit, a high-voltage bandgap reference, an internal power generation circuit, a high-efficiency output drive circuit, an overcurrent protection circuit, an overtemperature protection circuit, an undervoltage protection circuit, an oscillator OSC, a waveform modulation circuit, a control logic, and an error amplifier. It also includes 5 external pins, namely: the chip power supply pin VDD, the external input pulse pin INX, the current detection pin CS, the output drive switch pin VO, and the ground pin GND. The high-efficiency gate drive provided by the present invention improves the overall chip functional reliability by adopting a variety of chip abnormal state monitoring and protection circuits; the present invention also adopts an output drive circuit with high output efficiency, which adaptively identifies the load size and the frequency of the input control pulse, and adjusts the output drive current in real time and adaptively to provide the optimal output drive current, so as to achieve the goal of improving efficiency.

Description

Technical Field

[0001] The present invention relates to a high-efficiency gate drive circuit for power devices in a switching power supply, and belongs to the field of integrated circuit technology. Background Art

[0002] In recent years, various portable electronic products have emerged in an endless stream, and the corresponding power consumption has become larger and larger. Therefore, new requirements have been put forward for the conversion efficiency and power consumption of the power supply. Early power supplies mostly used linear power supplies. Linear power supplies have a simple structure, good stability, and better anti-noise performance. However, a large amount of heat will be generated by the regulating transistor when the linear voltage regulator works. Therefore, the efficiency is not high and the loss is serious. In order to eliminate the generated heat, a relatively large heat sink needs to be used in cooperation around the regulating transistor. Moreover, a linear voltage regulator generally needs to use a power frequency transformer, plus the heat sink of the regulating transistor, resulting in a large volume and low power efficiency of the linear voltage regulator, and generally the maximum can only reach 50%. For small and portable electronic products, the linear power supply can no longer meet their power supply requirements. Therefore, people have gradually started to turn to research switching power supplies to meet the new power supply requirements. The biggest advantage of a switching power supply is its relatively high conversion efficiency, and at the same time, it has a smaller volume and lighter weight, thus reducing the cost, providing convenience for charging small devices, and the switching power supply has various open-circuit / short-circuit / over-temperature / over-voltage protection functions, which ensures the safety of our use of electronic products. Compared with the linear power supply working in the linear state, the switching power supply controls the output voltage by the on and off of the power switch transistor.

[0003] Common power devices include bipolar junction transistors (BJTs), insulated gate bipolar transistors (IGBTs), metal-oxide-semiconductor field effect transistors (MOSFETs), and junction field effect transistors (JFETs). As the main power device in a switching power supply converter, the technology of Si IGBT has tended to mature, but its performance is gradually approaching the theoretical limit of Si materials. It is an inevitable trend to seek power devices with better performance. With the rise of wide-bandgap semiconductor devices, SiC MOSFETs have emerged in the field of power electronics with their advantages such as high frequency, high voltage resistance, high temperature resistance, and strong heat dissipation ability, and have the potential to replace Si IGBTs. To improve the efficiency of the switching power supply, the loss of the power switch device cannot be ignored, so its gate drive circuit needs to be optimized.

[0004] In practical applications, the pulse control signal required by the SiC MOSFET switch is a large current signal of 15V - 25V. To prevent the gate output drive current from damaging the gate terminal of the external power switch SiC MOSFET to be driven, a resistor is usually connected in series at the output end of the gate drive circuit to suppress the influence of the gate terminal voltage overshoot. When the equivalent capacitance of the gate terminal is large, the series protection resistor needs to be relatively small; conversely, a larger series protection resistor is required. However, a relatively large series protection resistor will bring two problems: one is that the switching loss on the resistor becomes larger, reducing the efficiency of the drive circuit; the other is that it increases the drive delay, ultimately reducing the system switching frequency. In addition, using a series protection resistor will also increase the design workload of design engineers and reduce the reliability of the entire machine system. Summary of the Invention

[0005] The present invention proposes a high - efficiency gate drive circuit with adaptively adjustable driving ability to improve efficiency. This circuit can adaptively identify the load size and the frequency of the input control pulse, and adaptively adjust the magnitude of the output drive current.

[0006] The high - efficiency gate drive circuit provided by the present invention has the following structure: an input receiving circuit, a high - voltage bandgap reference, an internal power generation circuit, a high - efficiency output drive circuit, an over - current protection circuit, an over - temperature protection circuit, an under - voltage protection circuit, an oscillator, a waveform modulation circuit, a control logic, and an error amplifier; it also includes 5 external pins, namely: the chip power supply pin VDD, the external input pulse pin INX, the current detection pin CS, the output drive switch pin VO, and the ground pin GND;

[0007] The input end of the input receiving circuit is connected to the external input pulse pin INX, the output end of the input receiving circuit is connected to the input end of the waveform modulation circuit, the input end of the waveform modulation circuit is also connected to the oscillator, and the output end of the waveform modulation circuit outputs a modulated pulse signal DX; the input end of the error amplifier is connected to the current detection pin CS, the error amplifier amplifies the externally sampled current to obtain a current input signal CSIN, which is connected to the over - current protection circuit; the high - voltage bandgap reference is used to provide a reference voltage Vref; the internal power generation circuit is used to generate an internal power supply voltage VCC and various bias signals according to the reference voltage Vref for use by other circuits in the chip; the over - current protection circuit, the over - temperature protection circuit, and the under - voltage protection circuit respectively generate an over - current protection signal OCP, an over - temperature protection signal OTP, and an under - voltage protection signal UVLO based on the reference voltage Vref; the over - current protection signal OCP, the over - temperature protection signal OTP, the under - voltage protection signal UVLO, and the modulated pulse signal DX are all connected to the control logic, and after processing, an output control pulse Din is obtained; the output control pulse Din is connected to the high - efficiency output drive circuit, and after being buffered and driven by the high - efficiency output drive circuit, an output drive signal is obtained and connected to the output drive switch pin VO;

[0008] After the chip power supply pin VDD meets the power-on requirements, the high-voltage bandgap reference first works normally and provides a 1.2V reference voltage Vref. The input receiving circuit receives an external input pulse and converts it into a logic level VIN with a high level of VCC. Then, the logic level VIN is modulated with the oscillation clock generated by the oscillator to obtain a modulated pulse signal DX. The error amplifier amplifies the external sampling current to obtain a current input signal CSIN, and the current input signal CSIN enters the overcurrent protection circuit for comparison to obtain an overcurrent protection signal OCP. The control logic performs logical processing on the overcurrent protection signal OCP, overtemperature protection signal OTP, undervoltage protection signal UVLO, and modulated pulse signal DX, and outputs an output control pulse Din for output driving. The output control pulse Din is then buffered and driven by a high-efficiency output driving circuit to obtain an output driving signal, which is output through the output driving switch pin VO.

[0009] Specifically, the overtemperature protection circuit includes: NPN transistors Q61 and Q60, resistors R61 and R62, PMOS transistor P60, inverter Inv60, capacitor C60, and Schmitt trigger Schmitt. The collector of NPN transistor Q61 is connected to the internal power supply voltage VCC, the emitter of NPN transistor Q61 is connected to the upper end of resistor R61, and the base of NPN transistor Q61 is connected to the reference voltage Vref. The lower end of resistor R61 is connected to the upper end of resistor R61 and the base of NPN transistor Q60. The collector of NPN transistor Q60 is connected to the upper end of capacitor C60, the output end of inverter Inv60, the drain of PMOS transistor P60, and the input end of Schmitt trigger Schmitt. The source of PMOS transistor P60 is connected to the internal power supply voltage VCC, and the gate of PMOS transistor P60 is connected to the bias voltage Vb6. The signal Ctrl connected to the input end of inverter Inv60 is a global chip control signal. The over-temperature protection signal OTP is output from the output end of the Schmitt trigger Schmitt. The lower ends of resistor R62, capacitor C60, and the emitter of NPN transistor Q60 are all connected to the ground voltage GND.

[0010] Specifically, the high-efficiency output driving circuit includes: a P-terminal output adjustable buffer driving circuit, an N-terminal output adjustable buffer driving circuit, a sampling switch SW, a working timing generation circuit, a load comparison quantization circuit, and a driving current selection circuit;

[0011] The output control pulse Din is simultaneously connected to the data input terminals of the adjustable buffer driving circuit at the P terminal, the adjustable buffer driving circuit at the N terminal, and the working timing generation circuit; the driving signal output terminals of the adjustable buffer driving circuit at the P terminal and the adjustable buffer driving circuit at the N terminal are connected to each other as the output terminal of the output driving signal, and are connected to the input terminal of the load comparison quantization circuit through the sampling switch SW; the working timing generation circuit tracks and discriminates the frequency of the output control pulse Din to obtain the frequency discrimination code Dfin, and generates non-overlapping high-level control clocks Ck1 and Ck2; wherein the frequency discrimination code Dfin is connected to the load comparison quantization circuit, the control clock Ck1 is connected to the load comparison quantization circuit and the drive current selection circuit, and the control clock Ck2 is connected to the drive current selection circuit; the output driving signal enters the load comparison quantization circuit after being sampled by the sampling switch SW, and obtains the load quantization code Dlot under the control of the reference voltage Vr, the control clock Ck1, and the frequency discrimination code Dfin, and is connected to the drive current selection circuit; the load quantization code Dlot, the control clock Ck1, and the control clock Ck2 enter the drive current selection circuit simultaneously to obtain n switch control signals Kp1 to Kpn and n switch control signals Kn1 to Knn; wherein the switch control signals Kp1 to Kpn are respectively connected to the n switch signal input terminals of the adjustable buffer driving circuit at the P terminal, and the switch control signals Kn1 to Knn are respectively connected to the n switch signal input terminals of the adjustable buffer driving circuit at the P terminal; n is any positive integer;

[0012] After the power supply voltage is powered on, the working timing generation circuit tracks and discriminates the frequency of the output control pulse Din to obtain the frequency discrimination code Dfin, and generates the control clock Ck1 and the control clock Ck2; when the Ck1 clock is valid, the load comparison and quantization circuit will generate a set of default load quantization codes Dlot_pre according to the output drive signal VO sampled by the sampling switch SW, the reference voltage Vr, and the state of the frequency discrimination code Dfin, and enter the drive current selection circuit. The drive current selection circuit will output a set of default switch control signals Kp1_pre~Kpn_pre and switch control signals Kn1_pre~Knn_pre. The output drive signal will drive the external load under the action of the default drive current and gradually increase the voltage of the output drive signal; when the Ck1 clock ends, the load quantization code Dlot_pre will be adjusted according to the magnitude of the output drive signal at this time to obtain the adjusted load quantization code Dlot_lock and remain unchanged; when the Ck2 clock is valid, the drive current selection circuit will output a new set of switch control signals Kp1_lock~Kpn_lock and switch control signals Kn1_lock~Knn_lock according to the load quantization code Dlot_lock. The output drive signal will drive the external load under the action of the new drive current and quickly increase the voltage to the voltage VCC; when the Ck2 clock ends, the load quantization code Dlot will be cleared, and the switch control signals Kp1~Kpn output by the drive current selection circuit will be cleared synchronously, turning off the control switches of the n P-terminal output inverters in the P-terminal output adjustable buffer drive circuit. At the same time, the switch control signals Kn1~Knn output by the drive current selection circuit are valid, turning on the control switches of the n N-terminal output inverters in the N-terminal output adjustable buffer drive circuit, and the output drive signal will quickly pull from the voltage VCC to the ground voltage GND, thereby turning off the external load power device.

[0013] Specifically, the P-terminal output adjustable buffer drive circuit includes: an inverter chain, the input end of the inverter chain is connected to the output control pulse Din, the output end of the inverter chain is respectively connected to the input ends of n P-terminal output inverters through n P-terminal output inverter control switches, and the output ends of the n P-terminal output inverters are respectively connected to the gate ends of n P-terminal output PMOS transistors. The source ends of the n P-terminal output PMOS transistors are simultaneously connected to the internal power supply voltage VCC; the n P-terminal output inverter control switches are respectively controlled by the switch control signals Kp1~Kpn;

[0014] The N-terminal output adjustable buffer driving circuit includes: an inverter chain, the input terminal of the inverter chain is connected to the output control pulse Din, and the output terminals of the inverter chain are respectively connected to the input terminals of n N-terminal output inverters through n N-terminal output inverter control switches. The output terminals of the n N-terminal output inverters are respectively connected to the gate terminals of n N-terminal output NMOS transistors, and the source terminals of the n N-terminal output NMOS transistors are simultaneously connected to the ground voltage GND; the n N-terminal output inverter control switches are respectively controlled by the switch control signals Kn1 to Knn;

[0015] The drain terminals of the n P-terminal output PMOS transistors are connected to the drain terminals of the n N-terminal output NMOS transistors together. One side is connected to the input terminal of the load comparison quantization circuit through the sampling switch SW, and is also connected to the output driving switch pin VO.

[0016] Specifically, the working timing generation circuit includes: an oscillator, a pulse width counter, a counting period selection circuit, a comprehensive counter, a first clock waveform generation circuit, and a second clock waveform generation circuit; the OSC signal generated by the oscillator is connected to the pulse width counter and the comprehensive counter, and the output control pulse Din is simultaneously connected to the pulse width counter and the comprehensive counter; the pulse width counter counts the pulse time width of the output control pulse Din according to the OSC signal, and performs tracking discrimination and comparison quantization on the counted pulse time width size to output a frequency discrimination code Dfin; the frequency discrimination code Dfin is connected to the counting period selection circuit to generate a comprehensive counter mode selection signal sel0; the comprehensive counter generates a clock control signal ct1 and a clock control signal ct2 according to the mode selection signal sel0, the OSC signal, and the output control pulse Din; finally, the clock control signal ct1 and the clock control signal ct2 are respectively connected to the first clock waveform generation circuit and the second clock waveform generation circuit, and the first clock waveform generation circuit and the second clock waveform generation circuit respectively output the final control clocks Ck1 and Ck2.

[0017] Specifically, the load comparison quantization circuit includes: a quantization voltage generation circuit, a high / low speed mode selection circuit, N comparators, an error filtering circuit, a path selection circuit, a serial shift register, a serial-to-parallel conversion circuit, and an M-bit buffer output circuit; the input end of the quantization voltage generation circuit is connected to a reference voltage Vr, a control clock Ck1, and a mode control signal mod output by the high / low speed mode selection circuit. The quantization voltage generation circuit converts the reference voltage Vr into N quantization reference voltages Vr1 to VrN under the control of the control clock Ck1, and respectively connects them to the reference voltage input ends of the N comparators; the detection voltage input ends of the N comparators are all connected to an output driving switch pin VO. The N comparators respectively compare the output driving signal with the N quantization reference voltages Vr1 to VrN, and output N-bit quantization values D1 to DN; then the N-bit quantization values D1 to DN enter the error filtering circuit and output an N-bit quantization code Dlo; the high / low speed mode selection circuit outputs the mode control signal mod according to the magnitude of the frequency discrimination code Dfin, thereby changing the mode of the load comparison quantization circuit to change the speed and power consumption of the load comparison quantization circuit. The mode control signal mod is respectively connected to the quantization voltage generation circuit, the N comparators, the error filtering circuit, and the path selection circuit; the path selection circuit selects the signal path of the N-bit quantization code Dlo under the control of the mode control signal mod; the high-speed path output port of the path selection circuit is N-bit parallel data, which is directly output to the first data input port of the M-bit buffer output circuit. The low-speed path output port of the path selection circuit is 1-bit serial data, which is first connected to the serial shift register, and the output of the serial shift register then enters the serial-to-parallel conversion circuit to obtain M-bit parallel quantization code Dlp, which is connected to the second data input port of the M-bit buffer output circuit; the M-bit buffer output circuit outputs the final M-bit load quantization code Dlot under the control of the control clock Ck1; where M and N are both integers greater than 1.

[0018] Specifically, the load comparison quantization circuit includes a high-speed mode and a low-speed mode;

[0019] The working mode of the high-speed mode is as follows: the quantization voltage generation circuit simultaneously outputs N quantization reference voltages under the control of the control clock Ck1. The N comparators respectively compare the output driving signal with the N quantization reference voltages simultaneously, and output N-bit parallel quantization values D1 to DN, and then obtain an N-bit quantization code Dlo through the error filtering circuit; at this time, the N-bit quantization code Dlo is N-bit parallel data, which is directly output to the first data input port of the M-bit buffer output circuit through the high-speed path output port of the path selection circuit. The M-bit buffer output circuit outputs the final M-bit load quantization code Dlot under the control of the control clock Ck1;

[0020] The low-speed mode operates as follows: Only the first comparator among the N comparators works, and the remaining N - 1 comparators are in a sleep state. The quantization voltage generation circuit outputs N quantization reference voltages in sequence from one output port under the control of the control clock Ck1. The first comparator compares the output drive signal with the N quantization reference voltages in sequence according to the time sequence, and outputs N-bit serial quantization values D1 to DN at the output port of the first comparator in sequence. Then, through the error filtering circuit, an N-bit quantization code Dlo is obtained. At this time, the N-bit quantization code Dlo is 1-bit serial data, which enters the serial shift register through the low-speed path output port of the path selection circuit in sequence. The output of the serial shift register then enters the serial-to-parallel conversion circuit, and an M-bit parallel quantization code Dlp is output to the second data input port of the M-bit buffer output circuit. The M-bit buffer output circuit obtains the final M-bit load quantization code Dlot under the control of the control clock Ck1.

[0021] The advantages of the present invention are as follows: The provided high-efficiency gate drive improves the overall chip functional reliability by adopting a variety of chip abnormal state monitoring and protection circuits. On the other hand, the output drive part of the present invention adopts a specially designed high-output-efficiency output drive circuit, which can adaptively identify the load size and the frequency of the input control pulse, and adjust the output drive current in real time and adaptively to provide the optimal output drive current, thus achieving the goal of improving efficiency. Brief Description of the Drawings

[0022] Figure 1 It is the overall circuit structure block diagram of the present invention.

[0023] Figure 2 It is the schematic diagram of the high-voltage bandgap reference circuit in the embodiment of the present invention.

[0024] Figure 3 It is the schematic diagram of the internal power generation circuit in the embodiment of the present invention.

[0025] Figure 4 It is the schematic diagram of the error amplifier circuit in the embodiment of the present invention.

[0026] Figure 5 It is the schematic diagram of the over-temperature protection circuit in the embodiment of the present invention.

[0027] Figure 6 It is the schematic diagram of the under-voltage protection circuit in the embodiment of the present invention.

[0028] Figure 7 It is the schematic diagram of the over-current protection circuit in the embodiment of the present invention.

[0029] Figure 8 It is the structure block diagram of the high-efficiency output drive circuit in the embodiment of the present invention.

[0030] Figure 9 Schematic diagram of the working waveform of the high-efficiency output drive circuit of the present invention.

[0031] Figure 10 Schematic diagram of the adjustable buffer drive circuit at the P end in the embodiment of the present invention.

[0032] Figure 11 Schematic diagram of the adjustable buffer drive circuit at the N end in the embodiment of the present invention.

[0033] Figure 12 Block diagram of the working timing generation circuit in the embodiment of the present invention.

[0034] Figure 13 Block diagram of the load comparison quantization circuit in the embodiment of the present invention. Detailed implementation manners

[0035] The present invention will be further described in detail below in conjunction with the accompanying drawings and examples.

[0036] As Figure 1 shown, the high-efficiency gate drive circuit of the present invention includes: an input receiving circuit 1, a high-voltage bandgap reference 2, an internal power generation circuit 3, a high-efficiency output drive circuit 4, an overcurrent protection circuit 5, an overtemperature protection circuit 6, an undervoltage protection circuit 7, an oscillator (OSC) 8, a waveform modulation circuit 9, a control logic 10, and an error amplifier 11. The high-efficiency gate drive circuit has 5 external pins: VDD in the figure is the chip power supply pin, INX is the external input pulse pin, CS is the current detection pin, VO is the output drive switch pin, and GND is the ground pin. In the following description, the signal names input or output by the pin are sometimes also represented by the pin names.

[0037] After the chip power supply pin VDD meets the power-on requirements, the high-voltage bandgap reference 2 first operates normally and provides a 1.2V reference voltage Vref. The internal power generation circuit 3 generates an internal power supply voltage VCC and various bias signals based on the reference voltage Vref. The overcurrent protection circuit 5, the overtemperature protection circuit 6, and the undervoltage protection circuit 7 generate an overcurrent protection signal OCP, an overtemperature protection signal OTP, and an undervoltage protection signal UVLO respectively based on the reference voltage Vref. The internal power supply voltage VCC and various bias signals are used by other circuit modules in the chip.

[0038] The input receiving circuit 1 receives an external input pulse INX and converts it into a logic level VIN with a high level of VCC. Then, VIN is modulated with the oscillation clock generated by the oscillator 8 to obtain a modulated pulse signal DX. The error amplifier 11 amplifies the external sampling current CS to obtain a current input signal CSIN, and the current input signal CSIN enters the overcurrent protection circuit 5 and is compared to obtain an overcurrent protection signal OCP. The overcurrent protection signal OCP, the overtemperature protection signal OTP, the undervoltage protection signal UVLO, and the modulated pulse signal DX are all connected to the control logic 10, and after processing, an output control pulse Din for output driving is obtained. The output control pulse Din is buffered and driven by the high-efficiency output driving circuit 4 to obtain an output driving signal VO.

[0039] The method of modulating the above logic level VIN with the oscillation clock to obtain the modulated pulse signal DX can be implemented by using existing conventional digital modulation techniques.

[0040] Figure 2 This is the circuit diagram of the embodiment of the high-voltage bandgap reference 2 of the present invention. The characteristics of the circuit reference in the chip circuit will greatly affect the performance of the entire chip, and an accurate and reliable reference is a strong guarantee for the normal operation of the chip. The core structure of this circuit is resistor R31, resistor R32, triode Q31, triode Q32, PMOS transistor P31, and PMOS transistor P32. MOS transistors P34 to P36 are high-voltage MOS transistors that can withstand high voltage between the source and the drain. After adding MOS transistors P34 to P36, since there is an isolation between the power supply and the reference voltage Vref at the output, the power supply rejection ability of the entire circuit will be significantly improved. The addition of MOS transistor P33 is to suppress the change of Vref caused by the change of the bias current.

[0041] Figure 2There are two feedback loops in the middle circuit. The first feedback loop is from below MOS transistor N31 to transistor Q32, and the second feedback loop is from above MOS transistor N31 to PMOS transistors P31 and P32. The function of the first feedback loop is to provide base current for transistors Q31 and Q32, and at the same time form negative feedback to ensure the stability of Vref. The second feedback loop exists due to MOS transistors P34 - P36. The change in the base voltage of MOS transistor N31 will directly and in the same direction affect the source voltage of PMOS transistor P31 through MOS transistor N31. Therefore, MOS transistor P33 is added here to cancel the influence of the change in the base voltage of MOS transistor N31 on the source voltage of PMOS transistor P31. Assume that the base voltage of MOS transistor N31 increases. Due to the effect of MOS transistor N31, the drain voltage of MOS transistor N31 will become smaller, and similarly the source voltage of PMOS transistor P31 will also become smaller. At the same time, due to the effect of transistor P33, the source voltage of PMOS transistor P31 will become larger. By appropriately selecting the sizes of MOS transistor N31 and MOS transistor P33, the combined effect of the two makes the source voltage of PMOS transistor P31 not affected by the base voltage of MOS transistor N31. In addition, the function of capacitor C31 is to compensate the capacitance and provide a better phase margin for the second feedback loop. R33 represents a resistor voltage division network, and its function is to generate some reference voltages lower than the bandgap reference voltage.

[0042] As Figure 3 Shown is a circuit diagram of an embodiment of the internal power generation circuit 3 of the present invention. The reference voltage obtained from the high - voltage bandgap reference 2 is only 1.2V, while the required operating voltage VCC for other operating modules in the chip is 5V. Relying solely on the bandgap reference circuit cannot meet the power supply requirements of other modules inside the chip. Therefore, a voltage regulator is needed to adjust the voltage to meet the requirements of other modules. Figure 3 The middle circuit can generate multiple slightly different internal power supply voltages for the chip. Since the gate and drain voltages of MOS transistors N41, N42, N43, and N44 are the same, we can draw a conclusion: If the same load is connected below MOS transistors N41 - N44, then the values of VCC1, VCC2, VCC3, and VCC4 are all equal; if the loads are not equal, then the magnitude of the voltage difference between these values is determined by the magnitude of the load. The larger the load one carries, the larger its voltage.

[0043] In this embodiment, VCC1 is used for some relatively static modules, while VCC2 to VCC4 are used for some dynamic modules. Generally speaking, VCC1 has the largest load. However, this may cause a problem. We are uncertain about the load carried at each voltage. If the load carried by VCC2 to VCC4 is much larger than that of VCC1, a large voltage difference will be generated, and this voltage difference will cause some logic circuits to malfunction. To solve this problem, three PMOS transistors can be added between VCC1 and VCC2 to VCC4 to form a voltage limiting circuit. When VCC2 to VCC4 is greater than VCC1 by more than a threshold voltage, the corresponding MOS transistors P42 to P44 will conduct, causing the voltage of VCC2 to VCC4 to drop below VCC1. This is not only simple and convenient, but also does not require an additional level conversion circuit, saving the chip area.

[0044] Figure 4 This is the circuit diagram of the error amplifier 11 according to the embodiment of the present invention. This circuit adopts a two-stage operational amplifier structure. The first-stage amplifier adopts a folded cascode structure. MOS transistors N53 and N54 are the input pair transistors of the first stage, enabling the error amplifier 11 to have a higher bandwidth and open-loop gain. Compared with the telescopic cascode operational amplifier, it has a larger input common-mode level, a larger output swing, and it is easier to short-circuit the input and output to form a proportional operation circuit. The second-stage amplifier adopts a common single-ended source circuit, which is composed of MOS transistors N57 and P58 to increase the output swing. At the same time, in order to improve the phase margin of the amplifier, resistors R53 and capacitor C51 are connected in series between the output stage of the second stage and the output stage of the first stage to form Miller compensation to increase the phase margin of the loop, and the output stage point of the first-stage amplifier is pushed to low frequency to become the main pole. If the feedback signal and the reference voltage differ too much, then the error amplifier 11 will operate in the comparator state, that is, when the sampled CS is much higher than the reference voltage Vref, the error amplifier 11 will output a high level, otherwise it will output a low level. If the feedback signal and the reference voltage do not differ much, then the error amplifier 11 will operate in the linear amplification state.

[0045] Figure 5 This is the circuit diagram of the over-temperature protection circuit 6 according to the embodiment of the present invention. The chip will generate heat when working, especially when the frequency increases. Therefore, there must be a thermal protection circuit inside the chip, otherwise the chip may be burned out due to excessive temperature. The thermal protection circuit must be extremely sensitive to temperature. Generally, the thermal protection circuit uses the change of the base-emitter voltage of the bipolar transistor with temperature sensitivity to generate an over-temperature protection signal. Therefore, this chip's thermal protection circuit design is also based on this characteristic of the triode. When the working temperature of the chip exceeds the set temperature threshold, the over-temperature protection circuit 6 outputs a protection signal to stop the chip from working, and when the temperature drops to a certain value, the chip restarts and enters the normal working state.

[0046] As Figure 5 , the over-temperature protection circuit 6 adopted in this embodiment includes: NPN transistor Q61, NPN transistor Q60, resistor R61, resistor R62, PMOS transistor P60, inverter Inv60, capacitor C60, and Schmitt trigger Schmitt. The collector of NPN transistor Q61 is connected to the internal power supply voltage VCC, the emitter of NPN transistor Q61 is connected to the upper end of resistor R61, and the base of NPN transistor Q61 is connected to the reference voltage Vref. The lower end of resistor R61 is connected to the upper end of resistor R61 and is also connected to the base of NPN transistor Q60. The collector of NPN transistor Q60 is connected to the upper end of capacitor C60, the output end of inverter Inv60, the drain of PMOS transistor P60, and the input end of Schmitt trigger Schmitt. The source of PMOS transistor P60 is connected to the internal power supply voltage VCC, and the gate of PMOS transistor P60 is connected to the bias voltage Vb6. The input Ctrl signal of inverter Inv60 is a global control signal of the chip, which can be a power-on reset signal or other control signals; the output end of Schmitt trigger Schmitt is the over-temperature protection signal OTP. The lower end of resistor R61, the lower end of capacitor C60, and the emitter of NPN transistor Q60 are all connected to the ground voltage GND.

[0047] The Vbe (base-emitter voltage) of transistor Q61 has a negative temperature coefficient. When the chip is working normally, the Vref voltage is less than the Vbe turn-on voltage of transistor Q61, so transistor Q61 will not conduct. When the temperature rises, the Vbe of transistor Q61 decreases, and the voltages on resistors R61 and R62 change with temperature at the same time. When Vbe drops to the Vref voltage, transistor Q61 will conduct. At this time, the voltage at point A rises until it rises to the turn-on voltage of transistor Q60, and then transistor Q60 will turn on, and the collector voltage of transistor Q60 (voltage at point B) becomes low level. Then the low level is delayed and triggered by Schmitt trigger Schmitt to flip from low level to high level OTP. At this time, OTP is the overheat protection signal. Here, the Schmitt trigger Schmidt hysteresis loop design can effectively prevent the problem that the chip cannot work normally due to thermal oscillation.

[0048] Figure 6 This is an embodiment of the under-voltage protection circuit 7 of the present invention. If the output voltage is lower than the rated value, the load will be damaged, and the output voltage must be limited. Therefore, the under-voltage protection circuit 7 is designed. According to the chip design specifications, the under-voltage protection is triggered when VDD is lower than 6.5V. First, the divided voltage of the VDD pin is detected through the negative input terminal of a two-stage operational amplifier comparator. When the amplifier detects that the VDD divided voltage is greater than the set reference voltage, the output level of the comparator latches the SR latch through an inverter to set it to "1" to generate the UVLO signal.

[0049] Figure 7 This is an embodiment of the overcurrent protection circuit 5 of the present invention. If the feedback resistor outside the current detection pin CS is short-circuited or open-circuited, the CSIN signal will be abnormal and the normal sampling output cannot be achieved. Therefore, an open-circuit and short-circuit protection circuit is designed inside the chip. Its working principle is as follows: When the Ctrl signal rises, it indicates that the primary side conducts, and the transformer delivers energy to the secondary winding. At this time, the internal power supply voltage VCC charges the capacitor C through PCH1 until it reaches the positive threshold voltage of the Schmitt trigger. At this time, the protection signal OCP is not triggered. When the Ctrl signal disappears after turning on, the capacitor C discharges to the ground through PCH2. After a short delay, the capacitor voltage drops to the inverted threshold voltage of the Schmitt trigger, and at this time, OCP will be triggered.

[0050] For the implementation of the output driving circuit, the prior art usually adopts a cascaded step-by-step amplified inverter chain. After the chip is designed and finalized, the output driving ability of the output driving circuit will be fixed. In practical applications, to prevent the output current of VO from damaging the gate terminal of the external power switch MOSFET to be driven, a resistor is usually connected in series at the VO output to suppress the overshoot of the gate terminal voltage. When the equivalent capacitance of the MOSFET gate terminal is large, the series protection resistor needs to be relatively small; conversely, a larger series protection resistor is required. However, a relatively large series protection resistor will bring two problems. One is that the switching loss on the resistor becomes larger, reducing the efficiency of the driving circuit; the other is that the driving delay is increased, ultimately reducing the system switching frequency. In addition, using a series protection resistor will also increase the design workload of design engineers and reduce the reliability of the entire machine system. The present invention designs a high-efficiency output driving circuit with an adjustable driving ability for the above problems. This circuit can adaptively identify the load size and the frequency of the input control pulse, and adaptively adjust the driving current size.

[0051] As Figure 8 shown, the high-efficiency output driving circuit 4 of the present invention includes: a P-terminal output adjustable buffer driving circuit 41, an N-terminal output adjustable buffer driving circuit 42, a sampling switch SW, a working timing generation circuit 43, a load comparison quantization circuit 44, and a driving current selection circuit 45.

[0052] The output control pulse Din is simultaneously connected to the data input terminals of the adjustable buffer driving circuit 41 at the P terminal output, the adjustable buffer driving circuit 42 at the N terminal output, and the working timing generation circuit 43. The driving signal output terminals of the adjustable buffer driving circuit 41 at the P terminal output and the adjustable buffer driving circuit 42 at the N terminal output are connected to each other as the output terminal of the output driving signal, which is connected to the output driving switch pin VO and connected to the left side of the sampling switch SW; the output driving signal enters the load comparison quantization circuit 44 after being sampled by the sampling switch SW, and obtains the load quantization code Dlot under the control of the reference voltage Vr, the control clock Ck1, and the frequency discrimination code Dfin, and then enters the driving current selection circuit 45. The working timing generation circuit 43 tracks and discriminates the frequency of the output control pulse Din to obtain the Din frequency discrimination code Dfin, and generates non-overlapping high-level control clocks Ck1 and Ck2. The load quantization code Dlot, the control clocks Ck1 and Ck2 enter the driving current selection circuit 45 simultaneously, and obtain n control signals Kp1 to Kpn (controlling the switches in the adjustable buffer driving circuit 41 at the P terminal output) and n switch control signals Kn1 to Knn (controlling the switches in the adjustable buffer driving circuit 42 at the N terminal output); the switch control signals Kp1 to Kpn are respectively connected to the n switch signal input terminals of the adjustable buffer driving circuit 41 at the P terminal output, and the switch control signals Kn1 to Knn are respectively connected to the n switch signal input terminals of the adjustable buffer driving circuit 41 at the P terminal output. Where n is any positive integer.

[0053] Figure 9Schematic diagram of the VO output waveform of the above high-efficiency output drive circuit 4 under three different loads. The waveforms from top to bottom correspond to loads of 0.5 nF, 1 nF, and 1.5 nF respectively. After the power supply voltage is powered on, the working timing generation circuit 43 tracks and discriminates the frequency of the output control pulse Din, obtains the frequency discrimination code Dfin, and generates the control clocks Ck1 and Ck2. When the Ck1 clock is valid, the load comparison and quantization circuit 44 will generate a set of default load quantization codes Dlot_pre according to the output drive signal VO sampled by the sampling switch SW, the reference voltage Vr, and the status of the frequency discrimination code Dfin, and enter the drive current selection circuit 45. The drive current selection circuit 45 will output a set of default switch control signals Kp1_pre~Kpn_pre (controlling the switches in the P-terminal output adjustable buffer drive circuit 41) and Kn1_pre~Knn_pre (controlling the switches in the N-terminal output adjustable buffer drive circuit 42). The output drive signal VO will drive the external load under the action of the default drive current Iout_pre and gradually increase the voltage of the output drive signal VO; when the Ck1 clock ends, the load quantization code Dlot_pre will be adjusted according to the magnitude of the output drive signal VO at this time to obtain the adjusted load quantization code Dlot_lock and remain unchanged; when the Ck2 clock is valid, the drive current selection circuit 45 will output a new set of switch control signals Kp1_lock~Kpn_lock (controlling the switches in the P-terminal output adjustable buffer drive circuit 41) and Kn1_lock~Knn_lock (controlling the switches in the N-terminal output adjustable buffer drive circuit 42) according to the load quantization code Dlot_lock. The output drive signal VO will drive the external load under the action of the new drive current Iout_lock and quickly increase the voltage of the output drive signal VO to the power supply voltage VCC; when the Ck2 clock ends, the load quantization code Dlot will be cleared, and the output switch control signals Kp1~Kpn of the drive current selection circuit 45 will be cleared synchronously (turn off the switches in the P-terminal output adjustable buffer drive circuit 41), and at the same time, the switch control signals Kn1~Knn will be turned on (turn on the switches in the N-terminal output adjustable buffer drive circuit 42). The output drive signal VO will be quickly pulled from the power supply voltage VCC to the ground voltage GND, thereby turning off the external load power device.

[0054] During the above working process, when the Ck1 clock is valid, the output driving signal VO will drive the external load under the action of the default driving current Iout_pre, and the voltage of the output driving signal VO will gradually increase. For different external loads, the output driving signal VO will have different dv / dt changes. For a fixed output driving current Iout_pre, obviously, the larger the load capacitance driven, the lower the rising slope of the output driving signal VO. At the end of the Ck1 clock, the voltage of the output driving signal VO is inversely proportional to the load capacitance. That is, the voltage of the output driving signal VO when the load is 0.5 nF should be 3 times that when the load is 1.5 nF. Therefore, under the condition of a fixed driving current, according to the voltage of the output driving signal VO at the end of the Ck1 clock, the size of the output driving load can be determined, and the size of the output driving load is quantified by the load comparison quantization circuit 44 to obtain the load quantization code Dlot_lock. When the Ck2 clock is valid, the driving current selection circuit 45 will output a new set of switch control signals according to the load quantization code Dlot_lock, and the output driving signal VO will drive the external load under the action of the new driving current Iout_lock, and the voltage of the output driving signal VO will quickly rise to the power supply voltage VCC. When the load quantization code Dlot_lock indicates that the external load is large, the driving current selection circuit 45 will output a set of larger switch control signals, so that the output driving signal VO outputs a larger output driving current Iout_lock; when the load quantization code Dlot_lock indicates that the external load is small, the driving current selection circuit 45 will output a set of smaller switch control signals, so that the output driving signal VO outputs a smaller output driving current Iout_lock.

[0055] Figure 10This is the circuit diagram of the embodiment of the adjustable buffer driving circuit 41 at the P terminal of the present invention. The adjustable buffer driving circuit 41 at the P terminal includes: an inverter chain, n P-terminal output inverter control switches Sp1 to Spn, n P-terminal output inverters Invpk_1 to Invpk_n, and n P-terminal output PMOS transistors Mp1 to Mpn. The input terminal of the inverter chain is connected to the output control pulse Din, and the output terminals of the inverter chain are respectively connected to the input terminals of the n P-terminal output inverters Invpk_1 to Invpk_n through the n P-terminal output inverter control switches Sp1 to Spn, that is: the control switch Sp1 is connected to the input terminal of the inverter Invpk_1, the control switch Sp2 is connected to the input terminal of the inverter Invpk_2, and the control switch Spn is connected to the input terminal of the inverter Invpk_n; the output terminals of the n P-terminal output inverters Invpk_1 to Invpk_n are respectively connected to the gate terminals of the n P-terminal output PMOS transistors Mp1 to Mpn, that is: the output of the inverter Invpk_1 is connected to the gate terminal of the PMOS transistor Mp1, the output of the inverter Invpk_2 is connected to the gate terminal of the PMOS transistor Mp2, and the output of the inverter Invpk_n is connected to the gate terminal of the PMOS transistor Mpn; the source terminals of the above n P-terminal output PMOS transistors Mp1 to Mpn are simultaneously connected to the power supply voltage VCC. The n P-terminal output inverter control switches Sp1 to Spn are respectively controlled by the switch control signals Kp1 to Kpn.

[0056] Figure 11 This is the circuit diagram of the embodiment of the adjustable buffer driving circuit 42 at the N terminal of the present invention. The adjustable buffer driving circuit 42 at the N terminal includes: an inverter chain, n N-terminal output inverter control switches Sn1 to Snn, n N-terminal output inverters Invnk_1 to Invnk_n, and n N-terminal output NMOS transistors Mn1 to Mnn. Its circuit structure is similar to that of the adjustable buffer driving circuit 41 at the P terminal, and will not be described in detail here. The input terminal of its inverter chain is also connected to the output control pulse Din, the source terminals of the n N-terminal output NMOS transistors Mn1 to Mnn are simultaneously connected to the ground voltage GND, and the n N-terminal output inverter control switches Sn1 to Snn are respectively controlled by the switch control signals Kn1 to Knn.

[0057] Figure 10 and Figure 11 The drain terminals of the n P-terminal output PMOS transistors Mp1 to Mpn and the drain terminals of the n N-terminal output NMOS transistors Mn1 to Mnn in are connected together to generate the output driving signal VO.

[0058] Figure 12 For the present invention Figure 8Block diagram of the working timing generation circuit 43. The working timing generation circuit 43 includes: an oscillator 121, a pulse width counter 122, a counting period selection circuit 123, a comprehensive counter 124, a first clock waveform generation circuit 125, and a second clock waveform generation circuit 126.

[0059] The oscillator 121 generates an OSC signal and is connected to the pulse width counter 122 and the comprehensive counter 124. The output control pulse Din is simultaneously connected to the pulse width counter 122 and the comprehensive counter 124. The pulse width counter 122 counts the pulse time width of the output control pulse Din according to the OSC signal, tracks and discriminates the magnitude of the counted pulse time width, and performs comparison and quantization to obtain a frequency discrimination code Dfin. The frequency discrimination code Dfin then enters the counting period selection circuit 123 to generate a comprehensive counter mode selection signal sel0. The comprehensive counter 124 generates a clock control signal ct1 and a clock control signal ct2 respectively according to the comprehensive counter mode selection signal sel0, the OSC signal, and the output control pulse Din. The clock control signal ct1 enters the first clock waveform generation circuit 125 to output a control clock Ck1. The clock control signal ct2 enters the second clock waveform generation circuit 126 to output a control clock Ck2.

[0060] The above-mentioned working timing generation circuit 43 can generate different Dfin codes according to the pulse width of the output control pulse Din to adjust the output clock frequencies of the control clock Ck1 and the control clock Ck2, thereby adjusting the load detection time during the effective period of the control clock Ck1 and improving the detection accuracy. For example, for a 2-bit Dfin code, when Dfin code = "11", it means that the input pulse width is very wide, the switching frequency of the output control pulse Din is very low, and the output clocks of the control clock Ck1 and the control clock Ck2 can output the control timing with a long clock period. When Dfin code = "00", it means that the input pulse width is very narrow, the switching frequency of the output control pulse Din is very high, and the output clocks of the control clock Ck1 and the control clock Ck2 need to output the control timing with the shortest clock period.

[0061] Figure 13 For Figure 8Structural block diagram of load comparison quantization circuit 44, the circuit includes: quantization voltage generation circuit 131, high / low speed mode selection circuit 132, N comparators, error filtering circuit 133, path selection circuit 134, serial shift register 135, serial / parallel conversion circuit 136 and M-bit buffer output circuit 137. The quantization voltage generation circuit 131 converts the reference voltage Vr into N quantization reference voltages Vr1~VrN under the control of the control clock Ck1, and the N quantization reference voltages Vr1~VrN are respectively connected to the reference voltage input terminals of the N comparators; the detection voltage input terminals of the N comparators are all connected to the output drive signal VO, and the N comparators compare the output drive signal VO with the N quantization reference voltages Vr1~VrN respectively to obtain N-bit quantization values D1~DN; the N-bit quantization values enter the error filtering circuit 133 and output an N-bit quantization code Dlo to the path selection circuit 134. The high / low speed mode selection circuit 132 changes the mode control signal mod according to the magnitude of the frequency discrimination code Dfin. The mode control signal mod is respectively connected to the quantization voltage generation circuit 131, the N comparators, the error filtering circuit 133 and the path selection circuit 134. The mode control signal mod can change the mode of the load comparison quantization circuit 44, and finally change the speed and power consumption of the load comparison quantization circuit 44.

[0062] The path selection circuit 134 selects the signal path of the N-bit quantization code Dlo under the control of the mode control signal mod. The high-speed path output port of the path selection circuit 134 is N-bit parallel data, which is directly output to the first data input port of the M-bit buffer output circuit 137. The low-speed path output port of the path selection circuit 134 is 1-bit serial data, which first enters the serial shift register 135, and then passes through the serial / parallel conversion circuit 136 to output an M-bit parallel quantization code Dlp, which is connected to the second data input port of the M-bit buffer output circuit 137.

[0063] The working modes of the load comparison quantization circuit 44 include two types: high-speed mode and low-speed mode. When in the high-speed mode, the quantization voltage generation circuit 131 outputs N quantization reference voltages Vr1 to VrN simultaneously under the control of the control clock Ck1. N comparators compare the output driving signal VO with the N quantization reference voltages Vr1 to VrN simultaneously to obtain the quantization values D1 to DN output in parallel of N bits, and then pass through the error filtering circuit 133 to obtain the N-bit quantization code Dlo. At this time, the N-bit quantization code Dlo is N-bit parallel data. After being output from the high-speed path output port of the path selection circuit 134, it is directly output to the first data input port of the M-bit buffer output circuit 137. The M-bit buffer output circuit 137 outputs the final M-bit load quantization code Dlot under the control of the control clock Ck1. When in the low-speed mode, only the first comparator in the N comparators works, and the remaining N - 1 comparators are in a sleep state. The quantization voltage generation circuit 131 outputs the N quantization reference voltages Vr1 to VrN in sequence according to the time sequence from the Vr1 output port under the control of the control clock Ck1. The first comparator compares the output driving signal VO with the N quantization reference voltages Vr1 to VrN output by Vr1 in sequence according to the time sequence, and outputs the quantization values D1 to DN output in series of N bits in sequence at the output port, and then passes through the error filtering circuit 133 to obtain the N-bit quantization code Dlo. At this time, the N-bit quantization code Dlo is 1-bit serial data. After being output from the low-speed path output port of the path selection circuit 134, it first enters the serial shift register 135, and then passes through the serial / parallel conversion circuit 136 to obtain the quantization code Dlp of M bits in parallel, and then outputs it to the second data input port of the M-bit buffer output circuit 137. The M-bit buffer output circuit 137 obtains the final M-bit load quantization code Dlot under the control of the control clock Ck1.

[0064] The load comparison quantization circuit 44 adopts two modes of high speed and low speed to save the power consumption of the circuit. The above-mentioned N reference voltages Vr1 to VrN can be set at uniform intervals using thermometer codes or set with different binary weights. Therefore, in actual implementation, the appropriate comparator type and combination strategy can be selected according to the requirements of the driving chip application system. Due to the existence of certain offsets in the comparators, and the higher the working speed of the comparators, the more serious the offsets. Therefore, it is necessary to filter the errors of the N-bit quantization values D1 to DN, and the implementation strategies of the error filtering circuit 133 are very different. If the N comparators work in parallel, a digital algorithm for offset calibration of Flash ADC comparators needs to be used for error filtering; if a single comparator is multiplexed for work, a digital algorithm for offset calibration of SAR ADC needs to be used for error filtering.

[0065] The above are only the preferred embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principle of the present invention shall be included within the protection scope of the present invention.

Claims

1. A high-efficiency gate driving circuit, characterized in that it comprises: Input receiving circuit, high-voltage bandgap reference, internal power generation circuit, high-efficiency output driving circuit, overcurrent protection circuit, overtemperature protection circuit, undervoltage protection circuit, oscillator, waveform modulation circuit, control logic, and error amplifier; it also includes 5 external pins, namely: chip power supply pin VDD, external input pulse pin INX, current detection pin CS, output driving switch pin VO, and ground pin GND; The input terminal of the input receiving circuit is connected to the external input pulse pin INX, the output terminal of the input receiving circuit is connected to the input terminal of the waveform modulation circuit, the input terminal of the waveform modulation circuit is also connected to the oscillator, and the output terminal of the waveform modulation circuit outputs a modulated pulse signal DX; the input terminal of the error amplifier is connected to the current detection pin CS, and the error amplifier amplifies the externally sampled current to obtain a current input signal CSIN, which is connected to the overcurrent protection circuit; The high-voltage bandgap reference is used to provide a reference voltage Vref; the internal power generation circuit is used to generate an internal power supply voltage VCC and various bias signals according to the reference voltage Vref for use by other circuits within the chip; The overcurrent protection circuit, overtemperature protection circuit, and undervoltage protection circuit respectively generate an overcurrent protection signal OCP, an overtemperature protection signal OTP, and an undervoltage protection signal UVLO based on the reference voltage Vref; the overcurrent protection signal OCP, overtemperature protection signal OTP, undervoltage protection signal UVLO, and modulated pulse signal DX are all connected to the control logic, and after processing, an output control pulse Din is obtained; the output control pulse Din is connected to the high-efficiency output driving circuit, and after being buffered and driven by the high-efficiency output driving circuit, an output driving signal is obtained and connected to the output driving switch pin VO; The high-efficiency output driving circuit includes: a P-terminal output adjustable buffer driving circuit, an N-terminal output adjustable buffer driving circuit, a sampling switch SW, a working timing generation circuit, a load comparison quantization circuit, and a driving current selection circuit; The output control pulse Din is simultaneously connected to the data input terminals of the adjustable buffer driving circuit at the P terminal, the adjustable buffer driving circuit at the N terminal, and the working timing generation circuit; the driving signal output terminals of the adjustable buffer driving circuit at the P terminal and the adjustable buffer driving circuit at the N terminal are connected to each other as the output terminal of the output driving signal, and are connected to the input terminal of the load comparison quantization circuit through the sampling switch SW; the working timing generation circuit tracks and discriminates the frequency of the output control pulse Din to obtain the frequency discrimination code Dfin, and generates the non-overlapping high-level control clock Ck1 and control clock Ck2; among them, the frequency discrimination code Dfin is connected to the load comparison quantization circuit, the control clock Ck1 is connected to the load comparison quantization circuit and the drive current selection circuit, and the control clock Ck2 is connected to the drive current selection circuit; the output driving signal enters the load comparison quantization circuit after being sampled by the sampling switch SW, and obtains the load quantization code Dlot under the control of the reference voltage Vr, the control clock Ck1, and the frequency discrimination code Dfin, and is connected to the drive current selection circuit; the load quantization code Dlot, the control clock Ck1, and the control clock Ck2 enter the drive current selection circuit simultaneously to obtain n switch control signals Kp1~Kpn and n switch control signals Kn1~Knn; among them, the switch control signals Kp1~Kpn are respectively connected to the n switch signal input terminals of the adjustable buffer driving circuit at the P terminal, and the switch control signals Kn1~Knn are respectively connected to the n switch signal input terminals of the adjustable buffer driving circuit at the P terminal; n is any positive integer.

2. The high-efficiency gate driving circuit according to claim 1, wherein The over-temperature protection circuit includes: NPN transistor Q61, NPN transistor Q60, resistor R61, resistor R62, PMOS transistor P60, inverter Inv60, capacitor C60, and Schmitt trigger Schmitt; the collector of NPN transistor Q61 is connected to the internal power supply voltage VCC, the emitter of NPN transistor Q61 is connected to the upper end of resistor R61, and the base of NPN transistor Q61 is connected to the reference voltage Vref; the lower end of resistor R61 is connected to the upper end of resistor R61 and the base of NPN transistor Q60, and the collector of NPN transistor Q60 is connected to the upper end of capacitor C60, the output terminal of inverter Inv60, the drain of PMOS transistor P60, and the input terminal of Schmitt trigger Schmitt; the source of PMOS transistor P60 is connected to the internal power supply voltage VCC, and the gate of PMOS transistor P60 is connected to the bias voltage Vb6; the signal Ctrl connected to the input terminal of inverter Inv60 is the global control signal of the chip; the over-temperature protection signal OTP is output from the output terminal of Schmitt trigger Schmitt; the lower end of resistor R62, the lower end of capacitor C60, and the emitter of NPN transistor Q60 are all connected to the ground voltage GND.

3. The high-efficiency gate driving circuit according to claim 1, wherein After the power supply voltage is powered on, the working timing generation circuit tracks and discriminates the frequency of the output control pulse Din to obtain the frequency discrimination code Dfin, and generates the control clock Ck1 and the control clock Ck2; when the Ck1 clock is valid, the load comparison and quantization circuit will, according to the output drive signal VO sampled by the sampling switch SW, the reference voltage Vr, and the state of the frequency discrimination code Dfin, first generate a set of default load quantization codes Dlot_pre and enter the drive current selection circuit. The drive current selection circuit will output a set of default switch control signals Kp1_pre~Kpn_pre and switch control signals Kn1_pre~Knn_pre. The output drive signal will drive the external load under the action of the default drive current and gradually increase the voltage of the output drive signal; when the Ck1 clock ends, the load quantization code Dlot_pre will be adjusted according to the magnitude of the output drive signal at this time to obtain the adjusted load quantization code Dlot_lock and remain unchanged; when the Ck2 clock is valid, the drive current selection circuit will output a new set of switch control signals Kp1_lock~Kpn_lock and switch control signals Kn1_lock~Knn_lock according to the load quantization code Dlot_lock. The output drive signal will drive the external load under the action of the new drive current and quickly increase the voltage to the voltage VCC; when the Ck2 clock ends, the load quantization code Dlot will be cleared, and the switch control signals Kp1~Kpn output by the drive current selection circuit will be cleared synchronously, turning off the control switches of the n P-terminal output inverters in the P-terminal output adjustable buffer drive circuit. At the same time, the switch control signals Kn1~Knn output by the drive current selection circuit are valid, turning on the control switches of the n N-terminal output inverters in the N-terminal output adjustable buffer drive circuit, and the output drive signal will quickly pull down from the voltage VCC to the ground voltage GND, thereby turning off the external load power device.

4. The high-efficiency gate driving circuit according to claim 3, wherein The P-terminal output adjustable buffer drive circuit includes: an inverter chain, the input end of the inverter chain is connected to the output control pulse Din, the output end of the inverter chain is respectively connected to the input ends of n P-terminal output inverters through n P-terminal output inverter control switches, the output ends of the n P-terminal output inverters are respectively connected to the gate ends of n P-terminal output PMOS transistors, and the source ends of the n P-terminal output PMOS transistors are simultaneously connected to the internal power supply voltage VCC; the n P-terminal output inverter control switches are respectively controlled by the switch control signals Kp1~Kpn; The N-terminal output adjustable buffer driving circuit includes: an inverter chain, the input end of the inverter chain is connected to the output control pulse Din, the output end of the inverter chain is respectively connected to the input ends of n N-terminal output inverters through n N-terminal output inverter control switches, the output ends of the n N-terminal output inverters are respectively connected to the gate ends of n N-terminal output NMOS transistors, and the source ends of the n N-terminal output NMOS transistors are simultaneously connected to the ground voltage GND; the n N-terminal output inverter control switches are respectively controlled by the switch control signals Kn1 to Knn; The drain ends of the n P-terminal output PMOS transistors are connected together with the drain ends of the n N-terminal output NMOS transistors, one side is connected to the input end of the load comparison quantization circuit through the sampling switch SW, and is also connected to the output drive switch pin VO.

5. The high-efficiency gate driving circuit according to claim 3, characterized in that, The working timing generation circuit includes: an oscillator, a pulse width counter, a counting period selection circuit, a comprehensive counter, a first clock waveform generation circuit and a second clock waveform generation circuit; the OSC signal generated by the oscillator is connected to the pulse width counter and the comprehensive counter, and the output control pulse Din is simultaneously connected to the pulse width counter and the comprehensive counter; the pulse width counter counts the pulse time width of the output control pulse Din according to the OSC signal, and performs tracking discrimination and comparison quantization on the counted pulse time width size to output the frequency discrimination code Dfin; the frequency discrimination code Dfin is connected to the counting period selection circuit to generate the comprehensive counter mode selection signal sel0; the comprehensive counter generates the clock control signal ct1 and the clock control signal ct2 according to the mode selection signal sel0, the OSC signal and the output control pulse Din; finally, the clock control signal ct1 and the clock control signal ct2 are respectively connected to the first clock waveform generation circuit and the second clock waveform generation circuit, and the first clock waveform generation circuit and the second clock waveform generation circuit respectively output the final control clocks Ck1 and Ck2.

6. The high-efficiency gate driving circuit according to claim 3, wherein, The load comparison quantization circuit includes: a quantization voltage generation circuit, a high / low speed mode selection circuit, N comparators, an error filtering circuit, a path selection circuit, a serial shift register, a serial-to-parallel conversion circuit, and an M-bit buffer output circuit; the input end of the quantization voltage generation circuit is connected to the reference voltage Vr, the control clock Ck1, and the mode control signal mod output by the high / low speed mode selection circuit. The quantization voltage generation circuit converts the reference voltage Vr into N quantization reference voltages Vr1 to VrN under the control of the control clock Ck1, and respectively connects them to the reference voltage input ends of the N comparators; the detection voltage input ends of the N comparators are all connected to the output drive switch pin VO. The N comparators respectively compare the output drive signal with the N quantization reference voltages Vr1 to VrN, and output N-bit quantization values D1 to DN; then the N-bit quantization values D1 to DN enter the error filtering circuit and output an N-bit quantization code Dlo; the high / low speed mode selection circuit outputs the mode control signal mod according to the magnitude of the frequency discrimination code Dfin, thereby changing the mode of the load comparison quantization circuit to change the speed and power consumption of the load comparison quantization circuit. The mode control signal mod is respectively connected to the quantization voltage generation circuit, the N comparators, the error filtering circuit, and the path selection circuit; the path selection circuit selects the signal path of the N-bit quantization code Dlo under the control of the mode control signal mod; the high-speed path output port of the path selection circuit is N-bit parallel data, which is directly output to the first data input port of the M-bit buffer output circuit. The low-speed path output port of the path selection circuit is 1-bit serial data, which is first connected to the serial shift register, and the output of the serial shift register then enters the serial-to-parallel conversion circuit to obtain M-bit parallel quantization code Dlp, which is connected to the second data input port of the M-bit buffer output circuit; the M-bit buffer output circuit outputs the final M-bit load quantization code Dlot under the control of the control clock Ck1; where M and N are both integers greater than 1.

7. The high-efficiency gate driving circuit according to claim 6, wherein The load comparison quantization circuit includes a high-speed mode and a low-speed mode; The working mode of the high-speed mode is as follows: the quantization voltage generation circuit simultaneously outputs N quantization reference voltages under the control of the control clock Ck1. The N comparators respectively compare the output drive signal with the N quantization reference voltages simultaneously, and output N-bit parallel quantization values D1 to DN. Then, an N-bit quantization code Dlo is obtained through the error filtering circuit; at this time, the N-bit quantization code Dlo is N-bit parallel data, which is directly output to the first data input port of the M-bit buffer output circuit through the high-speed path output port of the path selection circuit. The M-bit buffer output circuit outputs the final M-bit load quantization code Dlot under the control of the control clock Ck1; The low-speed mode works as follows: only the first comparator among the N comparators works, and the remaining N-1 comparators are in a sleep state. The quantization voltage generation circuit sequentially outputs N quantization reference voltages from one output port in chronological order under the control of the control clock Ck1. The first comparator sequentially compares the output drive signal with the N quantization reference voltages in chronological order, and sequentially outputs N-bit serial quantization values D1~DN at the output port of the first comparator. Then, the N-bit quantization code Dlo is obtained through the error filtering circuit. At this time, the N-bit quantization code Dlo is 1-bit serial data, which sequentially enters the serial shift register through the low-speed path output port of the path selection circuit. The output of the serial shift register then enters the serial-to-parallel conversion circuit to obtain an M-bit parallel quantization code Dlp, which is output to the second data input port of the M-bit buffer output circuit. The M-bit buffer output circuit obtains the final M-bit load quantization code Dlot under the control of the control clock Ck1.

8. The high-efficiency gate driving circuit according to claim 1, wherein After the chip power supply pin VDD meets the power-on requirements, the high-voltage bandgap reference first works normally and provides a 1.2V reference voltage Vref. The input receiving circuit receives an external input pulse and converts it into a logic level VIN with a high level of VCC. Then, the logic level VIN is modulated with the oscillation clock generated by the oscillator to obtain a modulation pulse signal DX. The error amplifier amplifies the external sampling current to obtain a current input signal CSIN, and the current input signal CSIN enters the overcurrent protection circuit and is compared to obtain an overcurrent protection signal OCP. The control logic performs logical processing on the overcurrent protection signal OCP, the overtemperature protection signal OTP, the undervoltage protection signal UVLO, and the modulation pulse signal DX, and outputs an output control pulse Din for output drive. The output control pulse Din is then buffered and driven by the high-efficiency output drive circuit to obtain an output drive signal, which is output through the output drive switch pin VO.

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