Method for Implementing Testability of Asynchronous Circuits

Abstract

The present invention provides a method for implementing testability of an asynchronous circuit, comprising: constructing an initial asynchronous circuit at a trigger transmission level, and performing testability modeling on the initial asynchronous circuit; obtaining a target asynchronous circuit by replacing the triggers in the initial asynchronous circuit after testability modeling; performing a primary formal verification on the functional consistency of the target asynchronous circuit and the initial asynchronous circuit; chaining the target asynchronous circuit after the primary formal verification according to a scan chain, and performing a secondary formal verification on the target asynchronous circuit before chaining and the target asynchronous circuit after chaining; simulating according to a test vector of the target asynchronous circuit after the secondary formal verification, and outputting the result of the primary formal verification, the result of the secondary formal verification, and the simulation verification result. The method is non-invasive, ensures the integrity of the original circuit, is easy to develop and transplant, and can be widely used in the field of integrated circuit technology.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuits, and in particular to a method for realizing testability of asynchronous circuits. Background Art

[0002] In recent years, integrated circuits have continued to scale, and process technology has become increasingly advanced, reaching design nodes such as three and five nanometers. At these advanced design nodes, reducing power consumption is a major challenge for both academia and industry. Traditional synchronous circuits have reached a research bottleneck in reducing power consumption. Against this backdrop, asynchronous circuit design has re-emerged in the research field. Its event-driven nature, in particular, offers low power consumption and strong robustness, making it well-suited for chip design in these emerging applications.

[0003] Testability is also a major concern in the industry today. As integrated circuits become larger and smaller, the probability of manufacturing defects increases during chip production. For synchronous circuit chips, testability design is already established, supported by corresponding electronic design automation tools and standardized processes. However, the reliability of asynchronous circuits, a new type of circuit, has been questioned, with concerns that they may not be as stable as synchronous designs. Therefore, research on testability design for asynchronous circuits is urgent. Asynchronous circuits are a relatively underrepresented area of testability, which is a major bottleneck in their industrialization.

[0004] However, among the relevant technical solutions that have been proposed so far, the asynchronous testability design method provided is too targeted and cannot be effectively designed using existing traditional electronic design automation tools, resulting in the industry being unable to effectively apply this testability design method. Summary of the Invention

[0005] In view of this, in order to at least partially solve the above-mentioned technical problems or one of the defects, the purpose of an embodiment of the present invention is to provide a method for implementing the testability of an asynchronous circuit, and to perform testability design on the control path part and the data path part of the Click circuit in the asynchronous circuit, which can be extended to any circuit with a structure similar to that of the Click circuit.

[0006] On the one hand, the technical solution of the present application provides a method for implementing testability of an asynchronous circuit, comprising the following steps:

[0007] constructing an initial asynchronous circuit of a trigger transmission level and performing testability modeling on the initial asynchronous circuit;

[0008] Obtaining a target asynchronous circuit by replacing the flip-flops in the initial asynchronous circuit after testability modeling;

[0009] Performing an initial formal verification on functional consistency between the target asynchronous circuit and the initial asynchronous circuit, and outputting a result of the initial formal verification;

[0010] Chaining the target asynchronous circuit after the initial formal verification according to the scan chain, performing a secondary formal verification on the target asynchronous circuit before the chaining and the target asynchronous circuit after the chaining, and outputting a result of the secondary formal verification;

[0011] Performing simulation based on the test vectors of the target asynchronous circuit after completing the secondary formal verification, and outputting simulation verification results;

[0012] The testability modeling of the initial asynchronous circuit comprises the following steps:

[0013] Constructing a control path module of the initial asynchronous circuit and constructing a control path testability module using triggers according to a capture process of a logic operation result;

[0014] A data path module of the initial asynchronous circuit is constructed, and according to the clock driving process of the data path and the control path, a data path testability module is constructed using a data selector and an external clock.

[0015] In a feasible embodiment of the present application, the construction of the control path module of the initial asynchronous circuit and the construction of the control path testability module using triggers according to the capture process of the logic operation result include:

[0016] Construct a control path module for the initial asynchronous circuit; the control path module includes a phase-decoupled Click circuit; wherein the Click circuit is used to implement a handshake protocol for two-phase bundled data; the Click circuit includes an XOR gate, an XNOR gate, and an AND gate; wherein the XOR gate, the XNOR gate, and the AND gate are used to generate a local pulse signal; the local pulse signal serves as a clock signal for a data path trigger of the initial asynchronous circuit.

[0017] Construct a control path testability module for the initial asynchronous circuit; wherein, the control path testability module includes the XOR gate, XNOR gate, AND gate and capture trigger of the Click circuit; the capture trigger is used to capture the logic operation result output from the AND gate.

[0018] In a feasible embodiment of the solution of the present application, the control path testability module for constructing the initial asynchronous circuit includes:

[0019] Adding the control path testability module to the path generating the local pulse;

[0020] The control path testability module captures and stores data according to the clock signal. The capture trigger stores data on a captured first value at this level. The first value is used to capture the result of an event-driven asynchronous action and is used to cache the data and start the next handshake protocol via a phase trigger and a data trigger when the next level clock arrives, thereby forming a shift-in and shift-out relationship.

[0021] The shift-in and shift-out relationship is used to describe the first value captured by each stage before the last stage outputs.

[0022] In a feasible embodiment of the solution of the present application, the data path module of the initial asynchronous circuit is constructed, and according to the clock driving process of the data path and the control path, a data path testability module is constructed using a data selector and an external clock, including:

[0023] Adding the data path testability module to the path for generating local pulses;

[0024] The data selector selects the external clock and the original Click pulse signal in the test mode; the data selector selects the external clock in the test mode and selects the original Click pulse signal in the functional mode;

[0025] The selected signal drives the original asynchronous circuit for clock according to the mode requirement, and performs the testability output of the event-driven asynchronous action in the test mode or the event-driven asynchronous action in the functional mode.

[0026] In a feasible embodiment of the solution of the present application, the initial asynchronous circuit is used to extend to a conditional selection multiplexer and demultiplexer of a control path; the control path module for constructing the initial asynchronous circuit includes:

[0027] The conditional selection multiplexer and / or the demultiplexer of the control path are analogized by the Click circuit, and a control path module of the conditional selection multiplexer and / or the demultiplexer is obtained by modeling.

[0028] In a feasible embodiment of the solution of the present application, the data path module for constructing the initial asynchronous circuit and constructing a data path testability module using a data selector and an external clock according to the clock driving process of the data path and the control path further include:

[0029] A clock bypass circuit is constructed by combining an OR gate and an AND gate, or a clock bypass circuit is constructed by a data selector;

[0030] The global clock and / or the internal clock are bypassed according to the clock bypass circuit to complete the testability modeling of the data path.

[0031] In a feasible embodiment of the solution of the present application, the process of constructing the initial asynchronous circuit includes:

[0032] Replace the global clock pulse in the synchronous circuit with an event-driven click pulse;

[0033] Bypass the Click pulse and add a scan clock pulse;

[0034] Adding a D-type flip-flop to the circuit after adding the scan clock pulse, we get an initial asynchronous circuit with testability.

[0035] The step of obtaining a target asynchronous circuit by replacing a trigger in the initial asynchronous circuit after testability modeling includes:

[0036] The D-type flip-flops in the control path and the data path are replaced with scan flip-flops to obtain the target asynchronous circuit.

[0037] In a feasible embodiment of the solution of the present application, chaining the target asynchronous circuit after the initial formal verification according to the scan chain, and performing a secondary formal verification on the target asynchronous circuit before the chaining and the target asynchronous circuit after the chaining, includes:

[0038] Setting the test mode type to constant 1, so that the scan clock pulse is effective, and the control path testability module and the data path testability module are enabled;

[0039] The scan enable type is set to scan enable, so that the scan trigger uses the data input from the scan input port in the shift mode, and uses the data input from the data port in the capture mode.

[0040] In a feasible embodiment of the solution of the present application, chaining the target asynchronous circuit after the initial formal verification according to the scan chain, and performing a secondary formal verification on the target asynchronous circuit before the chaining and the target asynchronous circuit after the chaining, further includes:

[0041] In the shift input stage, the preset value of the first test vector is assigned to the scan trigger, the preset value in the scan trigger is shifted according to the clock signal, and a combinational logic operation is performed on the shifted preset value;

[0042] In a data capture phase, the result of the combinational logic operation is captured according to the clock signal and through the control path testability module;

[0043] In the shift output stage, according to the clock signal, the result of the combinational logic operation is transmitted to the next stage trigger of the scan chain through the scan chain, and the shift output value is output;

[0044] The preset value of the next test vector is shifted into the front end of the scan chain, and the shift input stage, the data capture stage and the shift output stage are repeated until all test vectors are shifted in and out.

[0045] In some feasible implementations, simulating the target asynchronous circuit according to the test vector after completing the secondary formal verification and outputting the simulation verification result includes:

[0046] All shifted output values are compared with the expected values represented by the test vectors to obtain the simulation verification results.

[0047] The advantages and beneficial effects of the present invention will be partially given in the following description, and the rest can be understood through the specific embodiments of the present invention:

[0048] The technical solution of this application adds an additional dedicated clock and bypass logic to the data path part, and this dedicated clock and bypass logic are only effective in test mode. The addition of this dedicated clock and bypass logic makes the majority of the data path and control path of the asynchronous circuit from being unable to be recognized by traditional electronic design automation tools to being recognized by traditional electronic design automation tools, so that the control path and data path of the asynchronous circuit can be optimized and inserted for testability using traditional electronic design automation tools, ensuring the testability of the overall circuit and facilitating the traceability of subsequent problems. For the other small part of the control path that is not testable, the technical solution of this application adds an additional trigger and related logic to the control path part, and this trigger is only effective in test mode. The addition of this trigger makes this small part of the control path of the asynchronous circuit that is not testable from being unable to be recognized by traditional electronic design automation tools to being recognized by traditional electronic design automation tools, so that the circuit optimization and testability design of the asynchronous circuit can be inserted using traditional electronic design automation tools, and ensuring the testability of the control path, so as to improve the testability of the overall circuit and facilitate the traceability of subsequent problems. The data path part and the control path part of the technical solution of the present application effectively improve the efficiency of the testability design of the asynchronous circuit, and the method is non-invasive, ensuring the integrity of the original circuit, and is easy to develop and transplant. BRIEF DESCRIPTION OF THE DRAWINGS

[0049] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0050] Figure 1 A system for implementing the testability design of asynchronous circuits provided in the technical solution of this application;

[0051] Figure 2 A flowchart of the steps of the method for implementing testability of asynchronous circuits provided in the technical solution of this application;

[0052] Figure 3 Schematic diagram of the phase decoupling Click template structure provided in the relevant technical solution;

[0053] Figure 4 This is a schematic diagram of the overall position of the testability design module dedicated to the control circuit in the technical solution of this application;

[0054] Figure 5 The internal details of the testability design module specifically used for the control circuit in the technical solution of this application;

[0055] Figure 6 This is a diagram showing the structure of the CLICK2I10 (multiplexer) (two inputs, one output) in the technical solution of this application and its connection relationship with the dedicated module;

[0056] Figure 7 This is a diagram of the structure of CLICK1I2O (demultiplexer) (one input, two outputs) in the technical solution of this application and a schematic diagram of its connection relationship with the dedicated module;

[0057] Figure 8 This is a schematic diagram of the modeling of the asynchronous data path module in the technical solution of this application;

[0058] Figure 9 A schematic diagram of the dedicated module and connection relationship designed for the testability of the asynchronous data path in the technical solution of this application;

[0059] Figure 10 A schematic diagram of modeling a synchronous data path module in a related technical solution;

[0060] Figure 11 This is a schematic diagram of a combination of an inverter, an OR gate, and an AND gate in the second clock bypass circuit method of the technical solution of this application;

[0061] Figure 12 Schematic diagram of the relationship between the second clock bypass circuit method and the testability design of the control path in the technical solution of this application

[0062] Figure 13 This is a schematic diagram of the asynchronous pipeline structure in the technical solution of this application;

[0063] Figure 14 This is a schematic diagram of the asynchronous pipeline structure with testability design in the technical solution of this application;

[0064] Figure 15 This is a schematic diagram of the data path testability design principle of the asynchronous circuit in the technical solution of this application;

[0065] Figure 16 This is a schematic diagram of the control path testability design principle of the asynchronous circuit in the technical solution of this application;

[0066] Figure 17 This is a schematic diagram of an embodiment of a sequential pipeline in the technical solution of this application;

[0067] Figure 18 This is a schematic diagram of a non-sequential pipeline embodiment in the technical solution of this application;

[0068] Figure 19 This is a schematic diagram of an embodiment of the conditional selection data flow structure in the technical solution of this application. DETAILED DESCRIPTION

[0069] The embodiments of the present invention are described in detail below. Examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present invention and are not to be construed as limiting the present invention. The step numbers in the following embodiments are provided for ease of explanation only and do not limit the order of the steps. The order of execution of the steps in the embodiments can be adaptively adjusted according to the understanding of those skilled in the art.

[0070] Prior to this application, prior art proposals included numerous asynchronous circuit types, including single-rail, dual-rail, four-phase, two-phase, delay-insensitive, and delay-sensitive circuits. Typical circuit templates include micro-pipeline, mousetrap, and click. In the four-phase handshake protocol, the level signals represent the request and response of control signals, and the control signals must return to zero. In the two-phase handshake protocol, the request and response of control signals are represented by transition edges, with both rising and falling edges being usable. Ideally, the two-phase bundling protocol is faster than the four-phase bundling protocol, but the circuit implementation of event response is often complex. In the dual-rail encoding scheme, each bit is represented by two wires, and the request signal is encoded into the data signal, making it insensitive to line delays. In contrast, the bounded data (BD) encoding scheme includes a validity signal (similar to a clock signal without a period), also known as single-rail encoding, and is delay-sensitive. When the valid signal is valid, data transmission occurs, but when the valid signal is invalid, the data line can experience glitches; n-bit data communication requires n+1 wires.

[0071] In the classification of asynchronous circuits, BD circuits have received considerable attention because they can obtain an area similar to that of synchronous circuits. Among BD circuits, since the requirement of the technical solution of this application is to accelerate industrialization by using electronic design automation tools, one of the asynchronous circuits called Click is adopted in the technical solution of this application. The difference between this circuit and other circuits is that it operates in a manner similar to a synchronous circuit, which will synchronize the asynchronous circuit. It can use today's existing traditional electronic design automation tools to constrain the generation of handshake signals and event-driven pulses of the asynchronous circuit so that the generation of handshake signals and event-driven pulses of the asynchronous circuit can be recognized by traditional electronic design automation tools, and timing analysis can be performed to complete the synthesis and subsequent work of the asynchronous circuit. The advantages of using Click circuits are: 1) The use of traditional electronic design automation tools has lower time and labor costs; 2) The power consumption of asynchronous circuits is reduced; 3) It is beneficial for the industry to carry out synchronous and asynchronous development at the same time and compare the results, thereby transforming synchronization to asynchronousness.

[0072] There are many types of testability design, including scan chains and automatic test vector generation for standard cells, memory built-in self-test (BIST) for memory, and boundary scan for input and output pads, inter-chip interconnects between chips, and printed circuit board interconnects. For asynchronous processors, the difference between asynchronous testability design and synchronous testability design lies only in the differences between synchronous and asynchronous circuits. Therefore, relevant research on scan chains for standard cells is necessary, and other aspects can be used as supplementary. Therefore, the testability solutions described below in the description of the technical solution of this application are all scan chain solutions for standard cells and are no longer emphasized.

[0073] The current mainstream of testability design of asynchronous circuits is to carry out the test on asynchronous circuit templates based on C units. It mainly changes the structure of C units according to the testability design principles and breaks the combinational logic loop of C units to make C units conform to scannable design. Among them, some researchers have tried to use the LSSD method, the L1L2* method, and the data selector-based method. In addition, researchers have also developed special test algorithms or special test tools for asynchronous circuits to make asynchronous circuits more automated. However, the current research methods either design targeted new algorithms or develop targeted new tools, or are invasive and have high performance overhead, and cannot be widely used by the industry. Prior to the technical solution of this application, there was no related technical solution specifically targeting the testability design research of asynchronous circuits using Click templates as asynchronous circuit controllers.

[0074] The testability design implementation architecture of the present invention proposes a testability method architecture implementation method for data modules, ensuring overall test coverage. It also addresses the issue (in existing technical solutions) of testability circuits obstructing control path testing. Regarding control paths, the proposed testability method architecture implementation method improves overall test coverage.

[0075] The testability design implementation method of the asynchronous circuit proposed in the technical solution of this application is based on the Click template. First, Figure 1 As shown, the technical solution of this application provides a system for implementing testability design for asynchronous circuits. Based on this system, a testability design implementation method can be executed. This system is divided into a testability design implementation system for the control path of asynchronous circuits and a testability design implementation system for the data path of asynchronous circuits. Both systems are divided into four modules: an asynchronous circuit control path module and a dedicated module for testability design of the control path; an asynchronous circuit data path module and a dedicated module for testability design of the data path.

[0076] like Figure 2 As shown, the method for implementing testability of an asynchronous circuit provided in the technical solution of this application mainly includes steps S100-S500:

[0077] S100, constructing an initial asynchronous circuit of a trigger transmission level, and performing testability modeling on the initial asynchronous circuit;

[0078] The performing of testability modeling on the initial asynchronous circuit includes steps S110-S120:

[0079] S110, constructing a control path module of the initial asynchronous circuit, and constructing a control path testability module using triggers according to a capture process of a logic operation result;

[0080] S120: Construct a data path module of the initial asynchronous circuit, and construct a data path testability module using a data selector and an external clock according to the clock driving process of the data path and the control path.

[0081] S200, obtaining a target asynchronous circuit by replacing the flip-flops in the initial asynchronous circuit after testability modeling;

[0082] S300, performing an initial formal verification on the functional consistency of the target asynchronous circuit and the initial asynchronous circuit, and outputting a result of the initial formal verification;

[0083] S400, chaining the target asynchronous circuit after the initial formal verification according to the scan chain, performing a secondary formal verification on the target asynchronous circuit before the chaining and the target asynchronous circuit after the chaining, and outputting a result of the secondary formal verification;

[0084] S500 , performing simulation according to the test vector of the target asynchronous circuit after completing the secondary formal verification, and outputting the simulation verification result.

[0085] Specifically in the embodiment, the testability implementation method of the asynchronous circuit is completed based on the testability design process of the synchronous circuit. The synchronous testability design process in the related technical solution is as follows:

[0086] 1.RTL writing;

[0087] 2. Replace triggers during the synthesis phase;

[0088] 3.Formality performs formal verification to verify the functional consistency of RTL and synthesized circuits;

[0089] 4. Chain stage: The scan chain is connected in series according to the chain settings. The shift trigger chain pattern of the scan chain is: scan input - scan type - D type trigger - scan output - scan input - scan type - D type trigger - ...;

[0090] 5.Formality performs formal verification to verify the functional consistency of the circuit before synthesis and after chaining;

[0091] 6. The automatic test vector generation stage generates test vectors based on the chained circuit;

[0092] 7. VCS simulates and verifies the circuit based on the test vectors generated in the automatic test vector generation phase;

[0093] 8.Formality performs formal verification to verify the functional consistency of the circuit before and after synthesis.

[0094] In some feasible implementations, the step S110 of performing testability modeling on the control path of the initial asynchronous circuit may include steps S111-S112:

[0095] S111, constructing a control path module of the initial asynchronous circuit;

[0096] Among them, the control path module includes a phase-decoupled Click circuit; the Click circuit is used to implement a handshake protocol for two-phase bundled data; the Click circuit includes an XOR gate, an XNOR gate and an AND gate; the XOR gate, the XNOR gate and the AND gate are used to generate a local pulse signal; the local pulse signal serves as a clock signal for the data path trigger of the initial asynchronous circuit.

[0097] S112, constructing a control path testability module for the initial asynchronous circuit;

[0098] The control path testability module includes an XOR gate, an XNOR gate, an AND gate, and a capture trigger of the Click circuit; the capture trigger is used to capture the logic operation result output from the AND gate.

[0099] Specifically, in this embodiment, the asynchronous circuit control path testability implementation system modeling module consists of an asynchronous circuit control path module and a control circuit testability-specific module. The asynchronous circuit control path module primarily consists of click circuits, while the asynchronous circuit control circuit testability-specific module primarily consists of triggers specifically added for testability design. In this embodiment, the asynchronous circuit control path testability implementation system can be modeled using the Verilog HDL language.

[0100] Furthermore, the asynchronous control path module modeling part adopts the phase decoupled Click circuit template to implement the handshake protocol of the two-phase bundled data. The Click circuit template structure used in the embodiment is as follows: Figure 3 As shown in the figure, the control path testability design module is mainly composed of triggers, and the circuit used and the connection relationship with the control path of the asynchronous circuit are shown in the figure. Figure 4 shown.

[0101] like Figure 5 As shown in the embodiment, the asynchronous control path module Click template is composed of an XOR gate, an XNOR gate, and an AND gate to generate a local pulse signal. This local pulse signal is a high-pulse Click signal, which serves as the clock signal for the trigger of the asynchronous circuit's data path to capture and store data. It also drives the phase trigger and data trigger to buffer data and initiate the next handshake protocol, completing the event-driven asynchronous operation.

[0102] In an embodiment, the process of constructing the control path testability module of the initial asynchronous circuit mainly includes steps S1121-S1122:

[0103] S1121. Add the control path testability module to the path generating the local pulse;

[0104] S1122. Capture and store data according to the clock signal through the control path testability module;

[0105] The capture trigger stores the captured value at this level. This captured value captures and drives the result of the event-driven asynchronous action. When the clock of the next level arrives, this captured value is cached through the phase trigger and data trigger and the next handshake protocol is initiated, forming a shift-in / shift-out relationship. This shift-in / shift-out relationship completes the testability of the event-driven asynchronous action by capturing the value captured at each level before the final level outputs it. This shift-in / shift-out relationship describes the first value captured at each level before the final level outputs it.

[0106] In the embodiment, the reason for designing the trigger of the dedicated module for testability design of the control path is the principle requirement of testability design of synchronous circuits. In testability design, first, it is necessary to use the trigger to shift in the value, and this value is calculated through the combinational logic. Secondly, the result of the calculation is captured by the data end of the capture trigger. Then, a clock is given to shift out the value in the capture trigger. Finally, the shifted value is compared with the result value calculated by the tool's algorithm to obtain a match / mismatch result. In this process, the shift-in, capture, and shift-out actions of the trigger are necessary. Observation Figure 3 It can be found that on a path that generates local pulses, there are only triggers that move in, but no triggers that capture, and there is no way to move out. Therefore, it is necessary to add a testability design module dedicated to the control circuit, such as Figure 4 As shown; It should be noted that, the embodiment Figure 4 The method of the DFT module shown in the need to reuse another DFT module, Figure 14 The detailed usage is listed in the . Since the other DFT module is only used to provide clock, Figure 14 This module description is omitted in other descriptions.

[0107] In some feasible implementations, in addition to the conventional data flow controllers proposed above, actual circuit designs may also include more complex data flow controls, such as conditional select multiplexers and demultiplexers. In some feasible implementations, the initial asynchronous circuit can be expanded to complex gates, such as conditional select multiplexers and demultiplexers in the control path. Therefore, the step of constructing the control path module of the initial asynchronous circuit in this embodiment further includes: using the Click circuit to analogize the conditional select multiplexer and / or demultiplexer in the control path, and modeling the control path module of the conditional select multiplexer and / or demultiplexer.

[0108] Specifically in the embodiment, the conditional selection data flow controller is also modeled, namely CLICK2I10 (multiplexer) and CLICK1I2O (demultiplexer), and its structure is as follows: Figure 6 and Figure 7 As shown, a demultiplexer has one input and two or more outputs. Its function is to send input data to different outputs based on the value of a selection signal, achieving conditional data distribution. In contrast, a multiplexer has two or more inputs and one output. Its function is to select different input data based on the value of a selection signal and then send it to the next stage. The modeling of a multi-port multiplexer and / or demultiplexer can be derived by analogy with the modeling of a two-port multiplexer and / or demultiplexer.

[0109] Therefore, in an embodiment, constructing the data path module of the initial asynchronous circuit and constructing the data path testability module S120 using a data selector and an external clock according to the clock driving process of the data path and the control path may include steps S121-S123:

[0110] S121. Add the data path testability module to the path generating the local pulse;

[0111] S122, the data selector selects the external clock and the original Click pulse signal in the test mode; the data selector selects the external clock in the test mode and selects the original Click pulse signal in the functional mode;

[0112] S123 , the selected signal drives the original asynchronous circuit with a clock according to the test mode requirement, and performs testability output of an event-driven asynchronous action in the test mode or performs an event-driven asynchronous action in the functional mode.

[0113] Specifically, in this embodiment, the modeling component of the asynchronous circuit data path DFT implementation system is substantially identical to the modeling of the corresponding synchronous circuit. The asynchronous circuit data path DFT implementation system modeling module consists of an asynchronous circuit data path module and a dedicated data path DFT module. The asynchronous circuit data path module is substantially identical to the modeling of the corresponding synchronous circuit, while the dedicated data path DFT module primarily consists of a data selector circuit, an external clock, and test patterns. In this embodiment, the asynchronous circuit data path DFT implementation system can be modeled using the Verilog HDL language.

[0114] The modeling of the asynchronous data path module is basically the same as the modeling of the corresponding synchronous circuit. The circuit structure of the asynchronous data path module modeling is as follows: Figure 8 The data path testability design module mainly consists of a data selector circuit, an external clock, and a test mode. The circuit used and the connection relationship with the asynchronous circuit data path are shown in the figure. Figure 9 shown.

[0115] The difference between the asynchronous data path module and the synchronous circuit is that the clock input of the trigger in the synchronous circuit only needs to be replaced from a unified global clock to a local pulse generated by the corresponding click controller. The circuit structure of the synchronous data path module modeling based on the asynchronous data path module modeling is as follows Figure 10 As shown. Figure 8 and Figure 10 The two circuits differ only in the clock source of the triggers. The synchronous circuit's clock source is a clock tree generated by a unified global clock, while the asynchronous circuit's trigger clock source is a pulse signal generated by the control path block. This principle allows you to replace other synchronous circuits with asynchronous circuits, converting between synchronous and asynchronous circuits and performing design for testability.

[0116] In an embodiment, the step of performing testability modeling on the data path of the initial asynchronous circuit S120 may include steps S124-S125:

[0117] S121. Constructing a clock bypass circuit by combining an OR gate and an AND gate, or constructing a clock bypass circuit by using a data selector;

[0118] S122: Bypass the global clock and / or the internal clock according to the clock bypass circuit to complete the testability modeling of the data path.

[0119] Specifically, in the embodiment, the design of the data selector and external clock for the dedicated module for data path testability design is driven by the principles of synchronous circuit testability design. One reason is that testability design requires a global scan clock. In synchronous circuit testability design, the unified global clock of the synchronous circuit can be directly used. If different clocks exist, different clock domains can simply be designed, each chained together, and tested independently. However, in our asynchronous circuits, there is no global clock. The clock of each trigger is triggered by an event at each stage, making it impossible to use a unified global clock or separate clock domains for testing. A second reason is that the DFT design results need to be run on an integrated circuit automatic test machine (ICAT). ICATs currently do not support event-driven clocks like ours. They can only support global clocks or internal clocks generated by the OCC and PLL. However, these internal clocks differ significantly from our event-driven clocks and therefore cannot be used. For these reasons, the embodiment found that bypassing the original clock and providing a dedicated test clock offered the best results.

[0120] In the technical solution of this application, there are two solutions for the clock bypass circuit. The first solution is to use a data selector, such as Figure 9 As shown; it should be noted that, Figure 9 The DFT shown in is a dedicated module for the data path, but it is also reused for the control path. The second solution is to use a combination of OR gates and AND gates, such as Figure 11 As shown in the second scheme, when the test mode is 1, the AND gate is in the cutoff state, and only the scan clock of the lower OR gate will work, which is equivalent to completing the clock bypass function, so the data path works normally. However, because the output of the AND gate should also be connected to the capture trigger of the control path, as shown in Figure 12 As shown in the AND gate. Figure 12 It can be seen from the figure that the disabling of the AND gate in this test mode will block the capture of the control path and fail to detect the operation value of the combinational logic in the control path. The clock bypass solution given in the second solution can only test the data path, not the control path, and will hinder the test of the control path. Therefore, the embodiment proposes to Figure 9 The clock bypass solution based on the data selector is shown in the figure and is used for the Click circuit template instead of Figure 11 The method shown is based on inverters, AND gates and OR gates.

[0121] From this replacement solution, it can be concluded that the testability design implementation method proposed in the technical solution of this application can simultaneously realize the implementation scheme of Click's data module testability design and control module testability design, and improve the problem in the related technical solution that the testability circuit will hinder the testing of the control path.

[0122] like Figure 13 and Figure 14 As shown, the above-mentioned DFT implementation system for the control circuit of the asynchronous circuit and the DFT implementation system for the data path of the asynchronous circuit can construct a simple asynchronous pipeline with DFT.

[0123] Figure 13 It is an asynchronous circuit system that does not include testability design. In the asynchronous pipeline structure, the combinational logic of the data path is the same as the corresponding synchronous circuit, except that all the triggers of the data path are driven by the click signal generated by the control path of the corresponding stage.

[0124] Figure 14 It is an asynchronous circuit system with testability design. Figure 14 In the asynchronous pipeline structure with testability design, Figure 13 The difference is that the logic dedicated to testability is added, Figure 14 The testability design module 1401 includes a dedicated testability design module 1401 for the control path (hereinafter referred to as the control path testability module) and a dedicated testability design module 1402 for the data path (hereinafter referred to as the data path testability module). In the testability design process, the dedicated testability modules required by the data path and the control path share commonalities. Both require clock bypass functionality for proper operation, so the data path testability module is merged into the control path. This approach allows the data path and control path to be considered as a single entity, or they can be treated separately.

[0125] In the data path module and control path module, the click pulse signal generated by the click unit will be bypassed by the data selector in the dedicated testability module of the data path testability module in test mode. Using the scan clock provided by the external port as the clock end will make the data path system of this asynchronous circuit consistent with the data path system of the synchronous circuit, and the testability process is consistent with the testability process of the corresponding synchronous circuit. In the control path module, due to the addition of the control path testability module, this circuit complies with the serial scan chain and pattern test verification principles of synchronous testability design and will be completed according to the normal synchronous testability design process.

[0126] In the embodiment, the DFT process for asynchronous circuits is completed based on the DFT process for synchronous circuits. In the DFT process, the automatic test vector generation stage is an important stage for performing testability analysis on the circuit. In the related technical solutions, the principle of DFT in this stage is as follows:

[0127] like Figure 15As shown in the figure, two D-type flip-flops with testability are used as an example. The scan-D flip-flop is a D-type flip-flop replaced by an electronic design automation tool. The replaced scan-D flip-flop has a scan input and a scan output port. Due to the design of the data selector in the scan-D flip-flop, when the scan enable is 1, the circuit logic differs from that before the testability logic was added. The signal propagates through a shift flip-flop chain: "scan data input - scan-D flip-flop 1 (scan input) - scan-D flip-flop 1 (scan output) - scan-D flip-flop 2 (scan input) - scan-D flip-flop 2 (scan output) - scan data output," with no combinational logic in between. When the scan enable is 0, the circuit logic remains the same as before the testability logic was added. That is, the signal propagates through the normal functional logic sequence: "data input - scan-D flip-flop 1 (data) - scan-D flip-flop 1 (data output) - functional module - scan-D flip-flop 2 (data) - scan-D flip-flop 2 (data output)."

[0128] 1. Scan enable is 1: This is the shift-in phase. When the clock arrives, the preset value calculated by the tool is shifted in through the scan input of scan-type D-type flip-flop 1, and then sent to the data terminal of scan-type D-type flip-flop 2 through the combinational logic function module;

[0129] 2. Scan enable is 0: This is the capture phase. When the clock arrives, the scan-type D-type flip-flop 2 flip-flop captures the result value of the combinational logic operation from the data terminal;

[0130] 3. Scan enable is 1: This is the shift-out phase. When the clock arrives, the scan-type D-type flip-flop 2 transmits the value captured in step 2 through the scan chain (shift flip-flop chain) via the scan output terminal to the next flip-flop in the scan chain. Once this value is transmitted to the next flip-flop in the scan chain, the last bit of the scan chain (shift flip-flop chain) shifts out a bit, called the shift-out value. (At the same time, a new value also needs to be shifted in at the front end. This is a new value for each flip-flop, so this also becomes the shift-in phase for the next test vector.)

[0131] In the embodiment, after the clock bypass module is added, the above process is completely consistent with the process of synchronous circuit testability design.

[0132] In the embodiment of the technical solution of the present application, in the process of constructing the initial asynchronous circuit of the trigger transmission level in step S100, steps S130-S150 are included:

[0133] S130, replacing the global clock pulse in the synchronization circuit with an event-driven click pulse;

[0134] S140, bypassing the Click pulse and adding a scan clock pulse;

[0135] S150, adding a D-type flip-flop to the circuit after the scan clock pulse is added, to obtain an initial asynchronous circuit with testability;

[0136] Specifically, in this embodiment, the RTL programming phase for asynchronous circuits includes three main processes: First, the synchronous-to-asynchronous conversion process: replacing a unified global clock pulse with an event-driven click pulse; second, the asynchronous circuit data path testing process: bypassing the click pulse and using an external scan clock pulse; and third, the asynchronous circuit control path testing process: adding a capture trigger to facilitate testing of the circuit that generates the click pulse, thereby improving overall test coverage.

[0137] In the embodiment, the differences between the testability design processes of asynchronous circuits and synchronous circuits are: 1. To make the event-driven data path testable, this is part of the data path test process of the above-mentioned asynchronous circuit; 2. The Click element of the control path is tested in addition to the synchronous circuit, which is equivalent to testing the clock generation circuit, and is part of the control path test process of the above-mentioned asynchronous circuit.

[0138] In an embodiment of the technical solution of the present application, step S200, the process of obtaining the target asynchronous circuit by replacing the trigger in the initial asynchronous circuit after testability modeling, can be specifically as follows: replacing the D-type trigger in the control path and the data path with a scan trigger to obtain the target asynchronous circuit.

[0139] Specifically, in the embodiment, during the synthesis phase of the asynchronous circuit in the embodiment, all D-type flip-flops in the control path and the data path can be replaced with scan-type D-type flip-flops through electronic design automation tools, and the replacement range includes Figure 14 The control path testability module and the scan-type D-type flip-flop choose to use the MUX-D module which is the most commonly used in synchronous testability design in the industry.

[0140] In an embodiment of the technical solution of the present application, step S400 in the embodiment, chaining the target asynchronous circuit after the initial formal verification according to the scan chain, and performing secondary formal verification on the target asynchronous circuit before chaining and the target asynchronous circuit after chaining, may include steps S410-S420:

[0141] S410, setting the test mode type to constant 1, so that the scan clock pulse is effective, and the control path testability module and the data path testability module are enabled;

[0142] S420 , setting the scan enable type to scan enable, so that the scan trigger uses the data input from the scan input port in the shift mode, and uses the data input from the data port in the capture mode.

[0143] Specifically, in the embodiment, the tool used in the chaining stage may be Synopsys' Design Compiler. In the chaining stage of the asynchronous circuit in the embodiment, the following setting steps need to be performed:

[0144] Before chaining, set the DFT signal: Set the test mode type to Constant 1. This step bypasses the original click pulse in test mode, validating the scan clock added in Step 2 of the RTL development phase. Once the scan clock is valid, the control circuit's dedicated DFT module is enabled, ensuring that the asynchronous circuit's data path module is identical to that of the synchronous circuit, allowing testability to be applied according to the DFT methodology for synchronous circuits.

[0145] Before chaining, set the DFT signal: The scan enable type must be set to scan enable, with a high value of 1 and a low value of 0. This step is essential for synchronous testability design and a prerequisite for completing the scan chain. This step affects the flip-flop added to the control path. This flip-flop is replaced with a scan-type D-type flip-flop. When the scan enable is 1, the scan chain transmits data from the scan input to the scan-type D-type flip-flop. When the scan enable is 0, the combinational logic captures the result of the combinational logic operation from the data terminal, generating the click pulse. This conforms to the principles of synchronous testability design.

[0146] It's important to note that the asynchronous circuit DFT module requires the aforementioned dedicated DFT modules for the control circuit and the datapath to ensure the effectiveness and completeness of the DFT. Beyond these two steps, all other steps are identical to those for synchronous DFT.

[0147] In an embodiment of the technical solution of the present application, step 500, simulating to obtain a simulation circuit according to the test vector of the target asynchronous circuit after completing the secondary formal verification, may include steps S510-S530:

[0148] S510, in a shift input stage, assigning an initial value of a first test vector to the scan flip-flop, shifting the initial value in the scan flip-flop according to the clock signal, and performing a combinational logic operation on the shifted initial value;

[0149] S520, in a data capture phase, capturing a result of a combinational logic operation according to the clock signal and through the control path testability module;

[0150] S530 , in the shift output stage, according to the clock signal, the result of the combinational logic operation is transmitted to the next stage trigger of the scan chain through the scan chain, and the shift output value is output.

[0151] At the same time, the preset value of the next test vector is shifted in at the front end of the scan chain, which can also be called the shift input stage of the next test vector. The above process of S510-S530 is repeated until all test vectors are shifted in and out.

[0152] Specifically in the embodiment, during the automatic test vector generation stage, such as Figure 16 As shown, take two testable Click modules as an example:

[0153] 1) Scan enable is 1: This is the shift-in phase. When the clock arrives, the preset value calculated by the tool is shifted in through the scan input of phase input register 1. This value is then passed through the combinational logic (XOR gate and AND gate) to the data terminal of the trigger in the dedicated DFT module.

[0154] 2) Scan enable is 0: This is the capture phase. When the clock arrives, the trigger in the dedicated DFT module captures the result of the combinational logic operation from the data terminal.

[0155] 3) Scan enable is 1: This is the shift-out phase. When the clock arrives, the flip-flops within the dedicated DFT module transmit the value captured in step 2 through the scan chain (shift flip-flop chain) via the scan output to the next flip-flop in the scan chain. The final bit of the scan chain (shift flip-flop chain) shifts out a bit, called the shift-out value. (At the same time, a new value also needs to be shifted in at the front end. This is a new value for each flip-flop, so this also becomes the shift-in phase for the next test vector.)

[0156] In some feasible implementations, during the simulation test of the test vector, step S540 may be further included, comparing the shifted output value with the expected value represented by the test vector to obtain the simulation verification result.

[0157] Specifically in the embodiment, the actual value shifted out can be compared with the expected value designed by the tool, and the result obtained is that the actual value matches the expected value.

[0158] In summary, because the testability design of traditional electronic design automation tools and integrated circuit automatic test machines must require a unified clock drive, the present invention adds a data path testability module. After the addition of this testability module, the traditional electronic design automation tool can complete the above-mentioned process set for synchronous circuits in traditional electronic design automation tools for this asynchronous circuit, thereby completing the testability design of the control module of the asynchronous circuit. Because traditional electronic design automation tools must capture values of triggers, the present invention adds a control path testability module. After the addition of this trigger, the traditional electronic design automation tool can complete the above-mentioned process set for synchronous circuits in traditional electronic design automation tools for this asynchronous circuit, thereby completing the testability design of the control module of the asynchronous circuit. Similarly, other similar complex Click template-based asynchronous circuits containing multiplexers / demultiplexers can also be completed by traditional electronic design automation tools after adding triggers through the same steps. This will not be described in detail here.

[0159] By implementing a dedicated DFT module for control circuits, traditional electronic design automation tools can perform DFT checks on the combinatorial logic between all triggers in the asynchronous circuit's control module, particularly on the click pulse generation circuit. This allows traditional EDA tools to perform DFT on the pulses generated by asynchronous click circuits and identify any testability issues with the click pulses, facilitating error detection after chip manufacturing.

[0160] like Figure 17 As shown, the technical solution of this application provides an embodiment of a sequential pipeline structure asynchronous controller. Figure 17 Each level represents a Click controller.

[0161] The first-stage controller is configured so that its phase flip-flop's clock source is an external clock. An observation flip-flop 1 is added to the combinational logic within the control module. This observation flip-flop's clock source is also external. The data terminal of observation flip-flop 1 is connected to the output of the AND gate of the first-stage click, but not to the output of the data selector. During the scan unit replacement step in traditional electronic design automation tools, this circuit replaces observation flip-flop 1 with observation-scan D-type flip-flop 1. The scan input of observation-scan D-type flip-flop 1 is cleared, while the data terminal of observation-scan D-type flip-flop 1 remains connected to the output of the previously configured AND gate. After the scan chain is successfully chained, the tool's algorithm connects the scan input of observation-scan D-type flip-flop 1 to a manually defined input or the scan output of the previous scan-type D-type flip-flop. At this point, all the combinational and sequential logic in the first stage can be chained, completing the initial chaining of the scan chain shift flip-flops and enabling the scan chain shift-in operation. In the capture step, when the scan enable is set to 0, the data will enter the flip-flop through the data terminal of the observation-scan D-type flip-flop 1, and the output of the AND gate will be captured. Then, based on the tool's automatic test vector generation algorithm, it can be inferred which gate in the previous combinational logic is faulty. At this point, the definition of the first-level test case of Click is completed: the scan input of the first-level observation-scan D-type flip-flop will be connected to the manually defined input terminal, the scan output of the first-level observation-scan D-type flip-flop will be connected to the scan input of other scan-type D-type flip-flops in this level, and the scan output of the last scan-type D-type flip-flop in this level will be connected to the scan input of the second-level observation-scan D-type flip-flop, thus becoming the shift-in / shift-out path of the scan chain; the request_output and response_output of the first level will be connected to the data terminal of the second-level observation-scan D-type flip-flop in functional mode through the second-level combinational logic, becoming the captured data path.

[0162] The second-stage controller is configured so that its phase flip-flop is clocked by an external clock. An observation flip-flop 2 is added to the combinational logic circuit within the control module. This observation flip-flop 2 is clocked by an external clock. The data terminal of observation flip-flop 2 is connected to the output of the AND gate of the second-stage click, but not to the output of the data selector. During the scan unit replacement step in traditional electronic design automation tools, this circuit replaces observation flip-flop 2 with observation-scan-D flip-flop 2. The scan input of observation-scan-D flip-flop 2 is cleared, while the data terminal of observation-scan-D flip-flop 2 remains connected to the output of the previously configured AND gate. After the scan chain is successfully chained, the scan input of observation-scan-D flip-flop 2 is connected to the scan output of the previous scan-D flip-flop according to the tool's algorithm, typically to the scan-D flip-flop of the first stage. At this point, all the combinational logic and sequential logic of the first and second stages can be chained, completing the initial chaining of the scan chain shift flip-flops and enabling the shift-in operation of the scan chain. In the capture step, with scan enable set to 0, data will enter the flip-flop through the data terminal of the observation-scan D-type flip-flop 2, capturing the output of the AND gate. The tool's automatic test vector generation algorithm can then be used to infer which gate in the previous combinational logic is at fault. This completes the definition of the second-level test case for Click: the scan input of the second-level observation-scan D-type flip-flop is connected to the scan output of the last scan-type D-type flip-flop in the first level. The scan output of the second-level observation-scan D-type flip-flop is connected to the scan input of the other scan-type D-type flip-flops in this level. The scan output of the last scan-type D-type flip-flop in this level is connected to the scan input of the third-level observation-scan D-type flip-flop, forming the shift-in / shift-out path of the scan chain. The request output and response output of the second level are connected to the data terminal of the third-level observation-scan D-type flip-flop in functional mode through the third-level combinational logic, forming the captured data path.

[0163] Similarly, the scan input of the third-stage observation-scan D-type flip-flop is connected to the scan output of the last scan-type D-type flip-flop in the second stage. The scan output of the third-stage observation-scan D-type flip-flop is connected to the scan input of the other scan-type D-type flip-flops in the same stage. The scan output of the last scan-type D-type flip-flop in the same stage is linked to the scan input of the third-stage observation-scan D-type flip-flop, thus forming the shift-in / shift-out path of the scan chain. The request output and response output of the third-stage are connected to the data terminal of the third-stage observation-scan D-type flip-flop in functional mode through the combinational logic of the fourth stage, forming the captured data path. Alternatively, if the third stage is the last stage, it is directly connected to the output, and the output value is analyzed to see if it matches the preset value.

[0164] Similarly, there is a testability design of n Click units. The testability structure is replaced at each level. The input port is defined at the first level and the output port is defined at the last level. Each adjacent level has a combinational logic and an interconnection between the data ends of the observation-scan-D-type flip-flop. In addition, it should be noted that the specific order of the internal scan flip-flops can also be customized according to the chain rules.

[0165] like Figure 18 As shown, the technical solution of this application provides an embodiment of a non-sequential pipeline structure asynchronous controller. Figure 19 As shown, the technical solution of this application provides an embodiment of conditional selection of data flow structure constraints. Figure 18 、 19 The structural modifications to the first, second, and third stages are similar to those for the asynchronous controller in a sequential pipeline structure, differing only in the configuration between stages. Simply connect the data selectors where bifurcations are required, maintaining the same logic as the original circuit's combinational logic. When feedback is required, the scan chain endpoint is logically connected to the scan chain starting point. Feedback from the functional modules designed for testability is also connected via the functional mode selection.

[0166] In summary, the method for implementing testability of asynchronous circuits proposed in the technical solution of this application has at least the following advantages over related technical solutions:

[0167] ① Existing asynchronous DFT methods cannot effectively utilize traditional electronic design automation tools to complete DFT. Instead, they require the development of new algorithms and specialized tools. These specialized algorithms and tools pose challenges to the universal applicability of asynchronous circuits. However, the present invention utilizes traditional electronic design automation tools to complete DFT for asynchronous circuits.

[0168] ② Existing asynchronous testability design methods are mostly targeted at specific asynchronous templates, most of which have nothing in common with Click templates. Some circuit methods use state machines and algorithmic improvements to modify the circuit structure. This complex structure requires changing the structure between different processes, resulting in poor portability. However, the solution proposed in this invention does not require multiple circuit structure changes; only a single initial structural change is required to complete the entire process.

[0169] ③ The existing asynchronous templates that have something in common with the Click template are that they divide the circuit into a control module and a data module, and the asynchronous testability design method for the control circuit can either not be effectively used for the control circuit module of the Click template, or does not consider the test of "stuck faults". Most methods process the combinational logic circuit of the C unit, with a variety of processing methods, and require multiple manual iterations to meet the required asynchronous testability design. The solution proposed in the present invention can perform testability design for "stuck faults" on the control path of the Click template. Moreover, the method and ideas can be extended to related types of circuits. For example, if the coverage rate in the control circuit is low, the method of the present invention can be used to add observation logic; if the clock of the control circuit cannot be identified, the method of the present invention can be used to add an external clock.

[0170] ④ The existing asynchronous templates that have something in common with the Click template are that they divide the circuit into a control module and a data module, and the asynchronous testability design method for the data path therein is either not effectively applicable to the data circuit module of the Click template, or the extensibility of the method is not mentioned and is not applicable to the data circuit module of the Click template. For example, some additional circuits are used to make the data path appear as a pure combinational circuit for testing. The solution proposed in the present invention can perform testability design on the data path of the Click template without changing the circuit structure characteristics and maintaining the integrity of the original circuit. Moreover, the method and ideas can be extended to related types of circuits. For example, if the clock of the data path cannot be identified, an external clock can be added using the method of the present invention.

[0171] ⑤ The existing asynchronous circuit testability design method cannot effectively combine the control part and data part of the asynchronous circuit for testing. The present invention proposes an asynchronous circuit testability implementation system that can perform testability design on the control part and the data part separately and combine them at the top level. The test method for the two modules does not require multiple tests or separate tests, and the control module and the data module can be tested at one time.

[0172] Existing asynchronous circuit constraint methods only analyze the testability design of simple sequential pipelines, but fail to address the testability design of non-sequential data transmission and complex asynchronous controllers such as MUXs and DEMUXs. These structures are essential components for building complex scan input circuits. Building on the testability design of sequential pipelines, this present invention models and applies timing constraints to the testability design of non-sequential transmission and conditional control data flows, ensuring the correctness of the testability design for complex data flows.

[0173] In addition, although the present invention is described in the context of functional modules, it should be understood that, unless otherwise stated, one or more of the functions and / or features may be integrated into a single physical device and / or software module, or one or more functions and / or features may be implemented in separate physical devices or software modules. It is also understood that a detailed discussion of the actual implementation of each module is not necessary for understanding the present invention. More specifically, given the properties, functions, and internal relationships of the various functional modules in the devices disclosed herein, the actual implementation of the module will be understood within the ordinary skill of an engineer. Therefore, a person skilled in the art will be able to implement the present invention set forth in the claims using ordinary skill without undue experimentation. It is also understood that the specific concepts disclosed are merely illustrative and are not intended to limit the scope of the present invention, which is determined by the full scope of the appended claims and their equivalents.

[0174] The logic and / or steps represented in the flowchart or otherwise described herein may be considered, for example, as an ordered list of executable instructions for implementing logical functions, and may be embodied in any computer-readable medium for use by, or in conjunction with, an instruction execution system, apparatus, or device (such as a computer-based system, a system including a processor, or other system that can fetch and execute instructions from an instruction execution system, apparatus, or device).

[0175] Throughout this specification, reference to terms such as "one embodiment," "some embodiments," "examples," "specific examples," or "some examples" means that a specific feature, structure, material, or characteristic described in conjunction with that embodiment or example is included in at least one embodiment or example of the present invention. In this specification, schematic representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.

[0176] While embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that various changes, modifications, substitutions, and variations may be made to the embodiments without departing from the principles and spirit of the invention, and that the scope of the invention is defined by the claims and their equivalents.

[0177] The above is a specific description of the preferred implementation of the present invention, but the present invention is not limited to the above embodiments. Those skilled in the art can make various equivalent modifications or substitutions without violating the spirit of the present invention. These equivalent modifications or substitutions are all included in the scope defined by the claims of this application.

Claims

1. A method for implementing testability of an asynchronous circuit, characterized in that: The following steps are involved: constructing an initial asynchronous circuit of a trigger transmission level and performing testability modeling on the initial asynchronous circuit; Obtaining a target asynchronous circuit by replacing the flip-flops in the initial asynchronous circuit after testability modeling; Performing an initial formal verification on functional consistency between the target asynchronous circuit and the initial asynchronous circuit, and outputting a result of the initial formal verification; Chaining the target asynchronous circuit after the initial formal verification according to the scan chain, performing a secondary formal verification on the target asynchronous circuit before the chaining and the target asynchronous circuit after the chaining, and outputting a result of the secondary formal verification; Performing simulation based on the test vectors of the target asynchronous circuit after completing the secondary formal verification, and outputting simulation verification results; The testability modeling of the initial asynchronous circuit comprises the following steps: Constructing a control path module of the initial asynchronous circuit and constructing a control path testability module using triggers according to a capture process of a logic operation result; Constructing a data path module of the initial asynchronous circuit, and constructing a data path testability module using a data selector and an external clock according to the clock driving process of the data path and the control path; The data path module of the initial asynchronous circuit is constructed, and according to the clock driving process of the data path and the control path, a data path testability module is constructed using a data selector and an external clock, further comprising: A clock bypass circuit is constructed by combining an OR gate and an AND gate, or a clock bypass circuit is constructed by a data selector; The global clock and / or the internal clock are bypassed according to the clock bypass circuit to complete the testability modeling of the data path.

2. The method for implementing testability of an asynchronous circuit according to claim 1, wherein: The control path module of the initial asynchronous circuit is constructed, and according to the capture process of the logic operation result, a control path testability module is constructed using a trigger, including: Constructing a control path module for the initial asynchronous circuit; the control path module includes a phase-decoupled click circuit; wherein the click circuit is used to implement a handshake protocol for two-phase bundled data; the click circuit includes an exclusive-OR gate, an exclusive-OR gate, and an AND gate; the exclusive-OR gate, the exclusive-OR gate, and the AND gate are used to generate a local pulse signal; the local pulse signal serves as a clock signal for a data path trigger of the initial asynchronous circuit; Construct a control path testability module for the initial asynchronous circuit; wherein, the control path testability module includes the XOR gate, XNOR gate, AND gate and capture trigger of the Click circuit; the capture trigger is used to capture the logic operation result output from the AND gate.

3. The method for implementing testability of an asynchronous circuit according to claim 2, wherein: The control path testability module for constructing the initial asynchronous circuit includes: Adding the control path testability module to the path generating the local pulse; The control path testability module captures and stores data according to the clock signal. The capture trigger stores data on a captured first value at this level. The first value is used to capture the result of an event-driven asynchronous action. The first value is also used to cache data and initiate the next handshake protocol via a phase trigger and a data trigger when the next-level clock arrives, thereby forming a shift-in / shift-out relationship. The shift-in and shift-out relationship is used to describe the first value captured by each stage before the last stage outputs.

4. The method for implementing testability of an asynchronous circuit according to claim 1, wherein: The data path module of the initial asynchronous circuit is constructed, and according to the clock driving process of the data path and the control path, a data path testability module is constructed using a data selector and an external clock, including: Adding the data path testability module to the path for generating local pulses; The data selector selects the external clock and the original Click pulse signal in the test mode; the data selector selects the external clock in the test mode and selects the original Click pulse signal in the functional mode; The selected signal drives the original asynchronous circuit for clock according to the mode requirement, and performs the testability output of the event-driven asynchronous action in the test mode or the event-driven asynchronous action in the functional mode.

5. The method for implementing testability of an asynchronous circuit according to claim 3, wherein: The initial asynchronous circuit is used to extend to a conditional selection multiplexer and demultiplexer of a control path; the control path module for constructing the initial asynchronous circuit includes: The conditional selection multiplexer and / or the demultiplexer of the control path are analogized by the Click circuit, and a control path module of the conditional selection multiplexer and / or the demultiplexer is obtained by modeling.

6. The method for implementing testability of an asynchronous circuit according to claim 1, wherein: The process of constructing the initial asynchronous circuit includes: Replace the global clock pulse in the synchronous circuit with an event-driven click pulse; Bypass the Click pulse and add a scan clock pulse; Adding a D-type flip-flop to the circuit after adding the scan clock pulse, we get an initial asynchronous circuit with testability. The step of obtaining a target asynchronous circuit by replacing a trigger in the initial asynchronous circuit after testability modeling includes: The D-type flip-flops in the control path and the data path are replaced with scan flip-flops to obtain the target asynchronous circuit.

7. The method for implementing testability of an asynchronous circuit according to claim 6, wherein: The step of chaining the target asynchronous circuit after the initial formal verification according to the scan chain and performing a secondary formal verification on the target asynchronous circuit before the chaining and the target asynchronous circuit after the chaining includes: Setting the test mode type to constant 1, so that the scan clock pulse is effective, and the control path testability module and the data path testability module are enabled; The scan enable type is set to scan enable, so that the scan trigger uses the data input from the scan input port in the shift mode, and uses the data input from the data port in the capture mode.

8. The method for implementing testability of an asynchronous circuit according to claim 6, wherein: The step of chaining the target asynchronous circuit after the initial formal verification according to the scan chain and performing a secondary formal verification on the target asynchronous circuit before the chaining and the target asynchronous circuit after the chaining further includes: In the shift input stage, the preset value of the first test vector is assigned to the scan trigger, the preset value in the scan trigger is shifted according to the clock signal, and a combinational logic operation is performed on the shifted preset value; In a data capture phase, the result of the combinational logic operation is captured according to the clock signal and through the control path testability module; In the shift output stage, according to the clock signal, the result of the combinational logic operation is transmitted to the next stage trigger of the scan chain through the scan chain, and the shift output value is output; The preset value of the next test vector is shifted into the front end of the scan chain, and the shift input stage, the data capture stage and the shift output stage are repeated until all test vectors are shifted in and out.

9. The method for implementing testability of an asynchronous circuit according to claim 8, wherein: The simulating the test vector of the target asynchronous circuit after completing the secondary formal verification and outputting the simulation verification result includes: All shifted output values are compared with the expected values represented by the test vectors to obtain the simulation verification results.

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