A splitter circuit and device for use in bus systems

Abstract

This application relates to the technical field of bus systems, and in particular to a splitter circuit and device applied to a bus system. The circuit includes a signal input circuit whose output is connected to the input of a first control circuit; the output of the first control circuit is connected to the first control terminal of a first switching circuit; the first switching circuit is connected to the output terminal VC1 of a power theft circuit; the first switching circuit is connected to the first control terminal of a second switching circuit; the output of a signal inverting input circuit is connected to the input of the second control circuit; the first output of the second control circuit is connected to the second control terminal of the second switching circuit; the second switching circuit is connected to the output terminal VC1 of the power theft circuit; the second output of the second control circuit is connected to the second control terminal of the first switching circuit; and the input terminal VB of the power theft circuit is used to connect to the bus. This application provides better protection for devices and terminals.

Description

Technical Field

[0001] This application relates to the technical field of buses, and in particular to a splitter circuit and device for use in buses. Background Technology

[0002] A bus is a common trunk line used for transmitting information, serving as a common channel. Communication between various devices is achieved through the bus, enabling purposes such as control and information transmission.

[0003] The bus connects to bus chips, microcontrollers, etc. When the bus loses power unexpectedly, the microcontroller may be unable to output control signals due to power loss, causing the downstream devices to fail to shut down in time and remain connected. If the downstream devices are struck by lightning or a high-power electromagnetic pulse at this time, all downstream devices and terminals connected to the downstream devices will be damaged.

[0004] To avoid the above problems, there is an urgent need to invent a circuit or device that can still shut down the downstream devices when the bus is powered off, so as to better protect each device and terminal. Summary of the Invention

[0005] To better protect equipment and terminals, this application provides a splitter circuit and device for use in a bus.

[0006] Firstly, the splitter circuit for use in a bus provided in this application adopts the following technical solution:

[0007] A splitter circuit for use in a bus includes a signal input circuit, a signal inverting input circuit, a first control circuit, a second control circuit, a first switching circuit, a second switching circuit, and an electricity theft circuit.

[0008] The output terminal of the signal input circuit is connected to the input terminal of the first control circuit. The output terminal of the first control circuit is connected to the first control terminal of the first switch circuit. The first switch circuit is connected to the output terminal VC1 of the electricity theft circuit. The first switch circuit is connected to the first control terminal of the second switch circuit. The output terminal of the signal inversion input circuit is connected to the input terminal of the second control circuit. The first output terminal of the second control circuit is connected to the second control terminal of the second switch circuit. The second switch circuit is connected to the output terminal VC1 of the electricity theft circuit. The second output terminal of the second control circuit is connected to the second control terminal of the first switch circuit. The input terminal VB of the electricity theft circuit is used to connect to the bus.

[0009] The first switching circuit is connected to a first output terminal S, and the second switching circuit is connected to a second output terminal N. The first output terminal S and the second output terminal N work together to control the controlled device.

[0010] By adopting the above technical solution, after the signal input circuit and the signal inverting input circuit receive the signal, they are controlled by the first control circuit and the second control circuit. The first control circuit controls the first switching circuit to conduct, so that the first output terminal S outputs a high level. Correspondingly, the second control circuit controls the second switching circuit to deconduct, so that the second output terminal N outputs a low level; conversely, the first output terminal S outputs a low level, and the second output terminal N outputs a high level. The control of the controlled device is achieved by using the combination of the first output terminal S and the second output terminal N. Furthermore, the circuit is powered by a power-stealing circuit, which can utilize the bus to keep it energized, thereby storing electricity without affecting bus communication. Moreover, in the event of a bus power failure, this circuit design can automatically control the controlled device to stop working.

[0011] Optionally, the electricity theft circuit includes a diode D1 and a capacitor C3. The anode of the diode D1 is connected to the input terminal VB, the cathode of the diode D1 is connected to the capacitor C3, the other end of the capacitor C3 is connected to the ground terminal, and the cathode of the diode D3 is connected to the output terminal VC1.

[0012] By adopting the above technical solution, the input terminal VB is connected to the bus, thereby using the bus to charge the capacitor C3 so that the capacitor C3 stores electrical charge, and the diode D1 can prevent the current from flowing into the bus, thus avoiding the bus communication from being affected.

[0013] Optionally, the signal input circuit includes a resistor R13, a capacitor C1, and a resistor R4. One end of the resistor R13 is connected to the capacitor C1, and the other end of the resistor R13 is connected to the ground terminal. The other end of the capacitor C1 is connected to the resistor R4, and the other end of the resistor R4 is connected to the output terminal of the signal input circuit. The connection point of the resistor R13 and the capacitor C1 is connected to a connection terminal P0 for receiving signals. The connection terminal P0 is used to connect to a microcontroller.

[0014] By adopting the above technical solution, the setting of capacitor C1 and resistor R4 can convert the input signal into a pulse signal, which is then received by the first control circuit.

[0015] Optionally, the signal inverting input circuit includes resistors R9, R10, R19, and R20, transistor Q3, and capacitor C6. One end of resistor R9 is connected to the connection terminal P0, and the other end of resistor R9 is connected to the base of transistor Q3. The emitter of transistor Q3 is connected to ground, and the collector of transistor Q3 is connected to resistor R10. The other end of resistor R10 is connected to a power supply terminal. The collector of transistor Q3 is also connected to resistor R20, and the other end of resistor R20 is connected to ground. The collector of transistor Q3 is also connected to resistor R19, and the other end of resistor R19 is connected to capacitor C6. The other end of capacitor C6 is connected to the output terminal of the signal inverting input circuit.

[0016] By employing the above technical solution, the combination of capacitor C6 and resistor R19 can convert the input signal into a pulse signal. Furthermore, by utilizing transistor Q3 and the power supply terminal, signal conversion is achieved. When a high-level signal is input to terminal P0, the output of the signal inverting circuit outputs a low level; similarly, when a low-level signal is input to terminal P0, the output of the signal inverting circuit outputs a high level.

[0017] Optionally, the first control circuit includes resistor R5, resistor R14, and transistor Q4. One end of resistor R5 is connected to the output terminal VC1, the other end of resistor R5 is connected to the collector of transistor Q4, the base of transistor Q4 is connected to the input terminal of the first control circuit, the emitter of transistor Q4 is connected to resistor R14, the other end of resistor R14 is connected to ground, and the collector of transistor Q4 is also connected to the output terminal of the first control circuit.

[0018] Optionally, the second control circuit includes resistor R8, resistor R18, and transistor Q7. One end of resistor R8 is connected to the output terminal VC1, and the other end of resistor R8 is connected to the collector of transistor Q7. The base of transistor Q7 is connected to the input terminal of the second control circuit, and the emitter of transistor Q7 is connected to resistor R18. The other end of resistor R18 is connected to ground. The collector of transistor Q7 is also connected to the first output terminal of the second control circuit, and the emitter of transistor Q7 is also connected to the second output terminal of the second control circuit.

[0019] Optionally, the first switching circuit includes resistor R6, resistor R15, transistor Q1, and transistor Q5. One end of resistor R6 is connected to the first control terminal of the first switching circuit, and the other end of resistor R6 is connected to the base of transistor Q1. The emitter of transistor Q1 is connected to the connection terminal VC1, the collector of transistor Q1 is connected to the collector of transistor Q5, the emitter of transistor Q5 is connected to ground, the base of transistor Q5 is connected to resistor R15, and the other end of resistor R15 is connected to the second control terminal of the first switching circuit. The collector of transistor Q5 is also used to connect to the first control terminal of the second switching circuit, and the collector of transistor Q5 is also connected to the first output terminal S.

[0020] Optionally, the second switching circuit includes resistor R7, resistor R16, transistor Q2, and transistor Q6. One end of resistor R7 is connected to the second control terminal of the second switching circuit, and the other end of resistor R7 is connected to the base of transistor Q2. The emitter of transistor Q2 is connected to the connection terminal VC1, and the collector of transistor Q2 is connected to the collector of transistor Q6. The emitter of transistor Q6 is connected to ground, and the base of transistor Q6 is connected to resistor R17. The other end of resistor R17 is connected to the first control terminal of the second switching circuit, and the collector of transistor Q6 is also connected to the second output terminal N.

[0021] Optionally, a protection circuit for consuming electrical energy is provided between the first switching circuit and the second switching circuit. The protection circuit includes a capacitor C5 and a resistor R16. One end of the capacitor C5 is connected to the first switching circuit, and the other end of the capacitor C5 is connected to the resistor R16. The other end of the resistor R16 is connected to the second switching circuit.

[0022] By adopting the above technical solution, capacitor C5 and resistor R16 are used to absorb the consumed power, thereby achieving the function of protecting the circuit.

[0023] Secondly, the splitter device for use in a bus provided in this application adopts the following technical solution:

[0024] A splitter device for use on a bus includes a splitter circuit for use on a bus as described in the first aspect.

[0025] In summary, this application includes at least one of the following beneficial technical effects:

[0026] After receiving signals, the signal input circuit and the signal inverting input circuit use a first control circuit and a second control circuit for control. The first control circuit turns on the first switch circuit to make the first output terminal S output a high level, and correspondingly, the second control circuit turns off the second switch circuit to make the second output terminal N output a low level; conversely, the first output terminal S outputs a low level, and the second output terminal N outputs a high level. The control of the controlled device is achieved by using the combination of the first output terminal S and the second output terminal N. Furthermore, the circuit is powered by a power-stealing circuit, which can utilize the bus to store electricity without affecting bus communication. Moreover, in the event of a bus power failure, this circuit design can automatically control the controlled device to stop working.

[0027] The input terminal VB is connected to the bus, thereby charging capacitor C3 using the bus so that capacitor C3 stores electrical charge. Diode D1 can prevent current from flowing into the bus and avoid affecting bus communication. Attached Figure Description

[0028] Figure 1 This is the overall circuit schematic diagram of the embodiments of this application.

[0029] Explanation of reference numerals in the attached diagram: 1. Signal input circuit; 2. Signal inversion input circuit; 3. First control circuit; 4. Second control circuit; 5. First switch circuit; 6. Second switch circuit; 7. Electricity theft circuit; 8. Protection circuit. Implementation

[0030] The present application will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only for explaining the present application and are not intended to limit the present application.

[0031] This application discloses a splitter circuit applied to a bus. (Refer to...) Figure 1 A splitter circuit for use in a bus includes a signal input circuit 1, a signal inverting input circuit 2, a first control circuit 3, a second control circuit 4, a first switching circuit 5, a second switching circuit 6, and an electricity theft circuit 7.

[0032] The output terminal of signal input circuit 1 is connected to the input terminal of first control circuit 3. The output terminal of first control circuit 3 is connected to the first control terminal of first switch circuit 5. First switch circuit 5 is connected to the output terminal VC1 of electricity theft circuit 7. First switch circuit 5 is also connected to the first control terminal of second switch circuit 6. The output terminal of signal inversion input circuit 2 is connected to the input terminal of second control circuit 4. The first output terminal of second control circuit 4 is connected to the second control terminal of second switch circuit 6. Second switch circuit 6 is connected to the output terminal VC1 of electricity theft circuit 7. The second output terminal of second control circuit 4 is connected to the second control terminal of first switch circuit 5. The input terminal VB of electricity theft circuit 7 is used to connect to the bus.

[0033] The first switching circuit 5 is connected to the first output terminal S, and the second switching circuit 6 is connected to the second output terminal N. The first output terminal S and the second output terminal N work together to control the controlled device.

[0034] Both signal input circuit 1 and signal inversion input circuit 2 are used to connect to the control terminal. After the control terminal outputs the control signal, the signal inversion circuit is used to invert the signal. That is, the first control circuit 3 receives and acts according to the control signal, while the second control circuit 4 acts according to the signal opposite to the control signal.

[0035] For example, when the control terminal outputs a high-level signal, the signal input circuit 1 receives the high-level signal and transmits it to the first control circuit 3, which then operates according to the high-level signal. Meanwhile, the signal inversion circuit receives the high-level signal and inverts it to output a low-level signal, at which point the second control circuit 4 operates according to the low-level signal.

[0036] The electricity-stealing circuit 7 intercepts a portion of the electricity via the bus for its operation. When the first control circuit 3 receives a high-level signal, it controls a portion of the first switching circuit 5 to conduct. Simultaneously, the first switching circuit 5 controls a portion of the second switching circuit 6 to conduct, and the conducting portion of the second switching circuit 6 is grounded, resulting in a high-level output at the first output terminal S and a low-level output at the second output terminal N. When the first control circuit 3 receives a low-level signal, it controls a portion of the first switching circuit 5 to disconnect. The second control circuit 4 then receives a high-level signal, controls a portion of the second switching circuit 6 to conduct, and simultaneously controls another portion of the first switching circuit 5 to conduct, with the conducting portion of the first switching circuit 5 grounded. This results in a low-level output at the first output terminal S and a high-level output at the second output terminal N.

[0037] Based on the above principle, control can be achieved using the first output terminal S and the second output terminal N.

[0038] The electricity theft circuit 7 includes a diode D1 and a capacitor C3. The anode of the diode D1 is connected to the input terminal VB, the cathode of the diode D1 is connected to the capacitor C3, the other end of the capacitor C3 is connected to the ground terminal, and the cathode of the diode D3 is connected to the output terminal VC1.

[0039] The power-stealing circuit 7 steals electricity from the bus through its input terminal VB and stores it in capacitor C3. Diode D1 prevents current from being output back to the bus. The electricity stored in capacitor C3 is used to power the first switching circuit 5 and the second switching circuit 6, and also to power the controlled device connected to the first output terminal S and the second output terminal N, thereby achieving control. In this embodiment, the controlled device is a bistable pulse relay RL. A resistor R28 is provided between the first output terminal S and the bistable pulse relay RL. Resistor R28 is an adjustable resistor, which can adjust its resistance value so that different bistable pulse relays RL can be adapted.

[0040] The signal input circuit 1 includes a resistor R13, a capacitor C1, and a resistor R4. One end of the resistor R13 is connected to the capacitor C1, and the other end of the resistor R13 is connected to the ground terminal. The other end of the capacitor C1 is connected to the resistor R4, and the other end of the resistor R4 is connected to the output terminal of the signal input circuit 1. The connection point of the resistor R13 and the capacitor C1 is connected to the connection terminal P0 for receiving signals.

[0041] The first control circuit 3 includes resistor R5, resistor R14, and transistor Q4. One end of resistor R5 is connected to the output terminal VC1, and the other end of resistor R5 is connected to the collector of transistor Q4. The base of transistor Q4 is connected to the input terminal of the first control circuit 3, that is, the base of transistor Q4 is connected to the output terminal of signal input circuit 1. The emitter of transistor Q4 is connected to resistor R14, and the other end of resistor R14 is connected to the ground terminal. The collector of transistor Q4 is also connected to the output terminal of the first control circuit 3.

[0042] The first switching circuit 5 includes resistors R6 and R15, transistors Q1 and Q5. One end of resistor R6 is connected to the first control terminal of the first switching circuit 5, that is, one end of resistor R6 is connected to the output terminal of the first control circuit 3. The other end of resistor R6 is connected to the base of transistor Q1. The emitter of transistor Q1 is connected to the connection terminal VC1. The collector of transistor Q1 is connected to the collector of transistor Q5. The emitter of transistor Q5 is connected to the ground terminal. The base of transistor Q5 is connected to resistor R15. The other end of resistor R15 is connected to the second control terminal of the first switching circuit 5. The collector of transistor Q5 is also used to connect to the first control terminal of the second switching circuit 6. The collector of transistor Q5 is also connected to the first output terminal S.

[0043] The signal inverting input circuit 2 includes resistors R9, R10, R19, and R20, transistor Q3, and capacitor C6. One end of resistor R9 is connected to the connection terminal P0, and the other end of resistor R9 is connected to the base of transistor Q3. The emitter of transistor Q3 is connected to the ground terminal. The collector of transistor Q3 is connected to resistor R10, and the other end of resistor R10 is connected to the power supply terminal. The collector of transistor Q3 is also connected to resistor R20, and the other end of resistor R20 is connected to the ground terminal. The collector of transistor Q3 is also connected to resistor R19, and the other end of resistor R19 is connected to capacitor C6. The other end of capacitor C6 is connected to the output terminal of the signal inverting input circuit 2.

[0044] The power supply end can provide 5V voltage and is connected to the bus chip. The bus chip has a built-in LDO. After the bus is powered off, there will be residual voltage at the power supply end.

[0045] The second control circuit 4 includes resistors R8 and R18 and transistor Q7. One end of resistor R8 is connected to the output terminal VC1, and the other end of resistor R8 is connected to the collector of transistor Q7. The base of transistor Q7 is connected to the input terminal of the second control circuit 4, that is, the base of transistor Q7 is connected to the output terminal of the signal inverting input circuit 2. The emitter of transistor Q7 is connected to resistor R18, and the other end of resistor R18 is connected to the ground terminal. The collector of transistor Q7 is also connected to the first output terminal of the second control circuit 4, and the emitter of transistor Q7 is also connected to the second output terminal of the second control circuit 4, that is, the emitter of transistor Q7 is also connected to resistor R15.

[0046] The second switching circuit 6 includes resistors R7 and R16, transistors Q2 and Q6. One end of resistor R7 is connected to the second control terminal of the second switching circuit 6, that is, one end of resistor R7 is connected to the first output terminal of the second control circuit 4. The other end of resistor R7 is connected to the base of transistor Q2. The emitter of transistor Q2 is connected to the connection terminal VC1. The collector of transistor Q2 is connected to the collector of transistor Q2. The emitter of transistor Q6 is connected to the ground terminal. The base of transistor Q6 is connected to resistor R17. The other end of resistor R17 is connected to the first control terminal of the second switching circuit 6, that is, the other end of resistor R17 is connected to the collector of transistor Q5 in the first switching circuit 5. The collector of transistor Q6 is also connected to the second output terminal N.

[0047] A protection circuit 8 for consuming electrical energy is provided between the first switching circuit 5 and the second switching circuit 6. The protection circuit 8 includes a capacitor C5 and a resistor R16. One end of the capacitor C5 is connected to the collector of the transistor Q5, and the other end of the capacitor C5 is connected to the resistor R16. The other end of the resistor R16 is connected to the collector of the transistor Q6.

[0048] When the high and low level transitions of the first output terminal S and the second output terminal N are very fast, a high electromotive force will exist between the first output terminal S and the second output terminal N due to the connection of the bistable pulse relay RL. This electromotive force is absorbed and dissipated by the capacitor C5 and the resistor R16, thereby achieving the protection function.

[0049] The implementation principle of a splitter circuit applied to a bus according to an embodiment of this application is as follows: When a high-level signal is input to the connection terminal P0, the signal input circuit 1 transmits the high-level signal to the base of transistor Q4. The signal input to the connection terminal P0 can be a pulse or a level signal. Since capacitor C1 and resistor R4 are provided in the signal input circuit 1, both signals will be processed by the signal input circuit 1 and transmitted to transistor Q4 as pulses. After the base of transistor Q4 is at a high level, transistor Q4 conducts. At this time, the base of transistor Q1 is connected to the ground terminal, meaning the base of transistor Q1 is at a low level, and transistor Q1 conducts. At this time, the first output terminal S is connected to the connection terminal VC1, meaning the first output terminal S can output a high level signal.

[0050] Correspondingly, after a high-level signal is input to the connection terminal P0, the corresponding signal inversion circuit 2 is input. The base of transistor Q3 is at a high level, and the power supply terminal is connected to the ground terminal through resistor R10. At this time, the base of transistor Q7 is at a low level, and transistor Q7 is not conducting. The base of transistor Q5 is at a low level, and transistor Q5 is not conducting. The base of transistor Q2 is connected to capacitor C3, so the base of transistor Q2 is at a high level, and transistor Q2 is conducting. At the same time, since the base of transistor Q6 is connected to the collector of transistor Q5, the base of transistor Q6 is at a high level, and transistor Q6 is conducting. The second output terminal N is connected to the ground terminal, and the second output terminal N outputs a low level.

[0051] The signal inverting input circuit 2 includes a capacitor C6 and a resistor R19, so the signal input to the connection terminal P0 can be a pulse or a level. After being processed by the signal inverting input circuit 2, the signal can be transmitted to the transistor Q7 as a pulse.

[0052] The above working process requires a high-level input to the connection terminal P0.

[0053] When the input level to terminal P0 is low, the base of transistor Q4 is low and Q4 is not conducting. The base of transistor Q1 is connected to terminal VC1, so its base is high and Q1 is not conducting. Correspondingly, when the input level to terminal P0 is low, transistor Q3 is not conducting, allowing the base of transistor Q7 to be high and Q7 to conduct. Transistor Q2 is connected to ground and conducts. At this time, the second output terminal N is connected to capacitor C3, meaning the second output terminal N outputs a high level. After transistor Q7 conducts, the base of transistor Q5 is high, meaning Q5 conducts. At this time, transistor Q6 is not conducting, so it does not affect the high level output of the second output terminal N. Furthermore, after transistor Q5 conducts, the first output terminal S is connected to ground, meaning the first output terminal S outputs a low level.

[0054] The above working process involves a low-level input at connection terminal P0.

[0055] In this embodiment, a bistable pulse relay RL is connected between the first output terminal S and the first output terminal N. By using the high-low level conversion of the connection terminal P0, the bistable pulse relay RL can be closed and opened.

[0056] Furthermore, when the bus loses power, the microcontroller connected to terminal P0 cannot send signals in time, meaning the microcontroller also loses power. At this time, terminal P0 inputs a low-level signal. Since the power supply terminal is connected to the bus chip, which has a built-in LDO, there is residual voltage at the power supply terminal after the bus loses power, which is sufficient to turn on transistor Q7. Therefore, after the bus loses power, the residual voltage at the power supply terminal, capacitor C3, and various circuits can drive the bistable pulse relay RL, thereby causing the bistable pulse relay RL to disconnect, protecting the bus circuit and preventing the entire system from being damaged.

[0057] By switching between high and low levels at the connection terminal P0, the output levels at the first output terminal S and the second output terminal N are switched, thereby achieving the purpose of controlling the bistable pulse relay RL.

[0058] The power-stealing circuit 7 intercepts a portion of the electricity on the bus, which is then used to charge capacitor C3 via diode D1. The electricity stored in capacitor C3 then powers the circuit. Diode D1 is used to prevent reverse current from flowing into the bus.

[0059] This circuit only needs to operate for tens of milliseconds to complete the entire control process, requiring little power. The power stored in capacitor C3 is sufficient to meet the usage requirements.

[0060] Furthermore, using the power-stealing circuit 7 instead of a voltage regulator chip in the power supply circuit design reduces costs. Using a voltage regulator chip would introduce noise and harmonics, affecting communication signals within the bus. Conversely, using discrete components to build a voltage regulator circuit would lead to excessive power consumption, lowering the bus voltage and preventing normal signal transmission, thus causing the bus to malfunction. However, using the power-stealing circuit 7 does not affect normal bus transmission, and after a power outage, the residual voltage on capacitor C3 can drive the splitter circuit disclosed in this embodiment.

[0061] This application discloses a splitter device for a bus. The splitter device includes a splitter circuit for a bus as disclosed in the above embodiments. It enables control of an external bistable pulse relay RL without affecting bus communication.

[0062] The above are all preferred embodiments of the present application and are not intended to limit the scope of protection of this application. Unless otherwise specified, any feature disclosed in this specification (including the abstract and drawings) may be replaced by other equivalent or similar features. In other words, unless otherwise specified, each feature is merely an example of a series of equivalent or similar features.

Claims

1. A splitter circuit for use in a bus, characterized in that: It includes a signal input circuit (1), a signal inverting input circuit (2), a first control circuit (3), a second control circuit (4), a first switching circuit (5), a second switching circuit (6), and an electricity theft circuit (7); The output terminal of the signal input circuit (1) is connected to the input terminal of the first control circuit (3), the output terminal of the first control circuit (3) is connected to the first control terminal of the first switch circuit (5), the first switch circuit (5) is connected to the output terminal VC1 of the electricity theft circuit (7), the first switch circuit (5) is connected to the first control terminal of the second switch circuit (6), the output terminal of the signal inversion input circuit (2) is connected to the input terminal of the second control circuit (4), the first output terminal of the second control circuit (4) is connected to the second control terminal of the second switch circuit (6), the second switch circuit (6) is connected to the output terminal VC1 of the electricity theft circuit (7), the second output terminal of the second control circuit (4) is connected to the second control terminal of the first switch circuit (5), and the input terminal VB of the electricity theft circuit (7) is used to connect to the bus. The first switch circuit (5) is connected to a first output terminal S, and the second switch circuit (6) is connected to a second output terminal N. The first output terminal S and the second output terminal N work together to control the controlled device. The first control circuit (3) includes resistor R5, resistor R14 and transistor Q4. One end of resistor R5 is connected to the output terminal VC1, the other end of resistor R5 is connected to the collector of transistor Q4, the base of transistor Q4 is connected to the input terminal of the first control circuit (3), the emitter of transistor Q4 is connected to resistor R14, the other end of resistor R14 is connected to the ground terminal, and the collector of transistor Q4 is also connected to the output terminal of the first control circuit (3). The second control circuit (4) includes resistor R8, resistor R18 and transistor Q7. One end of resistor R8 is connected to the output terminal VC1, and the other end of resistor R8 is connected to the collector of transistor Q7. The base of transistor Q7 is connected to the input terminal of the second control circuit (4). The emitter of transistor Q7 is connected to resistor R18. The other end of resistor R18 is connected to the ground terminal. The collector of transistor Q7 is also connected to the first output terminal of the second control circuit (4), and the emitter of transistor Q7 is also connected to the second output terminal of the second control circuit (4).

2. A splitter circuit applied to a bus according to claim 1, characterized in that: The electricity theft circuit (7) includes a diode D1 and a capacitor C3. The anode of the diode D1 is connected to the input terminal VB, the cathode of the diode D1 is connected to the capacitor C3, the other end of the capacitor C3 is connected to the ground terminal, and the cathode of the diode D1 is connected to the output terminal VC1.

3. A splitter circuit applied to a bus according to claim 1, characterized in that: The signal input circuit (1) includes a resistor R13, a capacitor C1 and a resistor R4. One end of the resistor R13 is connected to the capacitor C1, and the other end of the resistor R13 is connected to the ground terminal. The other end of the capacitor C1 is connected to the resistor R4, and the other end of the resistor R4 is connected to the output terminal of the signal input circuit (1). The connection point of the resistor R13 and the capacitor C1 is connected to a connection terminal P0 for receiving signals. The connection terminal P0 is used to connect to a microcontroller.

4. A splitter circuit applied to a bus according to claim 3, characterized in that: The signal inverting input circuit (2) includes resistors R9, R10, R19, R20, transistor Q3, and capacitor C6. One end of resistor R9 is connected to the connection terminal P0, and the other end of resistor R9 is connected to the base of transistor Q3. The emitter of transistor Q3 is connected to the ground terminal, and the collector of transistor Q3 is connected to resistor R10. The other end of resistor R10 is connected to the power supply terminal. The collector of transistor Q3 is also connected to resistor R20, and the other end of resistor R20 is connected to the ground terminal. The collector of transistor Q3 is also connected to resistor R19, and the other end of resistor R19 is connected to capacitor C6. The other end of capacitor C6 is connected to the input terminal of the second control circuit (4).

5. A splitter circuit applied to a bus according to claim 1, characterized in that: The first switching circuit (5) includes resistor R6, resistor R15, transistor Q1 and transistor Q5. One end of resistor R6 is connected to the first control terminal of the first switching circuit (5), and the other end of resistor R6 is connected to the base of transistor Q1. The emitter of transistor Q1 is connected to the output terminal VC1. The collector of transistor Q1 is connected to the collector of transistor Q5. The emitter of transistor Q5 is connected to the ground terminal. The base of transistor Q5 is connected to resistor R15. The other end of resistor R15 is connected to the second control terminal of the first switching circuit (5). The collector of transistor Q5 is also used to connect to the first control terminal of the second switching circuit (6). The collector of transistor Q5 is also connected to the first output terminal S.

6. A splitter circuit applied to a bus according to claim 5, characterized in that: The second switching circuit (6) includes resistor R7, resistor R16, transistor Q2 and transistor Q6. One end of resistor R7 is connected to the second control terminal of the second switching circuit (6), and the other end of resistor R7 is connected to the base of transistor Q2. The emitter of transistor Q2 is connected to the output terminal VC1, and the collector of transistor Q2 is connected to the collector of transistor Q2. The emitter of transistor Q6 is connected to the ground terminal, and the base of transistor Q6 is connected to resistor R17. The other end of resistor R17 is connected to the first control terminal of the second switching circuit (6), and the collector of transistor Q6 is also connected to the second output terminal N.

7. A splitter circuit applied to a bus according to claim 1, 5, or 6, characterized in that: A protection circuit (8) for consuming electrical energy is provided between the first switching circuit (5) and the second switching circuit (6). The protection circuit (8) includes a capacitor C5 and a resistor R16. One end of the capacitor C5 is connected to the first switching circuit (5), and the other end of the capacitor C5 is connected to the resistor R16. The other end of the resistor R16 is connected to the second switching circuit (6).

8. A splitter device for use in a bus, characterized in that: Includes a splitter circuit applied to a bus as described in any one of claims 1 to 7.

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