A data processing method based on a matrix processor and a readable storage medium

Abstract

This application provides a data processing method and a readable storage medium based on a matrix processor. The method includes: reading W first elements from a first matrix and sending the W first elements to a computing unit of the matrix processor for calculation; wherein W is greater than the width N of the first matrix and less than or equal to the number K of the computing units of the matrix processor; repeating the above steps until the number of remaining elements in the first matrix is ​​less than W; and in response to the number of remaining elements in the first matrix being non-zero, sending the remaining elements to the computing unit for calculation. This method can improve the utilization rate of the matrix processor's computing units, reduce the number of calculation cycles, shorten the calculation time, and fully utilize the computing units of the matrix processor.

Description

Technical Field

[0001] This application belongs to the field of processor technology, specifically relating to a data processing method based on a matrix processor and a readable storage medium. Background Technology

[0002] In matrix processor design, multiple computing units are typically used. Efficiently utilizing these units is crucial. However, sometimes the width of the matrix to be computed is smaller than the width of the computing units. Current technology generally reads one row of data from the matrix at a time and performs calculations row by row. When computing small matrices, this approach cannot fully utilize all computing units, increasing the required computation cycle time and resulting in low computing unit utilization. Summary of the Invention

[0003] The purpose of this application is to provide a data processing method and a readable storage medium based on a matrix processor. This method can improve the utilization rate of the matrix processor's computing units, shorten the computing cycle, and make full use of the matrix processor's computing units.

[0004] According to one aspect of this application, a data processing method based on a matrix processor is provided. The method includes: reading W first elements from a first matrix and sending the W first elements to a computing unit of the matrix processor for calculation; wherein the W is greater than the width N of the first matrix and less than or equal to the number K of the computing units of the matrix processor; repeating the above steps until the number of remaining elements in the first matrix is ​​less than the W; and in response to the number of remaining elements in the first matrix being non-zero, sending the remaining elements to the computing unit for calculation.

[0005] Optionally, before reading the W first elements in the first matrix, the method further includes: receiving an operation instruction and parsing the received operation instruction to determine the operation type indicated by the operation instruction; and determining the value of W based on the determined operation type, the width of the first matrix, and the number of calculation units.

[0006] Optionally, W first elements from the first matrix are read into the first register unit of the matrix processor, and W = K is set.

[0007] Optionally, the step of sending the W first elements to the calculation unit of the matrix processor for calculation includes: in response to the set W=K, pruning the W first elements in the read first matrix according to the data order to obtain W1 elements, where W1=β*N≤W, β>1, and β is an integer; and sending the W1 elements to the calculation unit of the matrix processor for calculation.

[0008] Optionally, before reading W elements from the source matrix, the method further includes: determining the read address of the first matrix, wherein the read address is addr+β*N*(C-1), addr is the address of the first element of the first matrix, and C is the number of times the first matrix has been read.

[0009] Optionally, the step of reading W first elements from the first matrix and sending the W first elements to the computation unit of the matrix processor for calculation includes: reading W first elements from the first matrix into a first register unit of the matrix processor; reading the W first elements from the first register unit and sending them to the computation unit of the matrix processor; and reading the W calculation results from the result register unit of the matrix processor and sending them to the computation unit of the matrix processor, so that the computation unit performs calculations and updates the result of the calculations to the result register unit; wherein, the result register unit is used to cache the calculation results of each calculation by the computation unit.

[0010] Optionally, the step of reading W first elements from the first register unit and sending them to the calculation unit of the matrix processor for calculation, and outputting the calculation result to the result register unit of the matrix processor, further includes: in response to the number of remaining elements in the first matrix being zero, determining that the result register contains u*N elements; setting L equal to the integer part of u / 2; if u is even, dividing the elements in the result register into two groups according to the storage order, each group containing L*N elements, sending the two groups of elements to the calculation unit for calculation, and outputting the L*N elements of the calculation result to the result register unit; if u is odd, dividing the elements in the result register into three groups according to the storage order, wherein the first and second groups contain L*N elements, and the third group contains N elements, sending the first and second groups of elements to the calculation unit for calculation, and outputting the L*N elements of the calculation result to the result register unit, the result register unit containing the L*N elements of the calculation result and the N elements of the third group; repeating the above steps until u = 1.

[0011] According to two aspects of this application, a data processing method based on a matrix processor is provided, comprising: reading W first elements from a first matrix, and obtaining W second elements from a second matrix corresponding to the W first elements; wherein W is greater than the width N of the first matrix and less than or equal to the number K of the computing units of the matrix processor; feeding the W first elements and the W second elements into the computing units of the matrix processor for calculation; repeating the above steps until the number of remaining elements in the first matrix is ​​less than W; and in response to the number of remaining elements in the first matrix being non-zero, feeding the remaining elements into the computing units for calculation.

[0012] Optionally, Y second elements from the second matrix are read into the second register unit of the matrix processor. If the width and height of the second matrix are equal to the width and height of the matrix, respectively, then Y = W is set.

[0013] Optionally, the first matrix is ​​a matrix with multiple rows and columns, and the second matrix is ​​a matrix with multiple rows and columns. The width and height of the second matrix are equal to the width and height of the second matrix, respectively. Then W equals K and Y equals K.

[0014] Optionally, obtaining the W second elements in the second matrix corresponding to the W first elements includes:

[0015] In response to the setting W = α * N ≤ K, and the width of the first matrix being equal to the width of the second matrix, N second elements from the second matrix are read into the second register unit of the matrix processor; where α > 1, and α is an integer;

[0016] Within the second register unit, N second elements are copied α times to expand to obtain W second elements; or

[0017] In response to the setting W = α * N ≤ K, and the fact that the height of the first matrix is ​​equal to the height of the second matrix, α second elements in the second matrix are read into the second register unit of the matrix processor;

[0018] Within the second register unit, each of the α second elements is copied N times to expand to obtain W second elements; or

[0019] In response to the setting W=K, and the width and height of the second matrix being both 1, one second element from the second matrix is ​​read into the second register unit of the matrix processor;

[0020] Within the second register unit, one second element is copied W times to expand it into W second elements.

[0021] Optionally, before reading the W first elements in the first matrix, the method further includes: receiving an operation instruction and parsing the received operation instruction to determine the operation type indicated by the operation instruction; and determining the value of W based on the determined operation type, the width of the first matrix, and the number of calculation units.

[0022] Optionally, before reading the W first elements in the first matrix, the method further includes: configuring register parameters according to register instructions, the register instructions including at least the width, height, and row spacing of the first matrix; and confirming that the source addresses of the first matrix are continuous in response to the first matrix having the same width and row spacing.

[0023] According to three aspects of this application, a data processing apparatus based on a matrix processor is provided, comprising: a first reading module, configured to read W first elements from a first matrix and send the W first elements to a computing unit of the matrix processor for calculation; wherein, W is greater than the width N of the first matrix and less than or equal to the number K of the computing units of the matrix processor; repeating the above steps until the number of remaining elements in the first matrix is ​​less than W;

[0024] The second reading module is used to send the remaining elements into the calculation unit for calculation in response to the fact that the number of remaining elements in the first matrix is ​​not zero.

[0025] According to four aspects of this application, a data processing apparatus based on a matrix processor is provided, comprising: a first reading module, configured to read W first elements in a first matrix and obtain W second elements in a second matrix corresponding to the W first elements; wherein W is greater than the width N of the first matrix and less than or equal to the number K of the computing units of the matrix processor; and to input the W first elements and the W second elements into the computing units of the matrix processor for calculation; and a second reading module, configured to input the remaining elements into the computing units for calculation in response to the number of remaining elements in the first matrix being non-zero.

[0026] According to five aspects of this application, a computer-readable storage medium is provided having a computer program stored thereon, which, when executed by a processor, implements the methods described in the first and second aspects of the embodiments of this application.

[0027] According to six aspects of this application, a computer program product is provided that, when the computer program product is run on a computer, causes the computer to perform the method as described in the first and second aspects of the embodiments of this application.

[0028] According to seven aspects of this application, a chip is provided, wherein the chip includes a matrix processor and the apparatus of the third and fourth aspects of the embodiments of this application.

[0029] The beneficial effects of this application include:

[0030] The data processing method based on a matrix processor provided in this application optimizes the scheduling of matrix data for computation within the matrix processor computing unit during the computation cycle, thereby improving the utilization rate of the computing unit, reducing the number of computation cycles, and significantly shortening the computation time. Attached Figure Description

[0031] Figure 1 This is a schematic flowchart of a data processing method based on a matrix processor according to an embodiment of this application;

[0032] Figure 2 This is a schematic flowchart of a data processing method based on a matrix processor according to an embodiment of this application;

[0033] Figure 3 This is a diagram illustrating column-wise addition of a matrix.

[0034] Figure 4 This is a schematic diagram of the intermediate result of column accumulation operation of a matrix in a data processing method based on a matrix processor according to an embodiment of this application;

[0035] Figure 5 This is a schematic diagram of dot product operation between two matrices;

[0036] Figures 6(a) and 6(b) are schematic diagrams of a data processing method based on a matrix processor according to an embodiment of this application, before and after optimization of operations on two matrices;

[0037] Figure 7 This is a diagram illustrating the addition operation between a matrix and a single number;

[0038] Figure 8 This is a schematic diagram of the addition operation between a matrix and a row vector;

[0039] Figures 9(a)-9(c) are schematic diagrams of a data processing method based on a matrix processor according to an embodiment of this application, before and after optimization of operations on multi-row and multi-column matrices and single-row matrices;

[0040] Figure 10 This is a schematic diagram of the addition operation between a matrix and a column vector;

[0041] Figure 11 This is a schematic diagram illustrating the intermediate process of adding multi-row, multi-column matrices and single-column matrices according to a data processing method based on a matrix processor according to an embodiment of this application. Specific implementation methods

[0042] To make the objectives, technical solutions, and advantages of this application clearer, the application will be further described in detail below with reference to specific embodiments and accompanying drawings. It should be understood that these descriptions are merely exemplary and not intended to limit the scope of this application. Furthermore, descriptions of well-known structures and technologies are omitted in the following description to avoid unnecessarily obscuring the concepts of this application.

[0043] Unless otherwise defined, the technical or scientific terms used in this application shall have the ordinary meaning understood by one of ordinary skill in the art to which this application pertains. The terms "first," "second," and similar terms used in this application do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as "comprising" or "including" mean that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects.

[0044] Figure 1 This is a schematic flowchart of a data processing method based on a matrix processor according to an embodiment of this application. Figure 1 As shown, the data processing method based on a matrix processor in this embodiment mainly includes:

[0045] Step S101: Read W first elements from the first matrix and send them to the computing units of the matrix processor for calculation; where W is greater than N (the number of elements in each row of the first matrix) and less than or equal to K (the number of computing units of the matrix processor). The first matrix is ​​the source matrix to be calculated. Optionally, the source matrix stores data addresses; the corresponding data is read from memory according to the data addresses in the matrix, and then the read data is used for calculation.

[0046] In one embodiment, W first elements from the first matrix are read into the first register unit of the matrix processor. For the matrix processor, data needs to be read from an external source into the register before calculation, and then the data in the register is sent to the calculation unit for computation. The data source can be memory or other devices that directly input / output with the processor.

[0047] It should be noted that W is greater than the number of elements per row N of the first matrix (i.e., the width of the first matrix). Setting W > N ensures full utilization of the matrix processor's computing units in subsequent calculations. Due to hardware limitations, W is greater than the number of elements per row N of the first matrix, but less than or equal to the number of matrix processor computing units, which is K. In one embodiment, in the step of reading W first elements from the first matrix into the first register unit of the matrix processor, W can be set to K. When W = K, all matrix processor computing units can be utilized in subsequent calculations, achieving 100% utilization of the computing units.

[0048] Step S102: Repeat step S101 until the number of remaining elements in the first matrix is ​​less than W. In this step, W first elements from the first matrix are read and written to the calculation unit for calculation. When the matrix processor's calculation unit performs its first calculation, it first reads W first elements from the first matrix and sends them to the calculation unit, then reads W first elements from the first matrix again and sends them to the calculation unit. The calculation unit performs the calculation and outputs the result to the result register. When the matrix processor's calculation unit performs subsequent calculations, it first reads W first elements from the first matrix and sends them to the calculation unit, then reads W calculation results from the result register and sends them to the calculation unit. The calculation unit performs the calculation and updates the result register with the result. That is, the calculation result stored in the result register is the latest calculation result.

[0049] Step S103: In response to the non-zero number of remaining elements in the first matrix, retrieve the remaining elements from the first matrix and perform calculations in the calculation unit. If the number of remaining elements in the first matrix is ​​zero, the calculation is complete, and step S103 can be skipped. Iterate through all elements of the first matrix, repeating steps S101 and S102 until all elements in the first matrix have been read, i.e., the number of remaining elements in the first matrix is ​​zero.

[0050] If, after repeating steps S101 and S102 multiple times, the number of remaining elements in the first matrix is ​​less than W, then it is impossible to read W elements from the first matrix at once. Therefore, the remaining elements in the first matrix can be processed by the calculation unit at once, and the calculation is then completed. Optionally, after each calculation by the calculation unit, the result can be output to the result register unit of the matrix processor.

[0051] Compared to existing technologies, this method calculates W elements per computation cycle, where W is greater than the width N of the first matrix. This fully utilizes the computational units of the matrix processor, improving their utilization rate. For example, if W = 2N, the 2N elements are computed in parallel within the computational units, resulting in twice the computational efficiency of existing technologies.

[0052] Figure 2 This is a schematic flowchart of a data processing method based on a matrix processor according to an embodiment of this application. Figure 2 As shown, the data processing method based on a matrix processor in this embodiment mainly includes:

[0053] Step S201: Read W first elements from the first matrix and obtain W second elements corresponding to the W first elements from the second matrix; wherein W is greater than the width N of the first matrix and less than or equal to the number of computing units K of the matrix processor. In this embodiment, calculations can be performed on the first matrix and the second matrix. The first matrix is ​​a multi-row, multi-column matrix. The second matrix can be a multi-row, multi-column matrix, a single-row matrix with a height of 1, a single-column matrix with a width of 1, or a single number with both a height and width of 1.

[0054] Optionally, in obtaining the W second elements corresponding to the W first elements in the second matrix, Y second elements in the second matrix can be read first. In response to Y being less than W, the Y second elements are expanded to W second elements. Specifically, when both the first and second matrices are multi-row and multi-column matrices, W and Y are set to K. When both the first and second matrices are multi-row and multi-column matrices, Y is set to 1 and W is set to K. More specifically: in response to the setting W = α*N ≤ K, and the width of the first matrix being equal to the width of the second matrix, N second elements in the second matrix are read into the second register unit of the matrix processor; where α > 1 and α is an integer. Within the second register unit, the N second elements are copied α times to expand to obtain W second elements. Alternatively, in response to the setting W = α * N ≤ K, and the fact that the height of the first matrix is ​​equal to the height of the second matrix, α second elements from the second matrix are read into the second register unit of the matrix processor; within the second register unit, the α second elements are copied N times to expand to obtain W second elements. Alternatively, in response to the setting W = K, and the fact that the width and height of the second matrix are both 1, one second element from the second matrix is ​​read into the second register unit of the matrix processor; within the second register unit, this one second element is copied W times to expand to obtain W second elements.

[0055] Optionally, register parameters can be configured according to register instructions before data reading. These register instructions include at least the width, height, and row spacing of the first matrix. Since the width and row spacing of the first matrix are equal, the source addresses of the first matrix are confirmed to be contiguous, allowing multiple data entries from the first matrix to be read at once.

[0056] Step S202: Send W first elements and W second elements into the calculation unit of the matrix processor for calculation.

[0057] Step S203: Repeat the above steps until the number of remaining elements in the first matrix is ​​less than W.

[0058] Step S204: In response to the fact that the number of remaining elements in the first matrix is ​​not zero, the remaining elements are sent to the calculation unit for calculation.

[0059] According to this embodiment, W elements are calculated in each calculation cycle, making full use of the computing units provided by the matrix processor and improving the utilization rate of the computing units. For example, W = 2N, and 2N elements are calculated in parallel in the computing units, which is twice as efficient as the prior art.

[0060] One embodiment of this application discloses a data processing method based on a matrix processor, which includes:

[0061] Step S301: Receive an operation instruction and parse the received operation instruction to determine the operation type indicated by the operation instruction. In one embodiment, the matrix processor obtains the operation instruction, which includes at least the operation type to be performed. The operation type may include single matrix operation (i.e., calculation on the elements in a matrix, such as column element accumulation or row element accumulation), double matrix operation (i.e., operation between two matrices), operation between a matrix and a single number (i.e., a constant), operation between a matrix and a single row matrix, operation between a matrix and a single column matrix, etc.

[0062] The instruction is a RISC (Reduced Instruction Set Computer) instruction, and its format is shown in Table 1.

[0063] Table 1. Format examples of matrix operation instructions

[0064] Vector instructions 31 26 25 24 20 19 15 14 13 12 11 7 6 0 Veadd.mm 000001 0 rs2 rs1 0 00 rd 1111011

[0065] The instruction name for the example operation instruction in Table 1 is Veadd.mm. This instruction is used to perform a matrix addition operation on two matrices. As shown in the table above, bits 0-6 of the instruction indicate that this is a custom RISC instruction. rs1 and rs2 specify the first and second registers, and rd specifies the result register. The first and second registers are the source registers for the two matrices to be calculated, storing the data to be calculated in the source matrices; the result register is the destination register, storing the calculation result data. Reading the first, second, and result registers yields the starting addresses of the first, second, and third matrices. Bits 26-31 indicate that the operation indicated by this instruction is an add operation, i.e., adding the elements of the two matrices. Bits 25, 14, 13, and 12 together determine that the operation type of the current instruction is a two-matrix operation (represented by .mm). The instruction types also include .m, .mf, and .mv, where .m represents a single matrix operation, .mm represents an operation between two matrices, .mf represents an operation between a matrix and a single number, .mv represents an operation between a matrix and a vector, and .mv dim0 represents an operation between a matrix and a single row matrix (row vector), and .mv dim1 represents an operation between a matrix and a single column matrix (column vector).

[0066] Step S302: Determine the number W of elements to be periodically read based on the parsing results. Specifically, this determination can be made through pre-configuration, where the current number W of elements to be periodically read is already known and is fixed, requiring no real-time determination; alternatively, the value of W can be determined in real-time based on the received computation instructions, considering the type of computation, the width of the first matrix, and the number of computation units.

[0067] Due to the characteristics of different operation types, the number of data reads and operations will vary. For example, for column element accumulation in .m format, if the number of elements read each time is a whole row (1 row, 2 rows, or 3 rows, etc.), the column positions will correspond after the read data is written to the calculation unit. If the number of elements read each time is a whole row, the column information of each element read also needs to be recorded so that the column information of the elements obtained by each calculation unit is the same (i.e., located in the same column). Furthermore, the utilization rate of the calculation unit must also be considered when determining the value of W. Therefore, the number of elements read each time will vary depending on the operation type or the number of calculation units.

[0068] Therefore, in step S302, in response to the operation type being the first type, the number W of periodically read elements is determined to be the number K of computation units. The first type includes operation type .mm and operation type .mf. In response to the operation type being the second type, the number W of periodically read elements is determined to be an integer multiple of the width of the first matrix; the second type includes operation type .mv and operation type .m.

[0069] For example, when the matrix processor has 16 computation units and the source matrix has 7 row elements: if the received instruction type is .mm, 16 elements (W=K) of the source matrix can be read at once; if the received instruction type is .m, 14 elements (W=2N) of the source matrix can be read at once to perform row-by-row reading and calculation. When the matrix processor has 32 computation units and the source matrix has 7 row elements: if the received instruction type is .mm, 32 elements (W=K) of the source matrix can be read at once; if the received instruction type is .m, 28 elements (W=4N) of the source matrix can be read at once to perform row-by-row reading and calculation.

[0070] In one embodiment, a register instruction can be received, and register parameters can be configured according to the register instruction. The register instruction includes at least the width, height, and row spacing of the first matrix. The width of the first matrix is ​​N, the number of elements per row, and the row spacing is the address difference between adjacent rows in the same column. When the width and row spacing of the first matrix are equal, it is confirmed that the source addresses of the first matrix are contiguous. If the source addresses are contiguous, W data items can be read in a single memory read.

[0071] Step S303: Periodically read W elements from the first matrix and write them into the matrix processor's computing unit for calculation, until all elements in the first matrix have been read. In this step, based on the starting address of the first matrix, W elements of the source matrix are read from memory and written into the matrix processor's computing unit for calculation.

[0072] Furthermore, before periodically reading the W first elements in the first matrix, in response to the fact that the width and row spacing of the first matrix are equal, it is confirmed that the source addresses of the first matrix are continuous, so all W data can be read in at once by reading memory.

[0073] In one embodiment, in the step of sending W first elements to the matrix processor's computing unit for calculation, in response to the set W = K, the W first elements in the read first matrix are trimmed according to the data order to obtain W1 elements, that is, the W1 elements are the first W1 elements out of the W first elements. Here, W1 = β*N ≤ W, β > 1, and β is an integer; the W1 elements are then sent to the matrix processor's computing unit for calculation. For example, if the pre-configured value of W is fixed, assuming that the instruction type and the width of the source matrix are not considered, the value of W is fixed to the number of computing units. Since the positional correspondence of the data to be calculated needs to be considered, it is impossible to calculate W first elements at once. Therefore, during the process of writing data to the computing unit, the number of elements calculated each time, W1, is determined, where W1 is an integer multiple of the width of the source matrix.

[0074] For example, the matrix processor has 16 computation units, and the first matrix has 7 rows and 5 columns, i.e., K=16, M=7, N=5. Before reading W first elements from the first matrix into the first register unit of the matrix processor, W=16, so 16 first elements are read into the first register. Before sending the W first elements to the matrix processor computation unit for calculation, W1=β*N, for example, setting β=3. In this case, N=5, so W1=15, thus 15 elements are selected from the 16 read elements and sent to the computation unit for calculation. For some operation types, such as .m, the number of elements calculated each time is an integer multiple of N, which is beneficial for the output of the final result.

[0075] In one embodiment, the read address of the first matrix is ​​determined, where the read address is addr + β * N * (C - 1), addr is the address of the first element of the first matrix (i.e., the base address of the source matrix), and C is the number of times the first matrix is ​​read. The data of the first matrix can then be read based on this read address. The address of the first element of the first matrix, addr, can be pre-configured via register configuration before calculation, so that the address of the first element of the first matrix can be directly determined during data reading.

[0076] For example, if β=3, N=5, and the first element of the first matrix is ​​read for the first time, C=1, then the read address of the first matrix is ​​addr. When reading for the second time, C=2, then the read address of the first matrix is ​​addr+15.

[0077] In one embodiment, when reading the first matrix for the last time, if the number of unread first elements in the first matrix is ​​less than β*N, the first element in the first matrix is ​​read into the result register.

[0078] For example, column accumulation is performed on the first matrix. The matrix processor has 16 computational units, the first matrix has 7 rows and 5 columns (K=16, M=7, N=5), and β=3. During the third reading of the first matrix, the number of unread first elements is 5, which is less than 15. Therefore, the 5 unread first elements are read into the result register. Since 5 elements and 15 elements cannot be aligned, these 5 elements are read into the result register for subsequent operations.

[0079] Figure 3 This is a diagram illustrating column addition operations on a matrix. Figure 4 This is a schematic diagram of the intermediate result of a matrix column accumulation operation in a data processing method based on a matrix processor according to an embodiment of this application. For ease of description, in this embodiment, the operation instruction acc.m dim0 represents the matrix column accumulation operation, the first matrix is ​​M1, and the resulting target matrix is ​​V.

[0080] To perform column summation on a matrix, it is necessary to sum the column elements of all rows. However, according to the implementation of the operation instruction acc.m dim0 in this application embodiment, multiple rows of data are read and calculated at once. Therefore, it involves a process of folding intermediate results, that is, splitting intermediate results larger than the matrix width into multiple groups of data, with each group containing the same number of intermediate results as the matrix width. For example... Figure 4 As shown, in the last or penultimate calculation, assuming that the intermediate results c11, c12…c1N, c21, c22…c2N stored in the result register unit are 2N elements in total, these 2N elements are split into c11, c12…c1N and c21, c22…c2N respectively. Then, the two sets of data c11, c12…c1N and c21, c22…c2N are written into N calculation units respectively to calculate the target matrix V. Specifically: The result register contains u*N elements; L is set to the integer part of u / 2; if u is even, the elements in the result register are divided into two groups according to the storage order, each group containing L*N elements. The two groups of elements are sent to the calculation unit for calculation, and the L*N elements of the calculation result are output to the result register unit; if u is odd, the elements in the result register are divided into three groups according to the storage order, where the first and second groups contain L*N elements, and the third group contains N elements. The elements of the first and second groups are sent to the calculation unit for calculation, and the L*N elements of the calculation result are output to the result register unit. The result register unit contains the L*N elements of the calculation result and the N elements of the third group; if u is even, u is set to L; if u is odd, u is set to L+1; the above steps are repeated until u = 1.

[0081] For example, the first matrix is ​​calculated using `acc.m dim0`. The matrix processor has 16 computational units, and the first matrix has 7 rows and 5 columns (K=16, M=7, N=5). β=3 is set. After the second reading of the first matrix elements and their computation by the computational unit, the result register contains 15 elements. A third reading of 5 elements from the first matrix is ​​then added to the result register. The result register contains 20 elements (4*5 elements), u=4, and L=2. Since u is even, the elements in the result register are divided into two groups according to their storage order: the first 10 elements and the last 10 elements. These two groups are then added together by the computational unit, resulting in 10 elements in the result register. Since u is even and L=2, u=2 is set. Repeat the above steps, then divide the 10 elements into two groups of 5 elements each, with L=1. Input the elements from the first and second groups into the calculation unit for calculation. Output the 5 elements of the calculation result to the result register unit. Since u is even and L=1, set u=1, and the calculation ends. The 5 elements in the result register unit represent the calculation result of acc.mdim0 on the first matrix.

[0082] For example, the first matrix is ​​calculated using `acc.m dim0`. The matrix processor has 16 computation units, 8 rows, and 5 columns (K=16, M=8, N=5). β=3 is set. After the second reading of the first matrix elements and their computation by the computation unit, the result register contains 15 elements. A third reading of 10 elements from the first matrix is ​​then added to the result register. The result register contains 25 elements (5*5 elements), and u=5, so L=2. Since u is odd, the elements in the result register are divided into three groups according to storage order: the first and second groups contain 10 elements each, and the third group contains 5 elements. The elements from the first and second groups are sent to the computation unit for calculation. The resulting 10 elements are output to the result register unit, which contains the 10 elements of the calculation result and the 5 elements from the third group. Since u=5 is odd, u is set to 3. The above steps are repeated until u=1.

[0083] The implementation of the acc.m dim0 operation instruction specifically includes:

[0084] Step 1: Configure the register parameters to ensure that the addresses of the first matrix M1 and the destination matrix V are consecutive. Assume that the number of calculation units is 16, the width of M1 is 5, and the height is 7. Read 16 data (i.e. the first element) based on the base address of M1.

[0085] Step 2: During the implementation of the `acc.m dim0` operation instruction, each calculation by the 16 computation units of the matrix processor is performed on the entire row of the first matrix M1. Therefore, the 16 data points corresponding to M1 are truncated, with the width of the truncated data being three times the width of the matrix. This three-times-width matrix maximizes the utilization of the matrix processor's computation units. Since there is no other data to add during the first data read, these 15 data points can be temporarily stored in the first register. Alternatively, the truncated 15 data points can be temporarily written to the result register as intermediate results. During periodic calculations, each time the 16 data points of the first matrix M1 are read, truncated to obtain 15 data points, and then the result register is read, along with 15 data points, which are then sent to the computation unit. The computation unit then performs addition operations on the acquired data and writes the 15 calculated results sequentially into the result register. In the next calculation, these 15 calculation results and the data from the first matrix M1 can be used for further calculations.

[0086] Step 3: Calculate the base address of M1 plus the width of the matrix to determine the starting address for the second data reading (i.e., the address of the first column of the fourth row of M1). Then, read the 16 data corresponding to M1 based on this starting address.

[0087] Step 4: Trim the 16 data points corresponding to M1 read again, making the width of the trimmed data three times the width of the matrix. Write the trimmed data into 15 calculation units for calculation. Each calculation unit adds the two written data points and writes the intermediate result of the calculation into the result register.

[0088] Step 5: Calculate the base address of M1 + 2 * the width of the matrix to determine the starting address of the third data reading (i.e., the address of the first column of the seventh row of M1). Read the 5 data corresponding to M1 for the third time based on this starting address.

[0089] Step 6: Fold the intermediate results in the result register to form 10 data points and 5 data points. Combine the folded 5 data points with the 5 data points obtained in the third step to form 10 data points. Write the two sets of 10 data points into 10 calculation units for calculation. Write the intermediate results of the calculation into the result register.

[0090] Step 7: Fold the intermediate results in the result register again to form 5 data points and 5 data points. Write the 5 folded data points and 5 data points into 5 calculation units for calculation. Write the calculation result into the destination address. The calculation is complete.

[0091] It should be noted that, similar to the operation process of acc.m dim0, when calculating the maximum value of the first matrix's column (max.m dim0) and the minimum value of the column (min.m dim0), W first elements are also sent to the matrix processor's calculation unit. During the calculation, the result of the previous comparison (i.e., the intermediate result of the calculation) is compared with the data read this time, and the intermediate result is stored in the result register.

[0092] For example, `max.m dim0` represents extracting the maximum value of each column element of the first matrix to form a vector V1, V2…VN. Taking processing 2N elements at a time as an example, with W set to 2N, firstly, the 2N first elements of the first matrix are read into the first register. The data read for the first time does not have a base for calculating the maximum value; it is directly copied to the third memory as an intermediate result, for example, denoted as c11, c12…c1N, c21, c22…c2N. The second time, the 2N first elements of the first matrix are read into the first register, and the maximum value is calculated by combining them with the intermediate results c11, c12…c1N, c21, c22…c2N stored in the result register. The result is then assigned to c11, c12…c1N and c21, c22…c2N and stored in the result register. This process continues until all elements of the first matrix have been read. The final step involves folding c11, c12…c1N, and c21, c22…c2N and then performing a maximum value operation to obtain vectors V1, V2…VN. Correspondingly, the minimum value of the first matrix's column, min.m dim0, is also calculated using the same process.

[0093] Figure 5 This is a diagram illustrating the dot product operation between two matrices, where a... ij With b ij Multiplying them together, we get c. ij .like Figure 5 As shown, in this embodiment, the operation instruction mul.mm represents the dot product operation of two matrices, the first matrix is ​​M1, the second matrix is ​​M2, and the resulting target matrix is ​​M3.

[0094] The implementation of the mul.mm operation command specifically includes:

[0095] Step 1: Receive the mul.mm command. This command is 32-bit and has the following format:

[0096] 31 26 25 24 20 19 15 14 13 12 11 7 6 0 000001 6 rs2 rs1 0 0 rd 1111011

[0097] Bits 0 to 6 indicate that the instruction is a custom instruction of RISC-V;

[0098] rd is the base address of the destination matrix M3;

[0099] rs1 is the base address of the first matrix M1;

[0100] rs2 is the base address of the second matrix M2;

[0101] Bits 26 and 31 indicate that this instruction is a mul instruction, meaning that multiplication is performed in each computational unit;

[0102] 25, 14, 13:12 together determine that the current instruction is .mm, that is, the instruction type is a double matrix operation.

[0103] Step 2: Since the height, width, and row spacing of matrices M1 and M2, as well as the row spacing of matrix M3, have been set via CSR instructions (register instructions), the addresses of M1, M2, and M3 are determined to be contiguous based on these parameters. Assuming the number of computational units is 16, and the width and height of M1 and M2 are 5 and 7 respectively, according to the received `mul.mm` instruction, 16 data points corresponding to M1 are read from the base address of M1 (not read in whole rows, i.e., data is obtained in non-integer multiples of the row number), and 16 data points corresponding to M2 are read from the base address of M2 (not read in whole rows). The 16 data points corresponding to M1 and M2 are then written to the 16 computational units for calculation, and the calculation results are written to the destination address. In this embodiment, Y = W, and Y = K is set to ensure that the utilization rate of the matrix processor's computational units is 100%.

[0104] Step 3: Calculate the base address and calculation unit of M1 and M2 respectively to determine the starting address of the second data reading. Then, based on the starting address, read the 16 data corresponding to M1 and M2 respectively, write them into the calculation unit for calculation, and then write the calculation result into the destination address.

[0105] Step 4: Calculate the base address of M1 and M2 respectively + 2 * the number of calculation units to determine the starting address of the third data reading. Read the three data corresponding to M1 and M2 according to the starting address, write them into the calculation unit for calculation, and then write the calculation result to the destination address to complete the calculation.

[0106] It should be noted that since .mm represents the dot product of two matrices with the same shape, reading data in parts other than rows will not affect the data calculation. However, it is also possible to read data in whole rows. That is, for 16 calculation units, 15 data points (3 rows) corresponding to M1 and M2 are read each time for calculation. Specifically: First, 15 data points corresponding to M1 and M2 are read based on the base addresses of M1 and M2. Then, based on the base addresses of M1 and M2 plus the width of the matrix, the starting address for the second data reading is determined (i.e., the address of the first column of the fourth row of M1 and M2). The second 15 data points corresponding to M1 and M2 are read based on this starting address. Finally, based on the base addresses of M1 and M2 plus 2 * the width of the matrix, the starting address for the third data reading is determined (i.e., the address of the first column of the seventh row of M1 and M2). The third 5 data points corresponding to M1 and M2 are read based on this starting address.

[0107] Figures 6(a) and 6(b) are schematic diagrams of a data processing method based on a matrix processor according to an embodiment of this application, showing the operation of two matrices before and after optimization; wherein Figure 6(a) is the schematic diagram before optimization, and Figure 6(b) is the schematic diagram after optimization.

[0108] Referring to Figure 6(a), the matrix processor has 16 computing units (EU0-EU15), a first matrix and a second matrix of size 3*6. In the prior art, only 3 computing units can be used per cycle, and a total of 6 cycles are required to complete all the calculations.

[0109] In an optional embodiment, the first matrix is ​​a multi-row, multi-column matrix, the second matrix is ​​a multi-row, multi-column matrix, W equals K, and Y equals K. Referring to Figure 6(a), K is 16, then W and Y both take the value 16.

[0110] Referring to Figure 6(b), during the first cycle of calculation, the first 16 data points of the first and second matrices are read into the first and second registers respectively. During calculation, these data points are sent to 16 calculation units for one operation. Then, during the second cycle, the remaining two data points are calculated. In this way, the matrix operation of the chip can be completed in two cycles, which is 2 / 3 shorter than the original 6 cycles. For example, in this embodiment, the operation between the two matrices can be addition or Hadamard product multiplication.

[0111] For operations involving multiple matrices, there may be cases where the shapes of the first and second matrices differ. In such cases, for example, if the second matrix is ​​a constant, it can be expanded. During data acquisition, Y elements of the second matrix are read into the second register unit of the matrix processor. If Y is less than W, the Y elements are expanded into W elements within the second register unit. The W elements and W elements are then fed into K matrix processor calculation units for computation, and the result is output to the result register unit of the matrix processor.

[0112] Figure 7 This is a diagram illustrating the addition operation between a matrix and a single number, i.e., a ij Adding it to f gives c. ij .like Figure 7 As shown, in this embodiment, the operation instruction acc.mf represents the addition operation between a matrix and a single number. The first matrix is ​​M1, the second matrix is ​​f, and the resulting target matrix is ​​M3.

[0113] The implementation of acc.mf operation instructions specifically includes:

[0114] Step 1: Receive .mf operation instructions.

[0115] Step 2: Since the height, width, and row spacing of matrix M1, as well as the row spacing of matrix M3, have been set via the CSR instruction (register instruction), it can be determined that the addresses of M1 and M3 are contiguous based on these configured parameters. Assuming the number of computational units is 16, and the width and height of M1 are 5 and 7 respectively, the 16 data points (i.e., the first element) corresponding to M1 are read based on the base address of M1.

[0116] Step 3: f (i.e., the second element) is read only once. The data f is then copied multiple times. The width of the copied data is equal to the number of computational units K. In this embodiment, the number of computational units K is equal to the number of first elements read. The copied data is stored in the second register. By storing the copied data in the second register, f can be read only once. During the periodic calculations of the computational units, it is not necessary to read f from the outside each time; instead, it is read from the second register, which improves the calculation speed.

[0117] Step 4: Write the 16 data points corresponding to M1 read into 16 computing units, and write the 16 copied f data points into the same 16 computing units. Each computing unit adds the acquired data and writes the result to the destination address.

[0118] Step 5: Calculate the base address of M1 plus the number of calculation units to determine the starting address for the second data reading. Based on the starting address for the second reading, read the 16 data corresponding to M1. Write these 16 data and the data corresponding to the 16 copied f data back into the calculation unit for calculation. Then write the calculation result to the destination address.

[0119] Step 6: Calculate the base address of M1 + 2 * the number of calculation units to determine the starting address of the third data reading. Read the three data corresponding to M1 according to the starting address of the third reading, write the data corresponding to the three f to the calculation unit for calculation, and then write the calculation result to the destination address. All the calculation results written to the destination address constitute the destination matrix M3. The calculation is complete.

[0120] According to this embodiment, the addition operation between the first matrix and a single number is completed. The number of calculation cycles (the number of calculations by the calculation unit) is equal to the total number of elements in the first matrix (M*N) / W. Since W is greater than N, the number of calculation cycles is less than M, which improves the calculation efficiency compared to the prior art. For example, if W is 4 times N, then the number of calculation cycles is M / 4.

[0121] Figure 8 This is a schematic diagram of the addition operation between a matrix and a row vector, that is, a ij With V j Add them together to get c ij .like Figure 8 As shown, the calculation of the first matrix M1 and vector V in the row direction refers to the operation between the first row of M1 and the first row of V (V1-V). N The second row of data in M1 is also operated on with the first row of data in V, and so on, until all rows of the first matrix M1 are added to V. In this embodiment, the operation instruction acc.mv dim0 represents the addition operation between a matrix and a row vector, where a row vector is also a single-row matrix. The first matrix is ​​M1, the second matrix is ​​V, and the resulting target matrix is ​​M3.

[0122] The implementation of the `acc.mv dim0` operation instruction specifically includes:

[0123] Step 1: Receive the .mv dim0 operation command.

[0124] Step 2: Determine that the addresses of M1 and M3 are consecutive. Assume that the number of computing units is 16, the width of M1 is 5 and the height is 7, and the width of V is 5 and the height is 1. Read the 16 data corresponding to M1 according to the base address of M1.

[0125] Step 3: Trim the 16 data points corresponding to M1 read. The width of the trimmed data is 3 times the width of the matrix (i.e., calculate for 3 whole rows of data). If the number of data points W read each time is determined to be 15, that is, W is an integer multiple of the width of the source matrix, then it is not necessary to trim the read data.

[0126] Step 4: Read 16 data points based on the base address of V. Trim these 16 data points to obtain 5 data points corresponding to V. Alternatively, if you directly read the 5 data points of V, you don't need to trim them. Copy the trimmed data multiple times, specifically copying the entire row of V three times. The width of the copied data is three times the width of the matrix. Store the processed data in the second register so that you don't need to read the data from memory again when calculating subsequent rows.

[0127] Step 5: Write the 15 data corresponding to the clipped M1 into the calculation unit (at this time, one calculation unit will remain idle), and write the 15 copied V data corresponding to the calculation unit to perform addition calculation, and write the calculation result into the destination address.

[0128] Step 5: Calculate the base address of M1 plus the width of the matrix to determine the starting address for the second data reading (i.e., the address of the first column of the fourth row of M1). Then, read the 16 data corresponding to M1 based on this starting address.

[0129] Step 6: Trim the 16 data points corresponding to M1 again. The width of the trimmed data is three times the width of the matrix.

[0130] Step 7: Write the 15 data corresponding to the re-trimmed M1 into 15 calculation units, and write the 15 V data corresponding to the copied V in the register into 15 calculation units for calculation, and write the calculation result into the destination address.

[0131] Step 8: Calculate the base address of M1 + 2 * the width of the matrix to determine the starting address of the third data reading (i.e., the address of the first column of the seventh row of M1). Read the 5 data corresponding to M1 for the third time based on this starting address.

[0132] Step 9: Write the 5 data points read in the third reading and the corresponding data of the 5 V values ​​into the calculation unit for calculation, write the calculation result into the destination address, and the calculation is complete.

[0133] Figures 9(a)-9(c) are schematic diagrams of a data processing method based on a matrix processor according to an embodiment of this application, before and after optimization of operations on multi-row and multi-column matrices and single-row matrices;

[0134] Figure 9(a) schematically illustrates the operation of multi-row, multi-column matrices and single-row matrices in the prior art, where the first matrix is ​​operated on row by row with the second matrix. The matrix processor has 16 computing units, the first matrix is ​​3*6 in size, and the second matrix is ​​1*3. With the prior art, only 3 computing units can be used in each periodic calculation, and a total of 6 cycles are required to complete all calculations.

[0135] Figure 9(b) schematically illustrates the operation diagram after optimization of multi-row, multi-column matrices and single-row matrices. In one embodiment, the first matrix is ​​a multi-row, multi-column matrix, and the second matrix is ​​a single-row matrix; Y is the number of elements in the second matrix, which is 3. During the reading of elements of the second matrix, Y second elements are read from the outside for the first time. In the implementation of this type of instruction, setting W to an integer multiple of Y facilitates calculation and is beneficial to the output of the final result. The step of expanding Y second elements to W second elements is to copy Y second elements to W second elements within the second register unit. Referring to Figures 9(a) and 9(b), Y = 3 and W = 6. Each time, the six data points (two rows) of the first matrix are operated on with the second elements of the second matrix, and the calculation can be completed in 3 cycles. Thus, each cycle can use 6 calculation units, which is 1 / 2 shorter than the original 6 cycles.

[0136] It should be noted that W is an integer multiple of Y, as long as the value of W does not exceed the number of computing units in the matrix processor. For example, when W = 9, the calculation can be completed in only 2 computation cycles, which is 2 / 3 shorter than the original 6 cycles.

[0137] Figure 9(c) schematically illustrates the intermediate computational process after optimizing multi-row, multi-column matrices and single-row matrices. At this point, W is twice the size of Y, and V1, V2…VN are copied twice. W is also twice the number of columns N of the first matrix, that is, twice the number of elements per row. The W first elements are the first and second row elements of the first matrix, namely a11, a12…a1N and a21, a22…a2N. Since W is twice N, the number of cycles required to complete the computation is also half of the original.

[0138] Figure 10 This is a schematic diagram of the addition operation between a matrix and a column vector, that is, a ij With V i Add them together to get c ij .like Figure 10As shown, the first matrix M1 and vector V are added in the column direction. This means that the first row of data in M1 is calculated with V1, the second row of data in M1 is calculated with V2, and so on, until all columns of the first matrix M1 are added with V. In this embodiment, the operation instruction acc.mv dim1 represents the addition operation between a matrix and a column vector. A column vector is also a single-column matrix. The first matrix is ​​M1, the second matrix is ​​V, and the resulting target matrix is ​​M3.

[0139] The implementation of the `acc.mv dim1` operation instruction specifically includes:

[0140] Step 1: Receive the acc.mv dim1 operation command.

[0141] Step 2: Determine that the addresses of M1, V, and M3 are consecutive. Assume that the number of computing units is 16, the width of M1 is 5 and the height is 7, and the width of V is 1 and the height is 7. Read the 16 data corresponding to M1 according to the starting address of M1.

[0142] Step 3: Trim the 16 data points corresponding to M1 read. The width of the trimmed data is 3 times the width of the matrix (i.e., calculate for 3 whole rows of data).

[0143] Step 4: Read 16 data points based on the base address of V. Trim these 16 data points to obtain 7 data points corresponding to V. Alternatively, if you directly read the 7 data points of V, you don't need to trim them. Copy the trimmed data multiple times (copy data v1-v7 5 times each). Store the processed data in a register so that you don't need to read the data from memory again when calculating subsequent rows.

[0144] Step 5: Write the 15 data points corresponding to the clipped M1 into 15 calculation units, and write the 15 data points corresponding to the copied v1, v2, and v3 into 15 calculation units for calculation, and write the calculation results into the destination address.

[0145] Step 5: Calculate the base address of M1 plus the width of the matrix to determine the starting address for the second data reading (i.e., the address of the first column of the fourth row of M1). Then, read the 16 data corresponding to M1 based on this starting address.

[0146] Step 6: Trim the 16 data points corresponding to M1 again. The width of the trimmed data is three times the width of the matrix.

[0147] Step 7: Write the 15 data points corresponding to the re-trimmed M1 into 15 calculation units, and write the 15 data points corresponding to v4, v5, and v6 copied from the register into 15 calculation units for calculation. Write the calculation results into the destination address.

[0148] Step 8: Calculate the base address of M1 + 2 * the width of the matrix to determine the starting address for the third data reading (i.e., the address of the first column of the seventh row of M1). Read the 5 data corresponding to M1 for the third time based on this starting address.

[0149] Step 9: Write the 5 data points read in the third reading and the 5 data points corresponding to v7 into the calculation unit for calculation, write the calculation result into the destination address, and the calculation is complete.

[0150] Figure 11 This is a schematic diagram illustrating the intermediate process of adding multi-row, multi-column matrices and single-column matrices according to a data processing method based on a matrix processor according to an embodiment of this application.

[0151] In one embodiment, the first matrix is ​​a multi-row, multi-column matrix, and the second matrix is ​​a single-column matrix; Y is the number of elements in the second matrix, W is a multiple of N by R, where R is an integer; the steps to expand Y second elements into W second elements are as follows: within the second register unit, the Y second elements are copied N-1 times to form an intermediate matrix with Y×N elements, and R rows of second elements are taken from the intermediate matrix to form W second elements. (Reference) Figure 10 At this point, R = 2, and V1 and V2 are copied N-1 times in the second register, resulting in N V1 and V2 values ​​in the second register. The second row of the middle matrix is ​​taken as the second element, i.e., N V1 and N V2 values, and this is used to perform an operation with the first two rows of the first matrix, a11, a12…a1N, a21, a22…a2N. For example, addition can be performed. W is twice N, therefore the number of cycles required to complete the operation is also half of the original.

[0152] One embodiment of this application provides a data processing apparatus based on a matrix processor, including a first reading module for reading W first elements from a first matrix and sending the W first elements to a computing unit of the matrix processor for calculation; wherein W is greater than the width N of the first matrix and less than or equal to the number K of the computing units of the matrix processor; the above steps are repeated until the number of remaining elements in the first matrix is ​​less than W. A second reading module is used to send the remaining elements to the computing unit for calculation in response to the number of remaining elements in the first matrix being non-zero.

[0153] One embodiment of this application provides a data processing device based on a matrix processor, including a first reading module for reading W first elements in a first matrix and obtaining W second elements in a second matrix corresponding to the W first elements; wherein W is greater than the width N of the first matrix and less than or equal to the number K of the computing units of the matrix processor; the W first elements and W second elements are sent to the computing units of the matrix processor for calculation; and a second reading module for sending the remaining elements to the computing units for calculation in response to the number of remaining elements in the first matrix being non-zero.

[0154] One embodiment of this application provides a computer-readable storage medium storing a computer program thereon, which, when executed by a processor, implements the matrix processor-based data processing method of this application embodiment.

[0155] One embodiment of this application provides a computer program product that, when run on a computer, causes the computer to execute a matrix processor-based data processing method as described in this application embodiment.

[0156] One embodiment of this application provides a chip, wherein the chip includes a matrix processor and a data processing device based on the matrix processor according to an embodiment of this application.

[0157] In this embodiment, the number of matrix processor computing units is determined by hardware. If the matrix has continuous storage addresses outside the processor, the data processing method in this application can be used to improve the utilization rate of the matrix processor computing units, reduce the number of cycles used in the operation, and thus improve the computing efficiency.

[0158] It should be understood that the specific embodiments described above are merely illustrative or explanatory of the principles of this application and do not constitute a limitation thereof. Therefore, any modifications, equivalent substitutions, improvements, etc., made without departing from the spirit and scope of this application should be included within the protection scope of this application. Furthermore, the appended claims are intended to cover all variations and modifications falling within the scope and boundaries of the appended claims, or equivalent forms of such scope and boundaries.

Claims

1. A data processing method based on a matrix processor, characterized in that, include: Read W first elements from the first matrix into the first register unit of the matrix processor; W first elements are read from the first register unit and sent to the computation unit of the matrix processor, and W calculation results are read from the result register unit of the matrix processor and sent to the computation unit of the matrix processor, so that the computation unit performs calculations and updates the result register unit with the calculation results; wherein, the result register unit is used to cache the calculation results of the computation unit each time; W is greater than the width N of the first matrix and less than or equal to the number K of the computation units of the matrix processor; Repeat the above steps until the number of remaining elements in the first matrix is ​​less than W; In response to the fact that the number of remaining elements in the first matrix is ​​not zero, the remaining elements are sent to the computing unit for calculation; In response to the fact that the number of remaining elements in the first matrix is ​​zero, it is determined that the result register contains u*N elements; Set L to the integer part of u / 2; If u is even, the elements in the result register are divided into two groups according to the storage order, each group containing L*N elements. The two groups of elements are sent to the calculation unit for calculation, and the L*N elements of the calculation result are output to the result register unit. If u is odd, the elements in the result register are divided into three groups according to the storage order. The first and second groups contain L*N elements, and the third group contains N elements. The elements of the first and second groups are sent to the calculation unit for calculation. The L*N elements of the calculation result are output to the result register unit. The result register unit contains the L*N elements of the calculation result and the N elements of the third group. Repeat the above steps until u=1.

2. The method according to claim 1, characterized in that, The step of sending the W first elements into the calculation unit of the matrix processor for calculation includes: In response to the setting W=K, the W first elements in the read first matrix are pruned according to the data order to obtain W1 elements, where W1=β*N≤W, β>1, and β is an integer; The W1 elements are fed into the computing unit of the matrix processor for calculation.

3. The method according to claim 2, characterized in that, Before reading the W elements from the source matrix, the following steps are also included: Determine the read address of the first matrix, wherein the read address is addr+β*N*(C-1), addr is the address of the first element of the first matrix, and C is the number of times the first matrix is ​​read.

4. A data processing method based on a matrix processor, characterized in that, include: Read W first elements from the first matrix and obtain W second elements from the second matrix corresponding to the W first elements; wherein W is greater than the width N of the first matrix and less than or equal to the number K of the computing units of the matrix processor; The W first elements and the W second elements are fed into the computing unit of the matrix processor for calculation; The step of obtaining W second elements corresponding to the W first elements in the second matrix includes: in response to the setting W=α*N≤K and the width of the first matrix being equal to the width of the second matrix, reading N second elements from the second matrix into the second register unit of the matrix processor; where α>1 and α is an integer; within the second register unit, copying the N second elements α times to expand to obtain W second elements; or in response to the setting W=α*N≤K and the height of the first matrix being equal to the height of the second matrix, reading α second elements from the second matrix into the second register unit of the matrix processor; within the second register unit, copying the α second elements N times to expand to obtain W second elements; or in response to the setting W=K and the width and height of the second matrix being both 1, reading 1 second element from the second matrix into the second register unit of the matrix processor; within the second register unit, copying 1 second element W times to expand to obtain W second elements. Repeat the above steps until the number of remaining elements in the first matrix is ​​less than W; In response to the fact that the number of remaining elements in the first matrix is ​​not zero, the remaining elements are sent to the computing unit for calculation.

5. The method according to claim 4, characterized in that, Before reading the W first elements in the first matrix, the process also includes: Receive operation instructions and parse the received operation instructions to determine the type of operation indicated by the operation instructions; The value of W is determined based on the defined operation type, the width of the first matrix, and the number of computational units.

6. The method according to claim 4, characterized in that, Before reading the W first elements in the first matrix, the process also includes: Register parameters are configured according to register instructions, wherein the register instructions include at least the width, height and row spacing of the first matrix; In response to the fact that the width and row spacing of the first matrix are equal, it is confirmed that the source addresses of the first matrix are continuous.

7. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by a processor, it implements the method of any one of claims 1 to 3, 4 to 6.

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