Electrostatic discharge protection circuit

Abstract

An electrostatic discharge protection circuit includes a detection circuit, a voltage dividing element, and a discharge element. The detection circuit is coupled between a first power supply line and a second power supply line. When an electrostatic discharge event occurs, the detection circuit enables a conductive signal. The voltage dividing element is coupled between the first power supply line and a third power supply line and receives the conductive signal. The discharge element is coupled between the second and third power supply lines. When the conductive signal is enabled, the discharge element discharges an electrostatic discharge current to prevent integrated circuit damage from the electrostatic discharge event.

Description

TECHNICAL FIELD

[0001] The present invention relates to a protection circuit, and more particularly, to an electrostatic discharge protection circuit. BACKGROUND

[0002] Element damage caused by electrostatic discharge (ESD) has become one of the most important reliability problems for integrated circuit products. Especially as the size is continuously reduced to deep sub-micron level, the gate oxide layer of the metal-oxide-semiconductor is also getting thinner, and the integrated circuit is more likely to be damaged by electrostatic discharge phenomenon. SUMMARY

[0003] One embodiment of the present invention provides an electrostatic discharge protection circuit including a detection circuit (110), a voltage dividing element (120), and a discharge element (130). The detection circuit is coupled between a first power line (PL1) and a second power line (PL2). The voltage dividing element is coupled between the first power line (PL1) and a third power line (PL3) and receives a pass signal. The discharge element is coupled between the second and third power lines. When an electrostatic discharge event occurs at the third power line, the detection circuit is activated by the voltage dividing element, and the detection circuit enables a pass signal. When the pass signal is enabled, the discharge element discharges an electrostatic discharge current.

[0004] In another embodiment, the electrostatic discharge protection circuit includes a detection circuit (110), a voltage dividing element (120), a first transistor (130), and a second transistor (140). The detection circuit is coupled between a first power line (PL1) and a second power line (PL2). When an electrostatic discharge event occurs at the third power line, the detection circuit is activated by the voltage dividing element, and the detection circuit enables a pass signal. When the pass signal is enabled, the first transistor (130) discharges an electrostatic discharge current. When an electrostatic discharge event occurs at the first power line, the detection circuit enables a pass signal. When the pass signal is enabled, the second transistor (140) discharges an electrostatic discharge current. The first transistor includes a first base, a first gate, a first drain, and a first source. The first gate receives the pass signal. The first drain is coupled to a third power line. The first source and the first base are coupled to the second power line. The second transistor includes a second base, a second gate, a second drain, and a second source. The second gate receives the pass signal. The second drain is coupled to the first power line. The second source and the second base are coupled to the second power line. When the pass signal is enabled, the first and second transistors are turned on to discharge an electrostatic discharge current.

[0005] When no ESD event occurs, the detection circuit does not enable the on signal, and none of the high voltage transistors is turned on. Since the high voltage transistors block the high operating voltage from entering the detection circuit, the components (e.g. transistors) in the detection circuit are protected from damage; when the on signal is enabled, the release component releases an ESD current, and when the high voltage transistors are used as voltage dividing components, they can not only withstand the high operating voltage, but also protect the components in the detection circuit from damage by the high operating voltage. BRIEF DESCRIPTION OF DRAWINGS

[0006] Figure 1 A possible embodiment of the ESD protection circuit of the present application;

[0007] Figure 2 Another embodiment of the ESD protection circuit of the present application;

[0008] Figure 3 A possible schematic diagram of the detection circuit of the present application;

[0009] Figure 4 A schematic diagram of the low voltage transistor of the present application;

[0010] Figure 5 A schematic diagram of the high voltage transistor of the present application. BRIEF DESCRIPTION OF DRAWINGS

[0012] 100: ESD protection circuit

[0013] 110: Detection circuit

[0014] 120: Voltage dividing component

[0015] 130, 140: Release component

[0016] PL1-PL3: Power line

[0017] SON: On signal

[0018] VDD: Low operating voltage

[0019] VCC: High operating voltage

[0020] VSS: Ground voltage

[0021] HVN1, HVN2, 500: High voltage transistor

[0022] LVP, LVN1, LVN2, 400: Low voltage transistor

[0023] 121, 131, 141, 311, 315: Gate

[0024] 122, 132, 142, 313, 316: Drain

[0025] 123, 133, 143, 312, 317: source

[0026] 124, 134, 144, 314, 318: base

[0027] R: resistance

[0028] C: capacitance

[0029] A, B: node

[0030] 410, 510, 520: well

[0031] 421-423, 531-533: doped region

[0032] 424, 534: gate structure

[0033] 431-434, 541-544: contact pad DETAILED DESCRIPTION

[0034] In order to make the objects, features and advantages of the application more clear, the following embodiments are specifically given, and the accompanying drawings are used for detailed description. The present application provides different embodiments to explain the technical features of different embodiments of the application. The configuration of each element in the embodiments is for illustration, and is not intended to limit the application. In addition, part of the reference numerals in the embodiments is repeated, in order to simplify the description, and is not intended to indicate the relevance between different embodiments.

[0035] Figure 1 A possible embodiment of the electrostatic discharge protection circuit. As shown, the electrostatic discharge protection circuit 100 includes a detection circuit 110, a voltage dividing element 120, and a release element 130. The detection circuit 110 is coupled between power lines PL1 and PL2, and detects whether an electrostatic discharge event occurs. When an electrostatic discharge event occurs, the detection circuit 110 enables a conductive signal SON. If no electrostatic discharge event occurs, the detection circuit 110 does not enable the conductive signal SON. In a possible embodiment, when no electrostatic discharge event occurs, the power line PL1 receives a low operating voltage VDD, and the power line PL2 receives a ground voltage VSS. In this example, the low operating voltage VDD is greater than the ground voltage VSS. In a possible embodiment, the low operating voltage VDD is about 5V, and the ground voltage VSS is about 0V.

[0036] The voltage dividing element 120 is coupled between the power lines PLl and PL3 and receives the signal SON. In the present embodiment, the voltage dividing element 120 is a bridge between the high operating voltage VCC and the low operating voltage VDD. For example, in a normal mode (i.e., no electrostatic discharge event), the power line PLl receives a low operating voltage VDD and the power line PL3 receives a high operating voltage VCC. In a possible embodiment, the low operating voltage VDD is less than the high operating voltage VCC. For example, the low operating voltage VDD is about 1.8V, 3.3V, or 5V, and the high operating voltage VCC is about 30V. Since the voltage dividing element 120 is a high voltage device, it can withstand the high operating voltage VCC.

[0037] In the present embodiment, the voltage dividing element 120 is a high voltage transistor HVN2. The gate 121 of the high voltage transistor HVN2 receives the signal SON. The drain 122 of the high voltage transistor HVN2 is coupled to the power line PL3. The source 123 of the high voltage transistor HVN2 is coupled to the power line PLl. The bulk 124 of the high voltage transistor HVN2 is coupled to the power line PL2.

[0038] The present application is not limited to the type of the high voltage transistor HVN2. In the present embodiment, the high voltage transistor HVN2 is an N-type transistor, but is not intended to limit the present application. In other embodiments, the high voltage transistor HVN2 is a P-type transistor. In some embodiments, the junction voltage between the drain 122 and the bulk 124 of the high voltage transistor HVN2 is higher than the junction voltage between the source 123 and the bulk 124. In a possible embodiment, the drain of the high voltage transistor HVN2 is formed in a diffused region. Since the diffused region has a low impurity concentration, it can withstand a high voltage. In a possible embodiment, the high voltage transistor HVN2 is a Lateral Diffused Metal-Oxide-Semiconductor Field-Effect Transistor (LDMOSFET) or a Double Diffused Metal-Oxide-Semiconductor Field-Effect Transistor (DDMOSFET).

[0039] The release element 130 is coupled between the power lines PL2 and PL3. When the enable signal SON is enabled, the release element 130 releases an electrostatic discharge current. In the present embodiment, the release element 130 is a high voltage transistor HVNl. The gate 131 of the high voltage transistor HVNl receives the enable signal SON. The drain 132 of the high voltage transistor HVNl is coupled to the power line PL3. The source 133 and the base 134 of the high voltage transistor HVNl are coupled to the power line PL2. The present application is not limited to the type of the high voltage transistor HVNl. In the present embodiment, the high voltage transistor HVNl is an N-type transistor, but is not intended to limit the present application. In other embodiments, the high voltage transistor HVNl is a P-type transistor. In some embodiments, the junction voltage between the drain 132 and the base 134 of the high voltage transistor HVNl is higher than the junction voltage between the source 133 and the base 134. In one possible embodiment, the high voltage transistor HVNl is a LDMOSFET or a DDMOSFET.

[0040] When an electrostatic discharge event occurs on the power line PL3 and the power line PLl is floating, a portion of the electrostatic discharge current flows from the power line PL3, through the high voltage transistor HVN2, and into the detection circuit 110 because the high voltage transistor HVN2 is not completely off. At this time, the detection circuit 110 enables the enable signal SON. Therefore, the high voltage transistor HVNl is turned on. At this time, most of the electrostatic discharge current flows from the power line PL3, through the high voltage transistor HVNl, and into the power line PL2.

[0041] When no electrostatic discharge event occurs, the power lines PLl and PL3 receive a low operating voltage VDD and a high operating voltage VCC, respectively, and the power line PL2 receives a ground voltage VSS. At this time, the detection circuit 110 does not enable the enable signal SON. Therefore, the high voltage transistors HVNl and HVN2 are not turned on. Because the high voltage transistor HVN2 blocks the high operating voltage VCC from entering the detection circuit 110, the components (e.g., transistors) in the detection circuit 110 are protected from damage.

[0042] Figure 2 Another embodiment of the electrostatic discharge protection circuit of the present application. Figure 2 Similarly Figure 1 The difference is that, Figure 2A discharge element 140 is added. The discharge element 140 is coupled between the power lines PL1 and PL2. The discharge element 140 discharges an electrostatic discharge current when the enable signal SON is enabled. In this embodiment, the discharge element 140 is a low voltage transistor LVN1. The gate 141 of the low voltage transistor LVN1 receives the enable signal SON. The drain 142 of the low voltage transistor LVN1 is coupled to the power line PL1. The source 143 and the base 144 of the low voltage transistor LVN1 are coupled to the power line PL2.

[0043] The present application is not limited to the type of low voltage transistor LVN1. In this embodiment, the low voltage transistor LVN1 is an N-type transistor, but is not intended to limit the present application. In other embodiments, the low voltage transistor LVN1 is a P-type transistor. In some embodiments, the junction voltage between the drain 122 and the base 124 of the high voltage transistor HVN2 is higher than the junction voltage between the drain 142 and the base 144 of the low voltage transistor LVN1. In another possible embodiment, the junction voltage between the drain 132 and the base 134 of the high voltage transistor HVN1 is also higher than the junction voltage between the drain 142 and the base 144 of the low voltage transistor LVN1. In a possible embodiment, the drain 142 and the source 143 of the low voltage transistor LVN1 are formed between the same well (e.g., P-well).

[0044] Figure 3 A possible schematic diagram of the detection circuit 110 of the present application. As shown, the detection circuit 110 includes a resistor R, a capacitor C, low voltage transistors LVP and LVN2. The resistor R is coupled between the power line PL1 and a node A. The capacitor C is coupled between the node A and the power line PL2. In other embodiments, the capacitor C is formed by a transistor. In this case, the gate of the transistor is coupled to the node A, and the drain, source and base of the transistor are all coupled to the power line PL2.

[0045] The gate 311 of the low voltage transistor LVP is coupled to the node A, the source 312 of the low voltage transistor LVP is coupled to the power line PL1, and the drain 313 of the low voltage transistor LVP is coupled to a node B. The gate 315 of the low voltage transistor LVN2 is coupled to the node A, the source 317 of the low voltage transistor LVN2 is coupled to the power line PL2, and the drain 316 of the low voltage transistor LVN2 is coupled to the node B. In this embodiment, both the low voltage transistor LVP and the low voltage transistor LVN2 are low voltage transistors. In a possible embodiment, the low voltage transistor LVP is a P-type transistor, and the low voltage transistor LVN2 is an N-type transistor. In this case, the low voltage transistor LVP and the low voltage transistor LVN2 form an inverter to invert the level of the node A. For example, when an electrostatic discharge event occurs, the node A is at a low level. Therefore, the node B is at a high level. When an electrostatic discharge event does not occur, the node A is at a high level. Therefore, the node B is at a low level.

[0046] In this embodiment, the junction voltage between the source 312 and the base 314 of the low voltage transistor LVP or the junction voltage between the drain 313 and the base 314 of the low voltage transistor LVP is less than the junction voltage between the drain 122 and the base 124 of the high voltage transistor HVN2. In this embodiment, the junction voltage between the source 312 and the base 314 of the low voltage transistor LVP or the junction voltage between the drain 313 and the base 314 of the low voltage transistor LVP is less than the junction voltage between the drain 132 and the base 134 of the high voltage transistor HVNl.

[0047] In another possible embodiment, the junction voltage between the drain 316 and the base 318 of the low voltage transistor LVN2 or the junction voltage between the source 317 and the base 318 of the low voltage transistor LVN2 is less than the junction voltage between the drain 122 and the base 124 of the high voltage transistor HVN2. In this embodiment, the junction voltage between the drain 316 and the base 318 of the low voltage transistor LVN2 or the junction voltage between the source 317 and the base 318 of the low voltage transistor LVN2 is less than the junction voltage between the drain 132 and the base 134 of the high voltage transistor HVNl.

[0048] Figure 4 A schematic diagram of a low voltage transistor of the present application is shown in FIG. 4. As shown, the low voltage transistor 400 includes a well 410, doped regions 421-423, and a gate structure 424. The doped regions 421-423 are disposed in the well 410. In this embodiment, the well 410 and the doped region 421 have a first conductivity type, where the doped region 421 has a higher doping concentration than the well 410. The doped regions 422 and 423 have a second conductivity type. In this embodiment, the junction voltage between the doped region 423 and the well 410 is similar to the junction voltage between the doped region 422 and the well 410. In one possible embodiment, the first conductivity type is P-type and the second conductivity type is N-type. The gate structure 424 is formed over the well 410.

[0049] In some embodiments, the doped region 421 is electrically connected to a base contact pad 431. The doped region 422 is electrically connected to a source contact pad 432. The gate structure 424 is electrically connected to a gate contact pad 433. The doped region 423 is electrically connected to a drain contact pad 434. In this embodiment, the base contact pad 431 serves as the base of the transistor 400, the source contact pad 432 serves as the source of the transistor 400, the gate contact pad 433 serves as the gate of the transistor 400, and the drain contact pad 434 serves as the drain of the transistor 400.

[0050] Figure 5A schematic diagram of a high voltage transistor of the present application is shown in FIG. 5. As shown, the high voltage transistor 500 includes a well 510, a diffusion region 520, doped regions 531-533, and a gate structure 534. The doped regions 531 and 532 are disposed in the well 510. In this embodiment, the well 510 and the doped region 531 have a first conductivity type, and the doped region 531 has a higher doping concentration than the well 510. The doped region 532 has a second conductivity type. The second conductivity type is opposite to the first conductivity type. For example, when the first conductivity type is P-type, the second conductivity type is N-type.

[0051] The diffusion region 520 is disposed in the well 510. The doped region 533 is disposed in the diffusion region 520. The diffusion region 520 and the doped region 533 have the second conductivity type, and the diffusion region 520 has a lower doping concentration than the doped region 533. In one possible embodiment, the diffusion region 520 is a high voltage N-type diffusion region (HVNDD). In this embodiment, the junction voltage between the diffusion region 520 and the well 510 is higher than the junction voltage between the doped region 532 and the well 510. In one possible embodiment, the junction voltage between the doped region 532 and the well 510 is similar to the junction voltage between the doped region 423 and the well 410 and the junction voltage between the doped region 422 and the well 410. Figure 4

[0052] In some embodiments, the doped region 531 is electrically connected to a base contact pad 541. The doped region 532 is electrically connected to a source contact pad 542. The gate structure 534 is electrically connected to a gate contact pad 543. The doped region 533 is electrically connected to a drain contact pad 544. In this example, the base contact pad 541 serves as the base of the transistor 500, the source contact pad 542 serves as the source of the transistor 500, the gate contact pad 543 serves as the gate of the transistor 500, and the drain contact pad 544 serves as the drain of the transistor 500.

[0053] Because the diffusion region 520 has a lower doping concentration, the junction voltage between the doped region 533 and the well 510 can be increased, so that the doped region 533 can withstand a high operating voltage (e.g., VCC). In this embodiment, when the high voltage transistor 500 is used as the voltage dividing element 120, not only can the high operating voltage VCC be withstood, but also the internal components of the detection circuit 110 can be protected from the high operating voltage VCC. Figure 1

[0054] It must be understood that when an element or layer is referred to as being "coupled" to another element or layer, it can be directly coupled or connected to the other element or layer, or intervening elements or layers can be present. In contrast, when an element or layer is referred to as being "connected" to another element or layer, no intervening elements or layers are present. ​​

[0055] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art. Further, unless otherwise clear from the context, the terms used herein are to be construed as not limited to the special, idealized, or overly formal sense unless expressly so limited. Although the terms "first," "second," etc. can be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another.

[0056] While the application has been described by way of example with reference to preferred embodiments, it is to be understood that persons skilled in the art can make modifications and improvements to the application without departing from the spirit and scope thereof. For example, the system, device or method described in the embodiments of the application can be implemented in hardware, software or a combination of hardware and software. The scope of the application is therefore to be limited only by the scope of the appended claims.

Claims

1. An electrostatic discharge protection circuit, characterized by comprising: comprises: a detection circuit coupled between a first power line and a second power line, the detection circuit enabling a pass signal when an electrostatic discharge event occurs; a voltage dividing element coupled between the first power line and a third power line, the voltage dividing element receiving the pass signal; and a first discharge element coupled between the second and third power lines, the first discharge element discharging an electrostatic discharge current when the pass signal is enabled; wherein the voltage dividing element comprises a second transistor, a gate of the second transistor receiving the pass signal, a drain of the second transistor coupled to the third power line, a source of the second transistor coupled to the first power line, and a base of the second transistor coupled to the second power line; an interface voltage between the drain and the base of the second transistor being greater than an interface voltage between the source and the base of the second transistor. when the electrostatic discharge event does not occur, the first power line receives a first voltage, the second power line receives a second voltage, and the third power line receives a third voltage, the first voltage being greater than the second voltage, and the third voltage being greater than the first voltage.

2. The electrostatic discharge protection circuit of claim 1, wherein, the first discharge element comprises a first transistor, a gate of the first transistor receiving the pass signal, a drain of the first transistor coupled to the third power line, and a source and a base of the first transistor coupled to the second power line.

3. The electrostatic discharge protection circuit of claim 1, wherein, 4. The electrostatic discharge protection circuit of claim 3, wherein the first and second transistors are lateral diffused transistors. the detection circuit comprises:

5. The electrostatic discharge protection circuit of claim 3, wherein, a resistor coupled between the first power line and a first node; a capacitor coupled between the first node and the second power line; a third transistor having a gate coupled to the first node, a source coupled to the first power line, and a drain coupled to a second node; and a fourth transistor having a gate coupled to the first node, a source coupled to the second power line, and a drain coupled to the second node; wherein an interface voltage between the drain and the base of the third transistor is less than an interface voltage between the drain and the base of the first transistor. further comprising:

6. The electrostatic discharge protection circuit of claim 1, wherein, a second discharge element coupled between the first and second power lines, the second discharge element discharging the electrostatic discharge current when the pass signal is enabled.

7. The electrostatic discharge protection circuit of claim 6, wherein: the first discharge element comprises a first transistor, a gate of the first transistor receiving the pass signal, a drain of the first transistor coupled to the third power line, and a source and a base of the first transistor coupled to the second power line; and the second discharge element comprises a fifth transistor, a gate of the fifth transistor receiving the pass signal, a drain of the fifth transistor coupled to the first power line, and a source and a base of the fifth transistor coupled to the second power line. an interface voltage between the drain and the base of the fifth transistor is less than an interface voltage between the drain and the base of the first transistor. when the electrostatic discharge event occurs on the third power line, a portion of the electrostatic discharge current passes through the voltage dividing element into the detection circuit, causing the detection circuit to enable the pass signal.

8. The electrostatic discharge protection circuit of claim 7, wherein, comprises:

9. The electrostatic discharge protection circuit of claim 1, wherein, a detection circuit coupled between a first power line and a second power line, the detection circuit enabling a pass signal when an electrostatic discharge event occurs; 10. An electrostatic discharge protection circuit, characterized by, ​ ​ a first transistor including a first gate, a first drain, a first source, and a first base, the first gate receiving the pass signal, the first drain coupled to a third power line, the first source coupled to the second power line; and a second transistor including a second gate, a second drain, a second source, and a second base, the second gate receiving the pass signal, the second drain coupled to the third power line, the second source coupled to the first power line; wherein: when the pass signal is enabled, the first and second transistors are turned on to discharge an electrostatic discharge current; a junction voltage between the first drain and the first base is higher than a junction voltage between the first source and the first base; a junction voltage between the second drain and the second base is higher than a junction voltage between the second source and the second base.

11. The electrostatic discharge protection circuit of claim 10, wherein, further comprising: a third transistor including a third gate, a third drain, a third source, and a third base, the third gate receiving the pass signal, the third drain coupled to the first power line, the third source and the third base coupled to the second power line; wherein: when the pass signal is enabled, the third transistor is turned on to discharge the electrostatic discharge current.

12. The electrostatic discharge protection circuit of claim 11, wherein, a junction voltage between the first drain and the first base is higher than a junction voltage between the third drain and the third base, and a junction voltage between the second drain and the second base is higher than a junction voltage between the third drain and the third base.

13. The electrostatic discharge protection circuit of claim 10, wherein, the detection circuit includes: a resistor coupled between the first power line and a first node; a capacitor coupled between the first node and the second power line; a fourth transistor including a fourth gate, a fourth drain, a fourth source, and a fourth base, the fourth gate coupled to the first node, the fourth source coupled to the first power line, the fourth drain coupled to a second node; and a fifth transistor including a fifth gate, a fifth drain, a fifth source, and a fifth base, the fifth gate coupled to the first node, the fifth source coupled to the second power line, the fifth drain coupled to the second node; wherein: a junction voltage between the first drain and the first base is higher than a junction voltage between the fourth drain and the fourth base; a junction voltage between the first drain and the first base is higher than a junction voltage between the fifth drain and the fifth base.

14. The electrostatic discharge protection circuit of claim 13, wherein, the first, second, third, and fifth transistors are N-type transistors, and the fourth transistor is a P-type transistor.

15. The electrostatic discharge protection circuit of claim 10, wherein, the second base is coupled to the second power line.

16. The electrostatic discharge protection circuit of claim 10, wherein, when the electrostatic discharge event does not occur, the first power line receives a first voltage, the second power line receives a second voltage, and the third power line receives a third voltage, the first voltage is greater than the second voltage, and the third voltage is greater than the first voltage.

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