Power supply voltage detection circuit, electronic device, and detection method

Abstract

The application relates to a power supply voltage detection circuit, an electronic device and a detection method. The power supply voltage detection circuit comprises a first switch, a control circuit and a detection circuit. One end of the first switch is connected with a power supply end, and the other end of the first switch is connected with the ground. The control circuit is used for keeping the first switch on during detection and controlling the detection circuit to work, and is used for controlling the first switch to be turned off after the detection is completed. The first switch is used for inputting a target voltage into the detection circuit when being turned on and stopping the generation of the target voltage when being turned off. The detection circuit is used for obtaining a detection result according to the target voltage and a preset reference voltage. The target voltage is related to the power supply voltage. The method can reduce the static power consumption of a Flash ADC.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of voltage detection, in particular to a power supply voltage detection circuit, an electronic device and a detection method. BACKGROUND

[0002] An electronic system is in an unstable state when powered on, and it is often necessary to detect the power supply voltage to ensure that the power supply voltage is within a suitable voltage range, so as to ensure that the electronic system works normally.

[0003] At present, the detection of the power supply voltage is often realized by converting an analog voltage value into a digital voltage value through a full-parallel analog-to-digital converter (Flash ADC).

[0004] However, the existing Flash ADC has the problem of high static power consumption, resulting in resource waste. SUMMARY

[0005] The present application provides a power supply voltage detection circuit, an electronic device and a detection method, which can reduce the static power consumption of the Flash ADC.

[0006] In a first aspect, the present application provides a power supply voltage detection circuit. The power supply voltage detection circuit comprises a first switch, a control circuit and a detection circuit; one end of the first switch is connected with a power supply end, and the other end of the first switch is connected with a ground;

[0007] The control circuit is configured to keep the first switch on during detection and control the detection circuit to work, and control the first switch to be off after the detection is completed.

[0008] The first switch is configured to make a target voltage input the detection circuit when the first switch is on, and stop the generation of the target voltage when the first switch is off.

[0009] The detection circuit is configured to obtain a detection result according to the target voltage and a preset reference voltage; the target voltage is related to the power supply voltage.

[0010] In one of the embodiments, the power supply voltage detection circuit further comprises a plurality of resistors connected in series; and the first switch is arranged on a branch where the plurality of resistors are located.

[0011] In one of the embodiments, the detection circuit comprises a decoding circuit and at least three comparison branches; each comparison branch is connected with the first switch, the control circuit and the decoding circuit; the comparison branch is configured to compare the target voltage with the reference voltage to obtain a comparison result under the control of the control circuit, and latch the comparison result under the control of the control circuit; wherein the reference voltages corresponding to the comparison branches are different; and the decoding circuit is configured to output the detection result according to the comparison results of the at least three comparison branches.

[0012] In one of the embodiments, the comparison branch comprises a second switch, a third switch and a comparator; a first end of the second switch is connected with the first switch, and a second end of the second switch is connected with a first input end of the comparator; a first end of the third switch is connected with the first input end of the comparator and the second end of the second switch, and a second end of the third switch is connected with a second input end of the comparator; the second input end of the comparator is also connected with a reference voltage end, an output end of the comparator is connected with the decoding circuit, and an enable end of the comparator is connected with the control circuit.

[0013] In one of the embodiments, the control circuit comprises a first control sub-circuit, a second control sub-circuit and a third control sub-circuit; the first control sub-circuit, the second control sub-circuit and the third control sub-circuit are connected in sequence; an output end of the first control sub-circuit is also used for outputting a first control signal to the second switch of each comparison branch; an output end of the second control sub-circuit is also used for outputting a second control signal to the third switch of each comparison branch; and an output end of the third control sub-circuit is used for outputting a third control signal to the first switch.

[0014] In one of the embodiments, the first control sub-circuit comprises a buffer and a first delay unit; an output end of the buffer is connected with an input end of the first delay unit, and an output end of the first delay unit is connected with an input end of the second control sub-circuit.

[0015] In one of the embodiments, the second control sub-circuit comprises a first inverter; an input end of the first inverter is connected with an output end of the first control sub-circuit, and an output end of the first inverter is connected with an input end of the third control sub-circuit.

[0016] In one of the embodiments, the third control sub-circuit comprises a second inverter and a second delay unit; an input end of the second inverter is connected with an output end of the second control sub-circuit, an output end of the second inverter is connected with an input end of the second delay unit, and an output end of the second delay unit outputs the third control signal to the first switch.

[0017] In a second aspect, the application further provides an electronic device. The electronic device comprises the power supply voltage detection circuit as described in the above embodiments.

[0018] In a third aspect, the application further provides a detection method. The detection method comprises:

[0019] In the detection process, the first switch of the power supply voltage detection circuit is kept on; and the detection circuit of the power supply voltage detection circuit obtains a detection result according to the target voltage and a preset reference voltage.

[0020] After the detection is completed, the first switch is controlled to be turned off.

[0021] The embodiment of the present application provides a power voltage detection circuit, an electronic device and a detection method. The power voltage detection circuit comprises a first switch, a control circuit and a detection circuit. The control circuit can keep the first switch on during the detection process, so that the target voltage is input into the detection circuit, and the detection circuit detects the power voltage; after the detection is completed, the control circuit controls the first switch to be off, so that the generation of the target voltage is stopped, and the detection circuit is prevented from continuing to detect the power voltage when it is not needed, and the circuit loss is reduced. When the first switch is off, the branch in which the resistor is located is also disconnected, and no current passes through, so that the static power consumption of the circuit is reduced. BRIEF DESCRIPTION OF DRAWINGS

[0022] Figure 1 It is a structural schematic diagram of the power voltage detection circuit in one embodiment;

[0023] Figure 2 It is another structural schematic diagram of the power voltage detection circuit in one embodiment;

[0024] Figure 3 It is another structural schematic diagram of the power voltage detection circuit in one embodiment;

[0025] Figure 4 It is another structural schematic diagram of the power voltage detection circuit in one embodiment;

[0026] Figure 5 It is another structural schematic diagram of the power voltage detection circuit in one embodiment;

[0027] Figure 6 It is a signal schematic diagram of the power voltage detection circuit in one embodiment;

[0028] Figure 7 It is another structural schematic diagram of the power voltage detection circuit in one embodiment;

[0029] Figure 8 It is another structural schematic diagram of the power voltage detection circuit in one embodiment;

[0030] Figure 9 It is a flow schematic diagram of the detection method in one embodiment. DETAILED DESCRIPTION

[0031] In order to make the purpose, technical scheme and advantages of the present application clearer, the present application is further described in detail below with reference to the drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application, and are not used to limit the present application.

[0032] An electronic system is in an unstable state when powered on, and the power voltage often needs to be detected to ensure that the power voltage is in a proper voltage range, so that the electronic system can work normally.

[0033] At present, the analog voltage value is usually converted into a digital voltage value by a Flash ADC to realize detection of the power supply voltage.

[0034] However, the existing Flash ADC has the problem of large static power consumption, causing resource waste. Therefore, the present application provides a power supply voltage detection circuit, an electronic device and a detection method, which can reduce the static power consumption of the Flash ADC.

[0035] In one embodiment, as shown in Figure 1 A power supply voltage detection circuit is provided, which includes a first switch 10, a control circuit 20 and a detection circuit 30; one end of the first switch 10 is connected with a power supply end, and the other end of the first switch 10 is connected with the ground; the control circuit 20 is used for keeping the first switch 10 on during detection and controlling the detection circuit 30 to work, and controlling the first switch 10 to be off after detection is completed; the first switch 10 is used for making a target voltage input the detection circuit 30 when it is on, and stopping generation of the target voltage when it is off; the detection circuit 30 is used for obtaining a detection result according to the target voltage and a preset reference voltage; the target voltage is related to the power supply voltage.

[0036] The target voltage can be the power supply voltage or the voltage after the power supply voltage is divided by resistance. Figure 1 For example, as shown in

[0037] At this time, the target voltage input to the detection circuit 30 is the voltage after the power supply voltage is divided by the resistance 11. For example, if the resistance values of the three resistances are the same, the target voltage is VDD / 3.

[0038] The first switch 10 can be a P-type field effect transistor, an N-type field effect transistor or a transmission gate switch composed of a P-type field effect transistor and an N-type field effect transistor. Hereinafter, the P-type field effect transistor is taken as an example for description. The source of the first switch 10 is connected with the ground, the drain is connected with the power supply end, and the gate is connected with the control circuit 20.

[0039] In this embodiment, the control circuit 20 is connected to both the first switch 10 and the detection circuit 30. By keeping the first switch 10 on, the target voltage is input to the detection circuit 30, causing the detection circuit 30 to operate. For example, the control circuit 20 can control the on and off states of the first switch 10 using a square wave signal. When the first switch 10 is on, the target voltage is input to the detection circuit 30, which begins to detect the power supply voltage and outputs the detection result. After the detection is complete, the control circuit 20 controls the first switch 10 to turn off, and the target voltage generation stops. Simultaneously, the path between the power supply and ground is broken.

[0040] When the detection circuit 30 is working, it detects the target voltage according to the preset reference voltage. For example, it compares the target voltage with the preset reference voltage to obtain the comparison result of the target voltage and the preset reference voltage, that is, to obtain the range of the target voltage, thereby realizing the detection of the power supply voltage VDD.

[0041] After the detection circuit 30 obtains the detection result of the target voltage, it can determine the detection result of the power supply voltage based on the relationship between the target voltage and the power supply voltage.

[0042] The power supply voltage detection circuit provided in this embodiment includes a first switch, a control circuit, and a detection circuit. The control circuit can keep the first switch on during detection, allowing the target voltage to be input to the detection circuit, enabling the detection circuit to detect the power supply voltage. After detection is complete, the control circuit controls the first switch to turn off, stopping the generation of the target voltage and preventing the detection circuit from continuing to detect the power supply voltage when not needed, thus reducing circuit losses. When the first switch is off, the branch containing the resistor is also disconnected, and no current flows, reducing the circuit's static power consumption.

[0043] In one embodiment, such as Figure 2 As shown, the detection circuit 30 includes a decoding circuit 31 and at least three comparison branches 32; each comparison branch 32 is connected to the first switch 10, the control circuit 20, and the decoding circuit 31 respectively; the comparison branch 32 is used to compare the target voltage with the reference voltage under the control of the control circuit 20 to obtain the comparison result, and to latch the comparison result under the control of the control circuit 20; wherein, the reference voltage corresponding to each comparison branch 32 is different; the decoding circuit 31 is used to output the detection result based on the comparison results of the at least three comparison branches 32.

[0044] The reference voltages for different comparison branches are different. For example, the reference voltages for the three comparison branches can be Vref, 2Vref / 3, and Vref / 3, respectively.

[0045] In this embodiment, when the control circuit 20 controls the first switch 10 to turn on, each comparison branch 32 starts comparing the target voltage and the reference voltage and outputs the comparison result. The comparison result can be 0 or 1. 0 indicates that the target voltage is less than the reference voltage, and 1 indicates that the target voltage is greater than the reference voltage; this application does not impose any limitations on this.

[0046] After receiving the comparison results from the three comparison branches 32, the decoding circuit 31 outputs a detection result based on the three comparison results. The detection result can be a three-bit binary number; for example, a detection result of 001 indicates that the target voltage is between Vref / 3 and 2Vref / 3.

[0047] When the detection ends, the comparison branch 32 can latch the comparison result between the target voltage and the reference voltage to prevent the comparison result from failing to latch, which would cause the detection result output by the decoding circuit 31 to jump.

[0048] The circuit provided in this application embodiment includes at least three comparison branches and a decoding circuit. Each comparison branch has a different reference voltage to provide multiple voltage ranges, thereby determining the voltage range in which the target voltage is located and obtaining the detection result of the power supply voltage. In the circuit provided in this application embodiment, the comparison branches can also latch the comparison results when not performing voltage comparisons, avoiding jumps in the detection results and improving the stability and reliability of the circuit.

[0049] In one embodiment, such as Figure 3 As shown, the comparison branch 32 includes a second switch 321, a third switch 322, and a comparator 323; the first end of the second switch 321 is connected to the first switch 10, and the second end of the second switch 321 is connected to the first input terminal of the comparator 323; the first end of the third switch 322 is connected to the first input terminal of the comparator 323, and the second end of the third switch 322 is connected to the second input terminal of the comparator 323; the second input terminal of the comparator 323 is also connected to the reference voltage terminal, the output terminal of the comparator 323 is connected to the decoding circuit 31, and the enable terminal of the comparator 323 is connected to the control circuit 20.

[0050] The second and third switches can be P-type field-effect transistors (FETs), N-type field-effect transistors (FETs), or transmission gate switches composed of both P-type and N-type FETs. The following explanation uses an N-type FET as an example.

[0051] The gates of the second switch 321 and the third switch 322 are both connected to the control circuit 20; the drain of the second switch 321 is connected to the first switch 10, and the source is connected to the non-inverting input of the comparator 323; the source of the third switch 322 is connected to the non-inverting input of the comparator 323, and the drain is connected to the inverting input of the comparator 323; the inverting input of the comparator 323 is also connected to the reference voltage terminal, the output terminal is connected to the input terminal of the decoding circuit 31, and the enable terminal is connected to the control circuit 20.

[0052] In this embodiment of the application, during the detection process, the first switch 10 and the second switch 321 are turned on, the third switch 322 is turned off, the comparator 323 compares the target voltage and the reference voltage, and outputs the comparison result.

[0053] After the comparison is completed, control circuit 20 first controls the second switch 321 to turn off and controls the third switch 322 to turn on. At this time, both the non-inverting and inverting input terminals of comparator 323 are at the reference voltage, and the two input terminals are short-circuited. The comparator cannot output the comparison result, so the comparator latches the previous comparison result.

[0054] Then, the control circuit 20 controls the first switch 10 to turn off, thereby disconnecting the path between the power supply and the detection circuit 30 under the condition of latching the comparison result. This prevents the detection circuit from continuing to detect the power supply voltage when it is not needed, reducing circuit losses. At the same time, the branch containing the first switch is disconnected, and no current flows through the resistor, reducing the static power consumption of the circuit.

[0055] In the circuit provided in this application embodiment, two switches are connected before the comparator. When the comparator is not needed, the two switches work together to first latch the comparison result, and then disconnect the path between the power supply and the detection circuit. This prevents the detection circuit from continuing to detect the power supply voltage when it is not needed, thus reducing circuit losses. At the same time, the branch containing the first switch is disconnected, and no current flows through the resistor, reducing the static power consumption of the circuit.

[0056] In one embodiment, such as Figure 4 As shown, the control circuit 20 includes a first control sub-circuit 21, a second control sub-circuit 22, and a third control sub-circuit 23; the first control sub-circuit 21, the second control sub-circuit 22, and the third control sub-circuit 23 are connected in sequence; the output terminal of the first control sub-circuit 21 is also used to output a first control signal to the second switch 321 of each comparison branch 32; the output terminal of the second control sub-circuit 22 is also used to output a second control signal to the third switch 322 of each comparison branch 32; the output terminal of the third control sub-circuit 23 is used to output a third control signal to the first switch 10.

[0057] Let's take the example of using N-type field-effect transistors as the basis for further explanation.

[0058] The output terminal of the first control sub-circuit 21 is connected with the gate of the second switch 321 of each comparison branch 32; the output terminal of the second control sub-circuit 22 is connected with the gate of the third switch 322 of each comparison branch 32; the output terminal of the third control sub-circuit 23 is connected with the gate of the first switch 10.

[0059] During the detection process, the first control sub-circuit 21 controls the second switch 321 to be turned on, the second control sub-circuit 22 controls the third switch 322 to be turned off, the third control sub-circuit 23 controls the first switch 10 to be turned on, and the comparator 323 compares the target voltage with the reference voltage and outputs the comparison result.

[0060] After the comparison is completed, the first control sub-circuit 21 controls the second switch 321 to be turned off, and the second control sub-circuit 22 controls the third switch 322 to be turned on. At this time, the non-inverting input terminal and the inverting input terminal of the comparator 323 are both the reference voltage, the two input terminals are short-circuited, and the comparator cannot output the comparison result, so the comparator latches the previous comparison result.

[0061] Then, the third control sub-circuit 23 controls the first switch 10 to be turned off, so that the target voltage is stopped from being generated under the condition of latching the comparison result, thereby avoiding the detection circuit from continuing to detect the power supply voltage when it is not needed, and reducing the circuit loss. At the same time, the branch in which the first switch is located is disconnected, no current passes through the resistor, and the static power consumption of the circuit is reduced.

[0062] In the circuit provided by the embodiment of the present application, two switches are connected in front of the comparator, when the comparator does not need to work, three control sub-circuits control three switches respectively, the comparison result is latched first, and then the target voltage is stopped from being generated, thereby avoiding the detection circuit from continuing to detect the power supply voltage when it is not needed, and reducing the circuit loss. At the same time, the branch in which the first switch is located is disconnected, no current passes through the resistor, and the static power consumption of the circuit is reduced.

[0063] In one embodiment, as shown in FIG. 2, the first control sub-circuit 21 includes a buffer 211 and a first delay unit 212; the output terminal of the buffer 211 is connected with the input terminal of the first delay unit 212, and the output terminal of the first delay unit 212 is connected with the input terminal of the second control sub-circuit 22. Figure 5 The second control sub-circuit 22 includes a first inverter 221; the input terminal of the first inverter 221 is connected with the output terminal of the first control sub-circuit 21, and the output terminal of the first inverter 221 is connected with the input terminal of the third control sub-circuit 23.

[0064]

[0065] ​The third control sub-circuit 23 comprises a second inverter 231 and a second delay unit 232; an input end of the second inverter 231 is connected with the output end of the second control sub-circuit 22, an output end of the second inverter 231 is connected with an input end of the second delay unit 232, and an output end of the second delay unit 232 outputs the third control signal to the first switch 10.

[0066] In the embodiment of the present application, as shown in Figure 6 When the rising edge of the signal RESET comes (i.e. at t1), the comparator 323 starts to compare the target voltage with the reference voltage. At this time, the signal RESET_D1 inputted to the second switch 321 after being delayed by one unit by the first delay unit 212 is at low level, the second switch 321 is turned on; the signal RESET_D2 inputted to the third switch 322 after being inverted by the first inverter 221 is at high level, the third switch 322 is turned off; the signal RESET_D3 inputted to the first switch 10 after being inverted by the second inverter 231 and delayed by the second delay unit 232 is at low level, the first switch 10 is turned on. The comparator 323 compares the target voltage with the reference voltage and outputs the comparison result.

[0067] When the comparison ends (i.e. at t2), the signal RESET_D1 inputted to the second switch 321 after being delayed by one unit by the first delay unit 212 is at high level, the second switch 321 is turned off; the signal RESET_D2 inputted to the third switch 322 after being inverted by the first inverter 221 is at low level, the third switch 322 is turned on; the signal RESET_D3 inputted to the first switch 10 after being inverted by the second inverter 231 and delayed by the second delay unit 232 is at low level, the first switch 10 is turned on. At this time, the positive input end and the negative input end of the comparator 323 are both at the reference voltage, the voltage difference inputted by the two input ends is small, the comparator cannot identify the small difference and outputs the comparison result, thus the comparator latches the previous comparison result.

[0068] After the comparison result is latched (i.e. at t3), the signal RESET_D1 inputted to the second switch 321 after being delayed by one unit by the first delay unit 212 is at high level, the second switch 321 is turned off; the signal RESET_D2 inputted to the third switch 322 after being inverted by the first inverter 221 is at low level, the third switch 322 is turned on; the signal RESET_D3 inputted to the first switch 10 after being inverted by the second inverter 231 and delayed by the second delay unit 232 is at high level, the first switch 10 is turned off, and the target voltage stops being generated, avoiding the detection circuit from continuously detecting the power supply voltage when it is not needed, and reducing the circuit loss. At the same time, the branch where the first switch is located is disconnected, no current passes through the resistor, and the static power consumption of the circuit is reduced.

[0069] The buffer is used to improve the voltage transmission characteristic of the circuit.

[0070] In one embodiment, the signal RESET is also input to the enable end of the comparator 323, for indicating the comparator to start working.

[0071] The circuit provided by the embodiments of the present application realizes the conversion of the initial signal through the delay unit and the inverter, so that the control circuit can control the three switches based on different signals, first latches the comparison result, and then disconnects the path between the power supply end and the detection circuit, avoiding the detection circuit from continuously detecting the power supply voltage when it is not needed, and reducing the circuit loss. At the same time, the branch in which the first switch is located is disconnected, no current passes through the resistor, and the static power consumption of the circuit is reduced.

[0072] In one embodiment, the internal structure of the comparator 323 can be a differential structure as shown in Figure 7 , or a structure as shown in Figure 8 , as long as the comparison function can be realized, which is not limited in the present application.

[0073] In one embodiment, the power supply voltage detection circuit can further include more comparison branches 32, for example, 5 comparison branches, so as to provide more voltage intervals and improve the detection result accuracy.

[0074] In one embodiment, an electronic device is also provided, which includes the power supply voltage detection circuit as described in the above embodiments.

[0075] In one embodiment, a detection method is also provided, which is applied to the power supply voltage detection circuit as described in the above embodiments, as shown in Figure 9 , the detection method includes:

[0076] In step 101, in the detection process, the first switch of the power supply voltage detection circuit is kept on; and the detection circuit of the power supply voltage detection circuit obtains a detection result according to the target voltage and a preset reference voltage.

[0077] In the embodiments of the present application, in the process of detecting the power supply voltage, the first switch is kept on, the target voltage can be input to the detection circuit, the detection circuit can start to detect the power supply voltage, and outputs the detection result.

[0078] Then, the power supply voltage detection circuit detects the target voltage according to the preset reference voltage, for example, compares the target voltage with the preset reference voltage, obtains the comparison result of the target voltage and the preset reference voltage, that is, the range of the target voltage, and realizes the detection of the power supply voltage VDD.

[0079] The target voltage can be a power supply voltage or a voltage divided by the power supply voltage.

[0080] In step 102, after detection, the first switch is controlled to be off.

[0081] In the embodiment of the present application, after the detection of the power supply voltage, the power supply voltage detection circuit controls the first switch 10 to be off, and the target voltage stops being generated. Meanwhile, the path between the power supply end and the ground is disconnected.

[0082] The detection method provided by the embodiment of the present application can keep the first switch on during the detection process, so that the target voltage is input into the detection circuit, and the detection circuit detects the power supply voltage. After the detection is completed, the first switch is controlled to be off, and the target voltage stops being generated, which avoids the detection circuit from continuously detecting the power supply voltage when it is not needed, and reduces the circuit loss. When the first switch is off, the branch in which the resistor is located is also disconnected, and no current passes through, which reduces the static power consumption of the circuit.

[0083] Those skilled in the art can understand that all or part of the processes in the above-mentioned embodiment methods can be completed by instructing the relevant hardware through a computer program. The computer program can be stored in a non-volatile computer readable storage medium, and when the computer program is executed, the processes of the above-mentioned embodiments of the methods can be included. Any reference to memory, database or other medium used in the embodiments provided in the present application can include at least one of non-volatile and volatile memory. Non-volatile memory can include read-only memory (Read-Only Memory, ROM), magnetic tape, floppy disk, flash memory, optical storage, high-density embedded non-volatile memory, resistive memory (ReRAM), magnetoresistive random access memory (Magnetoresistive Random Access Memory, MRAM), ferroelectric memory (Ferroelectric Random Access Memory, FRAM), phase change memory (Phase Change Memory, PCM), graphene memory, etc. Volatile memory can include random access memory (Random Access Memory, RAM) or external cache memory, etc. As an illustration but not limitation, RAM can be in various forms, such as static random access memory (Static Random Access Memory, SRAM) or dynamic random access memory (Dynamic Random Access Memory, DRAM), etc. The database involved in the embodiments provided in the present application can include at least one of a relational database and a non-relational database. The non-relational database can include a distributed database based on a block chain, etc., without being limited thereto. The processor involved in the embodiments provided in the present application can be a general-purpose processor, a central processing unit, a graphics processing unit, a digital signal processor, a programmable logic device, a data processing logic device based on quantum computing, etc., without being limited thereto.

[0084] Any combination of the technical features of the above embodiments can be made. In order to make the description simple, all possible combinations of the technical features in the above embodiments are not described, however, as long as the combination of the technical features does not exist contradictory, it should be considered as the scope of the present application.

[0085] The above embodiments only express several implementation manners of the present application, and the description is more specific and detailed, but it should not be understood as a limitation on the scope of the patent of the present application. It should be pointed out that for ordinary skilled in the art, without departing from the concept of the present application, a number of modifications and improvements can be made, which are within the scope of protection of the present application. Therefore, the protection scope of the present application should be subject to the appended claims.

Claims

1. A power supply voltage detection circuit, characterized in that, The power supply voltage detection circuit includes a first switch (10), a control circuit (20), and a detection circuit (30); one end of the first switch (10) is connected to the power supply terminal, and the other end of the first switch (10) is connected to ground; The control circuit (20) is used to keep the first switch (10) on and control the detection circuit (30) to work during detection, and to control the first switch (10) to turn off after detection is completed. The first switch (10) is used to input the target voltage into the detection circuit (30) when it is turned on, and to stop the generation of the target voltage when it is turned off; The detection circuit (30) is used to obtain a detection result based on the target voltage and a preset reference voltage; the target voltage is related to the power supply voltage. The detection circuit includes a decoding circuit (31) and at least three comparison branches (32); each of the comparison branches (32) is connected to the first switch (10), the control circuit (20) and the decoding circuit (31), respectively. The comparison branch (32) is used to compare the target voltage with the reference voltage under the control of the control circuit (20) to obtain a comparison result, and to latch the comparison result under the control of the control circuit (20); wherein, the reference voltage corresponding to each comparison branch (32) is different; The decoding circuit (31) is used to output the detection result based on the comparison results of the at least three comparison branches (32); The comparison branch (32) includes a second switch (321), a third switch (322), and a comparator (323); The first end of the second switch (321) is connected to the first switch (10), and the second end of the second switch (321) is connected to the first input end of the comparator (323); The first end of the third switch (322) is connected to the first input end of the comparator (323) and the second end of the second switch (321), and the second end of the third switch (322) is connected to the second input end of the comparator (323); The second input terminal of the comparator (323) is also connected to the reference voltage terminal, the output terminal of the comparator (323) is connected to the decoding circuit (31), and the enable terminal of the comparator (323) is connected to the control circuit (20).

2. The power supply voltage detection circuit according to claim 1, characterized in that, The power supply voltage detection circuit also includes multiple resistors (11) connected in series; the first switch (10) is disposed on the branch where the multiple resistors (11) are located.

3. The power supply voltage detection circuit according to claim 1, characterized in that, The control circuit (20) includes a first control sub-circuit (21), a second control sub-circuit (22), and a third control sub-circuit (23); The first control sub-circuit (21), the second control sub-circuit (22), and the third control sub-circuit (23) are connected in sequence; The output terminal of the first control sub-circuit (21) is also used to output a first control signal to the second switch (321) of each of the comparison branches (32); The output of the second control sub-circuit (22) is also used to output a second control signal to the third switch (322) of each of the comparison branches (32); The output terminal of the third control sub-circuit (23) is used to output a third control signal to the first switch (10).

4. The power supply voltage detection circuit according to claim 3, characterized in that, The first control sub-circuit (21) includes a buffer (211) and a first delay unit (212). The output of the buffer (211) is connected to the input of the first delay unit (212), and the output of the first delay unit (212) is connected to the input of the second control sub-circuit (22).

5. The power supply voltage detection circuit according to claim 3, characterized in that, The second control sub-circuit (22) includes a first inverter (221); The input terminal of the first inverter (221) is connected to the output terminal of the first control sub-circuit (21), and the output terminal of the first inverter (221) is connected to the input terminal of the third control sub-circuit (23).

6. The power supply voltage detection circuit according to claim 3, characterized in that, The third control sub-circuit (23) includes a second inverter (231) and a second delay unit (232); The input terminal of the second inverter (231) is connected to the output terminal of the second control sub-circuit (22), the output terminal of the second inverter (231) is connected to the input terminal of the second delay unit (232), and the output terminal of the second delay unit (232) outputs the third control signal to the first switch (10).

7. An electronic device, characterized in that, The electronic device includes a power supply voltage detection circuit as described in any one of claims 1-6.

8. A detection method, characterized in that, The method, applied to the power supply voltage detection circuit as described in any one of claims 1-6, comprises: During the detection process, the first switch (10) of the power supply voltage detection circuit is kept on; the detection circuit (30) of the power supply voltage detection circuit is controlled to obtain the detection result based on the target voltage and the preset reference voltage; After the test is completed, the first switch (10) is turned off.

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