Operating system and control method

Abstract

The present application provides an operating system and a control method. The operating system includes a first storage circuit, a second storage circuit, a selection circuit, a core circuit and a trigger source management circuit. The first storage circuit stores a first control parameter. The second storage circuit stores a second control parameter. When a first trigger source enables a first trigger signal, the trigger source management circuit commands the selection circuit to output the first control parameter as an output parameter, so that the core circuit enters a first mode to perform a first operation. When a second trigger source enables a second trigger signal, the trigger source management circuit commands the selection circuit to output the second control parameter as an output parameter, so that the core circuit enters a second mode to perform a second operation.

Description

TECHNICAL FIELD

[0001] The present invention relates to an operating system, and in particular, to an operating system having multiple operating modes. BACKGROUND

[0002] With the advancement of technology, the types and functions of electronic devices are increasing. Most of the electronic devices have a central processing unit and a plurality of processing circuits inside. The central processing unit is used to control the operation of all processing circuits. However, the central processing unit can only communicate with a single processing circuit at the same time. Therefore, many processing circuits are idle. SUMMARY

[0003] An embodiment of the present invention provides an operating system, which includes a first storage circuit, a second storage circuit, a selection circuit, a core circuit, and a trigger source management circuit. The first storage circuit stores a first control parameter. The second storage circuit stores a second control parameter. The selection circuit is used to provide an output parameter. The core circuit receives the output parameter. The trigger source management circuit is used to control the selection circuit. When a first trigger source enables a first trigger signal, the trigger source management circuit instructs the selection circuit to take the first control parameter as the output parameter, so that the core circuit enters a first mode to perform a first operation. When a second trigger source enables a second trigger signal, the trigger source management circuit instructs the selection circuit to take the second control parameter as the output parameter, so that the core circuit enters a second mode to perform a second operation.

[0004] The present invention also provides a control method for controlling the operating mode of a core circuit. The control method of the present invention includes storing a first control parameter in a first storage circuit; storing a second control parameter in a second storage circuit; determining whether a first trigger source enables a first trigger signal; when the first trigger signal is enabled, providing the first control parameter to the core circuit, so that the core circuit enters a first mode to perform a first operation; determining whether a second trigger source enables a second trigger signal; and when the second trigger signal is enabled, providing the second control parameter to the core circuit, so that the core circuit enters a second mode to perform a second operation.

[0005] The control method of the present invention can be implemented through the operating system of the present invention, which is hardware or firmware that can perform specific functions, or can be included in a recording medium in the form of program code and implemented in combination with specific hardware. When the program code is loaded and executed by an electronic device, a processor, a computer, or a machine, the electronic device, the processor, the computer, or the machine becomes an operating system for implementing the present invention. BRIEF DESCRIPTION OF DRAWINGS

[0006] Figure 1 FIG. 1 is a schematic diagram of the operating system of the present invention.

[0007] Figure 2 A schematic diagram of the processing circuit of the present application.

[0008] Figure 3 A schematic diagram of the operation of the processing circuit of the present application.

[0009] Figure 4A A schematic diagram of a possible flow of the control method of the present application.

[0010] Figure 4B A schematic diagram of another possible flow of the control method of the present application.

[0011]

Symbol explanation

[0012] 100: Operating system

[0013] 102: Central processing unit

[0014] 104: Bus

[0015] 106, 200: Processing circuit

[0016] 108, 110, 112: Trigger source

[0017] STA1 ~ STAn: Trigger signal N , STB1 ~ STBn: Trigger signal M , STC1 ~ STCn: Trigger signal Q : Trigger signal

[0018] SOUT: Output signal

[0019] CLK1, CLK2: Clock signal

[0020] PA1 ~ PAk: Peripheral circuit N , PB1 ~ PBl: Peripheral circuit M , PC1 ~ PCm: Peripheral circuit Q : Peripheral circuit

[0021] RT1 ~ RT3: Storage circuit

[0022] 202: Selection circuit

[0023] 204: Core circuit

[0024] 206: Trigger source management circuit

[0025] P1 ~ P3: Control parameter

[0026] SEL: Selection signal

[0027] PO: Output parameter

[0028] ST: Trigger signal

[0029] Timeout, Overflow, Underflow: completion signals

[0030] 302, 304: time

[0031] S401-S407: steps DETAILED DESCRIPTION

[0032] In order to make the objects, features and advantages of the present application more clear, the following embodiments are specifically given, and the accompanying drawings are used for detailed description. The present application provides different embodiments to explain the technical features of different embodiments of the present application. The configuration of each element in the embodiments is for illustration, and is not intended to limit the present application. In addition, part of the repeated reference numerals in the embodiments is for simplifying the description, and is not intended to indicate the relevance between different embodiments.

[0033] Figure 1 Fig. 1 is a schematic diagram of an operating system of the present application. As shown in the figure, the operating system 100 includes a central processing unit (CPU) 102, a bus 104, a processing circuit 106, and trigger sources 108, 110 and 112. The central processing unit 102 communicates with the processing circuit 106 through the bus 104. In a possible embodiment, the central processing unit 102 writes data into a storage circuit (not shown) of the processing circuit 106. The present application does not limit the type of the bus 104. In a possible embodiment, the bus 104 transmits at least one of data, signals and power between the central processing unit 102 and the processing circuit 106 in a parallel manner or a serial manner.

[0034] The processing circuit 106 is coupled to the bus 104 to receive information (at least one of data, signals and power) from the central processing unit 102. The processing circuit 106 is also coupled to the trigger sources 108, 110 and 112 to receive trigger signals STA1-STA N , STB1-STB M and STC1-STC Q In the present embodiment, when one of the trigger signals STA1-STA N , STB1-STB M and STC1-STC Q is enabled, the processing circuit 106 enters a corresponding operation mode according to the source of the enabled trigger signal to perform a corresponding operation.

[0035] For example, when the trigger source 108 enables one of the trigger signals STA1-STA N , the processing circuit 106 enters a first mode. In the first mode, the processing circuit 106 performs a first operation. When the trigger source 110 enables one of the trigger signals STB1-STBM one of the trigger signals STC1~STC Q one of the trigger signals STC1~STC Q one of the trigger signals STC1~STC

[0036] In some embodiments, when the processing circuit 106 enters the first mode and performs the first operation, the processing circuit 106 ignores the trigger signals from the trigger sources 110 and 112. Therefore, in the first mode, even when the trigger source 110 enables the trigger signals STB1~STB M one of the trigger signals STC1~STC N one of the trigger signals STC1~STC

[0037] In a possible embodiment, the processing circuit 106 knows whether the trigger signals STA1~STA N , STB1~STB M and STC1~STC Q are enabled according to the levels of the trigger signals STA1~STA N , STB1~STB M and STC1~STC Q . Take the trigger signal STA1 as an example. When the trigger signal STA1 is at a first specific level, it indicates that the trigger source 108 enables the trigger signal STA1. Therefore, the processing circuit 106 enters the first mode. When the trigger signal STA1 is not at the specific level, it indicates that the trigger source 108 does not enable the trigger signal STA1. Therefore, the processing circuit 106 continues to detect the levels of the other trigger signals. The first specific level can be a high level or a low level.

[0038] The present application is not limited to the architecture of the processing circuit 106. In one possible embodiment, the processing circuit 106 is a timer / counter. In this case, when the processing circuit 106 enters the first mode, the processing circuit 106 performs a timing operation. At this time, the processing circuit 106 functions as a timer. When the processing circuit 106 enters the second mode, the processing circuit 106 performs a counting operation. At this time, the processing circuit 106 functions as a counter. In another possible embodiment, the processing circuit 106 is a series and parallel circuit. In this case, the processing circuit 106 can have a first interface and a second interface. The first interface is a serial interface, such as a Universal Asynchronous Receiver Transmitter (UART) interface, a Serial Peripheral Interface (SPI), or an Inter-Integrated Circuit (I2C) interface. The second interface is a parallel interface, such as a General-Purpose Interface Bus (GPIB). When the processing circuit 106 enters the first mode, the processing circuit 106 communicates with an external device (such as the central processing unit 102, at least one of the trigger sources 108 and 110) using the first interface. When the processing circuit 106 enters the second mode, the processing circuit 106 communicates with the external device using the second interface. In other embodiments, the processing circuit 106 has more operation modes for performing more operations.

[0039] In some embodiments, the processing circuit 106 can enable an output signal SOUT when the processing circuit 160 completes the corresponding operation. In one possible embodiment, the central processing unit 102 receives the output signal SOUT through the bus 104. In another embodiment, the central processing unit 102 can receive the output signal SOUT through another bus. In other embodiments, the central processing unit 102 can be directly coupled to the processing circuit 106 to receive the output signal SOUT. In some embodiments, the processing circuit 106 can provide the output signal SOUT to other external elements (such as at least one of the trigger sources 108, 110, and 112) through the bus 104, or directly provide the output signal SOUT to the other external elements.

[0040] In one embodiment, the central processing unit 102 determines whether the processing circuit 106 has completed the corresponding operation according to the output signal SOUT. For example, when the processing circuit 106 has completed the first operation or the second operation, the processing circuit 106 can set the output signal SOUT to a second specific level. Thus, the central processing unit 102 can know that the processing circuit 106 has completed the first operation or the second operation according to the output signal SOUT having the specific level. The second specific level can be a high level or a low level. In this embodiment, since the processing circuit 106 actively performs the corresponding operation according to the source of the enabled trigger signal without the central processing unit 102 monitoring the trigger sources 108, 110 and 112 whether to enable the trigger signal at all times, the power consumption of the central processing unit 102 can be saved.

[0041] In other embodiments, the processing circuit 106 also receives the clock signals CLK1 and CLK2. In this case, when the processing circuit 106 enters the first mode, the processing circuit 106 can perform the first operation according to the clock signal CLK1 or CLK2. Similarly, when the processing circuit 106 enters the second mode, the processing circuit 106 can perform the second operation according to the clock signal CLK1 or CLK2. In other embodiments, the processing circuit 106 can receive more or less clock signals.

[0042] The trigger source 108 includes the peripheral circuits PA1~PA N to provide the trigger signals STA1~STA N . The trigger source 110 includes the peripheral circuits PB1~PB M to provide the trigger signals STB1~STB M . The trigger source 112 includes the peripheral circuits PC1~PC Q to provide the trigger signals STC1~STC Q . In this embodiment, the peripheral circuits PA1~PA N are located in the same trigger source, so the peripheral circuits PA1~PA N may be called the first peripheral circuits. In this case, the peripheral circuits PB1~PB M are called the second peripheral circuits, and the peripheral circuits PC1~PC Q are called the third peripheral circuits.

[0043] The present application does not limit the types of the peripheral circuits PA1~PA N , PB1~PB M and PC1~PC Q . Any circuit can be used as the peripheral circuits PA1~PA N , PB1~PB M and PC1~PC Qone of the trigger sources 108, 110, and 112. Since the characteristics of the peripheral circuits PA1~PA N , PB1~PB M , and PC1~PC Q are similar, the peripheral circuit PA1 is taken as an example. In this example, when the peripheral circuit PA1 finishes its own operation, the peripheral circuit PA1 enables the trigger signal STA1. At this time, the trigger signal STA1 can be at a certain level. However, if the peripheral circuit PA1 has not finished its own operation, the peripheral circuit PA1 does not enable the trigger signal STA1. At this time, the trigger signal STA1 can not be at the certain level.

[0044] The trigger sources 108, 110, and 112 are independent of each other. In other words, the trigger sources 108, 110, and 112 do not share any peripheral circuit. In addition, the present application does not limit the number of peripheral circuits of the trigger sources 108, 110, and 112. In one possible embodiment, the number of peripheral circuits of one of the trigger sources 108, 110, and 112 can be the same as the number of peripheral circuits of another of the trigger sources 108, 110, and 112. In another possible embodiment, the number of peripheral circuits of one of the trigger sources 108, 110, and 112 can be different from the number of peripheral circuits of another of the trigger sources 108, 110, and 112.

[0045] Figure 2 Fig. 2 is a schematic diagram of a processing circuit according to the present application. As shown in the figure, the processing circuit 200 includes storage circuits RT1~RT3, a selection circuit 202, a core circuit 204, and a trigger source management circuit 206. The storage circuits RT1~RT3 are independent of each other. In one possible embodiment, the storage circuits RT1~RT3 are registers. The storage circuits RT1~RT3 store control parameters P1~P3, respectively. The control parameters P1~P3 are used to control the operation mode of the core circuit 204. In one possible embodiment, the control parameters P1~P3 are provided by an external device (such as the central processing unit 102 of Fig. 1) other than the processing circuit 200. In this example, the central processing unit 102 of Fig. 1 can write the control parameters P1~P3 into the storage circuits RT1~RT3, respectively, through the bus 104. The present application does not limit the number of storage circuits. In other embodiments, the processing circuit 200 can have more or fewer storage circuits. Figure 1 Figure 1

[0046] ​​The selection circuit 202 is coupled to the storage circuits RT1-RT3. In one embodiment, the selection circuit 202 selects one of the control parameters P1-P3 as an output parameter PO according to a selection signal SEL. For example, when the selection signal SEL has a first state (e.g., a first voltage), the selection circuit 202 selects the control parameter P1 as the output parameter PO. When the selection signal SEL has a second state (e.g., a second voltage), the selection circuit 202 selects the control parameter P2 as the output parameter PO. When the selection signal SEL has a third state (e.g., a third voltage), the selection circuit 202 selects the control parameter P3 as the output parameter PO. In other embodiments, the selection circuit 202 selects one of the control parameters P1-P3 as the output parameter PO according to a frequency of the selection signal SEL. In some embodiments, the selection circuit 202 selects one of the control parameters P1-P3 as the output parameter PO according to a plurality of selection signals. The present application does not limit the architecture of the selection circuit 202. In one embodiment, the selection circuit 202 is a multiplexer.

[0047] The core circuit 204 is coupled to the selection circuit 202 to receive the output parameter PO and enter a corresponding mode according to the output parameter PO. For example, when the selection circuit 202 selects the control parameter P1 as the output parameter PO, the core circuit 204 enters a first mode to perform a first operation. When the selection circuit 202 selects the control parameter P2 as the output parameter PO, the core circuit 204 enters a second mode to perform a second operation. When the selection circuit 202 selects the control parameter P3 as the output parameter PO, the core circuit 204 enters a third mode to perform a third operation. In other embodiments, when the selection circuit 202 selects the control parameter P3 as the output parameter PO, the core circuit 204 enters the first mode or the second mode.

[0048] The present application does not limit the architecture of the core circuit 204. In one embodiment, the core circuit 204 is a core circuit of a timer / counter. In this embodiment, the core circuit 204 has dual operation modes. When the selection circuit 202 selects the control parameter P1 as the output parameter PO, the core circuit 204 enters the first mode to perform a timing operation. When the selection circuit 202 selects the control parameter P2 as the output parameter PO, the core circuit 204 enters the second mode to perform a counting operation.

[0049] In one possible embodiment, when the selection circuit 202 outputs the control parameter P3 as the output parameter PO, the core circuit 204 enters a first mode to perform the timing operation. In this embodiment, when the selection circuit 202 outputs the control parameter PI as the output parameter PO, the core circuit 204 performs the timing operation for a first total execution time (e.g., 10 seconds). When the selection circuit 202 outputs the control parameter P3 as the output parameter PO, the core circuit 204 performs the timing operation for a second total execution time (e.g., 5 seconds). The first total execution time is different from the second total execution time.

[0050] In another possible embodiment, when the selection circuit 202 outputs the control parameter P3 as the output parameter PO, the core circuit 204 enters a second mode to perform the counting operation. In this embodiment, when the selection circuit 202 outputs the control parameter P2 as the output parameter PO, the core circuit 204 can set a first target value and reset a count value. The core circuit 204 can adjust the count value according to the number of pulses of the clock signal CLKl. When the count value reaches the first target value, the core circuit 204 stops performing the counting operation. When the selection circuit 202 outputs the control parameter P3 as the output parameter PO, the core circuit 204 sets a second target value and resets the count value. The core circuit 204 can adjust the count value according to the number of pulses of the clock signal CLKl. When the count value reaches the second target value, the core circuit 204 stops performing the counting operation. In this embodiment, the first target value is different from the second target value. The present application does not limit how the core circuit 204 adjusts the count value. The core circuit 204 can gradually decrease or gradually increase the count value.

[0051] In this embodiment, the core circuit 204 determines the total execution time of the timing operation, the clock source of the timing operation, the target value of the counting operation, the clock source of the counting operation, and the type of the counting operation (up counting or down counting) according to the output parameter PO. In other embodiments, the core circuit 204 counts the number of rising edges or falling edges of an external clock (e.g., CLKl or CLK2) according to the output parameter PO.

[0052] The trigger source management circuit 206 is coupled to the trigger sources 108, 110, and 112. The trigger source management circuit 206 determines whether the trigger sources 108, 110, and 112 output an enabled trigger signal. When the trigger source 108, 110, or 112 outputs an enabled trigger signal, the trigger source management circuit 206 commands the selection circuit 202 to output the corresponding control parameter as the output parameter PO through the selection signal SEL to control the operation mode of the core circuit 204.

[0053] For example, when the trigger source 108 outputs an enabled trigger signal (e.g., the trigger signal STA1), the trigger source management circuit 206 commands the selection circuit 202 to output the control parameter P3 as the output parameter PO through the selection signal SEL to control the core circuit 204 to enter the first mode to perform the timing operation. Figure 1 The trigger source management circuit 206 can output the trigger signals STA1 ~ STA3 of the trigger sources 108, 110, and 112 through the selection signal SEL to control the core circuit 204 to enter the first mode to perform the timing operation, the second mode to perform the counting operation, or the third mode to perform the counting operation. NWhen one of the following conditions is met, the trigger source management circuit 208 generates a selection signal SEL to command the selection circuit 202 to use the control parameter P1 as the output parameter PO. Therefore, the core circuit 204 enters a first mode to perform a first operation. In one possible embodiment, the core circuit 204 selects either clock signal CLK1 or CLK2 based on the output parameter PO (i.e., control parameter P1) and performs the first operation based on the selected clock signal. After completing the first operation, the core circuit 204 enables the output signal SOUT.

[0054] When trigger source 110 enables a trigger signal (such as...) Figure 1 Trigger signals STB1~STB M When one of the following conditions is met, the trigger source management circuit 206 commands the selection circuit 202 to use the control parameter P2 as the output parameter PO via the selection signal SEL. Therefore, the core circuit 204 enters the second mode to perform the second operation. In the second mode, the core circuit 204 may select either the clock signal CLK1 or CLK2 based on the output parameter PO (i.e., the control parameter P2), and perform the second operation based on the selected clock signal. After completing the second operation, the core circuit 204 enables the output signal SOUT.

[0055] When trigger source 112 enables a trigger signal (such as...) Figure 1 Trigger signals STC1~STC Q When one of the following conditions is met, the trigger source management circuit 208 may command the selection circuit 202 to use the control parameter P3 as the output parameter PO. At this time, the core circuit 204 may enter the first, second, or third mode. In this example, the core circuit 204 may select the clock signal CLK1 or CLK2 according to the output parameter PO (i.e., the control parameter P3).

[0056] In some embodiments, when the core circuit 204 enters a specific mode, even if the trigger source management circuit 206 detects other trigger source enable signals, the trigger source management circuit 206 ignores trigger signals from other trigger sources. For example, after the core circuit 204 enters the first mode, even if the trigger source 110 enables trigger signals STB1~STB... M When one of them is in operation, the core circuit 204 continues to perform the first operation.

[0057] Since the processing circuit 200 has a plurality of independent storage circuits, each of which stores a control parameter, the trigger source management circuit 206 can adjust the operation mode of the core circuit 204 by providing the corresponding control parameter to the core circuit 204 according to the source of the enabled trigger signal. Therefore, the mode switching of the core circuit 204 does not need the intervention of the central processing unit, so the power consumption of the central processing unit can be saved. Furthermore, when the core circuit 204 switches the mode, the central processing unit can perform other operations, so the performance of the central processing unit can be improved.

[0058] In some embodiments, the trigger source management circuit 206 also provides a trigger signal ST to the core circuit 204. The trigger signal ST is the trigger signal enabled by the trigger source 108, 110, and 112. For example, when the selection circuit 202 outputs the control parameter P1 as the output parameter PO, the trigger source management circuit 206 provides the trigger signal enabled by the trigger source 108 as the trigger signal ST. When the selection circuit 202 outputs the control parameter P2 as the output parameter PO, the trigger source management circuit 206 provides the trigger signal enabled by the trigger source 110 as the trigger signal ST. When the selection circuit 202 outputs the control parameter P3 as the output parameter PO, the trigger source management circuit 206 provides the trigger signal enabled by the trigger source 112 as the trigger signal ST.

[0059] Figure 3 The operation of the processing circuit of the present application is schematically shown. For convenience of explanation, it is assumed that the processing circuit is a timer / counter. In this example, when the trigger source 108 enables one of the trigger signals STA1~STA N , the trigger source management circuit 206 instructs the selection circuit 202 to output the control parameter P1 as the output parameter PO. Therefore, the core circuit 204 enters the first mode and is ready to perform a timing operation. At this time, the core circuit 204 can select the clock signal CLK1 according to the output parameter PO and is ready to perform a timing operation according to the pulses of the clock signal CLK1.

[0060] Then, the trigger source management circuit 206 provides the enabled trigger signal (e.g. STA1) as the trigger signal ST to the core circuit 204. The core circuit 204 starts to perform the timing operation according to the trigger signal ST (STA1). While the core circuit 204 performs the timing operation, if the trigger source 108 enables another trigger signal (e.g. STA N ), the trigger source management circuit 206 provides the enabled trigger signal (STA N ) as the trigger signal ST to the core circuit 204. At this time, the core circuit 204 can select the clock signal CLK2 according to the trigger signal ST (STA N) suspending the timing operation. When the trigger source 108 enables another trigger signal (e.g., STA2), the trigger source management circuit 206 provides the enabled trigger signal (STA2) as the trigger signal ST to the core circuit 204. At this time, the core circuit 204 can continue the timing operation according to the trigger signal ST (STA2). When the core circuit 204 completes the timing operation, the core circuit 204 enables a completion signal Timeout. In this example, the completion signal Timeout is provided as the output signal SOUT.

[0061] In another possible embodiment, when the trigger source 110 enables one of the trigger signals STB1 ~ STB M The trigger source management circuit 206 commands the selection circuit 202 to provide the control parameter P2 as the output parameter PO. Accordingly, the core circuit 204 enters the second mode to perform a counting operation. The core circuit 204 can select the clock signal CLK1 according to the output parameter PO and perform a counting operation according to the pulses of the clock signal CLK1. In another possible embodiment, the core circuit 204 can select the clock signal CLK2 according to the output parameter PO.

[0062] The trigger source management circuit 206 then provides the enabled trigger signal (e.g., STB M ) as the trigger signal ST to the core circuit 204. Accordingly, the core circuit 204 starts to perform a counting operation. In a possible embodiment, the core circuit 204 performs an up-counting operation or a down-counting operation according to the output parameter PO (i.e., the control parameter P2). When the trigger source 110 enables another trigger signal, the trigger source management circuit 206 provides the enabled trigger signal (e.g., STB2) as the trigger signal ST. At this time, the core circuit 204 can suspend the counting operation according to the trigger signal ST. When the trigger source 110 enables another trigger signal (e.g., STB1), the trigger source management circuit 206 provides the enabled trigger signal (STB1) as the trigger signal ST. At this time, the core circuit 204 can continue the counting operation according to the trigger signal ST (STB1). When the core circuit 204 completes the counting operation, the core circuit 204 enables a completion signal Overflow or Underflow. In a possible embodiment, when the core circuit 204 completes the up-counting operation, the core circuit 204 enables the completion signal Overflow. In this example, the completion signal Overflow is provided as the output signal SOUT. In another possible embodiment, when the core circuit 204 completes the down-counting operation, the core circuit 204 enables the completion signal Underflow. In this example, the completion signal Underflow is provided as the output signal SOUT.

[0063] In other embodiments, when the trigger source 112 enables one of the trigger signals STC1 ~ STCQ If the selected trigger source is one of the control parameters (e.g., STC1), the trigger source management circuit 206 instructs the selection circuit 202 to select the control parameter P3 as the output parameter PO. Thus, the core circuit 204 can enter the first mode again to perform a timing operation. In this example, the core circuit 204 selects one of the clock signals CLK1 and CLK2 (e.g., CLK2) according to the control parameter P3. The core circuit 204 performs a timing operation again according to the pulses of the clock signal CLK2.

[0064] Then, the trigger source management circuit 206 provides the enabled signal (e.g., STC1) as the trigger signal ST to the core circuit 204. Thus, the core circuit 204 starts to perform a timing operation. When the core circuit 204 finishes the timing operation, the core circuit 204 enables the finish signal Timeout. In a possible embodiment, when the selection circuit 202 selects the control parameter PI as the output parameter PO, the total execution time of the timing operation performed by the core circuit 204 is a time 302. When the selection circuit 202 selects the control parameter P3 as the output parameter PO, the total execution time of the timing operation performed by the core circuit 204 is a time 304. In this example, the time 302 is different from the time 304. In this embodiment, the length of the time 302 is related to the control parameter PI. Similarly, the length of the time 304 is related to the control parameter P3.

[0065] Figure 4A A possible flowchart of the control method of the present application is shown. The control method of the present application is used to control the operation mode of a core circuit. First, a plurality of control parameters are stored in a plurality of storage circuits (step S401). In a possible embodiment, the control parameters are written into the storage circuits by a central processing unit. In this example, each storage circuit stores a control parameter.

[0066] It is determined whether a first trigger source enables a first trigger signal (step S402). When the first trigger source enables the first trigger signal, the control parameter of a first storage circuit of the storage circuits is provided to the core circuit to instruct the core circuit to enter a first mode (step S403). In the first mode, the core circuit performs a first operation, such as a timing operation, according to the first trigger signal. In the first mode, if the first trigger source enables another trigger signal (or a fourth trigger signal), the core circuit can suspend the timing operation. When the first trigger source enables another trigger signal (or a fifth trigger signal), the core circuit continues the timing operation. In other embodiments, after the timing operation is finished, the step S402 is returned to determine whether the first trigger source enables the first trigger signal.

[0067] When the first trigger source does not enable the first trigger signal, it is determined whether a second trigger source enables a second trigger signal (step S404). When the second trigger source enables the second trigger signal, a control parameter of a second one of the storage circuits is provided to the core circuit to command the core circuit to enter a second mode (step S405). In the second mode, the core circuit performs a second operation, such as a counting operation, according to the second trigger signal. In this example, if the second trigger source enables another trigger signal (or a sixth trigger signal), the core circuit can suspend the counting operation. When the second trigger source enables another trigger signal (or a seventh trigger signal), the core circuit continues the counting operation. When the second trigger source does not enable the second trigger signal, the process returns to step S402. In some embodiments, after the core circuit finishes the counting operation, the process can return to step S402.

[0068] Figure 4B Another possible flowchart of the control method of the present application. Figure 4B Similarly Figure 4A except that Figure 4B Steps S406 and S407 are added. In step S406, it is determined whether a third trigger source enables a third trigger signal. When the third trigger source enables the third trigger signal, a control parameter of a third one of the storage circuits is provided to the core circuit to command the core circuit to enter the first or second mode (step S407). In one possible embodiment, when the core circuit receives the control parameter of the third storage circuit, the core circuit enters the first mode. In this example, the core circuit determines the total execution time of the timing operation according to different control parameters. For example, when the core circuit receives a first control parameter, the core circuit executes the timing operation for a first total execution time. When the core circuit receives a third control parameter, the core circuit executes the timing operation for a second total execution time. In this example, the first total execution time is different from the second total execution time.

[0069] In another possible embodiment, when the core circuit receives the control parameter of the third storage circuit, the core circuit enters the second mode. In this example, the core circuit determines the target value of the counting operation according to different control parameters. For example, the core circuit determines a first target value according to a second control parameter. The core circuit can adjust a count value according to the number of pulses of a first clock signal. When the count value reaches the first target value, the core circuit stops the counting operation. In this example, the core circuit determines a second target value according to a third control parameter. The core circuit can adjust the count value according to the number of pulses of a second clock signal (or the first clock). When the count value reaches the second target value, the core circuit stops the counting operation. The first target value is different from the second target value.

[0070] Since the core circuit receives different control parameters when the different trigger sources enable the trigger signals, and performs different operations according to the different control parameters, the central processing unit can perform other operations without continuously detecting whether the trigger sources send the enabled trigger signals, thereby improving the performance of the central processing unit.

[0071] The control method of the present application, or a specific form or part thereof, can exist in the form of program code. The program code can be stored in a physical medium, such as a floppy disk, an optical disk, a hard disk, or any other machine-readable (e.g., computer-readable) storage medium, or is not limited to an external form of a computer program product, wherein when the program code is loaded and executed by a machine, such as a computer, the machine becomes an operating system for participating in the operation of the present application. The program code can also be transmitted through some transmission medium, such as a wire or cable, an optical fiber, or any transmission form, wherein when the program code is received, loaded and executed by a machine, such as a computer, the machine becomes an operating system for participating in the operation of the present application. When actually operated in a general-purpose processing unit, the program code combines the processing unit to provide a unique device whose operation is similar to that of an application-specific logic circuit.

[0072] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. In addition, unless explicitly stated otherwise, the definitions of terms in common dictionaries should be interpreted consistent with their meanings in the articles of the relevant technical field, and should not be interpreted as ideal states or overly formal language. Although the terms "first", "second", etc. can be used to describe various signals, these signals should not be limited by these terms. These terms are only used to distinguish one signal from another.

[0073] Although the present application has been disclosed in the above-mentioned preferred embodiments, it is not intended to limit the present application, and anyone with ordinary knowledge in the art can make some changes and modifications without departing from the spirit and scope of the present application. For example, the system, device or method described in the embodiments of the present application can be implemented in a physical embodiment of hardware, software or a combination of hardware and software. Therefore, the scope of protection of the present application should be defined by the claims of the present application.

Claims

1. An operating system, characterized by The operation system comprises: a first storage circuit for storing a first control parameter; a second storage circuit for storing a second control parameter; a selection circuit for providing an output parameter; a core circuit for receiving the output parameter; and a trigger source management circuit for controlling the selection circuit; wherein: when a first trigger source enables a first trigger signal, the trigger source management circuit instructs the selection circuit to provide the first control parameter as the output parameter, so that the core circuit enters a first mode for performing a first operation; when a second trigger source enables a second trigger signal, the trigger source management circuit instructs the selection circuit to provide the second control parameter as the output parameter, so that the core circuit enters a second mode for performing a second operation, when the first trigger source enables the first trigger signal, the trigger source management circuit provides the first trigger signal to the core circuit, and the core circuit starts to perform the first operation according to the first trigger signal; while the core circuit is performing the first operation, when the first trigger source enables a fourth trigger signal, the trigger source management circuit provides the fourth trigger signal to the core circuit, and the core circuit suspends to perform the first operation according to the fourth trigger signal; after the trigger source management circuit provides the fourth trigger signal to the core circuit, when the first trigger source enables a fifth trigger signal, the trigger source management circuit provides the fifth trigger signal to the core circuit, and the core circuit continues to perform the first operation according to the fifth trigger signal.

2. The operating system of claim 1, wherein, The first operation is a timing operation, and the second operation is a counting operation.

3. The operating system of claim 2, wherein, When the selection circuit provides the second control parameter as the output parameter, the trigger source management circuit provides the second trigger signal to the core circuit.

4. The operating system of claim 3, wherein, The operation system further comprises: a third storage circuit for storing a third control parameter; wherein when a third trigger source enables a third trigger signal, the trigger source management circuit instructs the selection circuit to provide the third control parameter as the output parameter, and provides the third trigger signal to the core circuit.

5. The operation system of claim 4, wherein: when the selection circuit provides the third control parameter as the output parameter, the core circuit enters the first mode; when the selection circuit provides the first control parameter as the output parameter, the total execution time of the core circuit for performing the first operation is a first time, and when the selection circuit provides the third control parameter as the output parameter, the total execution time of the core circuit for performing the timing operation is a second time, the first time being different from the second time.

6. The operation system of claim 4, wherein: when the selection circuit provides the third control parameter as the output parameter, the core circuit enters the second mode; When the selection circuit selects the second control parameter as the output parameter, the core circuit performs a counting operation to adjust a count value, and stops the counting operation when the count value reaches a first target value. When the selection circuit selects the third control parameter as the output parameter, the core circuit performs the counting operation to adjust the count value, and stops the counting operation when the count value reaches a second target value. The first target value is different from the second target value.

7. The operating system of claim 1, wherein, The core circuit selects one of a plurality of clock signals according to the output parameter.

8. The operating system of claim 1, wherein, Further comprising: a central processing unit to provide the first control parameter and the second control parameter; and a bus to transmit the first control parameter to the first storage circuit and to transmit the second control parameter to the second storage circuit. A control method for controlling an operation mode of a core circuit, the control method comprising:

9. A control method characterized by, storing a first control parameter in a first storage circuit; storing a second control parameter in a second storage circuit; determining whether a first trigger source enables a first trigger signal; when the first trigger signal is enabled, providing the first control parameter to the core circuit so that the core circuit enters a first mode to perform a first operation; determining whether a second trigger source enables a second trigger signal; when the second trigger signal is enabled, providing the second control parameter to the core circuit so that the core circuit enters a second mode to perform a second operation; when the first trigger signal is enabled, providing the first trigger signal to the core circuit so that the core circuit starts to perform the first operation; while the core circuit performs the first operation, when the first trigger source enables a fourth trigger signal, providing the fourth trigger signal to the core circuit so that the core circuit suspends the first operation; and after providing the fourth trigger signal to the core circuit, when the first trigger source enables a fifth trigger signal, providing the fifth trigger signal to the core circuit so that the core circuit continues to perform the first operation. The first operation is a timing operation, and the second operation is a counting operation.

10. The control method according to claim 9, characterized by, ​

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