Memory system for determining a read voltage

Abstract

A system, method, and apparatus having a computer-readable medium for determining a read voltage for a memory system is provided. In one aspect, the memory system includes a memory storing data and a memory controller coupled to the memory. The memory controller is configured to obtain a first read output of target memory data of the memory using a first read voltage and provide the first read voltage to the memory in response to determining that the first read output fails an error-correcting code (ECC) check. The memory is configured to determine a second read voltage based on the first read voltage and generate a second read output of the target memory data using the second read voltage.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to memory systems, and particularly to memory systems for determining read voltages. BACKGROUND

[0002] Once a memory cell in a data storage device (e.g., a memory system) is programmed, a cell threshold voltage can be compared to one or more read voltages to sense a programmed state of the respective memory cell to read data from the memory cell. However, the cell threshold voltage can change (e.g., read disturb or data retention) due to one or more factors, which can cause the sensed programmed state to differ from the written programmed state and result in failed bits of the data read output. SUMMARY

[0003] The present disclosure describes systems and techniques for determining read voltages for a memory system (e.g., a non-volatile memory (NVM) system).

[0004] One aspect of the present disclosure provides a memory system including a memory and a memory controller coupled to the memory. The memory controller is to obtain a first read output of target memory data stored in the memory using a first read voltage, and in response to determining that the first read output fails a first error-correcting code (ECC) check, provide the first read voltage to the memory. The memory is to determine a second read voltage from the first read voltage, and generate a second read output related to the target memory data using the second read voltage.

[0005] In some embodiments, the memory is to provide the second read output to the memory controller, and the memory controller is to determine whether the second read output passes a second error-correcting code check. In some embodiments, the memory includes an error-correcting code circuit to determine whether the second read output passes the second error-correcting code check.

[0006] In some embodiments, the memory controller is to determine that the second read output passes the second error-correcting code check, and output the second read output as a target read output of the target memory data.

[0007] In some embodiments, the first read voltage is determined based on stored read voltage data with respect to a first set of parameters associated with the target memory data. A second read voltage can be determined in dependence on a second set of parameters associated with the first set of parameters. The second set of parameters can include the first read voltage and an associated valley-tracking range. The stored read voltage data and the first set of parameters can be stored in a lookup table.

[0008] In some embodiments, the memory controller is configured to: determine that the second read output fails the second error correction code check; determine a third read voltage in dependence on the second set of parameters, the second set of parameters including at least one of a result of the second error correction code check and the first set of parameters; obtain a third read output with respect to the target memory data from the memory using the third read voltage; and determine whether the third read output passes a third error correction code check.

[0009] In some embodiments, the memory controller is configured to: in response to determining that the third read output fails the third error correction code check, determine whether a predetermined read threshold has been reached; in response to determining that the predetermined read threshold has been reached, determine that the target memory data read from the memory has failed; and in response to determining that the predetermined read threshold has not been reached, determine a new read voltage in dependence on a result of the third error correction code check.

[0010] In some embodiments, the memory controller is configured to: in response to determining that the third read output passes the third error correction code check, output the third read output as the target read output of the target memory data. In some embodiments, the memory controller is configured to determine the first read voltage using stored read voltage data based on the first set of parameters, and the memory controller is configured to: in response to determining that the third read output passes the third error correction code check, update the stored read voltage data using the third read voltage and at least one of the second set of parameters.

[0011] In some embodiments, the memory controller is configured to determine the third read voltage using at least one machine learning (ML) algorithm based on the second set of parameters. The at least one machine learning algorithm can include at least one of a linear regression, a support vector regression, and a deep learning algorithm including a convolutional neural network (CNN) algorithm or a recurrent neural network (RNN) algorithm.

[0012] In some embodiments, the memory controller is to decode the first read output using a hard decision decoding scheme, and decode the third read output using at least one of the hard decision decoding scheme and a soft decision decoding scheme. The memory controller can be to decode the second read output using the hard decision decoding scheme. In some embodiments, the memory controller is to decode any one of the first read output, the second read output, and the third read output using the hard decision decoding scheme first, and decode any one of the first read output, the second read output, and the third read output using the soft decision decoding scheme if the hard decision decoding scheme fails.

[0013] In some embodiments, the first set of parameters includes at least one of address information, program / erase (P / E) cycle count, read temperature, read disturbance level, and retention time. In some embodiments, the second set of parameters includes at least one of error bit count of the second read output, number of "1" values obtained at respective read voltages, change in number of "1" values between a previous read voltage and a current read voltage, read time, syndrome of a low-density parity-check code (LDPC code), and number of iterations of the LDPC code.

[0014] In some embodiments, the stored read voltage data is generated based on supervised machine learning training using a plurality of inputs related to the memory and respective plurality of optimal read voltages, under each input of the plurality of inputs, each optimal read voltage corresponding to a minimum error bit count of a read output of a respective page of the memory, each input including respective values of a plurality of parameters, the plurality of parameters including the first set of parameters.

[0015] In some embodiments, the stored read voltage data includes a transfer function representing a relationship between inputs of the plurality of parameters and the optimal read voltages, the transfer function being generated based on the supervised machine learning training.

[0016] In some embodiments, the memory controller is to determine a valley tracking range from the first read voltage and the respective plurality of optimal read voltages of the plurality of inputs, and the memory is to determine the second read voltage using a valley tracking read scheme based on the valley tracking range and the first read voltage. In some embodiments, the valley tracking range is not greater than a predetermined upper threshold and not less than a predetermined lower threshold.

[0017] In some embodiments, the memory is to obtain a series of values associated with a target memory data read output using a range of sequence read voltages defined with the first read voltage and a valley tracking range; and determine a read voltage corresponding to a minimum series value as the second read voltage.

[0018] In some embodiments, the series of values includes at least one of a series of cell counts corresponding to the target memory data, a series of accumulated voltages or currents corresponding to read-out bits of the target memory data, and a series of differential voltages or currents of the accumulated voltages or currents.

[0019] In some embodiments, the memory controller is to update the stored read voltage data with the second read voltage in response to determining that the second read output passes the second error correction code check.

[0020] In some embodiments, the memory controller is to determine that the first read output fails the first error correction code check by determining that at least a portion of the first read output fails the first error correction code check, the at least a portion of the first read output corresponding to at least an erroneous portion of the target memory data, and the memory is to read the at least an erroneous portion of the target memory data using the second read voltage to generate a second read output.

[0021] In some embodiments, the memory controller is to provide information of the at least an erroneous portion of the target memory data to the memory.

[0022] In some embodiments, the memory controller is to determine that a remainder of the first read output passes the first error correction code check, wherein the remainder of the first read output corresponds to a remainder of the target memory data, and the remainder of the first read output passes the first error correction code check; and determine that the remainder of the first read output is a target read output of the remainder of the target memory data, wherein the memory does not use the second read voltage to read the remainder of the target memory data.

[0023] In some embodiments, the target memory data includes a page having a plurality of chunks, and the memory controller is to determine that a corresponding first read-out of at least a chunk of the page fails the first error correction code check using the first read voltage, and wherein the memory is to read the at least a chunk using the second read voltage.

[0024] In some embodiments, the memory controller is configured to: obtain, using a first particular read voltage, a first particular read output of particular memory data to be read from the memory, the first particular read voltage determined in accordance with a first particular set of parameters associated with the particular memory data; determine that the first particular read output fails a corresponding error correction code check; in response to determining that the memory is busy, determine a second particular read voltage in accordance with a second particular set of parameters, the second particular set of parameters including at least one of a result of the corresponding error correction code check of the first particular read output and the first particular set of parameters; read the particular memory data using the second particular read voltage to obtain a second particular read output; determine whether the second particular read output passes the corresponding error correction code check; and in response to determining that the second particular read output passes the corresponding error correction code check, output the second particular read output as a target read output of the particular memory data of the memory.

[0025] Another aspect of the present disclosure provides a memory system including a memory and a memory controller, the controller including a memory-side read circuit, the memory controller including a controller-side read circuit. The memory controller is configured to: determine, by the controller-side read circuit, a first read voltage using stored read voltage data based on a first set of parameters associated with target memory data to be read from the memory; obtain, using the first read voltage, a first read output of the target memory data; and in response to determining that at least a portion of the first read output fails a first error correction code check, provide the first read voltage and information corresponding to at least an erroneous portion of the target memory data to the at least the portion of the first read output to the memory. The memory is configured to: determine, by the memory-side read circuit, a second read voltage in accordance with the first read voltage; and generate, using the second read voltage, a second read output of the at least the erroneous portion of the target memory data.

[0026] In some embodiments, the memory controller is to: determine that the second read output fails the second error correction code check; determine, by the control-side read circuit, a third read voltage in accordance with a second set of parameters, the second set of parameters comprising at least one of a result of the second error correction code check and the first set of parameters; obtain, using the third read voltage, a third read output of at least an erroneous portion of the target memory data; determine whether the third read output passes a third error correction code check; in response to determining that the third read output passes the third error correction code check, output the third read output and a remaining portion of the first read output as a target read output of the target memory data, wherein the remaining portion of the first read output passes the first error correction code check; and update the stored read voltage data using at least one of the third read voltage and the second set of parameters.

[0027] In some embodiments, the storage-side read circuit is to determine the second read voltage using a valley tracking read architecture based on a valley tracking range determined by the memory controller, and the control-side read circuit is to determine the third read voltage using at least one machine learning algorithm based on the second set of parameters.

[0028] In some embodiments, the control-side read circuit is to determine the first read voltage using at least one machine learning algorithm based on the first set of parameters. In some embodiments, the memory controller is to determine the first read voltage using a lookup table.

[0029] Another aspect of the disclosure provides a memory system comprising a memory and a memory controller, the memory to store data, the memory controller coupled to the memory. The memory is to: determine a first read voltage based on a first set of parameters related to a memory data using a valley tracking read architecture; and generate a first read output of the memory data using the first read voltage. The memory controller is to: in response to determining that the first read output fails a first error correction code check, determine a second read voltage in accordance with a second set of parameters, the second set of parameters comprising at least one of a result of the first error correction code check and the first set of parameters; obtain a second read output of the memory data of the memory using the second read voltage; determine whether the second read output passes a second error correction code check; and in response to determining that the second read output passes the second error correction code check, output the second read output as a target read output of the memory data.

[0030] Another aspect of the disclosure provides a method comprising: obtaining, by a memory controller, a first read output of target memory data stored in a memory using a first read voltage; in response to determining that the first read output fails an error correction code check, providing, by the memory controller, the first read voltage to the memory; determining, by the memory, a second read voltage in accordance with the first read voltage; and generating, by the memory, a second read output related to the target memory data using the second read voltage.

[0031] Implementations of the techniques described above include methods, systems, circuits, computer programming products, and computer-readable media. In one example, a memory system having a memory and a memory controller coupled to the memory can perform a method that can include the above-described actions, such as actions for determining a read voltage for the memory system, performed by the memory controller and the memory. In another example, a computer programming product embodying such techniques suitably embodies a non-transitory machine-readable medium that can store instructions for execution by one or more processors. The instructions are to cause the one or more processors to perform the above-described actions. A computer-readable medium stores instructions that, when executed by one or more processors, cause the one or more processors to perform the above-described actions.

[0032] One or more disclosed implementations of the present disclosure are described in detail below with reference to the attached drawing figures and following description. Other features, aspects, and advantages of the present disclosure will become apparent from the description, the drawings, and the claims.

[0033] So that the manner in which the above recited aspects and advantages of the present disclosure are attained and utilized can be understood in detail, a brief description of the embodiments is summarized below. BRIEF DESCRIPTION OF DRAWINGS

[0034] Figure 1A An example of a system in accordance with one or more implementations of the present disclosure is illustrated.

[0035] Figure 1B A schematic diagram of an example block of two-dimensional (2D) memory in accordance with one or more implementations of the present disclosure is illustrated.

[0036] Figure 1C A schematic diagram of an example block of three-dimensional (3D) memory in accordance with one or more implementations of the present disclosure is illustrated.

[0037] Figure 2A An example graph of threshold voltage distributions of multi-level cell (MLC) memory cells in different states in accordance with one or more implementations of the present disclosure is illustrated.

[0038] Figure 2B An example graph of read voltage variations of triple-level cell (TLC) memory cells in different states in accordance with one or more implementations of the present disclosure is illustrated.

[0039] Figure 3An example graph illustrating a relationship between a number of memory cells and a read voltage for a read output having different numbers of program / erase (P / E) cycles in accordance with one or more embodiments of the present disclosure is depicted.

[0040] Figure 4 An example graph of a memory system determining a plurality of stages of read voltages in accordance with one or more embodiments of the present disclosure is depicted.

[0041] Figure 5A An example graph of a valley tracking range of a three-level storage cell memory cell not considering a determination of a previous read voltage by a memory controller in accordance with one or more embodiments of the present disclosure is depicted.

[0042] Figure 5B An example graph of a valley tracking range of a three-level storage cell memory cell considering a determination of a previous read voltage by a memory controller in accordance with one or more embodiments of the present disclosure is depicted.

[0043] Figure 6 An example flow graph of determining a read voltage of a memory system in accordance with one or more embodiments of the present disclosure is depicted.

[0044] BRIEF DESCRIPTION OF DRAWINGS

[0045] 100: system

[0046] 110: device

[0047] 112: device controller

[0048] 113: processor

[0049] 114: internal memory

[0050] 116, 420: memory

[0051] 120, 410: host

[0052] 140: block

[0053] 141, 157: memory cell

[0054] 142, 152: cell page

[0055] 143: string select transistor

[0056] 144, 154: cell string

[0057] 145, GST: ground select transistor

[0058] 146, 156, SSL: string select line

[0059] 148, 158, GSL: ground select line

[0060] 149, 159, CSL: common source line

[0061] 150: 3D memory block

[0062] 200, 250: example diagram

[0063] 202, 204, 206, 208, 502, 512, 522, PE0, PE3k, PE5k, PE10k, PE15k, PE20k: curve

[0064] 203: point curve

[0065] 252, 254: chart

[0066] 300: graph

[0067] 400: memory system

[0068] 422: phase II

[0069] 430: memory controller

[0070] 431: host interface

[0071] 432: phase I

[0072] 433: memory interface

[0073] 434: error correction code decoding

[0074] 436: phase III

[0075] 600: flow

[0076] 602, 604, 606, 608, 610, 612, 614, 616, 618, 620, 622, 624, 626, 628: step

[0077] BL0 ~ BL n : row bit line

[0078] WL0 ~ WL n : column word line

[0079] WL: word line

[0080] BL <n>< / n> , BL ＜n+1> : bit line

[0081] MSB: most significant bit

[0082] LSB: least significant bit

[0083] ER: erase state

[0084] A, B, C: programmed state

[0085] V10, V11, V12, V13: lower limit voltage

[0086] Vh0, Vh0', Vh1, Vh2, Vh3: upper limit voltage

[0087] V Disturb , V Rd1 , V Rd2 , V Rd3 , V1, V2, V3, RD[0]~RD[6], RD[0']~RD[6'],

[0088] RD[0:6]: read voltage

[0089] V Rdpass : pass voltage

[0090] V3': optimal read voltage DETAILED DESCRIPTION

[0091] Due to frequent read operations, data stored in a memory can suffer from read disturb, in which the state of memory cells of the memory (e.g., an erased state and one or more programmed states) can have rising threshold voltages. Read disturb can cause erroneous bits (or error bits) in data readouts. Depending on the error correction capability of an Error-Correcting Code (ECC) architecture, an ECC decoder can be used to decode data read from the memory to detect and correct any bit errors that can exist in the data.

[0092] The state of each memory cell can be sensed by comparing the cell threshold voltage to a read voltage (or reference read voltage) to read data from the memory cell. The read voltage can be optimized to an optimal read voltage (or optimized read voltage) such that the error bit count (or number of error bits) of the data read output is minimized (or minimum). The optimal read voltage can depend on a number of parameters, such as the number of program / erase (P / E) cycles, word line (WL) address or page address, temperature, retention time, layer by layer variation, block by block variation, and / or chip by chip variation. Determining the optimal read voltage can be both time consuming and tedious, and the computation time and power consumption can increase with the number of input parameters considered by the decision process. Therefore, it is desirable to develop a technique that can perform accurate read under limited read latency of a time-variant channel, and can reduce the error correction code decoding overhead by the optimal read voltage.

[0093] In some cases, the same verify read voltage is used to read data from the memory regardless of the changes in the input parameters. However, the verified read voltage can deviate from the optimal read voltage, resulting in additional overhead of error correction code decoding.

[0094] In some cases, a lookup table (LUT) storing a plurality of verify read voltages is utilized. The verified read voltages are in a static order according to a corresponding priority level regardless of the input parameters. The data is first read with a first priority verify voltage; if the data read output fails the error correction code check, a second priority verify voltage is used. The read process is repeated until the read output passes the error correction code check.

[0095] In some cases, data is first read using a read voltage determined based on input parameters. If the read output fails an error correction code check, a repeated read process is performed using a lookup table that stores a static sequence of read voltages that is independent of the input parameters. However, the lookup table architecture can take a significant amount of engineering resources and development time. Engineers can have to fine-tune the optimal read voltage on a case by case basis depending on the input parameters. As different process technologies and different operating conditions, the lookup table size can become increasingly large. This can cause unacceptable read latency for three-dimensional (3D) memory devices such as triple-level cell (TLC) / quad-level cell (QLC) NAND flash memory devices.

[0096] In some cases, machine learning (ML) techniques can be used to determine the optimal read voltage. In some cases, offline inference of machine learning can determine a relationship between the input parameters and the optimal read voltage, which can be recorded in a lookup table or connected by a transfer function. However, offline inference can result in a large memory burden to achieve high accuracy. In some cases, online inference by machine learning can calculate the optimal read voltage as long as there is a read request. Online inference can require additional computation and time burden to reduce read latency. Furthermore, implementing machine learning in a memory controller can result in additional computation and hardware cost of the memory controller. In addition, machine learning read cannot address inter-die or intra-die variations and retention issues, and can still require repeated reads to improve read reliability.

[0097] In some cases, a valley-tracking (or valley-searching) architecture can be used to determine the optimal read voltage. In a valley-tracking architecture, bits stored in a memory are read out and counted at successive distinct voltages, and a curve showing the change in the number of bits resulting from each change in read voltage is observed. The voltage with the smallest change in the number of bits can correspond to the valley of the curve and provide the optimal read voltage. The valley-tracking architecture can handle retention issues and inter-die and / or intra-die variations. However, the accuracy of determining the read voltage using the valley-tracking technique is worse than machine learning read or other on-chip optimized read techniques (e.g., when the distribution is significantly shifted, like under high temperature and severe retention). Thus, repeated reads can still be needed to further improve read reliability.

[0098] Embodiments of the present disclosure provide systems, methods, and techniques for determining a read voltage (e.g., an optimal read voltage) for a memory system (e.g., a non-volatile memory (NVM) system) with multi-stage read combination. This technique can optimize the read voltage by combining an initial offline read voltage determination (Stage I), an on-chip valley-tracking read voltage determination (Stage II), and / or an online read voltage determination (Stage III). In particular, the results from the initial offline read voltage determination can be used to determine the valley-tracking read voltage of Stage II, which can narrow down the search range (or valley-tracking range) of the optimal read voltage and can improve the read accuracy, reliability, and speed of the determination process.

[0099] In some embodiments, a memory controller (e.g., software or hardware) can perform the initial offline read voltage determination (Stage I). In some cases, a lookup table (e.g., dynamically updated), a function, a hash, or an exhaustive search can determine the initial offline read voltage. In some cases, a machine learning circuit utilizing at least one machine learning algorithm (e.g., supervised machine learning training utilizing offline inference machine learning read algorithm) can infer the initial offline read voltage.

[0100] While offline optimized read can achieve good accuracy under heavy memory load, the disclosed techniques can provide a reasonable initial read with some parameters that are less memory load intensive than a default read. To compensate for the reliability loss due to the spatial limitation of the offline initial read determination, on-chip valley-tracking read can be implemented on the memory chip and can be triggered when the offline initial read fails. The valley-tracking read can count the number of cells (e.g., by the number itself, voltage, or current) based on the information from Stage I and can be used to find the distribution trend due to the retention or die-to-die variation. The results from Stage I can be used to determine (or optimize) the valley-tracking range (or search range) and parameters of Stage II, so that the memory controller-assisted valley-tracking read can not only achieve lower latency, but also better read accuracy compared to the conventional valley-tracking read without the initial read voltage determination input.

[0101] To further improve read accuracy (e.g., reduce error bits before error correction code decoding), an online read voltage determination (Phase III) can be triggered if the on-chip valley tracking read fails. The online read voltage determination can be implemented by a microcontroller unit (MCU) or hardware design of a memory controller. The online read voltage determination can be performed using at least one machine learning algorithm based on results of the error correction code check in Phase II and a set of parameters with parameters of Phase I and / or Phase II. The machine learning algorithm can include linear regression, support vector regression, convolutional neural network (CNN), recurrent neural network (RNN), or other suitable algorithms. The online read voltage determination can not be limited to any machine learning algorithm or operation.

[0102] The initial offline read voltage determination can be updated based on results of Phase II and / or Phase III. For example, the lookup table or stored read voltage data for Phase I can be updated with the optimal read voltage determined in Phase II and / or Phase III and one or more parameters used in Phase II and / or Phase III. That is, the three phases can be triggered and dynamically updated in sequence.

[0103] For most read requests, the read voltage determined in Phase I can successfully achieve the read output. Phase II is not triggered for each read request, but only when Phase I fails. Moreover, if only a portion of the memory data (e.g., one or more blocks of a page to be read) fails the error correction code check, Phase II (and Phase III) can be triggered to perform read only for the error portion (e.g., one or more blocks) instead of the entire memory data (e.g., the entire page).

[0104] This technique can reduce error correction code decoding burden, average online inference time of machine learning algorithms, computation and extra memory burden, read latency and development cost, and improve read accuracy and reliability of memory systems. This technique can be applied to various types of volatile memory devices or non-volatile memory devices, such as NAND flash memory, NOR flash memory, resistive random-access memory (RRAM), phase-change memory (PCM) such as phase-change random-access memory (PCRAM), spin-transfer torque magnetoresistive random-access memory (STT-MRAM), and the like. This technique can also be applied to charge-trapping memory devices, such as silicon-oxide-nitride-oxide-silicon (SONOS) memory devices and floating-gate memory devices. This technique can be applied to two-dimensional (2D) memory devices or three-dimensional (3D) memory devices. This technique can be applied to various memory types, such as single-level cell (SLC) devices, multi-level cell (MLC) devices such as 2-level cell devices, triple-level cell (TLC) devices, quad-level cell (QLC) devices, or penta-level cell (PLC) devices. Additionally or alternatively, this technique can be applied to various types of devices and systems, such as secure digital (SD) cards, embedded multimedia cards (eMMC) or solid-state drives (SSD), embedded systems, and the like.

[0105] Figure 1A An example of a system 100 having a device 110 and a host 120 is illustrated. The device 110 includes a device controller 112 and a memory 116. The device controller 112 includes a processor 113 and an internal memory 114.

[0106] In some implementations, the device 110 is a storage device. For example, the device 110 can be an embedded multimedia card, a secure digital card, a solid state disk, or some other suitable memory. In some implementations, the device 110 is a smart watch, a digital camera, or a media player. In some implementations, the device 110 is a client device coupled to the host 120. For example, the device 110 is a secure digital card that is a digital camera or a media player of the host 120.

[0107] The device controller 112 is a general-purpose microprocessor or an application-specific microcontroller. In some implementations, the device controller 112 is a memory controller of the device 110. The following sections describe various techniques in accordance with implementations in which the device controller 112 is a memory controller. However, the techniques described in the following sections also apply to implementations in which the device controller 112 is another type of controller that is distinct from a memory controller.

[0108] The processor 113 is to execute instructions and process data. The instructions include firmware instructions and / or other programming instructions that are stored as firmware code and / or other programming code in a secondary memory, respectively. Among other suitable data, the data includes programming data that corresponds to firmware and / or other programming that the processor 113 executes. In some implementations, the processor 113 is a general-purpose microprocessor or an application-specific microcontroller. The processor 113 is also referred to as a central processing unit (CPU).

[0109] The processor 113 accesses instructions and data from the internal memory 114. In some implementations, the internal memory 114 is static random access memory (SRAM) or dynamic random access memory (DRAM). For example, in some implementations, when the device 110 is an embedded multimedia card, a secure digital card, or a smart watch, the internal memory 114 is static random access memory. In some implementations, when the device 110 is a digital camera or a media player, the internal memory 114 is dynamic random access memory.

[0110] In some implementations, asFigure 1A As shown, internal memory 114 is a cache memory included in device controller 112. Internal memory 114 stores instruction code corresponding to instructions executed by processor 113 and / or data requested by processor 113 during execution.

[0111] Device controller 112 transfers instruction code and / or data from memory 116 to internal memory 114. In some embodiments, memory 116 is a storage device or a non-volatile memory (e.g., a NAND flash memory device or some other suitable non-volatile memory device) for long-term storage of instructions and / or data. In embodiments where memory 116 is a NAND flash memory, device 110 is a flash memory device (e.g., a flash memory card) and device controller 112 is a NAND flash controller. For example, in some embodiments, when device 110 is an embedded multimedia card or a secure digital card, memory 116 is a NAND flash memory; in some embodiments, when device 110 is a digital camera, memory 116 is a secure digital card; and in some embodiments, when device 110 is a media player, memory 116 is a hard disk.

[0112] In some embodiments, device controller 112 is to receive data and instructions from host 120 and to send data to host 120. Device controller 112 is also to send data and commands to memory 116 and to receive data from memory 116. For example, device controller 112 is to send data and a write command to instruct memory 116 to store data to a specified address. As another example, device controller 112 is to receive a read request (or a read command) from host 120 and to send a corresponding read command to memory 116 to read data from a specified address of memory 116.

[0113] In some embodiments, as Figure 1AAs shown, the device controller 112 includes an error correction code circuit 160. The error correction code circuit 160 can include an error correction code encoder 162 and an error correction code decoder 164. The error correction code encoder 162 can be used to receive data to be stored in the memory 116 and can be used to generate codewords (e.g., encode the data using an error correction code encoding scheme). The error correction code encoder 162 can include a Reed Solomon encoder, a Bose-Chaudhuri-Hocquenghem (BCH) encoder, a Low Density Parity Check (LDPC) encoder, or any combination thereof. Depending on the error correction capability of the error correction code, the error correction code decoder 164 can be used to decode data read from the memory 116 to detect and correct any bit errors that can exist in the data.

[0114] In some embodiments, the error correction code circuit 160 is implemented in the memory 116. In some embodiments, the memory 116 includes a memory-side error correction code circuit that is similar to the error correction code circuit 160 of the device controller 112. By integrating the memory-side error correction code circuit into the memory 116, the amount of data transfer through the electrical interconnect board can be significantly reduced, which can reduce the power consumption of the device 110. In some cases, moving at least part of the error correction code encoding / decoding capability from the device controller 112 to the memory 116 can spread out (or separate) the heat source (or power source) of the overall device 110 and can increase the heat dissipation of the device controller 112.

[0115] As further detailed below, the device controller 112 can be used to determine a read voltage (e.g., an optimal read voltage) for reading data from the memory 116 (e.g., in response to a read request from the host 120). In some embodiments, the device controller 112 stores a lookup table, a function, or a hash that associates the optimal read voltage with a first set of parameters (e.g., address information, number of program / erase cycles, read temperature, degree of read disturbance, or retention time). A software component, such as a program instruction, can implement the lookup table, the function, or the hash.

[0116] In some embodiments, the device controller 112 includes a hardware component (e.g., offline read circuit 170) to determine an initial read voltage by offline read voltage determination (e.g., during phase I). The offline read circuit 170 can be a machine learning circuit. For example, supervised machine learning offline training and inference can be preformed on the memory 116 (e.g., during manufacturing of the device 110) to determine a relationship between input parameters and optimal read voltages for the memory 116. The result of the supervised machine learning offline training and inference (e.g., a transfer function) can be stored as machine learning data, which can be stored in the device controller 112 (e.g., internal memory 114). In some implementations, the machine learning data can also be stored in the memory 116.

[0117] In some embodiments, the device controller 112 includes a hardware component (e.g., online read circuit 180) to determine an optimized read voltage by online read voltage determination (e.g., during phase III) based on a second set of parameters and one or more results of previous read outputs. The second set of parameters of the online read voltage determination can include the first set of parameters of the offline read voltage determination. The online read circuit 180 can be a machine learning circuit to utilize one or more machine learning algorithms to determine a read voltage based on the second set of input parameters. The machine learning algorithms can include linear regression, support vector regression, convolutional neural network, recurrent neural network, or other suitable algorithms. If the memory data read output utilizing the determined read voltage fails the error correction code check, the online read circuit 180 can adjust the second set of input parameters (e.g., by adding or updating one or more parameters) and generate a new read voltage. If the memory data read output utilizing the new read voltage passes the error correction code check, the new read output is outputted as the target read output for the memory data. The result of the online read voltage determination (e.g., the read voltage and related information such as the second set of parameters) can be used to calibrate or update the read voltage data (or lookup table) stored by the offline read circuit 170. That is, the content of the stored read voltage data can be dynamically updated. In some implementations, a single circuit such as the machine learning circuit implements the offline read circuit 170 and the online read circuit 180.

[0118] As further detailed below, the memory 116 includes an on-chip valley tracking circuit 190 to determine a read voltage using a valley tracking architecture based on information from the off-line read circuit 170. For example, the off-line read circuit 170 can provide an initial read voltage and a valley tracking voltage range to the on-chip valley tracking circuit 190. The on-chip valley tracking circuit 190 can be triggered upon a failure of an off-line initial read using the off-line read circuit 170. In the valley tracking architecture, bits stored in the memory are read out and counted at successive distinct voltages, and a curve showing the change in the number of bits resulting from each change in the read voltage is observed. The voltage with the smallest change in the number of bits can correspond to the valley of the curve and can provide the best read voltage. Valley tracking reads can count the number of cells by voltage or current and can be used to find the trend of the distribution due to retention or die-to-die variation.

[0119] In some embodiments, the on-chip valley tracking circuit 190 includes an analog-to-digital converter (ADC) circuit. The ADC circuit can include an accumulating circuit to accumulate the current (or voltage) from a plurality of bits to obtain a sum of the current (or voltage) during a read operation. The accumulating circuit can include an ADC to convert the analog signal of the sum of the current (or voltage) to a digital value. The ADC circuit can enable a faster counting time, for example, to determine a calibrated read voltage (or a best read voltage) during a valley search. For example, starting from a predetermined read voltage (e.g., from the off-line read circuit 170), successive different read voltages of a valley tracking range (e.g., determined by the off-line read circuit 170) can be tested as part of the valley search. For each tested voltage, the ADC circuit can accumulate the current from a plurality of memory cells on a page corresponding to a word line and can obtain a sum of the current and can convert the sum to a digital value. The on-chip valley tracking circuit 190 can compare the digital values from the successive different read voltages and determine a calibrated read voltage from the plurality of digital values and the different read voltages. In some cases, the read voltage with the smallest change in the number of bits can correspond to the valley and can provide the best or calibrated read voltage. To improve accuracy, the on-chip valley tracking circuit 190 can also compare a first difference between the digital values of adjacent read voltages or even a second difference between adjacent first differences to determine the valley.

[0120] If the memory data read output with the on-chip valley tracking circuit 190 is passed by the error correction code check, the memory data read output can be output as a target read output of the memory data. If the memory data read output is not passed by the error correction code check, the on-line read circuit 180 can be triggered (e.g., by the device controller 112) to determine a new read voltage in accordance with the error correction code check result and the second set of parameters.

[0121] The memory 116 includes a plurality of blocks. The memory 116 can be a two-dimensional (2D) memory having 2D memory blocks. The memory 116 can also be a three-dimensional (3D) memory having 3D memory blocks. Each block can include the same number of pages. In a block, each page has a unique page number. Data is stored in the pages of a block in order of the unique page numbers of the pages of the block. Each page can be read or written individually, and the pages in a block can be erased collectively.

[0122] In some implementations, a block can be divided into a plurality of sub-blocks. Each sub-block can include one or more pages. Each page in a sub-block can be read or written individually. One or more pages of each sub-block can be erased collectively. In some implementations, the memory 116 includes one or more dies. Each die can be a memory die and include a plurality of memory arrays and peripheral circuitry. The memory arrays can include a plurality of planes, and each plane includes a plurality of physical blocks of memory cells. Each physical block can include a plurality of pages of memory cells that can store a plurality of sectors of data. For example, a memory controller, such as the device controller 112, can designate a super block to combine at least one physical block from different planes. Each physical block of the super block is from a different plane, i.e., no plane provides more than one block to the super block. The super block includes a plurality of super pages, each super page combining a plurality of pages from a respective plurality of physical blocks of the super block. Each page of a super page can have the same page number in its respective physical block. The super page and all pages in the super page can be programmed simultaneously. Figure 1A

[0123] Figure 1B An example configuration of a 2D memory block 140 of the memory 116 as a 2D memory is illustrated. The block 140 includes memory cells 141 coupled in series to row bit lines BL0, BL1, BL2, BL3, and BL4, and column bit lines BL0, BL1, BL2, BL3, and BL4. The block 140 includes a plurality of pages P0, P1, P2, P3, and P4. Each page includes a plurality of memory cells 141. Each page can be read or written individually, and the pages in the block 140 can be erased collectively. n-1 and BL​n to form a plurality of cell strings 144, and the memory cells 141 are coupled in series to row word lines WL0, WL1, …, WL n-1 and WL n to form a plurality of cell pages 142.

[0124] Each memory cell of a block includes a transistor structure having a gate, a drain, a source, and a channel defined between the drain and the source. Each memory cell is located at an intersection between a word line and a bit line, where the gate is connected to the word line, the drain is connected to the bit line, the source is connected to a source line, and the source line is connected in series to a common ground. In some examples, the gate of a flash memory cell has a dual-gate structure including a control gate and a floating gate, where the floating gate is suspended between two oxide layers to trap electrons for programming the cell.

[0125] A cell string 144 can include a plurality of memory cells 141, a string select transistor (SST) 143, and a ground select transistor (GST) 145, all connected in series. The gate of the string select transistor 143 is connected to a string select line (SSL) 146. The gates of the string select transistors 143 of different strings are also connected to the same string select line 146. The gates of the memory cells 141 are connected to word lines WL0, WL1, …, WL n-1 , WL n , respectively. The cell string 144 or the memory cells 141 are connected to a common source line (CSL) 149 through the ground select transistor 145. The common source line 149 can be coupled to a ground. The gate of the ground select transistor 145 is connected to a ground select line (GSL) 148. The gates of the ground select transistors 145 of different cell strings 144 are also connected to the same ground select line 148.

[0126] A cell page 142 can include a plurality of memory cells 141. The gates of the memory cells 141 of a cell page 142 are coupled in series to a respective word line (WL). When a voltage is applied to a word line, the voltage is also applied to the gates of the memory cells 141 of the cell page 142. To read a particular cell page 142 of a block 140 in a read operation, a lower voltage is applied to the word line corresponding to the particular cell page 142. Meanwhile, a higher voltage is applied to the other cell pages of the block 140.

[0127] Figure 1C An example of a 3D memory block 150 is shown when the memory 116 Figure 1A is a 3D memory. The 3D memory block 150 can be a stack of 2D memory blocks (e.g., block 140) of the 3D memory. Figure 1B The memory cells 157 are arranged in three dimensions (e.g., in an XYZ coordinate system) and are coupled to a plurality of word lines to form a plurality of cell pages (conductive layers or word line layers) 152, and the memory cells 157 are coupled to a plurality of bit lines (e.g., bit lines BL <n>< / n> , BL ＜n+1> ) to form a plurality of cell strings 154. A cell page 152 can be a layer (e.g., in an XY plane), and the memory cells 157 of the same layer can be coupled to a word line and have the same voltage. Each cell page 152 can be connected to a respective contact pad of a driving circuit (e.g., an X decoder or scan driver).

[0128] A cell string 154 includes a plurality of memory cells 157 connected in series vertically along the Z direction, where the memory cells can function as string selection transistors coupled to a string selection line 156, and the memory cells can function as ground selection transistors coupled to a ground selection line 158. The cell string 154 is connected to one or more drivers, such as a data driver. The cell string 154 of memory cells 157 is connected to a common source line 159 through the ground selection transistors. The string selection line 156 can be a conductive line or layer formed on top of the cell page (or word line layer) 152. The 3D memory block 150 can include a plurality of string selection lines 156 on top of the cell pages 152. The common source line 159 can be a conductive layer (or a plurality of conductive lines) formed on a substrate of the 3D memory. The common source line 159 can be coupled to a ground terminal.

[0129] A memory cell can represent a variety of states, including an erased state and one or more programmed states. For example, in some cases, a memory cell is a single-level memory cell (SLC) that can store 1 bit and can represent 2 states, including an erased state ER and a programmed state A. Memory cells of a word line can form a page. In some cases, a memory cell is a multi-level memory cell (e.g., a 2-level memory cell) that can store 2 bits and can represent 4 states, including an erased state ER and three programmed states A, B, and C. Memory cells of a word line can form two pages. In some cases, a memory cell is a 3-level memory cell that can store 3 bits and can represent 8 states, including an erased state ER and seven programmed states A, B, C, D, E, F, and G. Memory cells of a word line can form three pages. The states can have progressively higher voltage ranges, and the erased state can use the lowest voltage range.

[0130] Figure 2A An example graph 200 of threshold voltage distributions of different states of a memory cell of a memory and read voltages in accordance with one or more implementations is illustrated. The memory cell can be a memory cell 141 of the memory 116 of FIG. 1 or a memory cell 157 of the memory 150 of FIG. 1. The memory can be the memory 116 (e.g., a NAND flash memory) of FIG. 1. For illustrative purposes only, the memory cell is a multi-level memory cell that can store two bits of data. Figure 1B Figure 1C Figure 1A

[0131] The memory cell can be programmed or erased to have any one of four states (i.e., an erased state ER and programmed states A, B, C). In some examples, ER is an erased state (1, 1) and A, B, C are programmed states (0, 1), (0, 0), and (1, 0). The erased state ER and the programmed states A, B, C have progressively higher read voltages. A NAND flash memory of a multi-level memory cell can divide the two bits of each memory cell of a word line into two pages, which are units of data programming. The least significant bits (LSBs) of all memory cells of a word line form a least significant bit page of the word line, and the most significant bits (MSBs) of these memory cells on the word line form a most significant bit page of the word line.

[0132] ​​​Once programmed or erased, a memory cell has a corresponding threshold voltage. The threshold voltage is a characteristic of the memory cell. The memory cell can be a floating gate transistor. When a read voltage higher than or equal to the threshold voltage is applied to the gate of the memory cell, the memory cell can be turned on. When a read voltage lower than the threshold voltage is applied to the gate of the memory cell, the memory cell can be turned off. A read operation is not a program or erase operation and is not intended to change the state of the memory cell.

[0133] Various states correspond to threshold voltage distributions within a range between a lower limit voltage and a higher limit voltage. A memory cell with a threshold voltage within the range is considered to be in the corresponding state. In other words, a memory cell in a state has a threshold voltage within the range. For example, if a memory cell has a threshold voltage between a lower limit voltage V10 and a higher limit voltage VhO, the memory cell is in an erase state ER; if a memory cell has a threshold voltage between a lower limit voltage V11 and a higher limit voltage Vhl, the memory cell is in a program state A; if a memory cell has a threshold voltage between a lower limit voltage V12 and a higher limit voltage Vh2, the memory cell is in a program state B; and if a memory cell has a threshold voltage between a lower limit voltage V13 and a higher limit voltage Vh3, the memory cell is in a program state C. Curves 202, 204, 206, 208 show the threshold voltage distributions of the corresponding states (i.e., the erase state ER and the program states A, B, C) of the memory cell, respectively.

[0134] During a read operation, a read voltage can be applied to a word line coupled to the gate of a selected memory cell to determine whether the selected memory cell is in an on state or an off state. When a read voltage V Rd1 greater than the threshold voltage of the erase state ER and less than the threshold voltage of the program state A is applied, the memory cell has the erase state ER when on and the program states A, B, or C when off; when a read voltage V Rd2 greater than the threshold voltage of the program state A and less than the threshold voltage of the program state B is applied, the memory cell has the erase state ER or the program state A when on and the program states B or C when off; when a read voltage V Rd3 greater than the threshold voltage of the program state B and less than the threshold voltage of the program state C is applied, the memory cell has the erase state ER, the program states A or B when on and the program state C when off. When a pass voltage V Rdpass greater than the threshold voltages of all states (i.e., the erase state ER and the program states A, B, C) is applied, the memory cell is on regardless of the state of the memory cell.

[0135] During the read operation, through voltage V Rdpass An application is made to other memory cells (located on the same bit line as the selected memory cell), and these other memory cells are turned on. Therefore, if the selected memory cell is turned on at the read voltage VRd, a conductive path is formed in the memory cells of the corresponding bit line, and there will be a current or voltage change, which can be detected by a current or voltage sensor coupled to the bit line. If the selected memory cell is turned off at the read voltage, no conductive path is formed in the memory cells of the corresponding bit line, and there will be no current or voltage change, which can be detected by a current or voltage sensor coupled to the bit line.

[0136] Repeated read operations can cause read interference. In read interference, the threshold voltage of a memory cell rises abnormally. For example... Figure 2A As shown, in some cases, curve 202 of the erase state ER distribution includes a dotted curve 203, which includes a higher threshold voltage. For example, the new upper limit voltage Vh0' is greater than the upper limit voltage Vh0. When the new upper limit voltage Vh0' falls within the threshold voltage range of programming state A (i.e., the range between the lower limit voltage Vl1 and the upper limit voltage Vh1), the erase state ER overlaps with programming state A. That is, the memory cells have overlapping states. When a read voltage V is applied... Disturb When a memory cell with a threshold voltage of the erase state ER is turned off instead of turned on, it is considered to be in a closed state. Therefore, under specific read conditions, by detecting whether a memory cell is turned on or off, it can be determined whether the memory cell has been subjected to read interference. In some cases, memory cells with lower threshold voltage states (e.g., erase state ER and programming state A) are more susceptible to read interference than memory cells with higher threshold voltage states (e.g., programming state B and programming state C).

[0137] Figure 2B Example Figure 250 illustrates the read voltage variation of a third-order memory cell in different states according to one or more embodiments of this disclosure. The memory cell may be... Figure 1B memory cell 141 or Figure 1CThe memory cell 157. As described above, the three-level memory cell can store three bits of metadata. The memory cell can be programmed or erased to have any of eight states (i.e., erase state ER and seven programming states A, B, C, D, E, F, and G). In some examples, ER is the erase state (1, 1, 1), while A, B, C, D, E, F, and G are the programming states (1, 1, 0), (1, 0, 0), (0, 0, 0), (0, 1, 0), (0, 1, 1), (0, 0, 1), and (1, 0, 1). These eight states have progressively increasing read voltages. The three-level memory cell NAND flash memory can divide the three bits of each memory cell of a word line into three pages, which are units of data programming at one time. Each page may include multiple blocks, such as four blocks. Each page can be read at once. In some cases, partial pages (e.g., one or more blocks) can also be read individually.

[0138] like Figure 2B As shown in Figure 252, the third-order memory cell can be correctly read using seven default read voltages RD[0], RD[1], RD[2], RD[3], RD[4], RD[5], and RD[6]. There is no overlap between adjacent states, and each read voltage lies between the threshold voltage distributions of adjacent states. Due to repeated read operations, the third-order memory cell may experience read interference, and the threshold voltage of the third-order memory cell may rise abnormally (e.g., Figure 2B (As shown in Figure 254). If the seven default read voltages RD[0], RD[1], RD[2], RD[3], RD[4], RD[5], and RD[6] are still used to read the tertiary memory cells, the bits stored in the tertiary memory cells may be read incorrectly. Therefore, the default read voltages can be adjusted or updated to new read voltages (or optimal read voltages) RD[0]′, RD[1]′, RD[2]′, RD[3]′, RD[4]′, RD[5]′, and RD[6]′, which can be used to correctly read the bits stored in the tertiary memory cells.

[0139] The optimal read voltage can be related to several parameters, including address information, number of programming / erase cycles, read temperature, read interference level, or retention time.

[0140] Figure 3A profile 300 is shown that illustrates the relationship between the number of cells of a multi-level memory cell and the read voltage, e.g., profiles PE0, PE3k, PE5k, PE10k, PE15k, PE20k, for different program / erase cycles (0, 3000 (or 3k), 5000 (or 5k), 10000 (or 10k), 15000 (or 15k), 20,000 (or 20k)) on the memory. Figure 3 The threshold voltage distribution of the memory cells is shown so that the optimal read voltage can vary depending on one or more input parameters (e.g., program / erase cycles) of the memory cells. When there are no program / erase cycles, the profile PE0 can correspond to Figure 2A the threshold voltage distribution profile. The read voltage V1 corresponds to Figure 2A the read voltage V Rd1 , and the read voltage V1 can be the optimal read voltage to read the erase state ER(1, 1) of the memory cell. The read voltage V2 corresponds to Figure 2A the read voltage V Rd2 , and the read voltage V2 can be the optimal read voltage to read the erase state ER(1, 1) and the program state A(0, 1) of the memory cell. The read voltage V3 corresponds to Figure 2A the read voltage V Rd3 , and the read voltage V3 can be the optimal read voltage to read the erase state ER(1, 1), the program state A(0, 1), and the program state B(0, 0) of the memory cell, and can determine that the remaining memory cell has the program state C(1, 0). As the number of program / erase cycles on the memory increases, the optimal read voltage increases, and the profile becomes shallower.

[0141] As an example, in a valley tracking read architecture, if the read voltage V3 is used as the initial read voltage to read the multi-level memory cell with 10k program / erase cycles, the threshold voltage distribution profile changes significantly and the optimal read voltage shifts to V3', causing the valley tracking range can be too large, and the read can be time consuming. In contrast, offline read voltage determination (e.g., trained with supervised machine learning) can result in a large memory burden for high accuracy.

[0142] As further detailed below, embodiments of the present disclosure provide a controller-assisted valley tracking read architecture that utilizes offline read voltage determination results that can narrow the search range of the optimal read voltage, and can improve the read accuracy, reliability, and speed of the determination process. In addition, online optimized read (e.g., with at least one machine learning algorithm) can further improve the read accuracy.

[0143] Figure 4 An example of a memory system 400 having multiple stages of read voltage is illustrated according to one or more embodiments of this disclosure. The memory system 400 may be... Figure 1A The device 110. The memory system 400 can be connected to the host 410 (e.g., Figure 1A The host 120 communicates with the host computer.

[0144] Memory system 400 includes memory 420 (e.g., Figure 1A The memory 116) and the memory controller 430 (e.g., Figure 1A The device controller 430 may include a memory interface 433 for communicating with the memory 420. The memory interface 433 may be an Open NAND Flash Memory Interface (ONFI) or a toggle interface. The memory controller 430 may also include a host interface 431 for communicating with the host 410.

[0145] In some implementations, the memory controller 430 includes an error correction code decoder, for example... Figure 1A Error correction code decoder 164. Depending on the error correction capability of the error correction code architecture, the error correction code decoder can be used to perform error correction code decoding 434 (e.g., via BCH decoding or low-density parity check code decoding) to decode memory data read from memory 420, thereby detecting and correcting any bit errors that may exist in the data. Memory controller 430 can be used to respond to a received read request (e.g., receiving a read request from host 410 via host interface 431) to determine the read voltage (e.g., optimal read voltage) for reading memory data from memory 420. The read request may include relevant information about the memory data to be read from memory 420, such as block address, word line address, and / or page address.

[0146] In some implementations, in response to a read request from the host 410, the memory controller 430 can determine a first read voltage VI using an initial offline read voltage determination (Phase I 432). In Phase I, the memory controller can determine the first read voltage using stored read voltage data based on a first set of input parameters related to the memory data. The first set of input parameters can include a block address, a word line address, a page address, a number of program / erase cycles, a read temperature, a retention time, a read disturbance level, and / or any other appropriate parameter. The read temperature represents a temperature of the memory when the memory data is read. The retention time can represent a period of time in which the memory cells storing the memory data are not distorted. The read disturbance level represents a level of read disturbance of the memory data.

[0147] In some cases, a lookup table, function, or hash can determine the first read voltage and can be implemented by a software component with programmed instructions. In some cases, the memory controller 310 includes an engine, module, or circuit (e.g., offline read circuit 170) of the memory controller 310 that performs Phase I 432. The first read voltage can be determined by inference using a machine learning circuit with at least one machine learning algorithm (e.g., an offline inference machine learning read algorithm with supervised machine learning training). For example, a transfer function can be created by supervised machine learning offline training and inference. The transfer function can include a lookup table with a size smaller than a normal lookup table (e.g., based on group offline training). The transfer function can also include a hash function, k-means, or any other appropriate form. To reduce memory burden, in Phase I 432, the memory controller can utilize some parameters to provide a reasonable initial read over a default read. Figure 1A

[0148] The memory controller 430 can read the memory data from the memory 420 using the first read voltage determined in Phase I 432 to obtain a first read output, and then an error correction code decoder can decode 434 the first read output (e.g., by hard low density parity check code decoding) to detect error bits present in the memory data. The memory controller 430 can determine whether the first read output passes the error correction code check by determining whether the error bits are corrected by the error correction code decoder in a check step. If the error bits are correctable, the memory controller 430 determines that the first read output of the memory data passes the error correction code check, and the first read output of the memory data can be used as a target read output of the memory data to output to, e.g., the host 410.

[0149] ​If the erroneous bits cannot be corrected, the memory controller 430 may determine that the first read output failed the error correction code check. In some cases, the memory controller 430 may determine that at least a portion of the first read output failed the error correction code check and the remaining (or the remaining portion) of the first read output passed the error correction code check. For example, the memory data includes pages having four blocks. The read outputs of the first and second blocks failed the error correction code check, while the read outputs of the third and fourth blocks passed the error correction code check. The memory controller 430 may record the information of the first and second blocks and provide this information to the memory 420 for further reading in stage II 422, while the reading of the third and fourth blocks can be considered as the target read output without further reading of the third and fourth blocks.

[0150] Phase II 422 employs an on-chip valley tracking read architecture. In some implementations, memory 420 includes on-chip valley tracking circuitry (e.g., Figure 1A The on-chip valley tracking circuit 190 is used to determine a read voltage using an on-chip valley tracking read architecture based on a second set of parameters. The second set of parameters may include information from the memory controller 430. For example, the memory controller 430 may provide a first read voltage V1 and a valley tracking voltage range ΔV to the memory 420. The memory 420 may use the on-chip valley tracking architecture based on the first read voltage V1 and the valley tracking voltage range ΔV to determine a second read voltage V2. The first read voltage V1 and the valley tracking voltage range ΔV can determine a search voltage range [V1-ΔV / 2, V1+ΔV / 2]. Based on the first read voltage V1 and multiple parameters (e.g., a first set of input parameters), the memory controller 430 can determine the valley tracking voltage range ΔV. These multiple parameters may include block address, word line address, page address, number of program / erase cycles, read temperature, retention time, read interference level, and / or any other suitable parameters.

[0151] Figure 5A A diagram illustrating the valley tracking range of a third-order memory cell is provided. Figure 2B As shown, the three-level memory cell has eight states and can be read out using seven read voltages RD[0] to RD[6] (or RD[0:6]). Each read voltage and its associated valley tracking range can be determined individually based on multiple parameters. For example, Figure 5AInformation for a third order memory cell memory cell is shown, including a word line index (e.g., 2, 3), a page index (e.g., 0, 1, 2, 3), a program / erase cycle (e.g., 3K), and a retention time (e.g., 2 years). The default valley tracking range corresponding to each read voltage RD[0:6] is 8 units, where one unit is 0.0125V.

[0152] The optimal read voltage can be affected by multiple parameters. Different memory cells with different parameters can have different optimal read voltage variations. For example, memory cells with lower states can degrade more severely than memory cells with higher states, and thus, the valley tracking range for lower states can be set to be greater than the valley tracking range for higher states.

[0153] In some implementations, a memory controller (e.g., memory controller 430 of Figure 4 determines the valley tracking range for a memory cell based on results of previous reads by the memory controller (e.g., phase I 432 of the offline initial read of Figure 4 In some implementations, the memory 420 can also determine the valley tracking range based on the previous read results by the memory controller.

[0154] In the offline initial read, a first read voltage can be determined based on stored read voltage data associated with a first set of parameters for the target memory data. The stored read voltage data can be generated based on supervised machine learning training with multiple inputs associated with the memory and respective optimal read voltages. Based on the first read voltage and the respective optimal read voltage used to determine the first read voltage, a valley tracking range for the first read voltage can be determined.

[0155] In some examples, the valley tracking range can be determined based on the following equation:

[0156] Range VT = a • | R DML - AVG(RD Optimal for training | (Equation 1)

[0157] where Range VT represents the valley tracking range, RD ML represents the first read voltage obtained by the machine learning, RD Optimal for training represents the respective optimal read voltage for the training input of the machine learning, and a represents a scaling factor (e.g., 2).

[0158] In some examples, the valley tracking range is set to have an upper limit (or upper limit threshold) (e.g., 30) to avoid going beyond a reasonable range, and a lower limit (or lower limit threshold) (e.g., 2) to ensure that a valley tracking read decision (Phase II) can be triggered.

[0159] Figure 5B Illustration Figure 5A of the same default valley tracking range for the three-tier memory cell memory cells shown in Figure 5A the same default valley tracking range for the three-tier memory cell memory cells shown in For example, it is shown that the valley tracking range is larger for memory cells with larger threshold voltage variation, and smaller for memory cells with smaller threshold voltage variation. In this way, the valley tracking read architecture of Phase II can improve read accuracy, speed, and reliability.

[0160] Referring back to Figure 4 In Phase II, the bits stored in memory 420 are read out and counted at successive different read voltages in a determined search voltage range, and a curve showing the change in the number of bits resulting from each change in read voltage is observed. The voltage with the smallest change in the number of bits can correspond to the bottom of the curve, and can provide the best read voltage as the second read voltage V2. As mentioned above, the valley tracking read architecture can also count the number of cells by voltage or current.

[0161] After the second read voltage V2 is determined, memory 420 can generate a second read output of the memory data (e.g., the erroneous portion of the memory data of Phase I) using the second read voltage. In some cases, memory 420 includes an error correction code circuit to perform error correction code decoding. In some cases, memory 420 transmits the second read output to memory controller 430 through memory interface 433, and memory controller 430 decodes the second read output using error correction code decoding 434.

[0162] If the second read output passes error correction code check, memory controller 430 or memory 420 can output the second read output as the target read output of the memory data. Memory 420 or memory controller 430 can use the results of the valley tracking read (Phase II 422) (e.g., the second read voltage V2 and related parameters) to update the stored read voltage data used to determine the initial read voltage of Phase I 432.

[0163] If the second read output fails the error correction code check, the memory 420 or the memory controller 430 provides the result of the error correction code check to the online optimized read circuitry (e.g., Figure 1A An online read circuit 180 is included for online optimized reads (Stage III 436). The online optimized read circuit can be integrated into the memory controller 430 or an external microcontroller. The online read circuit can be triggered to generate a third read voltage based on a third set of parameters. The third set of parameters may include the results of previous error correction code checks, the first set of parameters for Stage I, and the second set of parameters for Stage II. In some examples, the third set of input parameters includes the error bit count of the second read output of the memory data, the syndrome of the low-density parity check code, the number of iterations of the low-density parity check code, the number of multiple "1" bit values ​​for each of the previous read voltages of the memory data, the decoding results of the previous error correction code, or any other suitable parameters.

[0164] The online optimization read circuit can be a machine learning circuit, which uses one or more machine learning algorithms to determine a third read voltage based on a third set of parameters. The machine learning algorithm may include linear regression, support vector regression, convolutional neural networks, recurrent neural networks, or other suitable algorithms. The memory controller 430 can use the third read voltage to read memory data (e.g., erroneous portions of the memory data) from the memory 420 to obtain a third read output of the memory data. The memory controller 430 can then use error correction code decoding 434 to decode the third read output to determine if it passes the error correction code check. If the third read output passes the error correction code check, the memory controller can determine that the third read output is the target read output of the memory data and output the target read output of the memory data (e.g., together with other target reads obtained in stage I) to the host 410. The memory controller can use the third read voltage and the third set of parameters to calibrate and update the read voltage data stored for stage I 432.

[0165] If the third read output fails the error correction code check, the memory controller 430 can modify the third set of parameters based on the result of the error correction code check, and determine a new read voltage based on the modified third set of parameters for reading. In some cases, if the number of read operations exceeds a predetermined threshold (e.g., a predetermined time period or a predetermined number of reads), the memory controller 430 can determine that the memory data read has failed. In some cases, the memory controller 430 can provide Stage III information to the memory 420 to perform another valley tracking read.

[0166] In some implementations, if the first read output fails the error correction code check of stage I, the memory controller determines that the memory is busy and cannot execute stage II. The memory controller can then directly trigger the online optimized read circuit to execute stage III, which can improve read efficiency.

[0167] Figure 6 This diagram illustrates a flow chart 600 for determining the read voltage of a memory system according to one or more embodiments. The memory system may be... Figure 1A Device 110 or Figure 4 The memory system 400 may include memory (e.g., memory ... Figure 1A memory 116 or Figure 4 The memory 420) and the memory controller (e.g., Figure 1A Device controller 112 or Figure 4 (Memory controller 430).

[0168] The memory system includes an error correction code decoder (e.g., Figure 1A The error correction code decoder 164), which is used to perform error correction code decoding (e.g., Figure 4 Error correction code decoding 434). In some cases, such as Figure 1A and Figure 4 As shown, the error correction code decoder is contained within the memory controller. In some cases, the error correction code decoder is contained within the memory. In some cases, the error correction code decoder is partially located in the memory controller and partially in the memory. In some cases, the memory controller includes a controller-side read circuit ECC decoder, and the memory includes a storage-side error correction code decoder.

[0169] The memory controller may include offline read circuitry (e.g., Figure 1A The offline read circuit 170 is used to perform an initial offline read (e.g., Figure 4 Stage I 432). The memory controller may also include in-circuit read circuitry (e.g., Figure 1A The online read circuit 180 is used to perform optimized online reads (e.g., Figure 4 Stage III 436). Offline readout circuitry and online readout circuitry can be implemented on integrated circuits or single circuits (e.g., machine learning circuitry). The memory may include valley tracking circuitry (e.g., Figure 1A The on-chip valley tracking circuit 190 is used to perform valley tracking reads (e.g., Figure 4 Phase II 422).

[0170] In step 602, process 600 begins. Process 600 may respond to receiving a read request (e.g., from a source like...). Figure 1A Host 120 or Figure 4 The process begins with the host device (410). A read request may instruct the reading of target memory data from the memory. The memory data may be stored at a specified address in the memory (e.g., a specified page of a specified block).

[0171] In step 604, during the offline initial reading phase (e.g., Figure 4 In stage I 432), the memory controller (e.g., an offline read circuit) determines a first read voltage, and the memory controller uses the first read voltage to obtain a first read output to read target memory data from the memory. The memory can use the first read voltage to read the target memory data to obtain the first read output, and transmit the first read output to the memory controller.

[0172] The memory controller may collect a first set of parameters related to the target memory data to be read from the memory. This first set of parameters may include at least one of the following address information: block address, page address, word line address, number of program / erase cycles (or program / erase cycle count), read temperature, read interference level, or retention time. The memory controller may use the stored read voltage data based on the first set of parameters to determine a first read voltage.

[0173] The stored read voltage data can be stored in a memory controller or memory. The stored read voltage data can be generated based on supervised machine learning training using multiple inputs related to the memory and the corresponding optimal read voltage. Under each of these inputs, the optimal read voltage corresponds to the minimum error bit count of the read output of an individual page of the memory. Each input can include corresponding values ​​of multiple parameters. The multiple parameters can include a first set of parameters. Each parameter can have a corresponding degree of influence on the memory cell characteristics of the memory, and the numerical intervals of the multiple parameters can be determined based on the corresponding degree of influence of the multiple parameters. Supervised machine learning training can be performed offline during and after the manufacture of the memory system. In some examples, the stored read voltage data includes a transfer function generated based on supervised machine learning training, and the transfer function represents the relationship between the input parameters and the optimal read voltage. The transfer function can include a lookup table, a hash function, or a k-means.

[0174] At step 606, the error correction code decoder decodes the first read output of the target memory data. In some cases, the error correction code decoder can utilize a hard decision decoding architecture (e.g., hard low density parity check code decoding). In some cases, the error correction code decoder can first utilize a hard decision decoding architecture. If unsuccessful, the error correction code decoder can utilize a soft decision decoding architecture (e.g., soft low density parity check code decoding). At step 608, the memory controller determines whether the first read output passes the first error correction code check (e.g., determines whether the error bits of the first read output can be corrected by the error correction code architecture).

[0175] If the first read output passes the first error correction code check, the flow 600 ends at step 624. The memory controller can determine the first read output as the target read output of the target memory data, and transmit the target read output to the host. If the memory cell is a multi-level memory cell, a triple-level memory cell, or a quintuple-level memory cell, a plurality of read voltages can be determined to read the target memory data (e.g., sequentially or in parallel) using the flow 600, respectively.

[0176] If the first read output does not pass the first error correction code check, at step 610, the memory is triggered to perform a valley tracking read architecture. The memory controller transmits the first read voltage determined at step 604 to the memory. The memory determines a second read voltage from the first read voltage, and generates a second read output related to the target memory data using the second read voltage.

[0177] In some embodiments, the second read voltage is determined from a second set of parameters related to the first set of parameters. The second set of parameters can include the first read voltage and a valley tracking range. In some cases, for example, the memory controller can determine the valley tracking range from the first read voltage and a corresponding optimal read voltage used for machine learning training to determine the first read voltage. The valley tracking range can be no greater than a predetermined upper threshold and no less than a predetermined lower threshold.

[0178] In the valley tracking read performed by the memory at step 610, the memory determines the second read voltage using a valley tracking read architecture based on the valley tracking range and the first read voltage. The memory can first utilize a sequence of read voltages defined by the first read voltage and the valley tracking range to obtain a sequence of values of read outputs related to the target memory data, and determine a read voltage corresponding to a minimum value of the sequence of values as the second read voltage. The sequence of values can include at least one of a sequence of cell counts corresponding to the target memory data, a sequence of accumulated voltages or currents corresponding to read-out bits of the target memory data, and a sequence of differential voltages or currents of the accumulated voltages or currents.

[0179] In some embodiments, at step 608, the memory controller determines that the first read output fails the first error correction code check by determining that at least a portion of the first read output fails the first error correction code check. The at least a portion of the first read output corresponds to at least an erroneous portion of the target memory data. The memory controller can record information of the at least an erroneous portion of the target memory data and provide the information to the memory. At step 610, the memory can only read the at least an erroneous portion of the target memory data using the second read voltage to generate a second read output.

[0180] The memory controller can also determine that a remaining portion of the first read output passes the first error correction code check. The remaining portion of the first read output corresponds to a remaining portion of the target memory data. The memory controller can determine that the remaining portion of the first read output is a target read output of the remaining portion of the target memory data. The memory can not read the remaining portion of the target memory data using the second read voltage. For example, if the target memory data includes a page having a plurality of blocks and a corresponding first read of at least one block of the page using the first read voltage fails the first error correction code check, the memory can only read the at least one block using the second read voltage and not other blocks of the page that pass the first error correction code check.

[0181] At step 612, the error correction code decoding decodes the second read output. In some cases, the error correction code decoder can first utilize a hard decision decoding architecture (e.g., hard low density parity check code decoding). If that fails, the error correction code decoder can utilize a soft decision decoding architecture (e.g., soft low density parity check code decoding. In some cases, the memory provides the second read output to the memory controller and the memory controller decodes the second read output and determines at step 614 whether the second read output passes the second error correction code check. In some cases, the memory includes error correction code circuitry that decodes the second read output and determines at step 614 whether the second read output passes the second error correction code check.

[0182] If the second read output passes the second error correction code check, the flow 600 proceeds to step 624. The memory controller outputs the second read output as a target read output of the target memory data. If the second read output is only for the erroneous portion of the target memory data, the memory controller can combine the first read output for the remaining portion of the target memory data and the second read output to obtain the target read output of the target memory data. At step 604, the memory controller can also update the stored read voltage data with the second read voltage used to determine the first read voltage.

[0183] If the second read output fails the second error correction code check, an online optimization read is triggered at step 616. The memory controller determines a third read voltage based on a third set of parameters. The third set of parameters includes a result of the second error correction code check or the first set of parameters and / or the second set of parameters. The memory controller can obtain a third read output of the target memory data of the memory using the third read voltage. If only a portion of the target memory data fails the first error correction code check and / or the second error correction code check, the online optimization read can only be performed on the portion of the target memory data using the third read voltage.

[0184] The memory controller can determine the third read voltage using at least one machine learning algorithm based on the second set of parameters. The at least one machine learning algorithm can include at least one of a linear regression, a support vector regression, and a deep learning algorithm with a convolutional neural network algorithm or a recurrent neural network algorithm. The third set of parameters can include at least one of an error bit count of the second read output, a number of “1” values obtained by each read voltage, a change in the number of “1” values between a previous read voltage and a current read voltage, a read time, a syndrome of a low density parity check code, and a number of iterations of the low density parity check code.

[0185] At step 618, the third read output is decoded by an error correction code decoding. In some cases, the third read output is decoded by a hard decision decoding architecture. In some cases, the third read output is decoded by a soft decision decoding architecture. In some cases, the third read output is decoded by a hard decision decoding architecture first. If the third read output fails the error correction code check, the third read output can be decoded by a soft decision decoding architecture.

[0186] At step 620, the memory controller determines whether the third read output passes a third error correction code check. In response to determining that the third read output passes the third error correction code check, at step 622, the memory controller updates the stored read voltage data using at least one of the third read voltage and the third set of parameters. The memory controller can also output the third read output as a target read output of the target memory data. In some cases, the memory controller outputs the third read output with a remaining portion of the first read output and / or a remaining portion of the second read output as the target read output of the target memory data. The remaining portion of the first read output passes the first error correction code check, and the remaining portion of the second read output passes the second error correction code check.

[0187] If the third read output fails the third error correction code check, the memory controller determines whether a predetermined read threshold has been reached at step 626. The predetermined read threshold can be a predetermined time period or a predetermined number of reads. For example, the predetermined number of reads can be 5 or 10. If the predetermined read threshold has been reached, the memory controller determines that the target memory data read from the memory has failed at step 628. If the predetermined read threshold has not been reached, the flow 600 returns to step 616. The memory controller can determine a new read voltage based on the result of the third error correction code check.

[0188] In some embodiments, the memory controller is to obtain a first particular read output of a particular memory data to be read from the memory using a first particular read voltage determined based on a first particular set of parameters associated with the particular memory data. If the memory controller determines that the first particular read output fails a corresponding error correction code check and the memory is busy, the memory controller can directly trigger an online optimization read at step 616. That is, the memory controller can determine a second particular read voltage based on a second particular set of parameters including at least one of the first particular set of parameters and a result of the corresponding error correction code check of the first particular read output. The memory controller can read the particular memory data using the second particular read voltage to obtain a second particular read output and determine whether the second particular read output passes the corresponding error correction code check. If the memory controller determines that the second particular read output passes the corresponding error correction code check, the memory controller can output the second particular read output as the target read output of the particular memory data of the memory.

[0189] In some embodiments, a memory system can first use a valley tracking read architecture to address retention time and die-to-die variation issues and then use an online optimization read architecture to improve detection accuracy. The memory can be to determine a first read voltage based on a first set of parameters associated with memory data using the valley tracking read architecture and generate a first read output of the memory data using the first read voltage. The memory controller can be to determine a second read voltage based on a second set of parameters including at least one of the first set of parameters and a result of a first error correction code check of the first read output in response to determining that the first read output fails the first error correction code check, obtain a second read output of the memory data of the memory using the second read voltage, determine whether the second read output passes a second error correction code check, and output the second read output as a target read output of the memory data in response to determining that the second read output passes the second error correction code check.

[0190] The present disclosure and other aspects can be implemented in one or more computer programming product(s) such as one or more computer programming instruction module(s) encoded on a computer readable medium (CRM). The CRM can be a machine-readable storage

[0191] The system can include all devices, apparatuses, and machines for processing data, such as including a programmable processor, a computer, or multiple processors or computers. In addition to hardware, the system can include code that creates an execution environment for the computer programming, such as code that forms a processor firmware, a protocol stack, a database management system, an operating system, or a combination of one or more of them.

[0192] Computer programming (also known as programs, software, software applications, scripts or code) can be written in any form of programming language, including compiled or interpreted languages, and it can be deployed in any form, including as a stand-alone program or a module, component, subroutine, or other unit suitable for use in a computing environment. Computer programming need not correspond to a file in a file system. A program can be stored in a portion of a file that holds other programs, in a single file dedicated to the program in question, or in multiple coordinated files stored in different locations. Computer programming can be deployed to be executed on one computer or on multiple computers that are located at one site or distributed across multiple sites and are interconnected by a communication network.

[0193] The functions described can be implemented in one or more computer programs that are executable on one or more programmable processors to perform these functions of the present application. The computer programs include program instructions that are executable on one or more processors including general purpose and special purpose microprocessors, as well as any kind of digital computer. Generally, a processor will receive instructions and data from a read-only memory or a random access memory (or both). The essential elements of a computer are a processor for executing instructions and one or more memory devices for storing instructions and data. Generally, a computer will also include, or be operatively coupled to receive data from or transfer data to, or both, one or more mass storage devices for storing data, such as magnetic, magneto optical or optical disks. However, a computer need not have such devices. Computer readable media suitable for storing computer program instructions and data include all forms of non-volatile memory, media and memory devices, including by way of example semiconductor memory devices, e.g., EPROM, EEPROM, flash memory devices, and magnetic disks. The processor and the memory can be supplemented by, or incorporated in, special purpose logic circuitry.

[0194] The processor suitable for the execution of a computer program includes, by way of example, one or more processors, including general and special purpose microprocessors. The processor generally will receive instructions and data from a read-only memory or a random access memory (or both). Computer elements can include a processor for executing instructions and one or more memory devices for storing instructions and data. Generally, a computer also can include, or be operatively coupled to receive data from or transfer data to, or both, one or more mass storage devices for storing data, such as magnetic, magneto optical or optical disks. However, a computer need not have such devices. Computer readable media suitable for storing computer program instructions and data include all forms of non-volatile memory, media and memory devices, including by way of example semiconductor memory devices, e.g., EPROM, EEPROM, flash memory devices, and magnetic disks. The processor and the memory can be supplemented by, or incorporated in, special purpose logic circuitry.

[0195] Although this document can describe many specifics, these should not be construed as limitations on the scope of the application or of any patent that can be issued thereon, but rather as descriptions of particular embodiments thereof. Certain features that are described in this document in the context of separate embodiments can also combine in a single embodiment. Conversely, various features that are described in the context of a single embodiment can also be implemented in multiple embodiments or in any suitable sub-combination. Moreover, although features can be described above as acting in certain combinations and even initially claimed as such, one or more features from a claimed combination can in some cases be excised from the combination and the claimed combination can be directed to a sub-combination or a variation of a sub-combination. Similarly, while operations are depicted in the drawings in a particular order, this should not be understood as requiring such order, nor that all illustrated operations be performed, to achieve desirable results.

[0196] Only some examples and embodiments are disclosed herein. Variations, modifications, and enhancements to the described examples and embodiments and other embodiments can be made based upon the disclosure herein by persons of ordinary skill in the art.

[0197] In view of the above, it will be seen that the several examples and embodiments disclosed herein are merely exemplary and are not to be construed as limiting the scope of the application. Those skilled in the art will readily understand that various modifications and adaptations can be made to the examples and embodiments disclosed herein without departing from the spirit and scope of the application. Accordingly, the scope of the application is to be construed in accordance with the appended claims, along with the full range of equivalents to which such claims are entitled.

Claims

1. A memory system, characterized in that, include: A memory used to store data; as well as A memory controller is coupled to the memory; The memory controller is used for: A first read output of target memory data stored in the memory is obtained using a first read voltage, wherein the first read voltage is determined based on a stored read voltage data using a first set of parameters related to the target memory data, the stored read voltage data being generated based on supervised machine learning training using multiple inputs related to the memory and corresponding multiple optimal read voltages, each of the optimal read voltages corresponding to a minimum error bit count of the read output of an individual page of the memory under individual inputs, each input including corresponding values ​​of multiple parameters including the first set of parameters; the memory controller is used to determine a valley tracking range based on the first read voltage and the corresponding optimal read voltages of these inputs; as well as In response to determining that the first read output failed a first error-correcting code (ECC) check, the first read voltage is supplied to the memory; and This memory is used for: A second read voltage is determined based on the first read voltage, wherein the memory is used to determine the second read voltage using a valley tracking read architecture based on the valley tracking range and the first read voltage; as well as The second read voltage is used to generate a second read output related to the target memory data.

2. The memory system according to claim 1, characterized in that, This memory controller is used for: The second read output is confirmed to pass a second error correction code check; and The second read output is output as a target read output of the target memory data.

3. The memory system according to claim 2, characterized in that, This memory controller is used for: It was determined that the second read output failed the second error correction code check; A third read voltage is determined based on a second set of parameters, the second set of parameters including the result of the second error correction code check or at least one of the first set of parameters; A third read output is obtained using the third read voltage, which relates to the target memory data of the memory. as well as Determine whether the third read output passes the third error correction code check.

4. The memory system according to claim 3, characterized in that, This memory controller is used for: In response to the determination that the third read output has failed the third error correction code check, it is determined whether a predetermined read threshold has been reached. In response to the determination that the predetermined read threshold has been reached, it is determined that the data read from the target memory from the memory has failed; as well as In response to the determination that the predetermined reading threshold has not been reached, a new reading voltage is determined based on the result of the third error correction code verification.

5. The memory system according to claim 3, characterized in that, This memory controller is used for: In response to the determination that the third read output passes the third error correction code check, the third read output is output as a target read output of the target memory data.

6. The memory system according to claim 5, characterized in that, The memory controller is used to determine the first read voltage using the stored read voltage data based on the first set of parameters; as well as The memory controller is used for: In response to the determination that the third read output passes the third error correction code check, the stored read voltage data is updated using the third read voltage and at least one of the second set of parameters.

7. The memory system according to claim 3, characterized in that, The memory controller is used to determine the third read voltage using at least one machine learning (ML) algorithm based on the second set of parameters.

8. The memory system according to claim 3, characterized in that, This memory controller is used for: The first read output is decoded using a hard decision decoding scheme. as well as The third read output is decoded using at least one of the hard-decision decoding architecture and a soft-decision decoding scheme.

9. The memory system according to claim 3, characterized in that, The second set of parameters includes at least one of the following: a count of error bits in the second read output, the number of "1" values ​​obtained by each read voltage, the change in the number of "1" values ​​between a previous read voltage and a current read voltage, a read time, a syndrome of a low-density parity-check code (LDPC code), and the number of iterations of the LDPC code.

10. The memory system according to claim 1, characterized in that, The first set of parameters includes at least one of the following: address information, number of programming / erasing (P / E) cycles, a read temperature, a read interference level, and a retention time.

11. The memory system according to claim 1, characterized in that, This memory controller is used for: Determining that at least a portion of the first read output fails the first error correction code check, the first read output fails the first error correction code check, wherein the at least a portion of the first read output corresponds to at least one erroneous portion of the target memory data; as well as The memory is used to read at least one erroneous portion of the target memory data using the second read voltage to generate the second read output.

12. The memory system according to claim 11, characterized in that, This memory controller is used for: The remaining portion of the first read output is determined to pass the first error correction code test, wherein the remaining portion of the first read output corresponds to the remaining portion of the target memory data and passes the first error correction code test; as well as A target read output that determines the remaining portion of the first read output as the remaining portion of the target memory data; The memory does not use the second read voltage to read the remaining portion of the target memory data.

13. The memory system according to claim 1, characterized in that, This memory controller is used for: A first specific read output is obtained by using a first specific read voltage to read a specific memory data from the memory, the first specific read voltage being determined based on a first specific set of parameters related to the specific memory data; It was determined that the first specific read output failed the corresponding error correction code check; In response to determining that the memory is busy, a second particular set of parameters is determined based on a second particular set of parameters, the second particular set of parameters including the result of the corresponding error correction code check related to the first particular read output or at least one of the first particular set of parameters; The specific memory data is read using the second specific read voltage to obtain a second specific read output; Determine whether the second specific read output passes the corresponding error correction code check; as well as In response to determining that the second specific read output passes the corresponding error correction code check, the second specific read output is output as a target read output of the specific memory data of the memory.

14. A memory system, characterized in that, include: A memory, including a memory-side read circuit; as well as A memory controller, including a controller-side read circuit; The memory controller is used for: The control-side read circuit uses stored read voltage data related to a first set of parameters associated with a target memory data to be read from the memory to determine a first read voltage. This stored read voltage data is generated based on supervised machine learning training using multiple inputs related to the memory and corresponding optimal read voltages. Under each of these inputs, each optimal read voltage corresponds to a minimum error bit count of the read output of an individual page of the memory. Each input includes corresponding values ​​for multiple parameters, including the first set of parameters. The memory controller determines a valley tracking range based on the first read voltage and the corresponding optimal read voltages of these inputs. A first read output of the target memory data is obtained using the first read voltage; as well as In response to determining that at least a portion of the first read output has failed a first error correction code check, the memory is provided with the first read voltage and information on at least a faulty portion of the target memory data corresponding to the at least portion of the first read output; as well as This memory is used for: The storage-side read circuit determines a second read voltage based on the first read voltage, wherein the storage-side read circuit is used to determine the second read voltage using a valley tracking read architecture based on the valley tracking range determined by the memory controller; as well as The second read voltage is used to generate a second read output of at least one erroneous portion of the target memory data.

15. The memory system according to claim 14, characterized in that, This memory controller is used for: It was determined that the second read output failed the second error correction code check; The control-side reading circuit determines a third reading voltage based on a second set of parameters, the second set of parameters including the result of the second error correction code verification and at least one of the first set of parameters; A third read output is obtained by using the third read voltage to obtain at least one erroneous portion of the target memory data; Determine whether the third read output passes the third error correction code check; In response to determining that the third read output passes the third error correction code check, the remaining portion of the third read output and the first read output is output as a target read output of the target memory data, wherein the remaining portion of the first read output passes the first error correction code check; as well as The stored read voltage data is updated using at least one of the third read voltage and the second set of parameters.

16. The memory system according to claim 15, characterized in that, The control-side readout circuit is used to determine the third readout voltage using at least one machine learning algorithm based on the second set of parameters.

17. A memory system, characterized in that, include: A memory used to store data; as well as A memory controller is coupled to the memory; This memory is used for: A first read voltage is determined based on a first set of parameters related to memory data using a valley tracking read architecture, wherein the first read voltage is determined based on stored read voltage data using the first set of parameters related to the memory data, the stored read voltage data being generated based on supervised machine learning training using multiple inputs related to the memory and corresponding multiple optimal read voltages, each of the optimal read voltages corresponding to a minimum error bit count of the read output of an individual page of the memory, each of the inputs including corresponding values ​​of multiple parameters, including the first set of parameters; as well as The first read voltage is used to generate a first read output of the memory data; The memory controller is used for: In response to the determination that the first read output failed a first error correction code check, a second read voltage is determined based on a second set of parameters, the second set of parameters including the result of the first error correction code check and at least one of the first set of parameters, the second read voltage being determined using the valley tracking read architecture based on a valley tracking range determined by the memory controller; A second read output is obtained by using the second read voltage to obtain the memory data of the memory; Determine whether the second read output passes the second error correction code check; as well as In response to determining that the second read output passes the second error correction code check, the second read output is output as a target read output of the memory data.

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