Multilayer ceramic capacitor

Abstract

The present invention provides a multilayer ceramic capacitor capable of maintaining a stable posture during installation, comprising: a multilayer body (11) having a substantially rectangular parallelepiped shape, including a plurality of dielectric ceramic layers (16) and a plurality of internal electrode layers (15) alternately laminated in a lamination direction (T), and having a first main surface (12a) and a second main surface (12b) opposite to each other in the lamination direction, a first side surface (13a) and a second side surface (13b) opposite to each other in a width direction (W), and a first end surface (14a) and a second end surface (14b) opposite to each other in a length direction (L); and a pair of external electrodes (20) disposed at both end portions in the length direction of the multilayer body so as to cover at least the first end surface and the second end surface respectively and be connected to the internal electrode layers, and first protrusions (30) are respectively formed at four corner portions of the surface on at least one of the first main surface side and the second main surface side of the substantially rectangular shape.

Description

Technical Field

[0001] The present invention relates to a multilayer ceramic capacitor. Background Art

[0002] Conventionally, a multilayer ceramic capacitor having a substantially rectangular parallelepiped shape has been known, which includes: a laminate formed by alternately laminating dielectric ceramic layers and internal electrode layers in a lamination direction; and a pair of external electrodes disposed at both ends in the length direction of the laminate and connected to the internal electrode layers. Patent Document 1 discloses a multilayer ceramic capacitor in which, due to the lamination structure of the internal electrode layers, the thickness in the lamination direction of the outer peripheral portion is thinner than that of the central portion where all the internal electrode layers are laminated.

[0003] Prior Art Documents

[0004] Patent Documents

[0005] Patent Document 1: Japanese Unexamined Patent Application Publication No. 2019-9463

[0006] In the multilayer ceramic capacitor disclosed in Patent Document 1 above, when mounted on a substrate, the posture placed on the substrate tends to become unstable. Therefore, a situation may occur in which it is difficult to perform mounting operations such as soldering. Summary of the Invention

[0007] Problems to be Solved by the Invention

[0008] Therefore, an object of the present invention is to provide a multilayer ceramic capacitor that can maintain a stable posture during mounting.

[0009] Means for Solving the Problems

[0010] The multilayer ceramic capacitor according to the present invention includes: a substantially rectangular parallelepiped-shaped laminate including a plurality of dielectric ceramic layers and a plurality of internal electrode layers alternately laminated in a lamination direction, and having a first main surface and a second main surface opposite to each other in the lamination direction, a first side surface and a second side surface opposite to each other in a width direction orthogonal to the lamination direction, and a first end surface and a second end surface opposite to each other in a length direction orthogonal to the lamination direction and the width direction; and a pair of external electrodes disposed at both ends in the length direction of the laminate so as to cover at least the first end surface and the second end surface, respectively, and connected to the internal electrode layers, and first convex portions are respectively formed at four corner portions on the surface of at least one of the first main surface side and the second main surface side of the substantially rectangular shape.

[0011] Advantages of the Invention

[0012] According to the present invention, it is possible to provide a multilayer ceramic capacitor that can maintain a stable posture during mounting. Brief Description of the Drawings

[0013] Figure 1 is a perspective view of the multilayer ceramic capacitor according to the first embodiment.

[0014] Figure 2 is Figure 1 a sectional view taken along line II-II.

[0015] Figure 3 is Figure 1 a sectional view taken along line III-III.

[0016] Figure 4 is Figure 2 a sectional view taken along line IV-IV.

[0017] Figure 5 is a view schematically showing the first stage of the manufacturing method capable of forming the first convex portion according to the first embodiment, with the upper side being a top view and the lower side being a sectional view taken along line A-A of the top view on the upper side.

[0018] Figure 6 is a view schematically showing the second stage of the above manufacturing method, with the upper side being a top view and the lower side being a sectional view taken along line B-B of the top view on the upper side.

[0019] Figure 7 is a view schematically showing the third stage of the above manufacturing method, with the upper side being a top view and the lower side being a sectional view taken along line C-C of the top view on the upper side.

[0020] Figure 8 is a view schematically showing the fourth stage of the above manufacturing method, with the upper side being a top view and the lower side being a sectional view taken along line D-D of the top view on the upper side.

[0021] Figure 9 is a sectional view showing the fifth stage of the above manufacturing method.

[0022] Figure 10 is a laminate model according to the first embodiment obtained by the above manufacturing method, with the upper side being a top view and the lower side being a sectional view taken along line E-E of the top view on the upper side.

[0023] Figure 11 is a perspective view of the multilayer ceramic capacitor according to the second embodiment.

[0024] Figure 12 is Figure 11 a sectional view taken along line XII-XII.

[0025] Figure 13 is Figure 11 a sectional view taken along line XIII-XIII.

[0026] Figure 14Yes Figure 12 Cross-sectional view XIV-XIV thereof.

[0027] Figure 15 It is a diagram schematically showing the first stage of the manufacturing method capable of forming the second convex portion according to the second embodiment. The upper side is a top view, and the lower side is a cross-sectional view F-F of the top view on the upper side.

[0028] Figure 16 It is a diagram schematically showing the second stage of the above manufacturing method. The upper side is a top view, and the lower side is a cross-sectional view G-G and a cross-sectional view H-H of the top view on the upper side.

[0029] Figure 17 It is a diagram schematically showing the third stage of the above manufacturing method. The upper side is a top view, and the lower side is a cross-sectional view I-I of the top view on the upper side.

[0030] Figure 18 It is a diagram schematically showing the fourth stage of the above manufacturing method. The upper side is a top view, and the lower side is a cross-sectional view J-J of the top view on the upper side.

[0031] Figure 19 It is a cross-sectional view showing the fifth stage of the above manufacturing method.

[0032] Figure 20 It is a laminate model according to the second embodiment obtained by the above manufacturing method. The upper side is a top view.

[0033] Figure 21 It is a side cross-sectional view of a laminate model according to a modified example of the first embodiment.

[0034] Figure 22 Yes Figure 21 Cross-sectional view XXII-XXII thereof.

[0035] Explanation of reference numerals

[0036] 10: Multilayer ceramic capacitor;

[0037] 11: Laminate;

[0038] 11A: Inner layer part;

[0039] 11B: Outer layer part;

[0040] 12a: First main surface;

[0041] 12b: Second main surface;

[0042] 13a: First side surface;

[0043] 13b: Second side surface;

[0044] 14a: First end surface;

[0045] 14b: Second end face;

[0046] 15: Internal electrode layer;

[0047] 15A1: First internal electrode layer;

[0048] 15A2: Second internal electrode layer;

[0049] 15b: Opposing portion;

[0050] 15c1: First lead-out portion;

[0051] 15c2: Second lead-out portion;

[0052] 15d1: First edge portion;

[0053] 15d2: Second edge portion;

[0054] 16: Dielectric ceramic layer;

[0055] 16A: First dielectric ceramic layer;

[0056] 16B: Second dielectric ceramic layer;

[0057] 16C: Third dielectric ceramic layer;

[0058] 18a: First peripheral portion;

[0059] 18b: Second peripheral portion;

[0060] 18c: Central region;

[0061] 18d: Crossing portion;

[0062] 20: External electrode;

[0063] 30: First convex portion;

[0064] 36: Second convex portion;

[0065] 39: Raised portion;

[0066] L: Length direction;

[0067] T: Laminating direction;

[0068] W: Width direction. Detailed implementation manners

[0069] Hereinafter, the implementation manners will be described with reference to the drawings.

[0070] (First implementation manner)

[0071] Figure 1It is a schematic perspective view of the multilayer ceramic capacitor 10 according to the first embodiment. Figure 2 It is along Figure 1 The sectional view taken along line II-II shown. Figure 3 It is along Figure 1 The sectional view taken along line III-III shown. Figure 4 It is along Figure 2 The sectional view taken along line IV-IV shown.

[0072] As Figure 1 shown, the multilayer ceramic capacitor 10 of the first embodiment has a substantially rectangular parallelepiped shape as a whole. The multilayer ceramic capacitor 10 includes a laminate 11 and a pair of external electrodes 20, and the laminate 11 has a substantially rectangular parallelepiped shape.

[0073] In Figures 1 to 3 it, the arrow T shows the stacking direction of the multilayer ceramic capacitor 10 and the laminate 11. In Figure 1 , Figure 2 and Figure 4 it, the arrow L shows the length direction of the multilayer ceramic capacitor 10 and the laminate 11 orthogonal to the stacking direction T. In Figure 1 , Figure 3 and Figure 4 it, the arrow W shows the width direction of the multilayer ceramic capacitor 10 and the laminate 11 orthogonal to the stacking direction T and the length direction L.

[0074] Figure 2 shows the LT section. Figure 3 shows the WT section, Figure 4 shows the LW section.

[0075] The laminate 11 has a first main surface 12a and a second main surface 12b opposite to each other in the stacking direction T, a first side surface 13a and a second side surface 13b opposite to each other in the width direction W, and a first end surface 14a and a second end surface 14b opposite to each other in the length direction L.

[0076] As Figures 2 to 4 shown, the laminate 11 includes a plurality of internal electrode layers 15 and a plurality of dielectric ceramic layers 16 stacked in the stacking direction T.

[0077] The plurality of internal electrode layers 15 include a first internal electrode layer 15A1 and a second internal electrode layer 15A2 adjacent to each other in the stacking direction T. The first internal electrode layer 15A1 and the second internal electrode layer 15A2 have rectangular shapes with substantially the same size. The first internal electrode layer 15A1 and the second internal electrode layer 15A2 each have rectangular opposed portions 15b adjacent to each other in the stacking direction T with a dielectric ceramic layer 16 therebetween.

[0078] The first internal electrode layer 15A1 has a first lead portion 15c1 that extends from the end portion on the side of the first end surface 14a in the opposed portion 15b to the first end surface 14a. The front end of the first lead portion 15c1 is exposed on the first end surface 14a. The second internal electrode layer 15A2 has a second lead portion 15c2 that extends from the end portion on the side of the second end surface 14b in the opposed portion 15b to the second end surface 14b. The front end of the second lead portion 15c2 is exposed on the second end surface 14b.

[0079] In addition, since the basic structures of the first internal electrode layer 15Al and the second internal electrode layer 15A2 are the same, they are sometimes collectively referred to as the internal electrode layer 15 without special distinction.

[0080] As Figure 4 shown, the internal electrode layer 15 includes a pair of first edge portions 15d1 that extend along the length direction L at both end portions in the width direction W and a pair of second edge portions 15d2 that extend along the width direction W at both end portions in the length direction L of the opposed portion 15b.

[0081] The internal electrode layer 15 is a conductive thin film containing metals such as Ni, Cu, Ag, Pd, alloys of Ag and Pd, and Au. The internal electrode layer 15 is not limited to these metal materials and can also be formed of other conductive materials. The internal electrode layer 15 can also further include dielectric particles having the same composition system as the ceramics contained in the dielectric ceramic layer 16.

[0082] The dielectric ceramic layer 16 includes a plurality of first dielectric ceramic layers 16A, a plurality of second dielectric ceramic layers 16B, and a pair of third dielectric ceramic layers 16C.

[0083] The plurality of first dielectric ceramic layers 16A are respectively arranged between the first internal electrode layer 15A1 and the second internal electrode layer 15A2 in the stacking direction T. The plurality of second dielectric ceramic layers 16B are respectively arranged to fill the regions where the internal electrode layer 15 is not arranged between the first dielectric ceramic layers 16A that are opposed to each other across the internal electrode layer 15. The plurality of second dielectric ceramic layers 16B respectively overlap with the first dielectric ceramic layers 16A on both sides in the stacking direction T in the stacking direction T. The pair of third dielectric ceramic layers 16C are arranged to sandwich the inner layer portion 11A and the outer layer portion 11B on the main surface side in the width direction W, constituting the outer layer portion on the side surface, and the first side surface 13a and the second side surface 13b are formed on their respective surfaces.

[0084] In addition, the first dielectric ceramic layer 16A, the second dielectric ceramic layer 16B, and the third dielectric ceramic layer 16C are formed of materials having the same characteristics, and based on this, they are sometimes collectively referred to as the dielectric ceramic layer 16 without special distinction.

[0085] The dielectric ceramic layer 16 is formed, for example, by firing a ceramic material mainly composed of barium titanate. The dielectric ceramic layer 16 may also be formed of other ceramic materials with a high dielectric constant (for example, ceramic materials mainly composed of CaTiO3, SrTiO3, CaZrO3, etc.). In the ceramic material for forming the dielectric ceramic layer 16, additives such as Si, Mg, Mn, Sn, Cu, rare earths, Ni, and Al are included, for example, for the purpose of adjusting the composition.

[0086] The laminate 11 further includes an inner layer portion 11A and an outer layer portion 11B.

[0087] In the inner layer portion 11A, a plurality of first internal electrode layers 15A1 and a plurality of second internal electrode layers 15A2 are alternately laminated with the first dielectric ceramic layer 16A therebetween. The inner layer portion 11A is a portion that generates capacitance and substantially functions as a capacitor. A pair of outer layer portions 11B are respectively arranged to sandwich the inner layer portion 11A in the lamination direction, and a first main surface 12a and a second main surface 12b are formed on their respective surfaces. The outer layer portion 11B is formed of the same dielectric ceramic material as the dielectric ceramic layer 16.

[0088] As Figure 1 and Figure 3 shown, a pair of external electrodes 20 are provided separately from each other so as to cover the surfaces of both ends in the longitudinal direction L of the laminate 11. The pair of external electrodes 20 are each formed of a conductive film. The pair of external electrodes 20 includes a first external electrode 20A disposed on the side of the first end face 14a and a second external electrode 20B disposed on the side of the second end face 14b.

[0089] The front end of the first lead portion 15c1 in each first internal electrode layer 15A1 is in contact with the first external electrode 20A. Thereby, the first internal electrode layer 15A1 is electrically connected to the first external electrode 20A. The front end of the second lead portion 15c2 in each second internal electrode layer 15A2 is in contact with the second external electrode 20B. Thereby, the second internal electrode layer 15A2 is electrically connected to the second external electrode 20B. That is, in the inner layer portion 11A, the opposing portions 15b of the first internal electrode layers 15A1 connected to the first external electrode 20A and the opposing portions 15b of the second internal electrode layers 15A2 connected to the second external electrode 20B are alternately laminated with the first dielectric ceramic layer 16A therebetween in the lamination direction T. Thereby, a structure is formed in which capacitor elements are electrically connected in parallel between the first external electrode 20A and the second external electrode 20B.

[0090] In addition, since the basic structures of the first external electrode 20A and the second external electrode 20B are the same, they are sometimes collectively referred to as the external electrode 20 when no special distinction is required.

[0091] The external electrode 20 is formed of, for example, a laminated film of a sintered metal layer and a plating layer. The sintered metal layer is formed, for example, by baking a paste of Cu, Ni, Ag, Pd, Ag-Pd alloy, Au, or the like. The plating layer includes, for example, a Ni plating layer and a Sn plating layer covering the Ni plating layer. Instead, the plating layer may be a Cu plating layer or an Au plating layer. In addition, the external electrode 20 may be formed only of a plating layer, and furthermore, a conductive resin paste may also be used.

[0092] In the multilayer ceramic capacitor 10 of the first embodiment, for example, ceramic materials such as a green sheet of the dielectric ceramic layer 16 and the pair of outer layer portions 11B and conductive material layers such as a conductive paste of the internal electrode layer 15 are laminated to form a laminate 11. Then, the laminate 11 is fired, and thereafter, the external electrode 20 is formed by baking, plating, or the like, thereby manufacturing the multilayer ceramic capacitor 10. In addition, regarding the formation of the external electrode 20, in addition to plating, it may be formed by baking a part or all of it simultaneously with the firing of the laminate 11.

[0093] In the multilayer ceramic capacitor 10 of the first embodiment, as Figure 1 shown, at four corners of the surface on the first main surface 12a side in the laminate 11, first convex portions 30 having a surface height higher than other portions are respectively formed. The first convex portions 30 are also formed at the four corners of the surface on the second main surface 12b side in the same manner. Each of the first convex portions 30 in the embodiment is formed to protrude from the flat surface of the external electrode 20. The four first convex portions 30 have substantially the same height.

[0094] As Figure 2 and Figure 3 shown, the first convex portions 30 are respectively formed by covering the first protruding portions 31 formed on the laminate 11 with the external electrode 20. The first protruding portions 31 of the laminate 11 are formed at the four corners of each of the first main surface 12a and the second main surface 12b.

[0095] For example, Figures 5 to 10 as a result of the manufacturing process shown, the first protruding portions 31 of the laminate 11 can be formed.

[0096] Hereinafter, the principle of forming the first protruding portions 31 through this manufacturing process will be described. In addition, for easy understanding, Figures 5 to 10 the manufacturing process of one laminate 11 is modeled and shown. Actually, a plurality of laminates 11 are manufactured together. In Figures 5 to 8 , Figure 10 the upper figure is a top view, and the lower figure of this top view is a cross-sectional view corresponding to the viewing section line shown in the upper top view.

[0097] In addition, in the following description, the thickness of one layer of each of the internal electrode layer 15 and the dielectric ceramic layer 16 is set to "1", and the thickness corresponding to the number of stacked layers is shown. For example, if the number of stacked layers is 2, it is "thickness 2", and if the number of stacked layers is 3, it is "thickness 3". In Figures 5 to 8 , Figure 10 In the top view, the thickness of each part divided by lines is indicated by circled numbers.

[0098] As Figure 5 shown, a dielectric ceramic layer 16 (thickness 1) that forms a base and includes the first dielectric ceramic layer 16A is formed, and a first internal electrode layer 15A1 (thickness 2) is formed thereon. The first lead-out portion 15c1 of the first internal electrode layer 15A1 is exposed on the side of the first end face 14a. Next, as Figure 6 shown, on the upper surface of the dielectric ceramic layer 16 on the side of the second end face 14b where the first internal electrode layer 15A1 is not formed, a second dielectric ceramic layer 16B (thickness 2) is formed over the entire length in the width direction W. Alternatively, the dielectric ceramic layer 16 may be formed first, and then the first internal electrode 15A1 may be formed.

[0099] In addition, the dielectric ceramic layer 16 and the internal electrode layer 15 are formed by screen printing. Alternatively, intaglio printing or the like may be used. In particular, in screen printing, a printing pattern is formed by using a high-precision screen printing plate based on electroforming processing or by changing the tension of the screen printing plate.

[0100] Next, as Figure 7 shown, dielectric ceramic layers 16 that form the third dielectric ceramic layer 16C are stacked over the entire length in the length direction L on the upper surfaces of the dielectric ceramic layer 16 on both sides in the width direction W of the first internal electrode layer 15A1, thereby obtaining a first raw sheet 1A. Since the third dielectric ceramic layer 16C is stacked over the entire length in the length direction L, at the corner portions at both ends in the width direction W on the side of the second end face 14b, the third dielectric ceramic layer 16C overlaps the second dielectric ceramic layer 16B, and only at this portion does it become three layers, that is, it becomes "thickness 3".

[0101] Next, through the same process as Figures 5 to 7 , a second raw sheet 1B having a second internal electrode layer 15A2 as shown in Figure 8 is obtained. In the second internal electrode layer 15A2 of the second raw sheet 1B, the second lead-out portion 15c2 is exposed on the side of the second end face 14b. In the second raw sheet 1B, at the corner portions at both ends in the width direction W on the side of the first end face 14a, the third dielectric ceramic layer 16C overlaps the second dielectric ceramic layer 16B, and only at this portion does it become three layers, that is, it becomes "thickness 3".

[0102] Next, as Figure 9As shown, the second raw material sheet 1B is superposed on the first raw material sheet 1A, and pressing is performed from both sides in the stacking direction T to obtain Figure 10 the laminated body model 11M1 shown. The laminated body 11 of the first embodiment described above is manufactured by superposing a large number of the first raw material sheets 1A and the second raw material sheets 1B. Here, the laminated body model formed by superposing two raw material sheets 1A and 1B is set as the laminated body model 11M1 of the first embodiment having a structure approximate to that of the laminated body 11. In this laminated body model 11M1, the corner portion of the "thickness 3" of the first raw material sheet 1A overlaps with the portion of the "thickness 2" of the second raw material sheet 1B, and the corner portion of the "thickness 3" of the second raw material sheet 1B overlaps with the portion of the "thickness 2" of the first raw material sheet 1A. As a result, "thickness 5" is formed at the four corners, and the other portions are "thickness 4".

[0103] In Figure 10 it, the same reference numerals are given to the portions corresponding to the first protrusions 31 in the laminated body 11 of the first embodiment.

[0104] When the laminated body 11 described above is manufactured in this way, first protrusions 31 are similarly formed at the four corners of each of the first main surface 12a and the second main surface 12b of the laminated body 11. Then, when a pair of external electrodes 20 are formed on such a laminated body 11, first convex portions 30 are formed.

[0105] In addition, the multilayer ceramic capacitor 10 is mounted on the substrate of a given device and used. At this time, it is preferable to place it on the substrate in a state where one of the first main surface 12a and the second main surface 12b faces the surface of the substrate, and then perform installation operations such as soldering. If one of the first main surface 12a and the second main surface 12b faces the surface of the substrate, a state is formed in which the first convex portions 30 at the four corners stand on the substrate, and it can be placed on the substrate in a stable posture. As a result, the installation operation can be carried out smoothly.

[0106] The multilayer ceramic capacitor 10 according to the first embodiment includes: a multilayer body 11 having a substantially rectangular parallelepiped shape, including a plurality of dielectric ceramic layers 16 and a plurality of internal electrode layers 15 alternately laminated in the lamination direction T, and having a first main surface 12a and a second main surface 12b opposite to each other in the lamination direction T, a first side surface 13a and a second side surface 13b opposite to each other in the width direction W orthogonal to the lamination direction T, and a first end surface 14a and a second end surface 14b opposite to each other in the length direction L orthogonal to the lamination direction T and the width direction W; and a pair of external electrodes 20 disposed at both ends in the length direction L of the multilayer body 11 so as to cover at least the first end surface 14a and the second end surface 14b respectively and connected to the internal electrode layer 15, and first convex portions 30 are formed at four corner portions of the surface on at least one of the first main surface 12a side and the second main surface 12b side of the substantially rectangular shape.

[0107] Thus, when the multilayer ceramic capacitor 10 is mounted on a substrate, by placing the first convex portions 30 at the four corners of the first main surface 12a or the second main surface 12b on the substrate, a stable posture can be maintained during mounting. For example, if the thickness in the lamination direction T at the central portion in the length direction L is the largest, the multilayer ceramic capacitor is likely to shake and the posture is unstable when the multilayer ceramic capacitor is placed on the substrate. However, according to the multilayer ceramic capacitor 10 of the first embodiment, as long as it is placed on the substrate by using the first convex portions 30 at the four corners, the posture will be stable.

[0108] (Second Embodiment)

[0109] Next, refer to Figures 11 to 20 The second embodiment will be described. The basic structure of the second embodiment is the same as that of the first embodiment described above, but the shape of specific constituent elements is partially different. Therefore, the same reference numerals are assigned to the constituent elements common to the first embodiment and the description thereof is omitted or simplified, and the description will be centered on the differences from the first embodiment and the parts related to the differences.

[0110] Figure 11 is a schematic perspective view of the multilayer ceramic capacitor 10 according to the second embodiment. Figure 12 is along Figure 11 The cross-sectional view taken along line XII-XII shown. Figure 13 is along Figure 11 The cross-sectional view taken along line XIII-XIII shown. Figure 14 is along Figure 12 The cross-sectional view taken along line XIV-XIV shown.

[0111] In the multilayer ceramic capacitor 10 of the second embodiment, as shown in Figures 12 to 14As shown, the dielectric ceramic layer 16 has a pair of first peripheral portions 18a and a pair of second peripheral portions 18b.

[0112] The first peripheral portion 18a is a portion between a first edge portion 15d1 in the first internal electrode layer 15A1 and a first edge portion 15d1 in the second internal electrode layer 15A2 that are adjacent and opposed to each other in the stacking direction T. The first peripheral portion 18a extends in the length direction L.

[0113] The second peripheral portion 18b is a portion between a second edge portion 15d2 in the first internal electrode layer 15A1 and a second edge portion 15d2 in the second internal electrode layer 15A2 that are adjacent and opposed to each other in the stacking direction T. The second peripheral portion 18b extends in the width direction W. The dielectric ceramic layer 16 has a rectangular central region 18c surrounded by the first peripheral portion 18a and the second peripheral portion 18b.

[0114] Furthermore, the dielectric ceramic layer 16 includes four crossing portions 18d where the first peripheral portion 18a and the second peripheral portion 18b cross.

[0115] The central region 18c of the dielectric ceramic layer 16 is generally the region of the first dielectric ceramic layer 16A. The thicknesses of the first peripheral portion 18a and the second peripheral portion 18b are thicker than the thickness of the central region 18c. The thickness of the first peripheral portion 18a and the thickness of the second peripheral portion 18b are substantially the same. In addition, the thickness of the dielectric ceramic layer 16 at each crossing portion 18d is thicker than the thicknesses of the first peripheral portion 18a and the second peripheral portion 18b.

[0116] For example, in the case of finally press-molding the laminate 11, the first edge portion 15d1 and the second edge portion 15d2 of the internal electrode layer 15 are particularly likely to be deformed, and the adjacent internal electrode layers 15 in this portion may come into contact with each other in the stacking direction T and short-circuit. Therefore, by making the first peripheral portion 18a and the second peripheral portion 18b in the dielectric ceramic layer 16 thicker than the central region 18c as in the second embodiment, the first internal electrode layer 15A1 and the second internal electrode layer 15A2 adjacent to each other in the stacking direction T are less likely to come into contact with each other, and short-circuit can be suppressed.

[0117] In addition, the corner portions at the four corners of the internal electrode layer 15 are more likely to be deformed than the first edge portion 15d1 and the second edge portion 15d2 during press-molding, and short-circuit is more likely to occur. However, by making the thickness of each crossing portion 18d of the dielectric ceramic layer 16 corresponding to the corner portion of the internal electrode layer 15 thicker than the thicknesses of the first peripheral portion 18a and the second peripheral portion 18b as in the second embodiment, the contact of the adjacent internal electrode layers 15 in the stacking direction T can be further suppressed, and short-circuit can be further suppressed.

[0118] As Figures 11 to 13As shown, the first main surface 12a of the laminate 11 has a pair of first linear protrusions 19a extending in the length direction L, and the second main surface 12b has a pair of second linear protrusions 19b extending in the width direction W. The pair of first linear protrusions 19a are formed by laminating a plurality of first peripheral portions 18a, so that the dielectric ceramic layer 16 bulges out on the first main surface 12a. The pair of second linear protrusions 19b are formed by laminating a plurality of second peripheral portions 18b, so that the dielectric ceramic layer 16 bulges out on the second main surface 12b.

[0119] Furthermore, the first main surface 12a and the second main surface of the laminate 11 each have four second protrusions 35. The four second protrusions 35 are formed by laminating the intersecting portions 18d of the dielectric ceramic layer 16, so as to bulge out on the first main surface 12a and the second main surface respectively. The intersecting portion 18d is thicker than the first peripheral portion 18a and the second peripheral portion 18b, so the height of the second protrusion 35 is higher than the height of the first linear protrusion 19a and the second linear protrusion 19b.

[0120] In the laminated ceramic capacitor 10 of the second embodiment, four first convex portions 30 of the first embodiment are respectively formed on the surfaces on the first main surface 12a side and the second main surface 12b side of the external electrode 20. In addition, four second convex portions 36 are formed. The second convex portions added in the second embodiment are respectively close to the first convex portions 30 formed at the four corners and are formed inside the first convex portions 30, that is, at positions closer to the centers of the first main surface 12a and the second main surface 12b. Therefore, each second convex portion 36 is also disposed at the four corner portions of the first main surface 12a and the second main surface 12b.

[0121] The second convex portions 36 of the second embodiment are respectively formed in the lamination direction T at portions corresponding to the four second protrusions 35. These four second convex portions 36 are formed by covering each second protrusion 35 with the external electrode 20. The heights of the four second convex portions 36 are substantially the same and are higher than the height of the first convex portion 30. Therefore, the height of the second convex portion 36 is the highest on each of the surfaces on the first main surface 12a side and the second main surface 12b side.

[0122] For example, Figures 15 to 20 As a result of the manufacturing process shown, the second protrusions 35 of the laminate 11 can be formed.

[0123] Hereinafter, the principle of forming the second protrusions 35 by this manufacturing process will be described. In addition, for easy understanding, Figures 15 to 20 the manufacturing process of one laminate 11 is modeled and shown. Actually, a plurality of laminates 11 are manufactured uniformly. In Figures 15 to 18 、 Figure 20In the figure, the upper figure is a top view, and the figure below the top view is a cross-sectional view corresponding to the viewing section line shown in the upper top view.

[0124] In addition, in the following description, the thickness of one layer of each of the internal electrode layer 15 and the dielectric ceramic layer 16 is set to "1", and the thickness corresponding to the number of stacked layers is shown. For example, if the number of stacked layers is 2, it is "thickness 2", and if the number of stacked layers is 3, it is "thickness 3". In Figures 15 to 18 , Figure 20 the top view, the thickness of each part divided by a line is indicated by a circled number.

[0125] As Figure 15 shown, a single-layer dielectric ceramic layer 16 (thickness 1) that forms the base and includes the first dielectric ceramic layer 16A is formed, and the first internal electrode layer 15A1 (thickness 2) is stacked thereon. The first lead-out portion 15c1 of the first internal electrode layer 15A1 is exposed on the side of the first end face 14a. Next, as Figure 16 shown, on the upper surface of the dielectric ceramic layer 16 on the side of the second end face 14b where the first internal electrode layer 15A1 is not formed, the second dielectric ceramic layer 16B (thickness 2) is stacked over the entire length in the width direction W. At this time, a material such as ceramic paste for forming the second dielectric ceramic layer 16B is overlapped on the second edge portion 15d2 of the first internal electrode layer 15A1 with a given width. The overlapping portion 16f overlapping the second edge portion 15d2 becomes the above-described second peripheral portion 18b. Since the material is overlapped and coated on the second edge portion 15d2, the portion of the overlapping portion 16f becomes "thickness 3".

[0126] Next, as Figure 17 shown, on the upper surfaces of the dielectric ceramic layers 16 on both sides in the width direction W of the first internal electrode layer 15A1, the third dielectric ceramic layer 16C is stacked over the entire length in the length direction L, thereby obtaining the first raw material sheet 2A according to the second embodiment. At this time, a material such as ceramic paste for forming the third dielectric ceramic layer 16C is overlapped on the first edge portion 15d1 of the first internal electrode layer 15A1 with a given width. The overlapping portion 16g overlapping the first edge portion 15d1 becomes the above-described first peripheral portion 18a. Since the material is overlapped and coated on the first edge portion 15d1, the portion of the overlapping portion 16g becomes "thickness 3". Further, at both ends in the width direction W of the overlapping portion 16f having "thickness 3", the third dielectric ceramic layer 16C covers the second dielectric ceramic layer 16B, and thus a double overlapping portion 16h having "thickness 4" is formed.

[0127] Next, through the same process as Figures 15 to 17 , Figure 18The second raw material sheet 2B according to the second embodiment having the second internal electrode layer 15A2 as shown. In the second internal electrode layer 15A2 of the second raw material sheet 2B, the second lead-out portion 15c2 is exposed on the side of the second end face 14b. In the second raw material sheet 2B, at both ends in the width direction W of the overlapping portion 16f on the side of the first end face 14a, a double overlapping portion 16h with a "thickness 4" is formed where the third dielectric ceramic layer 16C covers the second dielectric ceramic layer 16B.

[0128] As a result, four double overlapping portions 16h with a "thickness 4" are formed, and these double overlapping portions 16h become the above-mentioned crossing portions 18d.

[0129] As indicated by the thickness number, Figure 17 the first raw material sheet 2A as shown and Figure 18 the second raw material sheet 2B as shown each have three thickness portions of "thickness 2", "thickness 3", and "thickness 4".

[0130] Next, as Figure 19 shown, the second raw material sheet 2B is superposed on the first raw material sheet 2A and pressed from both sides in the thickness direction, thereby obtaining Figure 20 the laminate model 11M2 of the second embodiment as shown.

[0131] As Figure 20 shown, in the laminate model M2 of the second embodiment, there are four thickness portions of "thickness 4", "thickness 5", "thickness 6", and "thickness 7". In Figure 20 , the same reference numerals are assigned to the portions corresponding to the first peripheral portion 18a and the first linear protrusion 19a formed by the lamination of the first peripheral portion 18a, the second peripheral portion 18b and the second linear protrusion 19b formed by the lamination of the second peripheral portion 18b, the crossing portion 18d, and the second protrusion 35 formed by the lamination of the crossing portion 18d in the laminate 11 of the second embodiment.

[0132] The portion corresponding to the first peripheral portion 18a and the first linear protrusion 19a formed by the lamination of the first peripheral portion 18a is "thickness 6". This is because the three layers of the base dielectric ceramic layer 16, the internal electrode layer 15, and the overlapping portion 16f of the third dielectric ceramic layer 16C of the first raw material sheet 2A and the second raw material sheet 2B are doubly overlapped, resulting in six layers.

[0133] The portion corresponding to the second peripheral portion 18b and the second linear protrusion 19b formed by laminating the second peripheral portion 18b is "thickness 5". This is because, on the overlapping portion 16f of the dielectric ceramic layer 16, the internal electrode layer 15, and the third dielectric ceramic layer 16C at the base of the first raw material sheet 2A, the dielectric ceramic layer 16 and the internal electrode layer 15 at the base of the second raw material sheet 2B are laminated, resulting in five layers.

[0134] The portion corresponding to the crossing portion 18d and the second protrusion 35 formed by laminating the crossing portion 18d is "thickness 7". This is because, on the four layers of the overlapping portion 16f where the dielectric ceramic layer 16, the internal electrode layer 15, and the third dielectric ceramic layer 16C of the base of the first raw material sheet 2A overlap the first edge portion 15d1, and the overlapping portion 16f where the second dielectric ceramic layer 16B overlaps the second edge portion 15d2, the dielectric ceramic layer 16, the internal electrode layer 15, and the overlapping portion 16f where the second dielectric ceramic layer 16B overlaps the second edge portion 15d2 of the base of the second raw material sheet 2B are laminated, resulting in seven layers.

[0135] When the laminate 11 of the second embodiment is manufactured in this way, second protrusions 35 are similarly formed at the four corners of each of the first main surface 12a and the second main surface 12b of the laminate 11. Then, when a pair of external electrodes 20 are formed on such a laminate 11, second convex portions 36 are formed.

[0136] According to the multilayer ceramic capacitor 10 of the second embodiment, by placing it on the substrate using the second convex portions 36 at the four corners on one main surface side of the first main surface 12a and the second main surface 12b, it is not easily shaken on the substrate and can be mounted in a stable posture.

[0137] In the multilayer ceramic capacitor 10 according to the second embodiment, the plurality of internal electrode layers 15 include a first internal electrode layer 15A1 and a second internal electrode layer 15A2 adjacent to each other in the stacking direction T. The first internal electrode layer 15A1 and the second internal electrode layer 15A2 each have an opposing portion 15b that opposes each other in the stacking direction T with a dielectric ceramic layer 16 interposed therebetween. The first internal electrode layer 15A1 has a first lead-out portion 15c1 that leads out from an end portion on the first end face 14a side of the opposing portion 15b to the first end face 14a. The second internal electrode layer 15A2 has a second lead-out portion 15c2 that leads out from an end portion on the second end face 14b side of the opposing portion 15b to the second end face 14b. The external electrodes 20 include: a first external electrode 20A disposed on the first end face 14a side and connected to the first lead-out portion 15c1; and a second external electrode 20B disposed on the second end face 14b side and connected to the second lead-out portion 15c2. The dielectric ceramic layer 16 includes: a plurality of first dielectric ceramic layers 16A disposed between the first internal electrode layer 15A1 and the second internal electrode layer 15A2; a second dielectric ceramic layer 16B disposed in a region where no internal electrode layer 15 is disposed between the first dielectric ceramic layers 16A that oppose each other across the internal electrode layer 15 and configured to overlap the first dielectric ceramic layer 16A in the stacking direction T; and third dielectric ceramic layers 16C respectively disposed on the first side face 13a and the second side face 13b of the stacked body 11. The stacked body 11 has: an inner layer portion 11A in which the first internal electrode layer 15A1 and the second internal electrode layer 15A2 are alternately stacked with the dielectric ceramic layer 16 interposed therebetween; and a pair of outer layer portions 11B disposed to sandwich the inner layer portion 11A in the stacking direction T and including a ceramic material. The internal electrode layer 15 includes: a pair of first edge portions 15d1 extending along the length direction L at both end portions in the width direction W; and a pair of second edge portions 15d2 extending along the width direction W at both end portions in the length direction L of the opposing portion 15b. The dielectric ceramic layer 16 has: a first peripheral portion 18a between a pair of first edge portions 15d1 that oppose each other in the stacking direction T; a second peripheral portion 18b between a pair of second edge portions 15d2 that oppose each other in the stacking direction T; and a central region 18c surrounded by the first peripheral portion 18a and the second peripheral portion 18b. The first peripheral portion 18a and the second peripheral portion 18b are thicker than the central region 18c.

[0138] Thereby, it is possible to suppress the contact between the internal electrode layers 15 at the first edge portions 15d1 and the second edge portions 15d2 and effectively suppress short circuits.

[0139] In the multilayer ceramic capacitor 10 of the second embodiment, the dielectric ceramic layer 16 includes an intersection portion 18d where a first peripheral portion 18a and a second peripheral portion 18b intersect. The thickness of the dielectric ceramic layer 16 at the intersection portion 18d is thicker than the thicknesses of the first peripheral portion 18a and the second peripheral portion 18b. A second convex portion 36 is formed at a portion corresponding to the intersection portion 18d in the stacking direction T on at least one of the first main surface 12a and the second main surface 12b.

[0140] Thereby, a short circuit of the internal electrode layer 15 can be further suppressed.

[0141] (Modification example)

[0142] Figure 21 And Figure 22 A modification example of the above-described first embodiment is shown. Figure 21 It is a schematic perspective view of the multilayer ceramic capacitor 10 of this modification example, Figure 22 is Figure 21 a cross-sectional view taken along line XXII-XXII of

[0143] In this modification example, as Figure 22 shown, both end portions of the laminate 11 in the length direction L on the first main surface 12a and the second main surface 12b respectively have raised portions 39 that bulge in the stacking direction T and extend along the width direction W. The first external electrode 20A and the second external electrode 20B that respectively cover the first end surface 14a and the second end surface 14b of both end portions in the length direction L where the raised portions 39 are formed cover the raised portions 39. Thereby, bulging portions 38 that extend along the width direction W are also respectively formed on the first main surface 12a side of the first external electrode 20A and the second main surface 12b side of the second external electrode 20B.

[0144] Thereby, even if moisture infiltrates into the boundary portion between the laminate 11 and the external electrode 20, the moisture is blocked by the raised portion 39, and contact with the internal electrode layer 15 exposed on the first end surface 14a and the second end surface 14b can be suppressed. In addition, due to the presence of the raised portion 39, the distance of the interface between the boundary portion between the laminate 11 and the external electrode 20 and the first end surface 14a and the second end surface 14b becomes longer. Thereby, intrusion of moisture can also be suppressed.

[0145] The present invention is not limited to the structure of the above-described embodiments, and can be appropriately modified and applied within the scope without changing the gist of the present invention.

[0146] For example, although the first convex portion 30 and the second convex portion 36 may be formed on both the first main surface 12a and the second main surface 12b, they may also be formed only on one side of these main surfaces. In this case, the main surface on which the first convex portion 30 and the second convex portion 36 are formed is opposed to the substrate, and the first convex portion 30 or the second convex portion 36 is brought into contact with the substrate to perform mounting.

[0147] The first convex portion 30 and the second convex portion 36 are not limited to being formed by the manufacturing method described in the embodiment, and may be formed by any method.

Claims

1. A multilayer ceramic capacitor, comprising: A stacked body having a substantially rectangular parallelepiped shape, including a plurality of dielectric ceramic layers and a plurality of internal electrode layers alternately stacked in a stacking direction, and having a first main surface and a second main surface opposite to each other in the stacking direction, a first side surface and a second side surface opposite to each other in a width direction orthogonal to the stacking direction, and a first end surface and a second end surface opposite to each other in a length direction orthogonal to the stacking direction and the width direction; and A pair of external electrodes disposed at both ends in the length direction of the stacked body so as to cover at least the first end surface and the second end surface respectively, and connected to the internal electrode layers, First convex portions are respectively formed at four corner portions of the surface on at least one of the first main surface side and the second main surface side of the substantially rectangular shape, The plurality of internal electrode layers include a first internal electrode layer and a second internal electrode layer adjacent to each other in the stacking direction, The first internal electrode layer and the second internal electrode layer respectively have opposing portions opposed to each other in the stacking direction with the dielectric ceramic layer interposed therebetween, The first internal electrode layer has a first lead-out portion led out from an end portion on the first end surface side of the opposing portion to the first end surface, The second internal electrode layer has a second lead-out portion led out from an end portion on the second end surface side of the opposing portion to the second end surface, The external electrode includes: A first external electrode disposed on the first end surface side and connected to the first lead-out portion; and A second external electrode disposed on the second end surface side and connected to the second lead-out portion, The dielectric ceramic layer includes: A plurality of first dielectric ceramic layers disposed between the first internal electrode layer and the second internal electrode layer; A second dielectric ceramic layer disposed in a region where no internal electrode layer is disposed between the first dielectric ceramic layers opposed to each other across the internal electrode layer, and disposed to overlap the first dielectric ceramic layer in the stacking direction; and A third dielectric ceramic layer respectively disposed on the first side surface and the second side surface of the stacked body, The stacked body has: An inner layer portion in which the first internal electrode layer and the second internal electrode layer are alternately stacked with the dielectric ceramic layer interposed therebetween; and A pair of outer layer portions disposed to sandwich the inner layer portion in the stacking direction and including a ceramic material, The internal electrode layer includes: A pair of first edge portions extending along the length direction at both ends in the width direction; and A pair of second edge portions extending along the width direction at both ends in the length direction of the opposing portion, The dielectric ceramic layer has: A first peripheral portion between a pair of the first edge portions opposed to each other in the stacking direction; A second peripheral portion between a pair of the second edge portions opposed to each other in the stacking direction; and A central region surrounded by the first peripheral portion and the second peripheral portion, The first peripheral portion and the second peripheral portion are thicker than the central region.

2. The multilayer ceramic capacitor according to claim 1, wherein, The dielectric ceramic layer includes an intersection portion where the first peripheral portion and the second peripheral portion intersect, the thickness of the dielectric ceramic layer at the intersection portion is thicker than the thicknesses of the first peripheral portion and the second peripheral portion, a second convex portion is formed at a portion corresponding to the intersection portion in the stacking direction on at least one of the first main surface and the second main surface.

3. The multilayer ceramic capacitor according to claim 1 or 2, wherein, both end portions of the multilayer body in the length direction of the first main surface and the second main surface respectively have raised portions that bulge in the stacking direction and extend along the width direction, the external electrodes cover the raised portions.

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