Method for filling asymmetric deep trenches

Abstract

The application provides a filling method of asymmetric deep-width-ratio trench, comprising the following steps: 1) forming an asymmetric deep trench on a substrate; 2) depositing a first isolation medium layer for the first time, and gradually closing the first isolation medium layer to form a first sealing opening on the asymmetric deep trench; 3) etching the first isolation medium layer until the first sealing opening is opened to form an opening with a width; 4) depositing a second isolation medium layer for the second time, and gradually closing the second isolation medium layer to form a second sealing opening on the asymmetric deep trench, wherein the height of the second sealing opening is lower than that of the first sealing opening; and 5) repeating the steps 3) and 4) to reduce the height of the final sealing opening to a target height. The application can effectively control the top sealing position of the pore by using the traditional isolation medium layer deposition and etching process technology, solves the problem of filling the asymmetric deep-width-ratio silicon trench which cannot be solved by using more advanced equipment, and greatly reduces the filling cost.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor design and manufacturing, and in particular relates to a method for filling asymmetric trenches with a large aspect ratio. Background Technology

[0002] The development trend of integrated circuits is towards shallow junctions, shallow steps, and advanced processes. Typically, the aspect ratio of silicon trenches is no greater than 2, and all silicon trenches are symmetrical. Asymmetric silicon trenches, especially "V"-shaped ones, require equipment below the 65nm node for filling, such as high aspect ratio process (HARP) equipment, cHARP process technology equipment, and flow chemical vapor deposition (FCVD) technology equipment. Currently, there is no effective method to control the position of the via tops for asymmetric, high aspect ratio silicon trenches.

[0003] Thick silicon processes in silicon photonics introduce silicon trenches with aspect ratios exceeding 10, requiring controllable top positions of the resulting vias. Traditional integrated circuit filling methods are no longer sufficient to solve the filling challenges faced by thick silicon photonics.

[0004] It should be noted that the above introduction to the technical background is only for the purpose of providing a clear and complete explanation of the technical solutions of this application and facilitating understanding by those skilled in the art. It should not be assumed that these technical solutions are known to those skilled in the art simply because they have been described in the background section of this application. Summary of the Invention

[0005] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide a method for filling asymmetric trenches with a large aspect ratio, in order to solve the problem that the top position of the asymmetric silicon trench apertures with a large aspect ratio is difficult to control in the prior art.

[0006] To achieve the above and other related objectives, the present invention provides a method for filling asymmetric trenches with a large aspect ratio. The method includes: 1) providing a substrate and etching deep trenches in the substrate, etching the substrate such that the height of the substrate on a first side of the deep trench is less than the height of the substrate on a second side of the deep trench, thereby forming an asymmetric deep trench; 2) depositing a first isolation medium layer in the asymmetric deep trench and on the surface of the substrate for the first time, wherein as the first isolation medium layer grows, the first isolation medium layer gradually closes above the opening of the asymmetric deep trench to form a first seal; 3) etching the first isolation medium layer to gradually thin the first isolation medium layer until the first seal is opened, forming an opening with a width; 4) depositing a second isolation medium layer in the asymmetric deep trench and on the surface of the substrate for the second time, wherein as the second isolation medium layer grows, the second isolation medium layer gradually closes above the opening of the asymmetric deep trench to form a second seal, the height of the second seal being lower than the height of the first seal; 5) repeating steps 3) and 4) to reduce the final seal height of the isolation medium layer above the asymmetric deep trench to a target height.

[0007] Optionally, in step 2), the deposition thickness of the first isolation medium layer is 80% to 150% of the width of the asymmetric deep trench.

[0008] Optionally, in step 3), the thickness of the first isolation medium layer is thinned by corrosion to 30-70% of the deposition thickness of the first isolation medium layer, and the width of the opening after corrosion is 0.2 micrometers to 0.4 micrometers.

[0009] Optionally, the second isolation medium layer deposited in step 4) is 50% to 80% of the thickness of the first isolation medium layer.

[0010] Optionally, when repeating steps 3) and 4), the thickness of the isolation medium layer increased by the current deposition is less than the thickness of the isolation medium layer increased by the previous deposition, and the thickness of the isolation medium layer increased by the current deposition is 50% to 80% of the thickness of the isolation medium layer increased by the previous deposition.

[0011] Optionally, when repeating steps 3) and 4), the thickness of the isolation medium layer that is currently thinned by corrosion is greater than or equal to the thickness of the isolation medium layer that is deposited in the previous step, and the thickness of the isolation medium layer that is currently thinned by corrosion is 100% to 150% of the thickness of the isolation medium layer that is deposited in the previous step.

[0012] Optionally, the aspect ratio of the deep trench in step 1) is greater than or equal to 10.

[0013] Optionally, in step 5), during the final sealing of the isolation medium layer, the asymmetric deep trench contains pores sealed by the sealing, and the final sealing height of the isolation medium layer above the asymmetric deep trench is lower than the height of the top surface of the substrate on the second side of the deep trench.

[0014] Optionally, the material of the isolation dielectric layer includes one of silicon dioxide, silicon nitride, and silicon oxynitride, and the method of etching the isolation dielectric layer in steps 3) and 5) includes one of wet etching process and isotropic dry etching process.

[0015] Optionally, the material of the isolation dielectric layer includes one of amorphous silicon and polycrystalline silicon. Before etching the isolation dielectric layer in steps 3) and 5), the method further includes a step of thermally oxidizing the amorphous silicon or polycrystalline silicon to form silicon dioxide. The method of etching the silicon dioxide includes one of wet etching process and isotropic dry etching process.

[0016] As described above, the filling method for asymmetric trenches with a large aspect ratio of the present invention has the following beneficial effects:

[0017] The filling method for asymmetric trenches with large aspect ratios of the present invention can effectively control the top sealing position of the filled pores, solving the problem of filling thick silicon optoelectronic isolation trenches, especially solving the problem of filling asymmetric trenches with large aspect ratios of depth. It can be widely used in products similar to silicon photonics technology, and can be extended to the production of special process products of integrated circuits and the process research and development of MEMS products, with broad application prospects.

[0018] This invention can effectively control the top sealing position of the pores by using only traditional isolation dielectric layer deposition and etching processes, solving the problem of asymmetric large aspect ratio silicon trench filling that cannot be solved even with more advanced equipment, while greatly reducing filling costs. Attached Figure Description

[0019] The accompanying drawings, which form part of this specification, are used to provide a further understanding of the embodiments of this application and to illustrate the implementation of this application, together with the textual description, to explain the principles of this application. Obviously, the drawings described below are merely some embodiments of this application.

[0020] Figures 1-5 The diagram shows the structural schematics of each step in the filling method for asymmetric trenches with a large aspect ratio according to an embodiment of the present invention.

[0021] Component designation explanation

[0022] 10 Asymmetric deep trenches

[0023] 101 The first side of the asymmetric deep trench

[0024] 102 The second side of the asymmetric deep trench

[0025] 11 First isolation medium layer

[0026] 111 First Sealing

[0027] 112 Opening

[0028] 113 Second sealing

[0029] 21 Base Detailed Implementation

[0030] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0031] It should be emphasized that the term "including / comprises" as used herein refers to the presence of a feature, whole, step, or component, but does not exclude the presence or addition of one or more other features, wholes, steps, or components.

[0032] Features described and / or illustrated for one embodiment may be used in the same or similar manner in one or more other embodiments, combined with features in other embodiments, or substituted for features in other embodiments.

[0033] In the detailed description of embodiments of the present invention, for ease of explanation, the cross-sectional views illustrating the device structure may be partially enlarged and not to scale. Furthermore, the schematic diagrams are merely examples and should not limit the scope of protection of the present invention. In actual fabrication, the three-dimensional spatial dimensions of length, width, and depth should be included.

[0034] For ease of description, spatial relation terms such as “below,” “under,” “lower than,” “below,” “above,” and “upper” may be used herein to describe the relationship between one element or feature shown in the accompanying drawings and other elements or features. It will be understood that these spatial relation terms are intended to include directions other than those depicted in the drawings for devices in use or operation. Furthermore, when a layer is referred to as being “between” two layers, it may be the only layer between the two layers, or there may be one or more layers in between.

[0035] In the context of this application, the structure described above the first feature may include embodiments in which the first and second features are formed in direct contact, or embodiments in which additional features are formed between the first and second features, such that the first and second features may not be in direct contact.

[0036] It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the illustrations only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0037] Example 1

[0038] like Figures 1-5 As shown, this embodiment provides a method for filling asymmetric trenches with a large aspect ratio. The filling method includes the following steps:

[0039] like Figures 1-2 As shown, step 1) is performed first, a substrate 21 is provided, and deep trenches are etched in the substrate 21. The substrate 21 is etched so that the height of the substrate 21 on the first side 101 of the deep trench is less than the height of the substrate 21 on the second side 102 of the deep trench, so as to form an asymmetric deep trench 10.

[0040] In one embodiment, the substrate 21 may be a silicon substrate 21. Of course, in other embodiments, the substrate 21 may also be a germanium substrate 21, a germanium-silicon substrate 21, a III-V compound semiconductor substrate 21, a silicon carbide substrate 21, etc.

[0041] In one embodiment, a deep trench is first etched into the substrate 21 using a first photolithography-etching step. The aspect ratio of the deep trench is greater than or equal to 10; for example, the aspect ratio can be 10, 12, 15, etc. Then, a second photolithography-etching process is used to etch the substrate 21 on the first side 101 of the deep trench, making the height of the substrate 21 on the first side 101 of the deep trench less than the height of the substrate 21 on the second side 102 of the deep trench, thereby forming an asymmetric deep trench 10. Figure 2 As shown.

[0042] In one embodiment, the height of the substrate 21 on the first side 101 of the deep trench may be 0.1 to 100 micrometers smaller than the height of the substrate 21 on the second side 102 of the deep trench. For example, the height of the substrate 21 on the first side 101 of the deep trench may be 0.2 micrometers or 0.5 micrometers smaller than the height of the substrate 21 on the second side 102 of the deep trench. In other embodiments, the difference between the height of the substrate 21 on the first side 101 of the deep trench and the height of the substrate 21 on the second side 102 of the deep trench may be set according to different substrate 21 thicknesses and device requirements, and is not limited to the examples listed herein.

[0043] like Figure 3 As shown, then step 2) is performed, in which a first isolation medium layer 11 is deposited for the first time in the asymmetric deep trench 10 and on the surface of the substrate 21. As the first isolation medium layer 11 grows, the first isolation medium layer 11 gradually closes above the opening of the asymmetric deep trench 10 to form a first seal 111.

[0044] In one embodiment, the deposition thickness of the first isolation medium layer 11 is 80% to 150% of the width of the asymmetric deep trench 10. For example, the deposition thickness of the first isolation medium layer 11 can be 100% or 120% of the width of the asymmetric deep trench 10, etc.

[0045] In one specific implementation, the deposition thickness of the first isolation medium layer 11 is the same as the isolation medium layer thickness when the asymmetric deep trench 10 is just completely sealed, so as to save the material and deposition cost of the isolation medium layer, and at the same time save the subsequent corrosion cost.

[0046] Specifically, the first isolation dielectric layer 11 is formed on the bottom and sidewalls of the asymmetric deep trench 10, as well as on the surface of the substrate 21. At the same time, the first isolation dielectric layer 11 will also grow laterally, so that as its deposition thickness gradually increases, a first seal 111 is gradually formed above the opening of the asymmetric deep trench 10. The first seal 111 may be located above the top surface of the substrate 21, which may make subsequent processes difficult or cause the first seal 111 to be damaged, seriously affecting the process progress and device performance. Therefore, it is necessary to lower it below the top surface of the substrate 21.

[0047] like Figure 4 As shown, step 3) is then performed, which involves corroding the first isolation medium layer 11 to gradually thin the first isolation medium layer 11 until the first seal 111 is opened, forming an opening 112 with a width.

[0048] In one embodiment, the corrosion thins the thickness of the first isolation medium layer 11 to 30-70% of the deposited thickness of the first isolation medium layer 11, for example, 50%. The width of the opening 112 after corrosion is 0.2 micrometers to 0.4 micrometers.

[0049] In one embodiment, the material of the isolation dielectric layer includes one of silicon dioxide, silicon nitride, and silicon oxynitride, and the method of etching the first isolation dielectric layer 11 includes one of wet etching process and isotropic dry etching process.

[0050] like Figure 5 As shown, step 4) is then performed, in which a second isolation medium layer is deposited for the second time in the asymmetric deep trench 10 and on the surface of the substrate 21. As the second isolation medium layer grows, the second isolation medium layer gradually closes above the opening of the asymmetric deep trench 10 to form a second seal 113. The height of the second seal 113 is lower than the height of the first seal 111.

[0051] In one embodiment, the second isolation medium layer deposited in step 4) is 50% to 80% of the thickness of the first isolation medium layer 11. Preferably, the deposition thickness of the second isolation medium layer is the additional isolation medium layer thickness required when the asymmetric deep trench 10 is completely sealed. Since the asymmetric deep trench 10 itself retains the first isolation medium layer 11, the lateral growth rate of the second isolation medium layer during growth is greater than the lateral growth rate of the first isolation medium layer 11. Ultimately, the second isolation medium layer gradually closes above the opening of the asymmetric deep trench 10 to form a second seal 113, and the height of the second seal 113 is lower than the height of the first seal 111.

[0052] Finally, proceed to step 5), repeating steps 3) and 4) to reduce the final sealing height of the isolation medium layer above the asymmetric deep trench 10 to the target height. It should be noted that steps 3) and 4) can be repeated 0 to 10 times. If the sealing position meets the requirements after steps 3) and 4), then steps 3) and 4) do not need to be repeated.

[0053] In one embodiment, when steps 3) and 4) are repeated, the thickness of the current deposition of the isolation medium layer is less than the thickness of the previous deposition of the isolation medium layer. The thickness of the current deposition of the isolation medium layer is 50% to 80% of the thickness of the previous deposition of the isolation medium layer, for example, it can be 60%, 70%, etc.

[0054] In one embodiment, when steps 3) and 4) are repeated, the thickness of the isolation medium layer that is currently thinned by corrosion is greater than or equal to the thickness of the isolation medium layer that is deposited in the previous step. The thickness of the isolation medium layer that is currently thinned by corrosion is 100% to 150% of the thickness of the isolation medium layer that is deposited in the previous step, for example, it can be 120%, 130%, 140%, etc.

[0055] In one embodiment, during step 5) of the final sealing of the isolation medium layer, the asymmetric deep trench 10 contains pores sealed by the sealing, and the final sealing height of the isolation medium layer above the asymmetric deep trench 10 is lower than the top surface height of the substrate 21 on the second side 102 of the deep trench. For example, the final sealing height can be located between the top surface of the substrate 21 on the second side 102 of the deep trench and the top surface of the substrate 21 on the first side 101, or even below the top surface of the substrate 21 on the first side 101 of the deep trench.

[0056] In one embodiment, the material of the above-mentioned isolation dielectric layer includes one of silicon dioxide, silicon nitride and silicon oxynitride, and the method of etching the isolation dielectric layer in step 5) includes one of wet etching process and isotropic dry etching process.

[0057] The filling method for asymmetric trenches with large aspect ratios of the present invention can effectively control the top sealing position of the filled pores, solving the problem of filling thick silicon optoelectronic isolation trenches, especially solving the problem of filling asymmetric trenches with large aspect ratios of depth. It can be widely used in products similar to silicon photonics technology, and can be extended to the production of special process products of integrated circuits and the process research and development of MEMS products, with broad application prospects.

[0058] Example 2

[0059] This embodiment provides a method for filling asymmetric trenches with a large aspect ratio. The basic steps are the same as in Embodiment 1, except that the material of the insulating dielectric layer includes either amorphous silicon or polycrystalline silicon. Before etching the insulating dielectric layer in steps 3) and 5), the method further includes thermally oxidizing the amorphous silicon or polycrystalline silicon to form silicon dioxide. The method for etching the silicon dioxide includes either a wet etching process or an isotropic dry etching process. This embodiment can further expand the types of insulating dielectric layers, thereby further increasing the application scope of the method for filling asymmetric trenches with a large aspect ratio.

[0060] As described above, the filling method for asymmetric trenches with a large aspect ratio of the present invention has the following beneficial effects:

[0061] The filling method for asymmetric trenches with large aspect ratios of the present invention can effectively control the top sealing position of the filled pores, solving the problem of filling thick silicon optoelectronic isolation trenches, especially solving the problem of filling asymmetric trenches with large aspect ratios of depth. It can be widely used in products similar to silicon photonics technology, and can be extended to the production of special process products of integrated circuits and the process research and development of MEMS products, with broad application prospects.

[0062] This invention can effectively control the top sealing position of the pores by using only traditional isolation dielectric layer deposition and etching processes, solving the problem of asymmetric large aspect ratio silicon trench filling that cannot be solved even with more advanced equipment, while greatly reducing filling costs.

[0063] Therefore, this invention effectively overcomes the various shortcomings of the prior art and has high industrial application value.

[0064] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A method of filling asymmetric large aspect ratio trenches, characterized by, The filling method comprises: 1) providing a substrate, etching a deep trench in the substrate, etching the substrate to make the height of the substrate on the first side of the deep trench less than the height of the substrate on the second side of the deep trench to form an asymmetric deep trench; wherein the aspect ratio of the deep trench is greater than or equal to 10; 2) depositing a first isolation medium layer in the asymmetric deep trench and on the surface of the substrate for the first time, as the first isolation medium layer grows, the first isolation medium layer gradually closes the opening of the asymmetric deep trench to form a first seal; 3) etching the first isolation medium layer to gradually thin the first isolation medium layer until the first seal is opened to form an opening with a width; 4) depositing a second isolation medium layer in the asymmetric deep trench and on the surface of the substrate for the second time, as the second isolation medium layer grows, the second isolation medium layer gradually closes the opening of the asymmetric deep trench to form a second seal, the height of the second seal is lower than the height of the first seal; 5) repeating steps 3) and 4) to reduce the final seal height of the isolation medium layer above the asymmetric deep trench to a target height, when the final seal of the isolation medium layer is formed, the asymmetric deep trench contains a pore sealed by the seal, and the final seal height of the isolation medium layer above the asymmetric deep trench is lower than the height of the top surface of the substrate on the second side of the deep trench.

2. The method of claim 1, wherein: The deposition thickness of the first isolation medium layer in step 2) is 80% to 150% of the width of the asymmetric deep trench.

3. The method of claim 1, wherein: The thickness of the first isolation medium layer thinned by etching in step 3) is 30% to 70% of the deposition thickness of the first isolation medium layer, and the width of the opening after etching is 0.2 microns to 0.4 microns.

4. The method of claim 1, wherein: The deposition thickness of the second isolation medium layer in step 4) is 50% to 80% of the thickness of the first isolation medium layer.

5. The method of claim 1, wherein: When steps 3) and 4) are repeated, the thickness of the current deposition of the increased isolation medium layer is less than the thickness of the last deposition of the increased isolation medium layer, and the thickness of the current deposition of the increased isolation medium layer is 50% to 80% of the thickness of the last deposition of the increased isolation medium layer.

6. The method of claim 1, wherein: When steps 3) and 4) are repeated, the thickness of the current etching-thinned isolation medium layer is greater than or equal to the thickness of the last deposition of the increased isolation medium layer, and the thickness of the current etching-thinned isolation medium layer is 100% to 150% of the thickness of the last deposition of the increased isolation medium layer.

7. The method of claim 1, wherein: The material of the isolation medium layer includes one of silicon dioxide, silicon nitride and silicon oxynitride, and the method of etching the isolation medium layer in steps 3) and 5) includes one of a wet etching process and an isotropic dry etching process.

8. The method of claim 1, wherein: The material of the isolation medium layer includes one of amorphous silicon and polycrystalline silicon, and before etching the isolation medium layer in steps 3) and 5), a step of heat-oxidizing the amorphous silicon or polycrystalline silicon to form silicon dioxide is further included, and the method of etching the silicon dioxide includes one of a wet etching process and an isotropic dry etching process.

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