Delay-locked loop circuit and method of measuring delay of delay-locked loop circuit

Abstract

The present application provides a delay-locked loop circuit and a method for measuring the delay of the delay-locked loop circuit. A delay-locked loop (DLL) circuit is introduced, which includes a delay line, a pattern injection circuit, a pattern detection circuit and a counter. The delay line can align the phase of a reference clock signal with the phase of a feedback clock signal. The pattern injection circuit injects a predetermined pattern into the reference clock signal to generate an injected reference clock signal and asserts the injected reference clock signal to the delay line. The pattern detection circuit detects the predetermined pattern in the feedback clock signal. The counter determines the delay of the delay-locked loop circuit according to a first timing when the injected reference clock signal is asserted to the delay line and a second timing when the predetermined pattern is detected in the feedback clock signal. A method for measuring the delay of the DLL circuit is also introduced.

Description

Technical Field

[0001] This disclosure relates to a delay-locked loop circuit, and more particularly to a delay-locked loop circuit and a method for measuring the delay of the delay-locked loop circuit. Background Technology

[0002] A delay-locked loop (DLL) circuit is used to provide phase alignment between an input reference clock and a clock originating from the DLL output and typically fed back to the DLL feedback clock input via a feedback path external to the DLL. The DLL output driving the feedback path is a controlled buffered version of the input reference clock, and the DLL circuit operates by adjusting the delay of a buffer (DLL delay line) inside the DLL until phase alignment is achieved at the DLL input.

[0003] In electronic devices that include DLL circuits, such as memory, a critical parameter that must be measured is the delay around the DLL circuit. This delay is typically designed to match the delay of components in the signal path from the memory chip edge to the memory array. Using DLL circuits, these delays can be essentially eliminated, and phase alignment can be provided between desired points in the system. Accurately determining the delay of the DLL is important for tuning memory operation. Summary of the Invention

[0004] This disclosure describes a delay-locked loop (DLL) circuit and a method for accurately measuring the delay around the DLL circuit.

[0005] In some embodiments, the DLL circuit includes a delay line, a pattern injection circuit, a pattern detection circuit, and a counter. The delay line is configured to align the phase of a reference clock signal with the phase of a feedback clock signal. The pattern injection circuit is coupled to the delay line and configured to inject a predetermined pattern into the reference clock signal to generate an injected reference clock signal. The pattern injection circuit may assert the injected reference clock signal onto the delay line. The pattern detection circuit is coupled to the delay line and configured to detect the predetermined pattern in the feedback clock signal. The counter is coupled to the pattern detection circuit and configured to determine the delay of the delay-locked loop circuit based on a first timing when the injected reference clock signal is asserted onto the delay line and a second timing when the predetermined pattern is detected in the feedback clock signal.

[0006] In some embodiments, the method for measuring the delay of a DLL circuit includes the following steps: setting a reference clock signal to a delay line of the delay-locked loop circuit, wherein the delay line is configured to align the phase of the reference clock signal with the phase of a feedback clock signal; injecting a predetermined pattern into the reference clock signal to generate an injected reference clock signal; setting the injected reference clock signal to the delay line; detecting the predetermined pattern in the feedback clock signal; and determining the delay of the delay-locked loop circuit based on a first timing when the injected reference clock signal is set to the delay line and a second timing when the predetermined pattern is detected in the feedback clock signal.

[0007] According to embodiments of this disclosure, DLL delay measurement can be performed after the delay line is calibrated and the DLL circuit is locked. This ensures that the measured DLL reflects the delay observed during normal operation of the DLL circuit, achieving a highly accurate DLL delay measurement. Furthermore, since the DLL delay measurement is performed based on injecting a predetermined pattern into a reference clock signal and detecting the predetermined pattern in the feedback clock signal, the measurement can be performed at any time without disrupting the system environment. Attached Figure Description

[0008] Figure 1 A schematic diagram of a delay-locked loop (DLL) circuit according to some embodiments is shown;

[0009] Figure 2A and Figure 2B A timing diagram of signals in a DLL circuit according to some embodiments is shown;

[0010] Figure 3A and Figure 3B A schematic diagram of a pattern injection circuit for a DLL circuit according to some embodiments is shown;

[0011] Figures 4A to 4E A schematic diagram of a pattern detection circuit according to some embodiments and a timing diagram of signals in the pattern detection circuit are shown.

[0012] Figure 5 A schematic diagram of a counter based on a DLL circuit according to some embodiments is shown;

[0013] Figure 6 A schematic diagram of a DLL circuit according to some alternative embodiments is shown;

[0014] Figure 7 A flowchart illustrating a method for measuring the delay of a DLL circuit according to some embodiments is shown. Detailed Implementation

[0015] The preferred embodiments of the present invention will now be described in detail with reference to the accompanying drawings, examples of which are illustrated. Wherever possible, the same reference numerals are used in the drawings and description to refer to the same or similar parts.

[0016] Figure 1 A schematic diagram of a DLL circuit 100 according to some embodiments of the present disclosure is shown. The DLL circuit 100 may include a pattern injection circuit 110, a delay line 120, a pattern detection circuit 130, a counter 140, and a feedback path 150. The pattern injection circuit 110 receives a reference clock signal REF and a reset signal RST and is configured to inject a predetermined pattern (also referred to as a bubble) into the reference clock signal REF when the reset signal RST is set, to generate an injected reference clock signal REF_P. In other words, the reset signal RST is used to trigger the pattern injection circuit 110 to inject the predetermined pattern into the reference clock signal REF. In some embodiments, the pattern injection circuit 110 may inject the predetermined pattern into the reference clock signal REF by adjusting at least one clock pulse of the reference clock signal REF. In an example, the predetermined pattern may include the addition of at least one clock pulse to the reference clock signal REF, wherein the addition of the at least one clock pulse refers to maintaining the reference clock signal REF in a first logic state (i.e., a high logic state) for at least one clock cycle of the reference clock signal REF. In another example, the predetermined pattern may include the absence of at least one clock pulse in the reference clock signal REF, wherein the absence of at least one clock pulse refers to maintaining the reference clock signal REF in a second logic state (i.e., a low logic state) for at least one clock cycle of the reference clock signal REF. When the predetermined pattern includes the absence of multiple clock pulses in multiple clock cycles of the reference clock signal REF, the clock cycles may be sequential or non-sequential clock cycles in the reference clock signal REF. These more complex patterns can be used for various purposes, such as eliminating the effects of noise, distorted signals, or other destructive effects. It should be understood that this disclosure is not intended to limit the definition of the predetermined pattern. Any pattern that can be injected into the reference clock signal and detected from the feedback clock signal falls within the scope of this disclosure.

[0017] In some embodiments, when the reset signal RST is set to the pattern injection circuit 110 (i.e., when the reset signal RST is in the first logic state), the pattern injection circuit 110 injects a predetermined pattern into the reference clock signal REF to generate an injected reference clock signal REF_P and outputs the injected reference clock signal REF_P to the delay line 120. When the reset signal RST is not set to the pattern injection circuit 110 (i.e., when the reset signal RST is in the second logic state), the pattern injection circuit 110 does not inject the predetermined pattern into the reference clock signal REF and outputs the reference clock signal REF to the delay line 120.

[0018] Delay line 120 is coupled to pattern injection circuit 110 to receive an input signal (i.e., a reference clock signal REF or an injected reference clock signal REF_P) from pattern injection circuit 110. Delay line 120 may include at least one delay element circuitry (not shown) configured to delay the input signal propagating through delay line 120 to generate an output signal OUT. In some embodiments, the delay element circuitry of delay line 120 may be controlled to align the phase of the input signal with the phase of a feedback clock signal FB transmitted from the output signal OUT. Feedback path 150 is coupled to delay line 120 and configured to generate a feedback clock signal FB based on the output signal OUT of delay line 120. It should be noted that this disclosure is not intended to limit the circuit structure of feedback path 150, and therefore any circuit with feedback signal functionality falls within the scope of feedback path 150. In some embodiments, the DLL circuit 100 may include circuitry (not shown) for comparing the phase of the feedback clock signal FB with the phase of the input signal to generate a phase error signal and for controlling the delay line 120 to align the phase of the input signal with the phase of the feedback clock signal FB based on the phase error signal. When the phase of the input signal is aligned with the phase of the feedback clock signal FB, the DLL circuit 100 is in a locked state. It should be understood that the components of the DLL circuit 100 may vary depending on design requirements; and the DLL circuit 100 may include more or fewer components. Figure 1 The circuit shown.

[0019] In this example, when the reference clock signal REF is input to the delay line 120, the DLL circuit 100 can control the delay line 120 to align the phase of the reference clock signal REF with the phase of the feedback clock signal FB. When the injected reference clock signal REF_P is input to the delay line 120 while the DLL circuit 100 is in a locked state, the DLL circuit 100 remains in a locked state even when a predetermined pattern exists in the injected reference clock signal REF_P. In other words, the predetermined pattern included in the injected reference clock signal REF_P can propagate through the delay line 120 during the locked state of the DLL circuit 100. In this way, based on the injection and detection of the predetermined pattern, the delay around the DLL circuit 100 can be measured during the locked state of the DLL circuit 100. The measurement of the delay around the DLL circuit 100 in the locked state is only illustrated by way of example, and this disclosure is not limited thereto. The delay around the DLL circuit 100 can be measured at any time after the phase of the reference clock signal REF is aligned with the phase of the feedback clock signal FB. This alignment can occur during the locking process. After the locking process, the DLL circuit 100 can be placed in a freeze mode in which all updates to the delay line 120 of the DLL circuit 100 are suspended. In this freeze mode, the delay around the DLL circuit 100 can be measured. Alternatively, the DLL circuit 100 can have a manual override mode that forces clock alignment between the reference clock signal REF and the feedback clock signal FB, and the delay around the DLL circuit 100 can also be measured in this manual override mode. In other words, delay measurement can be performed either conventionally when the DLL is locked, or at any time when clock alignment between the reference clock signal REF and the feedback clock signal FB is provided.

[0020] In some embodiments, the DLL circuit 100 may further include delay lines other than delay line 120. Delay line 120 may be a dedicated delay line calibrated to provide alignment of clock signals REF and FB, and this delay line can be used for delay measurements of the DLL circuit 100. Control settings for this calibrated dedicated delay line can be shared with other delay lines, and these other delay lines can be used to send clocks and commands to the system. In other words, the dedicated delay line (i.e., delay line 120) can be used to align clock signals and measure delays around the DLL circuit 100, and the other delay lines (i.e., duplicate delay lines) can be used to send clocks and commands to the system. In some alternative embodiments, there is no dedicated delay line solely for aligning clock signals and for delay measurements of the DLL circuit, and delay line 120 is used for clock alignment, measuring delays around the DLL circuit 100, and sending clocks to the system.

[0021] In some embodiments, the pattern detection circuit 130 receives a reference clock signal REF and a feedback clock signal FB and is configured to detect a predetermined pattern included in the feedback clock signal FB. The pattern detection circuit 130 can detect the predetermined pattern by detecting the pulse edges of the feedback clock signal FB and the pulse edges of the reference clock signal REF. For example, the pattern detection circuit 130 can detect misalignment between the pulse edges of the feedback clock signal FB and the pulse edges of the reference clock signal REF to detect the predetermined pattern included in the feedback clock signal FB. When the predetermined pattern in the feedback clock signal FB is detected, the pattern detection circuit 130 outputs a detection signal DS to the counter 140.

[0022] Counter 140 can receive a detection signal DS, a reference clock signal REF, and a reset signal RST, and is configured to count the number of clock cycles from the time when a predetermined pattern is set to the time when the pattern detection circuit 130 detects the predetermined pattern. In some embodiments, counter 140 is enabled by setting the reset signal RST and starts counting when the reset signal RST is set to counter 140. Counter 140 can stop counting when the detection signal DS from the pattern detection circuit 130 is set to counter 140. Counter 140 can output a count value CNT indicating the delay of DLL circuit 100. The count value CNT can indicate the number of clock cycles of the reference clock signal REF during the time period from the time when the reset signal RST is set to counter 140 to the time when the detection signal DS is set to counter 140.

[0023] In some embodiments, the DLL circuit 100 further includes a signal generator 160, which includes a signal generation circuit 161 for generating a reset signal RST. The signal generation circuit 161 can receive a trigger signal START and a reference clock signal REF and is configured to generate the reset signal RST when the trigger signal START is set. The generated reset signal RST is output to the pattern injection circuit 110 and the counter 140. This disclosure is not intended to limit any particular circuit structure of the signal generation circuit 161; therefore, any circuit that has the function of outputting a reset signal RST when the trigger signal START is set falls within the scope of the signal generator 160.

[0024] In some embodiments, when the reset signal RST is not set to the pattern injection circuit 110, the pattern injection circuit 110 provides a reference clock signal REF to the delay line 120. The delay line 120 is controlled to align the phase of the reference clock signal REF with the phase of the feedback clock signal FB. After the phases of the reference clock signal REF and the feedback clock signal FB are aligned (i.e., when the DLL circuit 100 is in a locked state), the reset signal RST can be set to the pattern injection circuit 110 to measure the delay of the DLL circuit 100. In this way, the delay measurement triggered by the reset signal RST can be performed at any time. Once the reset signal RST is set to the pattern injection circuit 110, the pattern injection circuit 110 injects a predetermined pattern into the reference clock signal REF to generate an injected reference clock signal REF_P, and then outputs the injected reference clock signal REF_P to the delay line 120. In this way, the predetermined pattern can propagate through the delay line 120 during the locked state of the DLL circuit. Simultaneously, when the reset signal RST is set, the counter 140 is enabled and begins counting. The output signal OUT of the delay line 120 is fed back as a feedback clock signal FB by the feedback path 150, and then the feedback clock signal FB is set to the pattern detection circuit 130. When the pattern detection circuit 130 detects a predetermined pattern, the pattern detection circuit 130 stops counting and outputs a count value CNT indicating the delay around the DLL circuit 100. Furthermore, since the delay measurement is performed during the period when the DLL circuit 100 is locked and fully operational, the delay measurement reflects the true delay in the normal operating system environment, and therefore the delay measurement is accurate and reliable.

[0025] Figure 2A A timing diagram is shown for the reference clock signal REF, the injected reference clock signal REF_P, and the feedback clock signal FB in a DLL circuit 100 according to some embodiments. (Refer to...) Figure 1 and Figure 2A At time t1, pattern injection circuit 110 injects a predetermined pattern (i.e., a missing clock pulse Pa) into reference clock signal REF to generate injected reference clock signal REF_P and provides injected reference clock signal REF_P to delay line 120. Simultaneously, counter 140 starts counting. The predetermined pattern propagates through delay line 120 and is fed back in feedback clock signal FB. Once pattern detection circuit 130 detects the predetermined pattern (i.e., a missing clock pulse Pa) in feedback clock signal FB at time t2, counter 140 stops counting. The number of clock cycles N from the time counter 140 starts counting to the time counter 140 stops counting is output as a count value CNT indicating the delay around DLL circuit 100.

[0026] Figure 2BA timing diagram is shown for the reference clock signal REF, the injected reference clock signal REF_P, and the feedback clock signal FB in a DLL circuit 100 according to some embodiments. (Refer to...) Figure 1 and Figure 2B At time t3, pattern injection circuit 110 injects a predetermined pattern (i.e., the addition of a clock pulse Pb) into the reference clock signal REF to generate an injected reference clock signal REF_P, and provides the injected reference clock signal REF_P to delay line 120. Simultaneously, counter 140 starts counting. The predetermined pattern propagates through delay line 120 and is fed back in the feedback clock signal FB. Once pattern detection circuit 130 detects the predetermined pattern (i.e., the addition of a clock pulse Pb) in the feedback clock signal FB at time t4, counter 140 stops counting. The number of clock cycles N from the time counter 140 starts counting to the time counter 140 stops counting is output as a count value CNT indicating the delay around DLL circuit 100.

[0027] Figures 3A to 3B A schematic diagram of pattern injection circuits 110_1 and 110_2 of a DLL circuit according to some embodiments is shown. Figure 1 The pattern injection circuit 110 of the DLL circuit 100 can be any pattern injection circuit, but is not limited to it. Figure 3A and Figure 3B The pattern injection circuits 110_1 and 110_2 are shown. (Refer to...) Figure 3AThe pattern injection circuit 110_1 may include a logic circuit 111 having input terminals for receiving a reference clock signal REF and a reset signal RST. The logic circuit 111 is configured to perform a logic operation on the received signals (i.e., the reference clock signal REF and the reset signal RST) to generate the reference clock signal REF or inject a reference clock signal REF_P. In some embodiments, the logic circuit 111 is configured to generate the injected reference clock signal REF_P when the reset signal RST is in a first logic state; and the logic circuit 111 is configured to generate the reference clock signal REF when the reset signal RST is in a second logic state. In some embodiments, the logic circuit 111 is an OR logic gate configured to perform an OR operation on the reference clock signal REF and the reset signal RST. When the reset signal RST is in the first logic state (i.e., logic state "1"), the logic circuit 111 may insert a predetermined pattern (i.e., a high pulse) into the clock signal REF to generate the injected reference clock signal REF_P. When the reset signal RST is in the second logic state (i.e., logic state "0"), the logic circuit 111 can output the reference clock signal REF to the output terminal of the logic circuit 111. In this way, the pattern injection circuit 110_1 can inject a predetermined pattern (i.e., a high pulse) into the reference clock signal REF based on the reset signal RST.

[0028] Reference Figure 3B The pattern injection circuit 110_2 may include logic circuits 112 and 114. Figure 3B In the example shown, logic circuit 112 is an inverter configured to invert a reference clock signal REF to generate an inverted reference clock signal REF_I; and logic circuit 114 is a NOR gate that performs a NOR operation on the inverted reference clock signal REF_I and a reset signal RST to generate an injected reference clock signal REF_P. In some embodiments, when the reset signal RST is in a first logic state (i.e., logic state "1"), pattern injection circuit 110_2 injects a predetermined pattern (i.e., a low pulse) into the reference clock signal REF to generate the injected reference clock signal REF_P. When the reset signal RST is in a second logic state (i.e., logic state "0"), pattern injection circuit 110_2 outputs the reference clock signal REF. In this way, pattern injection circuit 110_2 can inject a predetermined pattern into the reference clock signal REF based on the reset signal RST. It should be understood that the pattern injection circuit of the DLL circuit is not limited to... Figure 3A and Figure 3B The pattern injection circuit shown is a circuit whose structure can be varied according to design requirements.

[0029] Figures 4A to 4E A schematic diagram of a pattern detection circuit 130 according to some embodiments and a timing diagram of the signals in the pattern detection circuit are shown. (Refer to...) Figure 4A The pattern detection circuit 130 may include an edge detection circuit 130a formed by a delay circuit 131 and a latching circuit 133. The edge detection circuit 130a can detect the edges of a reference clock signal REF and a feedback clock signal FB, and thus can detect the absence of at least one clock pulse in the feedback clock signal FB. The edge detection circuit 130a can detect a predetermined pattern when the predetermined pattern includes the absence of at least one clock pulse. The delay circuit 131 of the edge detection circuit 130a receives the reference clock signal REF and is configured to delay the reference clock signal REF by a predetermined delay period to generate a delayed reference clock signal 1311. The latching circuit 133 of the edge detection circuit 130a receives the delayed reference clock signal 1311 and the feedback clock signal FB and is configured to perform a latching operation based on the logic state of the delayed reference clock signal 1311 and the logic state of the feedback clock signal FB to detect the predetermined pattern. The edge detection circuit 130a can output a signal DS_1 to indicate the detection of a missing clock pulse (i.e., a predetermined pattern) in the feedback clock signal FB. Figure 4B As shown in the example, when the feedback clock signal FB includes a missing clock pulse (i.e., a predetermined pattern), the edge detection circuit 130a can output a signal DS_1 with a pulse P1 at timing tx to indicate that a predetermined pattern has been detected in the feedback clock signal FB. In this example, the latch circuit 133 is an edge-triggered flip-flop configured to capture and release data on the rising edge of the delayed reference clock signal 1311. Figure 4A and Figure 4B As shown, the delay circuit 131 causes a delay period Td from the rising edge of the reference clock signal REF to the timing tx of the pulse P1.

[0030] Figure 4C A schematic diagram of a pattern detection circuit 130 according to some embodiments is shown. (Refer to...) Figure 4CThe pattern detection circuit 130 may include an edge detection circuit 130b formed by a delay circuit 132 and a latch circuit 134. The edge detection circuit 130b can detect the edges of a reference clock signal REF and a feedback clock signal FB, and thus can detect the addition of at least one clock pulse in the feedback clock signal FB. The edge detection circuit 130b can detect the predetermined pattern when the predetermined pattern includes the addition of at least one clock pulse. The delay circuit 132 receives the feedback clock signal FB and is configured to delay the feedback clock signal FB by a predetermined delay period to generate a delayed feedback clock signal 1321. The latch circuit 134 receives the delayed feedback clock signal 1321 and the reference clock signal REF and is configured to perform a latching operation based on the logic state of the delayed feedback clock signal 1321 and the logic state of the reference clock signal REF to detect the addition of at least one clock pulse (i.e., the predetermined pattern). The edge detection circuit 130b may output a signal DS_2 to indicate that an added clock pulse (i.e., the predetermined pattern) has been detected in the feedback clock signal FB. Figure 4D As shown in the example, when the feedback clock signal includes the addition of clock pulses (i.e., a predetermined pattern), the edge detection circuit 130b can output a signal DS_2 with pulse P2 at timing ty to indicate that the predetermined pattern has been detected in the feedback clock signal FB. In the example, the latch circuit 134 is an edge-triggered flip-flop configured to capture and release data on the rising edge of the reference clock signal REF. Figure 4C and Figure 4D As shown, pulse P2 is aligned with the rising edge of the reference clock signal REF at timing ty.

[0031] Figure 4E A schematic diagram of a pattern detection circuit 130 according to some embodiments is shown. The pattern detection circuit 130 includes logic circuitry 135 and edge detection circuits 130a and 130b. Edge detection circuits 130a and 130b in... Figure 4A and Figure 4C As shown and described above, detailed descriptions of edge detection circuits 130a and 130b are omitted below. Logic circuit 135 is coupled to the output terminals of edge detection circuits 130a and 130b to receive signals DS_1 and DS_2, and is configured to perform a logic operation on the received signals to generate signal DS_3. In some embodiments, logic circuit 135 is an XOR logic circuit configured to perform an XOR operation on the received signals DS_1 and DS_2 to generate signal DS_3. In this manner, Figure 4E The pattern detection circuit 130 can detect the addition of at least one clock pulse, the absence of at least one clock pulse, or a combination thereof. In this way, Figure 4E The pattern detection circuit 130 in the circuit can be applied to a wide range of applications. However, when the predetermined pattern includes only the absence of at least one clock pulse or the addition of at least one clock pulse, Figure 4A and Figure 4C The pattern detection circuit 130 is sufficient to detect a predetermined pattern. Therefore, the design of the pattern detection circuit 130 can vary depending on the actual design and design requirements of the predetermined pattern. This disclosure is not intended to limit the structure of the pattern detection circuit 130, and any circuit structure capable of detecting a predetermined pattern should fall within the scope of the pattern detection circuit 130.

[0032] Figure 5 A schematic diagram of a counter 140 of a DLL circuit 100 according to some embodiments is shown. The counter 140 may include a stop signal generation circuit 141 and a counter circuit 143. The stop signal generation circuit 141 receives a detection signal DS, a reset signal RST, and a reference clock signal REF, and is configured to generate a stop signal STOP based on the reception of the detection signal DS. In some embodiments, the stop signal generation circuit 141 includes an OR logic circuit 1411 and a latch circuit 1412, wherein the OR logic circuit 1411 receives the detection signal DS and the output of the latch circuit 1412 as input signals. The OR logic circuit 1411 performs an OR operation on the input signals, and the output of the OR logic circuit 1411 is provided to the latch circuit 1412. The latch circuit 1412 is enabled by the reset signal RST and is configured to perform a latch operation based on the reference clock signal REF and the output of the OR logic circuit 1411 to generate the stop signal STOP.

[0033] Counter circuit 143 can receive a stop signal STOP, a reset signal RST, and a reference clock signal REF, and is configured to count the number of clock cycles of the reference clock signal REF from the timing when the reset signal is set to the timing when the stop signal STOP is set. More specifically, at the timing when the reset signal RST is set to counter circuit 143, counter circuit 143 begins counting by incrementing the count value CNT by one for each clock cycle. At the timing when the stop signal STOP is set to counter circuit 143, counter circuit 143 stops counting and outputs an indicator DLL circuit (i.e., Figure 1 The count value CNT of the delay around the DLL circuit 100 shown.

[0034] Figure 6 A schematic diagram of a DLL circuit 200 according to some embodiments is shown. Figure 1 The DLL circuit 100 shown is... Figure 6The difference between the DLL circuits 200 shown is that each DLL circuit 200 includes a signal generator 210 and delay circuits 211 and 213. Signal generator 210 includes signal generation circuit 161. Delay circuit 211 receives a reference clock signal REF and delays it by a delay period to generate a delayed reference clock signal REF_D. Signal generation circuit 161 is configured to generate a reset signal RST when trigger signal START is set. Delay circuit 213 is coupled to signal generation circuit 161 to receive the reset signal RST and is configured to delay the reset signal RST by a delay period to generate a reset signal RST_1. In some embodiments, delay circuits 211 and 213 have the same circuit structure, and the delay period generated by delay circuit 211 is substantially the same as the delay period generated by delay circuit 213.

[0035] Delay circuits 211 and 213 in DLL circuit 200 enable DLL circuit 200 to adapt to and support a trimming function. In an example, when trimming DLL circuit 200, delay circuit 211 can add a delay to the reference clock signal REF to generate a delayed reference clock signal REF_D. With this delay, when DLL circuit 200 is locked, the edge of the delayed reference clock signal REF_D will be aligned with the edge of the feedback clock signal FB, and the reference clock signal REF and the feedback clock signal FB will be biased by the same delay value. Thus, without trimming (i.e., the delay through delay circuit 211 is "0"), the edge of the reference clock signal REF and the edge of the feedback clock signal FB are ideally aligned. With trimming, the edge of the reference clock signal REF and the edge of the feedback clock signal FB can be skewed with the trimming delay. Delay circuit 211 may support a trimming function, and delay circuit 213 may be a copy delay, which, even when the trimming function is implemented, allows for proper measurement of the delay around DLL circuit 200. In an example, the trimming function may be used for tuning purposes of memory devices coupled to or including DLL circuit 200.

[0036] Figure 1 The DLL circuit 100 shown is... Figure 6Another difference between the DLL circuits 200 shown is that the pattern detection circuit 130 and counter 140 of the DLL circuit 200 operate based on the delayed reset signal RST_1 and the delayed reference clock signal REF_D, instead of the reset signal RST and the reference clock signal REF. It should be noted that the pattern injection circuit 110 of the DLL circuit 200 still operates based on the reset signal RST and the reference clock signal REF. Because the pattern detection circuit 130 and counter 140 operate based on the reset signal RST_1 and the delayed reference clock signal REF_D, the pattern injection circuit 110 of the DLL circuit 200 has more time to inject the predetermined pattern into the reference clock signal REF. In this way, even when the trimming function is implemented, the delay around the DLL circuit 200 can be properly measured by inserting and detecting the predetermined pattern.

[0037] Figure 7 A flowchart illustrating a method for measuring the delay of a DLL circuit according to some embodiments is shown. In block 710, a reference clock signal is set to the delay line of a delay-locked loop circuit, wherein the delay line is configured to align the phase of the reference clock signal with the phase of a feedback clock signal. In block 720, a predetermined pattern is injected into the reference clock signal to generate an injected reference clock signal. In block 730, the injected reference clock signal is set to the delay line. In block 740, the predetermined pattern in the feedback clock signal is detected. In block 750, the delay of the delay-locked loop circuit is determined based on a first timing when the injected reference clock signal is set to the delay line and a second timing when the predetermined pattern is detected in the feedback clock signal.

[0038] In summary, according to embodiments of this disclosure, the pattern injection circuit of the DLL circuit can inject a predetermined pattern into a reference clock signal, wherein the predetermined pattern can be propagated through a delay line, fed back during the locked state of the DLL circuit, and detected by the pattern detection circuit. Since the DLL delay is measured during the locked state of the DLL circuit, the measured delay reflects the true delay under normal operating system conditions, thus improving the accuracy of delay measurement. Furthermore, since the delay measurement is triggered at any time when the reset signal is set, the delay measurement can be repeated without interrupting system behavior. The delay measurement can be performed when the system is in normal functional operation, and the delay measurement can be performed without affecting the normal operation of the system. Additionally, in some embodiments, the signal generator of the DLL circuit can insert delays into the reference clock signal and the reset signal, thereby enabling the DLL circuit to adapt to trimming functions. Moreover, complex predetermined patterns with multiple sequential or non-sequential pulses can be used to mitigate the effects of noise and distorted signals on the delay measurement.

[0039] Although embodiments of the present disclosure have been described in detail, the present disclosure is not limited to the specific embodiments, and various modifications and changes can be made within the scope of the present disclosure as disclosed in the claims.

Claims

1. A method for measuring the delay of a delay-locked loop circuit, comprising: A reference clock signal is set to the delay line of the delay-locked loop circuit, wherein the delay line is configured to align the phase of the reference clock signal with the phase of the feedback clock signal. A predetermined pattern is injected into the reference clock signal to generate an injected reference clock signal; Set the injected reference clock signal to the delay line; Detect the predetermined pattern in the feedback clock signal; as well as The delay of the delay-locked loop circuit is determined based on a first timing when the injected reference clock signal is set to the delay line and a second timing when the predetermined pattern is detected in the feedback clock signal.

2. The method of claim 1, wherein injecting the predetermined pattern into the reference clock signal to generate the injected reference clock signal comprises: Perform logic operations to inject the predetermined pattern into the reference clock signal, thereby generating the injected reference clock signal when the reset signal is set.

3. The method according to claim 2, wherein The predetermined pattern includes pulses that are held in a first logic state for at least one clock cycle of the reference clock signal.

4. The method according to claim 2, wherein The predetermined pattern includes pulses that are held in a second logic state for at least one clock cycle of the reference clock signal.

5. The method according to claim 2, wherein After the phase of the reference clock signal is aligned with the phase of the feedback clock signal, the injected reference clock signal is set to the delay line.

6. The method according to claim 2, further comprising: The reference clock signal is delayed to generate a delayed reference clock signal; as well as The reset signal is delayed to generate a delayed reset signal, wherein The predetermined pattern in the feedback clock signal is detected based on the delayed reference clock signal and the feedback clock signal, and The delay of the delay-locked loop circuit is determined based on the delayed reference clock signal and the delayed reset signal.

7. The method of claim 1, wherein detecting the predetermined pattern in the feedback clock signal comprises: Detect the pulse edge of the reference clock signal and the pulse edge of the feedback clock signal; Determine the misalignment between the pulse edge of the reference clock signal and the pulse edge of the feedback clock signal; as well as A detection signal is output in response to the detection of misalignment between the pulse edge of the reference clock signal and the pulse edge of the feedback clock signal.

8. The method of claim 1, wherein determining the delay of the delay-locked loop circuit based on the time period from the first timing when the injected reference clock signal is supplied to the delay line to the second timing when the predetermined pattern is detected in the feedback clock signal comprises: The number of clock cycles of the reference clock signal from the first timing to the second timing is counted to obtain a count value; as well as The count value is output as the delay of the delay-locked loop circuit.

9. The method of claim 8, wherein counting the number of clock cycles of the reference clock signal from the first timing to the second timing comprises: At the first timing point when the injected reference clock signal is set to the delay line, the counter of the delay-locked loop circuit begins counting; as well as At the second timing point when the predetermined pattern is detected in the feedback clock signal, the counter of the delay-locked loop circuit stops counting.

10. A delay-locked loop circuit, comprising: A delay line that receives a reference clock signal and generates a feedback clock signal, wherein the delay line is configured to align the phase of the reference clock signal with the phase of the feedback clock signal; A pattern injection circuit, coupled to the delay line, injects a predetermined pattern into the reference clock signal to generate an injection reference clock signal, and sets the injection reference clock signal to the delay line; A pattern detection circuit, coupled to the delay line, detects the predetermined pattern in the feedback clock signal; as well as A counter, coupled to the pattern detection circuit, determines the delay of the delay-locked loop circuit based on a first timing when the injected reference clock signal is set to the delay line and a second timing when the predetermined pattern is detected in the feedback clock signal.

11. The delay-locked loop circuit according to claim 10, wherein... The pattern injection circuit includes logic circuitry, and The logic circuit is configured to perform a logic operation to inject the predetermined pattern into the reference clock signal, thereby generating the injected reference clock signal when a reset signal is set to the logic circuit.

12. The delay-locked loop circuit according to claim 11, wherein... The pattern detection circuit detects the predetermined pattern in the feedback clock signal according to the reference clock signal, and The counter determines the delay of the delay-locked loop circuit based on the reference clock signal and the reset signal.

13. The delay-locked loop circuit according to claim 11, wherein... The predetermined pattern is a pulse that is kept in a first logic state for at least one clock cycle of the reference clock signal.

14. The delay-locked loop circuit according to claim 11, wherein... The predetermined pattern is a pulse that is kept in the second logic state for at least one clock cycle of the reference clock signal.

15. The delay-locked loop circuit according to claim 11, wherein... The pattern injection circuit is configured to set the injected reference clock signal to the delay line after the phase of the reference clock signal is aligned with the phase of the feedback clock signal.

16. The delay-locked loop circuit according to claim 11, further comprising: A signal generator generates the reset signal, wherein the signal generator includes: A first delay circuit delays the reference clock signal to generate a delayed reference clock signal; and The second delay circuit delays the reset signal to generate a delayed reset signal.

17. The delay-locked loop circuit according to claim 16, wherein... The pattern detection circuit detects the predetermined pattern in the feedback clock signal based on the delayed reference clock signal, and The counter determines the delay of the delay-locked loop circuit based on the delayed reference clock signal and the delayed reset signal.

18. The delay-locked loop circuit of claim 10, wherein the pattern detection circuit includes an edge detection circuit, the edge detection circuit being configured to: Detect the pulse edge of the reference clock signal and the pulse edge of the feedback clock signal; Determine the misalignment between the pulse edge of the reference clock signal and the pulse edge of the feedback clock signal; and A detection signal is output in response to the detection of misalignment between the pulse edge of the reference clock signal and the pulse edge of the feedback clock signal.

19. The delay-locked loop circuit of claim 18, wherein the counter comprises: A stop signal generation circuit is coupled to the pattern detection circuit and generates a stop signal based on the detection signal. as well as A counter circuit, coupled to the stop signal generation circuit, counts the number of clock cycles of the reference clock signal from the first timing to the second timing to obtain a count value, and outputs the count value as the delay of the delay-locked loop circuit.

20. The delay-locked loop circuit according to claim 19, wherein... At the first timing point when the injected reference clock signal is set to the delay line, the counter circuit begins counting, and At the second timing point when the predetermined pattern is detected in the feedback clock signal, the counter circuit stops counting.

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