A satellite base station baseband processing board based on COTS devices

Abstract

The present invention discloses a satellite base station baseband processing board based on COTS devices to realize on-board 5G protocol processing. The baseband processing board circuit composition is designed, including baseband processing FPGA chip 1, baseband processing FPGA chip 2, baseband processing CPU chip 1, baseband processing CPU chip 2, control anti-fuse FPGA chip, configuration FLASH chip of baseband processing FPGA chip 1 and FPGA chip 2, configuration FLASH chip of baseband processing CPU chip 1 and CPU chip 2, RF direct sampling transceiver chip, power-on reset monitoring chip, lock detection circuit, RS422 communication interface circuit; by adopting the principle of single particle upset reinforcement and single particle lock protection technology, COTS device single particle upset and single particle lock failure are alleviated, the adaptability of COTS device to low orbit space environment is improved, and the problems faced by COTS device low orbit application are solved.

Description

Technical field:

[0001] The invention relates to satellite mobile communications, in particular to a satellite base station baseband processing board based on COTS devices, belonging to the technical field of satellite communication payloads. Background technology:

[0002] As an important part of the new generation of information infrastructure, satellite Internet is an important guarantee for universal information services. Satellite Internet, represented by low-orbit broadband communication satellite constellations, has become an important solution for 5G and even 6G global satellite communication network coverage because of its advantages such as full coverage, large bandwidth, low latency, and low cost. In addition, with the continuous development of the aerospace industry in recent years, the explosive growth of commercial satellite launches has led to the use of high-performance COTS devices instead of aerospace-grade devices to meet the needs of high-throughput, low-cost, and rapid deployment in low-orbit. This can simplify system design, improve onboard business processing capabilities, and reduce development costs. Therefore, it has become a major research direction in the design of commercial aerospace payloads. Summary of the invention:

[0003] The purpose of the present invention is to provide a satellite base station baseband processing board based on COTS devices to realize on-board 5G protocol processing. For the rapidly deployed low-orbit broadband communication commercial satellite payloads, the processing capabilities of traditional domestic aerospace devices are relatively weak, while the implementation of a large number of aerospace-grade processors is complex and costly; this contradiction is resolved by adopting low-cost, high-performance COTS devices. Space electronic products are in a radiation environment, and the single-particle effect is significant. Compared with aerospace devices, COTS devices are more susceptible to it; by adopting single-particle flip reinforcement and single-particle locking protection measures, COTS device single-particle flips are alleviated and single-particle locking failures are eliminated, thereby improving the adaptability of COTS devices to the low-orbit space environment and solving the problems faced by COTS devices in low-orbit applications.

[0004] In this regard, the present invention proposes a satellite base station baseband processing board based on COTS devices, which is suitable for low-orbit Internet satellite communication payloads. Figure 1 As shown, it includes: baseband processing FPGA chip 1, baseband processing FPGA chip 2, baseband processing CPU chip 1, baseband processing CPU chip 2, control anti-fuse FPGA chip, configuration FLASH chip of baseband processing FPGA chip 1 and FPGA chip 2, configuration FLASH chip of baseband processing CPU chip 1 and CPU chip 2, RF direct sampling transceiver chip, power-on reset monitoring chip, lock detection circuit, RS422 communication interface circuit, etc.

[0005] Baseband processing FPGA chip 1 and baseband processing FPGA chip 2 are used to implement physical layer communication protocol processing in baseband processing; wherein baseband processing FPGA chip 1 is interconnected with the receiving channel of the RF direct acquisition transceiver chip to implement the processing task of the uplink physical layer communication protocol part; baseband processing FPGA chip 2 is interconnected with the transmitting channel of the RF direct acquisition transceiver chip to implement the processing task of the downlink physical layer communication protocol part.

[0006] The baseband processing CPU chip 1 and the baseband processing CPU chip 2 are used to implement L2 and L3 layer protocol processing in baseband processing; the baseband processing CPU chip 1 is interconnected with the baseband processing FPGA chip 1, receives the uplink data processed by the baseband processing FPGA chip 1, implements uplink L2 and L3 layer protocol processing, and sends the processed uplink data back to the baseband processing FPGA chip 1, which is forwarded to the routing board; the baseband processing CPU chip 2 is interconnected with the baseband processing FPGA chip 2, receives the downlink data forwarded by the baseband processing FPGA chip 2 from the routing board, performs L2 and L3 layer protocol processing on the baseband processing CPU chip 2, and sends it back to the baseband processing FPGA chip 2, and sends it to the external antenna through the sending channel of the RF direct acquisition transceiver chip.

[0007] Among them, the baseband processing CPU chip 2 also has the management function of the baseband processing control plane, and exchanges control plane information with the baseband processing CPU chip 1 through the data interface; the baseband processing CPU chip 2 receives the signaling data forwarded by the baseband processing FPGA chip 2 from the control / signaling board, and after the beam control information is obtained through the solution processing, it is sent back to the baseband processing FPGA chip 2, and interconnected with the antenna array beam control interface through the RS422 interface.

[0008] The anti-fuse FPGA chip is managed to perform single-particle upset reinforcement on baseband processing FPGA chip 1, baseband processing FPGA chip 2, baseband processing CPU chip 1 and baseband processing CPU chip 2, and configuration FLASH chip, which are COTS devices, and detect and protect against possible single-particle locking failures.

[0009] Among them, the control anti-fuse FPGA chip is responsible for the configuration and loading of the programs of the baseband processing FPGA chip 1 and the baseband processing FPGA chip 2, and accesses the baseband processing FPGA chip 1 and the baseband processing FPGA chip 2 in time-sharing through the dedicated program configuration interface; the dedicated program configuration interfaces of the two baseband processing FPGA chips are interconnected with the control anti-fuse FPGA. The control anti-fuse FPGA chip is connected to four FLASH chips for storing the configuration programs of the baseband processing FPGA chip; each two chips form a group of two groups, which are used for the baseband processing FPGA chip 1 and the baseband processing FPGA chip 2 respectively. The configuration FLASH chips in each group adopt a master-backup design to store the same configuration program. The control anti-fuse FPGA periodically reads back, compares and refreshes the configuration data of the baseband processing FPGA to reduce the probability of single particles in the baseband processing FPGA.

[0010] Among them, the control anti-fuse FPGA chip is responsible for the configuration and loading of the baseband processing CPU chip 1 and the baseband processing CPU chip 2 programs, and accesses the baseband processing CPU chip 1 and the baseband processing CPU chip 2 through an independent data bus. The control anti-fuse FPGA is connected to three baseband processing CPU configuration FLASH chips, and the three FLASH chips store the same baseband processing CPU configuration program; when the baseband processing CPU does not load the program, the control anti-fuse FPGA chip periodically reads the configuration program in the three FLASH chips at the same time and compares them to achieve triple-mode redundant refresh. When the baseband processing CPU needs to load the program, the control anti-fuse FPGA chip stops the periodic comparison and refresh of the three FLASH chips, and defaults to the first FLASH chip for baseband processing CPU chip 1 to load the program, and defaults to the second FLASH chip for baseband processing CPU chip 2 to load the program. After the two CPU programs are loaded, the periodic comparison and refresh of the three FLASH chips are restarted.

[0011] Among them, the control anti-fuse FPGA chip is responsible for monitoring the reset of the entire board to prevent abnormal operation caused by single-particle flips. It has operation monitoring logic, AND logic, and CPU runaway monitoring logic inside. After the power-on initialization is completed, the control anti-fuse FPGA chip outputs a fixed-period square wave signal to the reset signal input end of the power-on reset monitoring chip through the internal operation monitoring logic. The power-on reset monitoring chip determines whether the working state of the control anti-fuse FPGA chip is normal through the reset pulse signal. If the output reset pulse signal is abnormal, the power-on reset monitoring chip outputs an overflow pulse signal to the control anti-fuse FPGA chip; the input overflow pulse signal and another external input hard reset signal of the control anti-fuse FPGA are combined with the internal AND logic, and then the reset trigger pulse is output to the trigger end of the power-on reset monitoring chip. The power-on reset monitoring chip outputs a reset signal, causing the internal monitoring logic of the control anti-fuse FPGA chip, baseband processing FPGA chip 1, baseband processing FPGA chip 2, baseband processing CPU chip 1 and baseband processing CPU chip 2 to reset.

[0012] Among them, the CPU runaway monitoring logic runs inside the control anti-fuse FPGA chip, and receives the reset pulse sent by the baseband processing CPU chip 1 and the baseband processing CPU chip 2 through the IO port. When the control anti-fuse FPGA monitors that the reset pulse is abnormal, it will output an abnormal reset signal, and after the reset signal output by the power-on reset monitoring chip is passed through the control anti-fuse FPGA internal AND logic, it outputs the baseband processing CPU reset signal to the external CPU chip.

[0013] Among them, the control anti-fuse FPGA chip receives the upper configuration program through the reconstruction / telemetry remote control interface, and reconstructs the two baseband processing FPGA configuration FLASH chips and the two baseband processing CPU configuration FLASH chips.

[0014] The lock detection circuit detects the target load power supply current of the baseband processing FPGA chip and related peripherals, the baseband processing CPU chip and related peripherals, and sends the periodic sampling data to the anti-fuse FPGA chip via the acquisition data bus. After data processing, judgment and comparison, the control signal is output to turn on / off the load power supply.

[0015] The beneficial effects of the present invention are:

[0016] 1. The design is implemented using COTS devices such as high-performance SRAM FPGA and high-performance CPU, which greatly improves the computing power of the processing platform.

[0017] 2. Use high-performance COTS devices to reduce the number of processing devices used, do not use or use fewer aerospace-grade devices, reduce hardware costs, and be suitable for low-orbit short-mission and rapid response application requirements.

[0018] 3. Use aerospace-grade anti-fuse FPGA to monitor the operating status of SRAM FPGA and CPU, control the configuration memory, refresh and reconstruct the configuration program, and improve the reliability of aerospace applications.

[0019] 4. Use single-particle lock detection circuit to prevent single-particle lock failures that may occur in COTS devices in space application environments and improve reliability. Description of the drawings:

[0020] The drawings are only for the purpose of illustrating the preferred embodiment modes and are not to be construed as limiting the invention.

[0021] Figure 1 The present invention is a schematic diagram of the circuit composition principle of a satellite base station baseband processing board based on COTS devices.

[0022] Figure 2 This is a schematic diagram of an example of the circuit composition of a baseband processing board.

[0023] Figure 3 This is the baseband protocol processing function allocation diagram of the baseband processing board.

[0024] Figure 4 It is a schematic diagram of the circuit principle for configuring, loading and managing the baseband processing FPGA chip in the baseband processing board.

[0025] Figure 5 It is a schematic diagram of the circuit principle for configuring, loading and managing the baseband processing CPU chip in the baseband processing board.

[0026] Figure 6 This is a schematic diagram of the reset monitoring circuit in the baseband processing board.

[0027] Figure 7 This is a schematic diagram of the lock detection circuit principle in the baseband processing board. Specific implementation method:

[0028] In order to more clearly illustrate the embodiments of the present invention or the technical methods in the prior art, the specific implementation methods of the present invention will be described below with reference to the accompanying drawings. It is obvious that the contents described in the following drawings are only some examples of the present invention, and other drawings and other implementation methods can also be obtained based on these drawings.

[0029] The design of the satellite base station baseband processing board based on COTS devices proposed by the present invention is further described in detail below in conjunction with the accompanying drawings and specific embodiments.

[0030] See also Figure 2 This embodiment provides a design method for a baseband processing board. Figure 2As known, the overall structure of this implementation consists of: baseband processing FPGA chip 1, baseband processing FPGA chip 2, baseband processing CPU chip 1, baseband processing CPU chip 2, control anti-fuse FPGA chip, configuration FLASH chip 1 and configuration FLASH chip 2 of baseband processing FPGA chip 1, configuration FLASH chip 3 and configuration FLASH chip 4 of baseband processing FPGA chip 2, configuration FLASH chip 5, FLASH chip 6, FLASH chip 7 of baseband processing CPU chip 1 and CPU chip 2, RF direct sampling transceiver chip, power-on reset monitoring chip, lock detection circuit, and RS422 and other communication interface circuits.

[0031] See also Figure 3 , used to implement communication protocol processing in baseband processing, the following COTS devices are used respectively. The RF direct acquisition transceiver chip uses the CX8242 chip, the baseband processing FPGA chip uses the XC7VX690T, and the baseband processing CPU chip uses the Feiteng eight-core D2000 processing chip.

[0032] On the one hand, for downlink baseband data processing, the baseband processing FPGA chip 1 receives the uplink baseband sampling data sent by the RF direct sampling transceiver CX8242 chip through the JESD204B interface, and after completing the physical layer communication protocol processing of the uplink baseband sampling data, sends the processed data to the baseband processing CPU chip 1 through the PCIE bus. After the L2 and L3 layer protocol processing of the baseband processing CPU chip 1, the data is sent back to the baseband processing FPGA chip 1 through the PCIE bus interface, and then sent to the external routing board through the high-speed interface. Among them, the uplink baseband sampling data sent by the RF direct sampling transceiver CX8242 chip comes from the external antenna array.

[0033] On the other hand, for uplink baseband data processing, the baseband processing CPU chip 2 is interconnected with the baseband processing FPGA chip 2 through the PCIE bus, and the receiving baseband processing FPGA chip 2 forwards the downlink communication data to be processed from the routing board. After being processed by the L2 and L3 layer protocols of the baseband processing CPU chip 2 and the physical layer protocol of the baseband processing FPGA chip 2, it is input to the RF direct acquisition transceiver CX8242 chip through the JESD204B interface, and finally sent to the external transmitting antenna.

[0034] See also Figure 3It can also be known that the baseband processing CPU chip 2 is also responsible for the management function of the baseband processing control plane, interacting with the baseband processing CPU chip 1 through the RGMII Ethernet interface to exchange control plane information, and receiving the control plane information forwarded by the baseband processing FPGA chip 2 through PCIE, which is processed by the baseband processing CPU chip 2 to form beam control information, and sent back to the baseband processing FPGA chip 2 to generate control timing, and finally output to the antenna array beam control interface through RS422. Among them, the control plane information forwarded by the baseband processing FPGA chip 2 comes from the control / command board.

[0035] See also Figure 4 For example, the control anti-fuse FPGA chip is interconnected with the baseband processing FPGA chip 1 and the baseband processing FPGA chip 2 through the dedicated configuration SelectMap interface, and is responsible for loading, reading and refreshing its configuration program. The control anti-fuse FPGA chip is connected to four FLASH chips, which read and write external FLASH chips through the parallel port bus and are used to store the configuration program of the baseband processing FPGA chip; each two chips form a group, and there are two groups in total, which are used for baseband processing FPGA chip 1 and baseband processing FPGA chip 2 respectively. The configuration FLASH chips in each group adopt a master-backup design and store the same configuration program.

[0036] See also Figure 5 For example, the control anti-fuse FPGA chip is interconnected with the baseband processing CPU chip 1 and the baseband processing CPU chip 2 through a set of QSPI interfaces to assist the baseband processing CPU in completing program loading. The control anti-fuse FPGA is connected to three baseband processing CPU configuration FLASH chips, and the three FLASH chips store the same baseband processing CPU configuration program; when the baseband processing CPU does not load the program, the control anti-fuse FPGA chip periodically reads the configuration program in the three FLASH chips at the same time and compares them to achieve triple-mode redundant refresh. When the baseband processing CPU needs to load the program, the control anti-fuse FPGA chip stops the periodic comparison and refresh of the three FLASH chips, and selects the first FLASH chip by default for baseband processing CPU chip 1 to load the program, and the second FLASH chip by default for baseband processing CPU chip 2 to load the program. After the two CPU programs are loaded, the periodic comparison and refresh of the three FLASH chips are restarted.

[0037] See also Figure 6 For example, the anti-fuse FPGA chip is connected to a power-on reset monitoring chip. The chip can use the JSR706 aerospace-grade chip to prevent abnormal operation caused by single-particle upset.

[0038] The control anti-fuse FPGA chip is equipped with operation monitoring logic, AND logic and CPU runaway monitoring logic. The monitoring logic running inside the control anti-fuse FPGA chip will output a square wave clear signal with a fixed period, which is input to the power-on reset monitoring chip. The clear pulse signal is used to determine whether the working state of the control anti-fuse FPGA chip is normal; when the output clear pulse signal is abnormal, the power-on reset monitoring chip outputs an overflow pulse signal to the control anti-fuse FPGA chip.

[0039] A hard reset signal is also input to the outside of the anti-fuse control FPGA. After the overflow pulse signal output by the power-on reset monitoring chip and the logic, a reset trigger pulse is output to the power-on reset monitoring chip, causing the power-on reset monitoring chip to output a reset signal, thereby resetting external chips such as the baseband processing FPGA1 and the base processing FPGA2.

[0040] The control anti-fuse FPGA chip runs CPU runaway monitoring logic inside and receives the reset pulse sent by the baseband processing CPU through the GPIO port; when the control anti-fuse FPGA monitors that the reset pulse is abnormal, it outputs the baseband processing CPU reset signal to the external CPU chip after the reset and logic input by the power-on reset monitoring chip.

[0041] See also Figure 7 For example, the single-particle lock detection recovery circuit consists of a current detection amplifier circuit, a sampling circuit, a switch circuit, and a lock judgment processing circuit. The input power passes through the sampling resistor in the current detection amplifier circuit and the switch tube in the switch circuit to supply power to the target load; the current detection amplifier circuit detects the voltage across the sampling resistor, and sends it to the acquisition ADC after linear amplification; the sampling circuit sends the data to the anti-fuse FPGA in the lock judgment processing circuit, and after data processing, judgment and comparison, the switch control signal is output to the switch circuit for opening / closing operations, so as to realize the processing of the power latch of the monitoring baseband processing FPGA, baseband processing CPU and configuration FLASH.

Claims

1. A satellite base station baseband processing board based on COTS devices, characterized in that: include: Baseband processing FPGA chip 1, baseband processing FPGA chip 2, baseband processing CPU chip 1, baseband processing CPU chip 2, control anti-fuse FPGA chip, configuration FLASH chip of baseband processing FPGA chip 1 and FPGA chip 2, configuration FLASH chip of baseband processing CPU chip 1 and CPU chip 2, RF direct sampling transceiver chip, power-on reset monitoring chip, lock detection circuit, and communication interface circuit; Baseband processing FPGA chip 1 and baseband processing FPGA chip 2 are used to implement physical layer communication protocol processing in baseband processing; The baseband processing FPGA chip 1 is interconnected with the receiving channel of the RF direct acquisition transceiver chip to realize the processing task of the uplink physical layer communication protocol part; the baseband processing FPGA chip 2 is interconnected with the sending channel of the RF direct acquisition transceiver chip to realize the processing task of the downlink physical layer communication protocol part; The baseband processing CPU chip 1 and the baseband processing CPU chip 2 are used to implement L2 and L3 layer protocol processing in baseband processing; The baseband processing CPU chip 1 is interconnected with the baseband processing FPGA chip 1, receives the uplink data processed by the baseband processing FPGA chip 1, implements uplink L2 and L3 layer protocol processing, and sends the processed uplink data back to the baseband processing FPGA chip 1, which is forwarded to the routing board; the baseband processing CPU chip 2 is interconnected with the baseband processing FPGA chip 2, receives the downlink data forwarded by the baseband processing FPGA chip 2 from the routing board, and after the baseband processing CPU chip 2 performs L2 and L3 layer protocol processing, sends it back to the baseband processing FPGA chip 2, and sends it to the external antenna through the sending channel of the RF direct acquisition transceiver chip; The baseband processing CPU chip 2 also has the management function of the baseband processing control plane, and exchanges control plane information with the baseband processing CPU chip 1 through the data interface; the baseband processing CPU chip 2 receives the signaling data forwarded by the baseband processing FPGA chip 2 from the control / signaling board, obtains the beam control information through the solution processing, and sends it back to the baseband processing FPGA chip 2, and is interconnected with the antenna array beam control interface through the RS422 interface; The control anti-fuse FPGA chip performs single-particle upset reinforcement on the baseband processing FPGA chip 1, baseband processing FPGA chip 2, baseband processing CPU chip 1 and baseband processing CPU chip 2, and the configuration FLASH chip using COTS devices. The control anti-fuse FPGA chip is externally connected to a power-on reset monitoring chip to detect and protect against single-particle locking faults. The control anti-fuse FPGA chip receives the configuration program through the reconstruction / telemetry remote control interface, and reconstructs the two baseband processing FPGA configuration FLASH chips and the two baseband processing CPU configuration FLASH chips; The lock detection circuit detects the target load power supply current of the baseband processing FPGA chip and related peripherals, the baseband processing CPU chip and related peripherals, and sends the periodic sampling data to the anti-fuse FPGA chip via the acquisition data bus. After data processing, judgment and comparison, the control signal is output to turn on / off the load power supply.

2. The satellite base station baseband processing board based on COTS devices according to claim 1, characterized in that: The RF direct acquisition transceiver chip uses the CX8242 chip, the baseband processing FPGA chip uses the XC7VX690T, and the baseband processing CPU chip uses the Feiteng eight-core D2000 processing chip.

3. The satellite base station baseband processing board based on COTS devices according to claim 2, characterized in that: For downlink baseband data processing, the baseband processing FPGA chip 1 receives the uplink baseband sampling data sent by the RF direct sampling transceiver CX8242 chip through the JESD204B interface. After completing the physical layer communication protocol processing of the uplink baseband sampling data, the processed data is sent to the baseband processing CPU chip 1 through the PCIE bus. After L2 and L3 layer protocol processing by the baseband processing CPU chip 1, the data is sent back to the baseband processing FPGA chip 1 through the PCIE bus interface, and then sent to the external routing board through the high-speed interface; among them, the uplink baseband sampling data sent by the RF direct sampling transceiver CX8242 chip comes from the external antenna array.

4. The satellite base station baseband processing board based on COTS devices according to claim 2, characterized in that: For uplink baseband data processing, the baseband processing CPU chip 2 is interconnected with the baseband processing FPGA chip 2 through the PCIE bus, and the receiving baseband processing FPGA chip 2 forwards the downlink communication data to be processed from the routing board. After being processed by the L2 and L3 layer protocols of the baseband processing CPU chip 2 and the physical layer protocol of the baseband processing FPGA chip 2, it is input to the RF direct sampling transceiver CX8242 chip through the JESD204B interface, and finally sent to the external transmitting antenna.

5. The satellite base station baseband processing board based on COTS devices according to claim 1, characterized in that: The baseband processing CPU chip 2 is also responsible for the management function of the baseband processing control plane. It exchanges control plane information with the baseband processing CPU chip 1 through the RGMII Ethernet interface, and receives control plane information forwarded by the baseband processing FPGA chip 2 through PCIE. After being processed by the baseband processing CPU chip 2, beam control information is formed, and sent back to the baseband processing FPGA chip 2 to generate control timing, and finally output to the antenna array beam control interface via RS422; among them, the control plane information forwarded by the baseband processing FPGA chip 2 comes from the control / command board.

6. The satellite base station baseband processing board based on COTS devices according to claim 1, characterized in that: The baseband processing FPGA chip 1 is configured with FLASH chip 1 and FLASH chip 2; the baseband processing FPGA chip 2 is configured with FLASH chip 3 and FLASH chip 4; the baseband processing CPU chip 1 and CPU chip 2 are configured with FLASH chip 5, FLASH chip 6, and FLASH chip 7.

7. The satellite base station baseband processing board based on COTS devices according to claim 6, characterized in that: The control anti-fuse FPGA chip is responsible for the configuration and loading of the programs of the baseband processing FPGA chip 1 and the baseband processing FPGA chip 2, and accesses the baseband processing FPGA chip 1 and the baseband processing FPGA chip 2 in a time-sharing manner through a dedicated program configuration interface; the dedicated program configuration interfaces of the two baseband processing FPGA chips are interconnected with the control anti-fuse FPGA; the control anti-fuse FPGA chip is externally connected to four FLASH chips for storing the configuration programs of the baseband processing FPGA chips; each two chips form a group of two groups, which are used for the baseband processing FPGA chip 1 and the baseband processing FPGA chip 2 respectively, and the FLASH chips configured in each group adopt a master-backup design to store the same configuration program; the control anti-fuse FPGA periodically reads back, compares and refreshes the configuration data of the baseband processing FPGA to reduce the probability of single particles occurring in the baseband processing FPGA.

8. The satellite base station baseband processing board based on COTS devices according to claim 1, characterized in that: The control anti-fuse FPGA chip is responsible for the configuration and loading of the programs of the baseband processing CPU chip 1 and the baseband processing CPU chip 2, and accesses the baseband processing CPU chip 1 and the baseband processing CPU chip 2 through an independent data bus; the control anti-fuse FPGA is externally connected to three baseband processing CPU configuration FLASH chips, and the three FLASH chips store the same baseband processing CPU configuration program; when the baseband processing CPU does not load the program, the control anti-fuse FPGA chip periodically reads the configuration programs in the three FLASH chips at the same time and compares them to achieve triple-mode redundant refresh; when the baseband processing CPU needs to load the program, the control anti-fuse FPGA chip stops the periodic comparison and refresh of the three FLASH chips, and defaults to selecting the first FLASH chip for loading the program for the baseband processing CPU chip 1, and defaults to selecting the second FLASH chip for loading the program for the baseband processing CPU chip 2. After the two CPU programs are loaded, the periodic comparison and refresh of the three FLASH chips are restarted.

9. The satellite base station baseband processing board based on COTS devices according to claim 1, characterized in that: The control anti-fuse FPGA chip is responsible for monitoring the reset of the entire board to prevent abnormal operation caused by single-particle flips. It has operation monitoring logic, AND logic, and CPU runaway monitoring logic inside. After the power-on initialization is completed, the control anti-fuse FPGA chip outputs a fixed-period square wave signal to the reset signal input terminal of the power-on reset monitoring chip through the internal operation monitoring logic. The power-on reset monitoring chip determines whether the working state of the control anti-fuse FPGA chip is normal through the reset pulse signal. If the output reset pulse signal is abnormal, the power-on reset monitoring chip outputs an overflow pulse signal to the control anti-fuse FPGA chip. The input overflow pulse signal and another external input hard reset signal of the control anti-fuse FPGA are internally ANDed, and then a reset trigger pulse is output to the trigger end of the power-on reset monitoring chip. The power-on reset monitoring chip outputs a reset signal, causing the internal monitoring logic of the control anti-fuse FPGA chip, baseband processing FPGA chip 1, base station processing FPGA chip 2, baseband processing CPU chip 1, and baseband processing CPU chip 2 to reset; The CPU runaway monitoring logic runs inside the control anti-fuse FPGA chip, and receives the reset pulses sent by the baseband processing CPU chip 1 and the baseband processing CPU chip 2 through the IO port. When the control anti-fuse FPGA monitors that the reset pulse is abnormal, it will output an abnormal reset signal. After the reset signal output by the power-on reset monitoring chip is passed through the control anti-fuse FPGA internal AND logic, it outputs the baseband processing CPU reset signal to the external CPU chip.

10. The satellite base station baseband processing board based on COTS devices according to claim 1, characterized in that: The lock detection circuit consists of a current detection amplifier circuit, a sampling circuit, a switch circuit and a lock judgment processing circuit; the input power supply passes through the sampling resistor in the current detection amplifier circuit and the switch tube in the switch circuit in turn to supply power to the target load; the current detection amplifier circuit detects the voltage across the sampling resistor, and sends it to the acquisition ADC after linear amplification; the sampling circuit sends the data to the anti-fuse FPGA in the lock judgment processing circuit, and after data processing, judgment and comparison, the switch control signal is output to the switch circuit for opening / closing operation, thereby realizing the monitoring and processing of the power latch status of the baseband processing FPGA, baseband processing CPU and configuration FLASH.

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