DFE tap adaptive acquisition method and device based on clock phase shift

Abstract

The present invention provides a method and device for adaptively acquiring DFE taps based on clock phase shift. The method includes: selecting a current TAP1 value based on a current TAP1 value adjustment range; outputting an eye diagram based on the currently selected TAP1 value, determining the vertex of the eye diagram, and adding an auxiliary decision line to the eye diagram based on the vertex; sequentially sampling data based on a sampling clock, and outputting a first mark or a second mark based on the positional relationship between each sampled data and the auxiliary decision line; adjusting the current TAP1 value adjustment range based on a comparison of the number of first marks and second marks within a preset time period; and looping back and forth through all of the above steps until a preset condition is met, thereby acquiring a final TAP1 value. By adding auxiliary lines and guiding the adjustment of the TAP1 value based on the position of the sampled data and the auxiliary lines, the present invention obtains the final TAP1 value through multiple adjustments until convergence. This allows the optimal TAP1 value to be adaptively selected based on different user scenarios, making the eye diagram bilaterally symmetrical and improving Jtol performance.

Description

Technical Field

[0001] The present invention relates to the field of signal processing technology, and in particular to a method, apparatus, device and storage medium for adaptively acquiring DFE taps based on clock phase shift. Background Art

[0002] DFE is commonly used in the SerDes (SERDES) receiver (RX) to eliminate inter-signal interference (ISI) caused by lossy channels. The DFE consists of a finite impulse response (FIR) filter, an adder, and a decision slicer for signal processing. For SerDes RX circuits, Jtol (Jtol) is a critical metric. Various communication protocols typically impose certain constraints and specifications on the Jtol of the receiver module. To achieve good Jtol in high-speed circuits, the DFE module is required to correctly slice and reassemble the data stream.

[0003] Figure 2 The data stream eye diagram after DFE slicing and reassembly is shown. The center eye diagram needs to be expanded as much as possible and kept as symmetrical as possible. This design will give the system as much margin as possible to meet the Jtol requirements of various communication protocols.

[0004] The TAP value refers to the taps within the DFE's internal structure. The DFE module stores a version of the data delayed by 1 to n clock cycles. Each tap, numbered i, corresponds to the data delayed by i cycles. Each tap value is sent back to the DFE input and subtracted from the original signal to eliminate ISI caused by the signal tail from the previous 1 to n clock cycles overlapping with the current bit signal.

[0005] In high-speed applications, due to process speed limitations and circuit architecture, the processing and calculation time of TAP1 in the FIR may exceed one UI, resulting in erroneous results. Therefore, TAP1 cannot use the same delayed feedback structure as TAP2 through TAPn to add or subtract input signals. To circumvent speed limitations, TAP1 in the existing architecture does not participate in feedback and addition. Instead, it directly subtracts a set value from the input signal in a static manner. The TAP1 set value is dependent on the parameters of the preceding channel.

[0006] In high-speed RX applications, the TAP1 value directly determines the symmetry of the eye diagram, which in turn directly determines Jtol performance. Currently, because the TAP1 value is manually set, in practice, customer environments and channel parameters are uncertain, making a fixed TAP1 value difficult to cover diverse customer scenarios. An unreasonable TAP1 value can compress the Jtol performance range, potentially causing RX to fail protocol requirements, increase bit error rates, or even lose lock, disrupting normal data communication. Summary of the Invention

[0007] The present invention aims to provide a method, apparatus, device, and storage medium for adaptively acquiring DFE taps based on clock phase shift to solve the above-mentioned technical problems. The method can adaptively select the optimal value of TAP1 according to different user scenarios, make the eye diagram bilaterally symmetrical, and improve Jtol performance.

[0008] In order to solve the above technical problems, the present invention provides a DFE tap adaptive acquisition method based on clock phase shift, comprising:

[0009] Select the current TAP1 value based on the current TAP1 value adjustment range;

[0010] Outputting an eye diagram based on the currently selected TAP1 value, determining a vertex of the eye diagram, and adding an auxiliary decision line in the eye diagram based on the vertex;

[0011] sequentially sampling data based on a sampling clock, and outputting a first mark or a second mark according to a positional relationship between each sampled data and the auxiliary determination line;

[0012] Adjust the current TAP1 value adjustment range according to the comparison relationship between the number of the first mark and the second mark within the preset time period;

[0013] Return to the loop and execute all the above steps until the preset conditions are met to obtain the final TAP1 value.

[0014] Furthermore, selecting the current TAP1 value based on the current TAP1 value adjustment range includes:

[0015] The current TAP1 value adjustment range is divided into a plurality of TAP1 optional values ​​based on preset equally divided intervals, the plurality of TAP1 optional values ​​are sorted, and the current TAP1 value is selected based on the middle position of the sorted plurality of TAP1 optional values.

[0016] Furthermore, the outputting of the eye diagram based on the currently selected TAP1 value, determining the vertex of the eye diagram, and adding an auxiliary decision line in the eye diagram based on the vertex specifically includes:

[0017] Outputting an eye diagram based on the currently selected TAP1 value, determining a vertex of the eye diagram, and adding horizontal and vertical auxiliary decision lines with the vertex as an origin, so that the eye diagram is divided into four quadrants by the auxiliary decision lines;

[0018] The method of sequentially sampling data based on a sampling clock and outputting a first mark or a second mark according to a positional relationship between each sampled data and the auxiliary determination line specifically includes:

[0019] Data sampling is performed sequentially based on a sampling clock. If the sampled data falls in the third quadrant corresponding to the auxiliary determination line, a first mark is output; if the sampled data falls in the first quadrant corresponding to the auxiliary determination line, a second mark is output.

[0020] Furthermore, the adjusting of the current TAP1 value adjustment range according to the comparison relationship between the number of the first mark and the number of the second mark within the preset time period includes:

[0021] If it is determined that the number of the first marks within the preset time period is greater than the number of the second marks, the current TAP1 value adjustment range is adjusted based on a range between a middle value and a maximum value of the current TAP1 value adjustment range;

[0022] If it is determined that the number of the first marks within the preset time period is not greater than the number of the second marks, the current TAP1 value adjustment range is adjusted based on a range between a middle value and a minimum value of the current TAP1 value adjustment range.

[0023] Furthermore, the step of satisfying a preset condition includes:

[0024] The maximum number of adjustments corresponding to the initial TAP1 value adjustment range is determined based on the dichotomy method. If it is determined that the number of adjustments to the current TAP1 value adjustment range reaches the maximum number of adjustments, it is determined that the preset condition is met.

[0025] Furthermore, the initial TAP1 value is adjusted in the range of 0 to 0.5.

[0026] Furthermore, the initial TAP1 value adjustment range is divided into 256 TAP1 optional values; the maximum number of adjustments corresponding to the initial TAP1 value adjustment range is 8 times.

[0027] The present invention also provides a DFE tap adaptive acquisition device based on clock phase shift, comprising:

[0028] A TAP1 value selection module is used to select the current TAP1 value based on the current TAP1 value adjustment range;

[0029] a decision line adding module, configured to output an eye diagram based on a currently selected TAP1 value, determine a vertex of the eye diagram, and add an auxiliary decision line to the eye diagram based on the vertex;

[0030] a data marking module, configured to sequentially sample data based on a sampling clock, and output a first mark or a second mark according to a positional relationship between each sampled data and the auxiliary determination line;

[0031] A range adjustment module, configured to adjust the current TAP1 value adjustment range according to a comparison relationship between the number of the first mark and the second mark within a preset time period;

[0032] The loop control module is used to return to loop and execute the steps corresponding to the TAP1 value selection module, the determination line adding module, the data marking module and the range adjustment module until a preset condition is met to obtain a final TAP1 value.

[0033] The present invention also provides a terminal device, comprising a processor and a memory storing a computer program, wherein when the processor executes the computer program, the method for adaptively acquiring DFE taps based on clock phase shift is implemented.

[0034] The present invention also provides a non-transitory computer-readable storage medium having a computer program stored thereon. When the computer program is executed by a processor, the method for adaptively acquiring DFE taps based on clock phase shift described in any one of the above is implemented.

[0035] Compared with the prior art, the present invention has the following beneficial effects:

[0036] The present invention provides a method, apparatus, device, and storage medium for adaptively acquiring DFE taps based on clock phase shift. The method comprises: selecting a current TAP1 value based on a current TAP1 value adjustment range; outputting an eye diagram based on the currently selected TAP1 value, determining the vertex of the eye diagram, and adding an auxiliary decision line to the eye diagram based on the vertex; sequentially sampling data based on a sampling clock, and outputting a first mark or a second mark based on the positional relationship between each sampled data and the auxiliary decision line; adjusting the current TAP1 value adjustment range based on a comparison of the number of first marks and second marks within a preset time period; and looping back and forth through all of the above steps until a preset condition is met, thereby obtaining a final TAP1 value. By adding auxiliary lines and guiding the adjustment of the TAP1 value based on the position of the sampled data and the auxiliary lines, the present invention obtains the final TAP1 value through multiple adjustments until convergence. This allows the optimal TAP1 value to be adaptively selected based on different user scenarios, making the eye diagram bilaterally symmetrical and improving Jtol performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] Figure 1 This is one of the flow charts of the DFE tap adaptive acquisition method based on clock phase shift provided by the present invention;

[0038] Figure 2 This is the data stream eye diagram after ISI is eliminated by DFE provided by the present invention;

[0039] Figure 3 This is a flow chart of the DFE signal processing process with n taps provided by the present invention;

[0040] Figure 4Schematic diagram of the waveform of the single-bit pulse signal input waveform VS with ISI after channel attenuation provided by the present invention;

[0041] Figure 5 Schematic diagram of the working principle of the three-tap DFE provided by the present invention;

[0042] Figure 6 3-TAP DFE input pulse and the modified waveform comparison diagram of the output pulse after DFE provided by the present invention;

[0043] Figure 7 This is a schematic diagram of the eye diagram judgment method provided by the present invention;

[0044] Figure 8 This is the second flow chart of the DFE tap adaptive acquisition method based on clock phase shift provided by the present invention;

[0045] Figure 9 This is the whole process of TAP1 in each stage provided by the present invention and the data flow eye diagram drawn using TAP1_final;

[0046] Figure 10 It is a structural diagram of a DFE tap adaptive acquisition device based on clock phase shift provided by the present invention. DETAILED DESCRIPTION

[0047] The following will provide a clear and complete description of the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of them. All other embodiments obtained by ordinary technicians in this field based on the embodiments of the present invention without making any creative efforts shall fall within the scope of protection of the present invention.

[0048] See Figure 1 The embodiment of the present invention provides a method for adaptively acquiring DFE taps based on clock phase shift, which may include the following steps:

[0049] S1. Select the current TAP1 value based on the current TAP1 value adjustment range;

[0050] S2. Output an eye diagram based on the currently selected TAP1 value, determine a vertex of the eye diagram, and add an auxiliary decision line to the eye diagram based on the vertex;

[0051] S3, sampling data sequentially based on a sampling clock, and outputting a first mark or a second mark according to a positional relationship between each sampled data and the auxiliary determination line;

[0052] S4. Adjust the current TAP1 value adjustment range according to the comparison relationship between the number of the first mark and the number of the second mark within the preset time period;

[0053] S5. Return to loop and execute steps S1 to S4 until the preset conditions are met, and obtain the final TAP1 value.

[0054] It is understandable that before executing step S1 for the first time, a preset initial TAP1 value adjustment range is first obtained as the "current TAP1 value adjustment range" for the first execution of S1; when executing step S5 and returning to step S1, the adjusted TAP1 value adjustment range is used as the "current TAP1 value adjustment range". Each time a TAP1 value is selected from the TAP1 value adjustment range, the middle value of the TAP1 value adjustment range can be selected as the TAP1 value of the current cycle, so as to reach a convergence state as quickly as possible and obtain the final TAP1 value. After adding auxiliary lines and outputting marks based on the sampled data, it can be determined whether the TAP1 value of the current cycle is too large or too small based on the number of the two marks, thereby guiding the adjustment of the TAP1 value adjustment range for the next time, and then obtaining the next more suitable TAP1 value, and so on until the TAP1 value that makes the eye diagram aligned is finally obtained.

[0055] In the embodiment of the present invention, further, selecting the current TAP1 value based on the current TAP1 value adjustment range includes:

[0056] The current TAP1 value adjustment range is divided into a plurality of TAP1 optional values ​​based on preset equally divided intervals, the plurality of TAP1 optional values ​​are sorted, and the current TAP1 value is selected based on the middle position of the sorted plurality of TAP1 optional values.

[0057] For example, the initial TAP1 value adjustment range may be divided into 256 values, and the 256 values ​​are sorted from largest to smallest, and the middle value is selected as the current TAP1 value.

[0058] In an embodiment of the present invention, further, outputting an eye diagram based on the currently selected TAP1 value, determining a vertex of the eye diagram, and adding an auxiliary decision line to the eye diagram based on the vertex specifically includes:

[0059] Outputting an eye diagram based on the currently selected TAP1 value, determining a vertex of the eye diagram, and adding horizontal and vertical auxiliary decision lines with the vertex as an origin, so that the eye diagram is divided into four quadrants by the auxiliary decision lines;

[0060] The method of sequentially sampling data based on a sampling clock and outputting a first mark or a second mark according to a positional relationship between each sampled data and the auxiliary determination line specifically includes:

[0061] Data sampling is performed sequentially based on a sampling clock. If the sampled data falls in the third quadrant corresponding to the auxiliary determination line, a first mark is output; if the sampled data falls in the first quadrant corresponding to the auxiliary determination line, a second mark is output.

[0062] In the embodiment of the present invention, further, adjusting the current TAP1 value adjustment range according to the comparison relationship between the number of the first mark and the number of the second mark within the preset time period includes:

[0063] If it is determined that the number of the first marks within the preset time period is greater than the number of the second marks, the current TAP1 value adjustment range is adjusted based on a range between a middle value and a maximum value of the current TAP1 value adjustment range;

[0064] If it is determined that the number of the first marks within the preset time period is not greater than the number of the second marks, the current TAP1 value adjustment range is adjusted based on a range between a middle value and a minimum value of the current TAP1 value adjustment range.

[0065] It should be noted that if the number of first marks is greater than the number of second marks, it indicates that the currently selected TAP1 value is too large, causing the vertex of the eye diagram to be shifted to the right. In this case, the TAP1 value should be appropriately reduced. Therefore, the right part of the current TAP1 value adjustment range should be selected as the TAP1 value adjustment range for the next cycle. Preferably, the current TAP1 value adjustment range can be adjusted based on the range between the middle value and the maximum value of the current TAP1 value adjustment range, so that the most appropriate TAP1 value can be obtained as quickly as possible based on the dichotomy principle.

[0066] In the embodiment of the present invention, further, the step of satisfying a preset condition includes:

[0067] The maximum number of adjustments corresponding to the initial TAP1 value adjustment range is determined based on the dichotomy method. If it is determined that the number of adjustments to the current TAP1 value adjustment range reaches the maximum number of adjustments, it is determined that the preset condition is met.

[0068] It should be noted that the cycle ends and the final TAP1 value is output when the preset condition is met. The preset condition can be a fixed number of cycles, or it can be determined based on the initial TAP1 value adjustment range. For example, if the initial TAP1 value adjustment range is divided into 256 grids, then based on the binary division principle, it can be determined that the corresponding maximum number of adjustments is 8 times.

[0069] In the embodiment of the present invention, further, the initial TAP1 value is adjusted in the range of 0 to 0.5.

[0070] In the embodiment of the present invention, further, the initial TAP1 value adjustment range is divided into 256 TAP1 optional values; the maximum number of adjustments corresponding to the initial TAP1 value adjustment range is 8 times.

[0071] It should be noted that the embodiment of the present invention adds auxiliary lines and guides the adjustment of the TAP1 value according to the position of the sampled data and the auxiliary lines. The final TAP1 value is obtained through multiple adjustments until convergence. This can adaptively select the optimal TAP1 value according to different user scenarios, make the eye diagram bilaterally symmetrical, and improve Jtol performance.

[0072] The following explains the relevant terms of the embodiments of the present invention:

[0073] Serdes: short for SERializer (serializer) / DESerializer (deserializer). Its specific function is: at the sending end, multiple low-speed parallel signals are converted into high-speed serial signals, which are then transmitted through the transmission media (optical cable or copper wire) and finally converted back into low-speed parallel signals at the receiving end.

[0074] RX: RX receive is short for communication receiving unit in Chinese. In this article, it specifically refers to the receiving module in the Serdes communication system.

[0075] Channel loss: Channel attenuation is the distortion of signal amplitude and phase caused by the physical non-ideality of the signal path. Excessive channel loss makes the signal difficult for the receiver to identify, resulting in bit errors.

[0076] DFE (Decision Feedback Equalizer) is commonly used in SerDes (Serdes) receivers (RXs). Through a specific circuit structure and digital algorithm, DFE delays the signal by n clock cycles to obtain different tap values, which are then fed back to the input signal for addition and subtraction, thereby eliminating inter-signal interference (ISI) caused by lossy channels.

[0077] ISI stands for intersymbol interference. During data transmission, as the data rate increases, the interval between consecutive data decreases, causing signal quality to deteriorate. To a certain extent, the overlapping data cannot be accurately distinguished, resulting in ISI.

[0078] TAP1 to TAPn specifically refer to taps within the DFE. The DFE module stores data delayed by 1 to n clock cycles. Each tap, numbered i, corresponds to data delayed by i cycles. The value of each tap is sent back to the DFE input and subtracted from the original signal to eliminate ISI caused by the signal tail from the previous 1 to n clock cycles overlapping with the current bit signal.

[0079] BER: Bit Error Ratio, also known as bit error rate, is the number of erroneous bits divided by the total number of bits transmitted during a study time interval, usually expressed as a percentage.

[0080] Jitter tolerance (Jtol) characterizes the ability of a communication system or device interface (including electrical and optical interfaces) to withstand input jitter. A sinusoidally modulated random sequence is typically used as the input test sequence. The jitter tolerance is defined as the amplitude of sinusoidal jitter that produces a specified degradation in error performance (such as error power penalty and error occurrence criteria). Various communication protocols typically impose specific constraints and regulatory requirements on the Jtol of receiver modules.

[0081] FIR filter: Finite length unit impulse response filter.

[0082] Summer: Adder, in this article, specifically refers to a circuit module that provides addition and subtraction between signals.

[0083] Slicer: Slicer.

[0084] Eye diagram: A graph obtained by overlapping the waveforms of each code element obtained by scanning the data stream.

[0085] UI: Short for unit, the code element time length of one bit is 1UI.

[0086] The following further describes the background technology related to the embodiments of the present invention:

[0087] 1) The functional description of DFE is as follows: Figure 3 An example of an n-tap DFE is shown, k is the input signal. Due to channel loss, ISI, noise and other non-ideal factors superimposed on the signal, y k The eye diagram formed by the superposition of 1 (high level) and 0 (low level) of the data is of poor quality (eye diagram at the label), and the data cannot be correctly read by the subsequent receiving end. By adding a DFE structure for feedback calculation, the z behind the adder k The eyelids in the signal are stretched, and the judgment slicer can normally judge the data of 1 level and 0 level, so d kCan output correct data.

[0088] 2) The principle by which DFE can widen the eye diagram and improve signal quality is described as follows: Figure 4 The ideal single-bit pulse signal Drxinput at the RX input port is shown, and the waveform Dloss is formed after the RX channel is superimposed with non-ideal factors such as ISI and channel loss. As a demonstration, the Dloss signal is used as Figure 5 The input of a three-tap DFE is shown. First, the ISI interference caused by the superposition of the current signal with the past signal is obtained by using the FIR module through three levels of delay and multiplication by the corresponding coefficients (C0, C1, C2), where the signs of C0, C1, and C2 are given by the previous slicer decision. Then, the interference is subtracted from the input signal using a summer (adder). Finally, the slicer (slicer) decides and sends the signal back to the FIR module. In this example, if the sampling time point of the current signal is t[0], TAP=3 means that the ISI that can be eliminated by the DFE is the impact of the code signal at time t[-1], t[-2], and t[-3] on the signal at t[0]. The more TAPs, the more impact of past code symbols can be eliminated.

[0089] From the principle explanation, it can be seen that the parameter selection of C0, C1, C2...Cn is very important. The ideal DFE state is to just eliminate the impact of ISI at the moment of each sampling. Figure 6 The following figure shows a comparison of the corrected waveforms of the input pulse and the output pulse after DFE, with ideal values ​​for C0-C2. Each "×" in the figure represents the current sampling point. By accurately selecting C0-C2, the system successfully eliminates third-order ISI and acquires accurate data at sampling points T0-T3. The schematic also shows that the value of TAP1 is generally larger than that of the other TAP taps.

[0090] It should be noted that in the above-mentioned existing technical solutions, the TAP1 value is manually set. However, in actual applications, customer environments and channel parameters are uncertain, and a fixed TAP1 value is difficult to cover different customer application scenarios. An unreasonable TAP1 value will compress the Jtol performance range, potentially causing RX to fail to meet protocol requirements, increase bit error rates, or even lose lock, preventing normal data communication.

[0091] To facilitate a better understanding of the DFE tap adaptive acquisition method based on clock phase shift provided by an embodiment of the present invention, the following is a detailed description:

[0092] In this circuit, the minimum value of TAP1 is 0 and the maximum value is 0.5. The digital algorithm divides the entire TAP1 adjustment range into 256 grids, each of which is 0.001953125. The algorithm is based on the following: Figure 7 As shown, decision lines x and y divide the eye diagram into four quadrants from the vertex. The algorithm focuses on only one quadrant. If the sampled data is in the third quadrant, the sampling point is to the left, and the decision logic outputs a 1. If the sampled data is in the first quadrant, the sampling point is to the right, and the decision logic outputs a 0. During the algorithm loop, the TAP1 value is adjusted, and the decision line is adjusted accordingly. The clock phase is shifted, and the number of 1s and 0s during the entire period is counted and compared. This in turn guides the next TAP1 adjustment. After several iterations, a final TAP1 value is obtained, at which the decision logic outputs an equal number of 1s and 0s, indicating a symmetrical eye diagram.

[0093] For example, the sampling process means: the edge of the data sampling clock hits once, and the sampled data is output. Figure 7 The arrow is the data sampling clock position. Click it to see the current edge position of the eye. If it is below the decision line x, the decision logic will output 1. If it is above the decision line, the decision logic will output 0.

[0094] It should be noted that, in the embodiment of the present invention, the Y line is not a real line, and without the X line, it will be impossible to distinguish left from right. Figure 7 The top of the eye is drawn downward simply to better illustrate the four quadrants. In this embodiment, quadrants 2 and 4 are obscured from view, leaving only quadrants 1 and 3. Only X-rays are truly achievable by the circuit. Therefore, left and right are actually distinguished by X-rays.

[0095] Each time the TAP1 value is adjusted, an algorithm automatically searches for a new vertex. The position of this vertex is strongly correlated with the TAP1 value. A larger TAP1 value shifts the vertex to the left, while a smaller value shifts it to the right. Our goal is to find a reasonable TAP1 value through repeated convergence, placing the vertex in the center of the UI. This means that the inner eyelid, the innermost part of the eye diagram, appears symmetrical on both sides.

[0096] Combined with the circuit architecture, the specific algorithm flow of this solution is as follows Figure 8 As shown, the basic steps include:

[0097] Step 1: Select an initial TAP1 value (usually a value in the middle of the initial adjustable range) and set the loop counter to 0. The TAP1 value is evenly divided into 256 parts and stored in a number D of length 256. The transformation of each number in the array is D[0], D[1], ...D

[255] .

[0098] Step 2: Using the selected TAP1 value, with the current clock position as the counting origin, continuously move the clock. Count the number of 0s and 1s output by the decision logic within a certain period (wtime).

[0099] Step 3: If the number of 1s output in one cycle > the number of 0s output, it means that the current eye diagram vertex is biased to the right and the initial value of TAP1 is too high. The TAP1 for the next cycle is modified as follows: Execute the instruction H = mid - 1 (to determine the upper limit of the adjustable range after adjustment), and adjust the TAP1 value according to the middle value of the adjusted adjustable range; if the number of 1s < the number of 0s, it means that the current eye diagram vertex is biased to the left and the initial value of TAP1 is too low. The TAP1 for the next cycle is modified as follows: Execute the instruction L = mid + 1 (to determine the lower limit of the adjustable range after adjustment), and adjust the TAP1 value according to the middle value of the adjusted adjustable range. At this time, the loop counter counter = counter + 1.

[0100] Step 4: Determine whether the value of the loop counter meets the specified condition (for example, the number of loops reaches 8 times). If it does not meet the condition, update the TAP1 value and return to step 2 to rescan and count the number of 0s and 1s, make a determination through step 3, and update the TAP1 value; if the condition is met, determine that the entire search process is completed and output the finally found TAP1_final value.

[0101] It should be noted that H = mid - 1 means that the value of H is updated to mid - 1. For example, Figure 8 in, for the first time, L = 0, H = 256, at this time mid = 128, Tap1 selects the value within the array D

[128] , and then goes down continuously; if count is less than 8 and sum0 < sum1, then execute H = mid - 1, at this time H is updated to 128 - 1 = 127; follow the arrow back, the mid value uses the newly updated L and H, and becomes (0 + 127) / 2 to take the integer = 63, Tap1 selects D

[63] (note that the D array count starts from 0, so the actually selected is the 64th number). For the embodiment of the present invention, the number of loops is 8 times. Due to dividing TAP1 into 256 grids, according to the principle of the dichotomy method, after 8 loops, the entire dichotomy search path can be completed.

[0102] Figure 9 Shows the whole process of the entire search algorithm. The right half of the figure is the data stream eye diagram drawn using TAP1_final. It can be seen that the adaptively calculated TAP1 successfully achieves the left - right symmetry of the inner eye.

[0103] Compared with the prior art, the TAP1 adaptive algorithm based on phase determination in the embodiment of the present invention has the following advantages: reliable determination conditions, simple algorithm, no need to add additional circuit costs, and TAP1 search can be achieved solely by digital software.

[0104] It should be noted that for the above method or process embodiments, for the sake of simplicity, they are all expressed as a series of action combinations, but those skilled in the art should be aware that the embodiments of the present invention are not limited by the order of the actions described, because according to the embodiments of the present invention, certain steps can be performed in other orders or simultaneously. Secondly, those skilled in the art should also be aware that the embodiments described in this specification are all optional embodiments, and the actions involved are not necessarily required by the embodiments of the present invention.

[0105] See Figure 10 The embodiment of the present invention further provides a DFE tap adaptive acquisition device based on clock phase shift, comprising:

[0106] A TAP1 value selection module 1 is used to select a current TAP1 value based on a current TAP1 value adjustment range;

[0107] a decision line adding module 2, configured to output an eye diagram based on the currently selected TAP1 value, determine a vertex of the eye diagram, and add an auxiliary decision line to the eye diagram based on the vertex;

[0108] A data marking module 3 is configured to sequentially sample data based on a sampling clock, and output a first mark or a second mark according to a positional relationship between each sampled data and the auxiliary determination line;

[0109] Range adjustment module 4, used to adjust the current TAP1 value adjustment range according to the comparison relationship between the number of the first mark and the second mark within a preset time period;

[0110] The loop control module 5 is used to return to loop and execute the steps corresponding to the TAP1 value selection module, the determination line adding module, the data marking module and the range adjustment module until a preset condition is met to obtain a final TAP1 value.

[0111] It can be understood that the above-mentioned device embodiment corresponds to the method embodiment of the present invention. The DFE tap adaptive acquisition device based on clock phase shift provided in the embodiment of the present invention can implement the DFE tap adaptive acquisition method based on clock phase shift provided in any method embodiment of the present invention.

[0112] The present invention also provides a non-transitory computer-readable storage medium having a computer program stored thereon. When the computer program is executed by a processor, the method for adaptively acquiring DFE taps based on clock phase shift described in any one of the above is implemented.

[0113] It should be noted that the device embodiments described above are merely illustrative, wherein the units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, they may be located in one place, or they may be distributed across multiple network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the present embodiment. In addition, in the drawings of the device embodiments provided by the present invention, the connection relationship between the modules indicates that there is a communication connection between them, which may be specifically implemented as one or more communication buses or signal lines. A person of ordinary skill in the art can understand and implement the present invention without inventive effort.

[0114] Those skilled in the art will clearly understand that for the sake of convenience and brevity, the specific working process of the device described above can refer to the corresponding process in the aforementioned method embodiment, and will not be repeated here.

[0115] The terminal device may be a computing device such as a desktop computer, a notebook computer, a PDA, a cloud server, etc. The terminal device may include, but is not limited to, a processor and a memory.

[0116] The processor may be a central processing unit (CPU), other general-purpose processors, digital signal processors (DSP), application-specific integrated circuits (ASIC), field-programmable gate arrays (FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. The general-purpose processor may be a microprocessor or any conventional processor, etc. The processor is the control center of the terminal device, connecting various parts of the entire terminal device using various interfaces and lines.

[0117] The memory can be used to store the computer program, and the processor realizes various functions of the terminal device by running or executing the computer program stored in the memory and calling the data stored in the memory. The memory can mainly include a program storage area and a data storage area, wherein the program storage area can store an operating system, at least one application required for a function, etc.; the data storage area can store data created based on the use of the mobile phone, etc. In addition, the memory can include a high-speed random access memory and can also include a non-volatile memory, such as a hard disk, a memory, a plug-in hard disk, a smart memory card (Smart Media Card, SMC), a secure digital (Secure Digital, SD) card, a flash card (Flash Card), at least one disk storage device, a flash memory device, or other volatile solid-state storage device.

[0118] The storage medium is a computer-readable storage medium, and the computer program is stored in the computer-readable storage medium. When the computer program is executed by the processor, it can implement the steps of the above-mentioned various method embodiments. The computer program includes computer program code, and the computer program code can be in source code form, object code form, executable file or some intermediate form. The computer-readable medium may include: any entity or device that can carry the computer program code, recording medium, USB flash drive, mobile hard disk, magnetic disk, optical disk, computer memory, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), electric carrier signal, telecommunication signal and software distribution medium. It should be noted that the content contained in the computer-readable medium can be appropriately increased or decreased according to the requirements of legislation and patent practice in the jurisdiction. For example, in some jurisdictions, according to legislation and patent practice, computer-readable media do not include electric carrier signals and telecommunication signals.

[0119] The above is a preferred embodiment of the present invention. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principles of the present invention. These improvements and modifications are also considered to be within the scope of protection of the present invention.

Claims

1. A DFE tap adaptive acquisition method based on clock phase shift, characterized in that: include: Select the current TAP1 value based on the current TAP1 value adjustment range; Outputting an eye diagram based on the currently selected TAP1 value, determining a vertex of the eye diagram, and adding an auxiliary decision line to the eye diagram based on the vertex, wherein the method specifically includes: outputting an eye diagram based on the currently selected TAP1 value, determining a vertex of the eye diagram, and adding horizontal and vertical auxiliary decision lines with the vertex as an origin, so that the eye diagram is divided into four quadrants by the auxiliary decision lines; The method includes sequentially sampling data based on a sampling clock, and outputting a first mark or a second mark according to a positional relationship between each sampled data and the auxiliary determination line, wherein the method specifically includes: sequentially sampling data based on a sampling clock, and outputting a first mark if the sampled data falls in the third quadrant corresponding to the auxiliary determination line, and outputting a second mark if the sampled data falls in the first quadrant corresponding to the auxiliary determination line; Adjust the current TAP1 value adjustment range according to the comparison relationship between the number of the first mark and the second mark within the preset time period; Return to the loop and execute all the above steps until the preset conditions are met to obtain the final TAP1 value.

2. The method for adaptively acquiring DFE taps based on clock phase shift according to claim 1, wherein: The selecting of the current TAP1 value based on the current TAP1 value adjustment range includes: The current TAP1 value adjustment range is divided into a plurality of TAP1 optional values ​​based on preset equally divided intervals, the plurality of TAP1 optional values ​​are sorted, and the current TAP1 value is selected based on the middle position of the sorted plurality of TAP1 optional values.

3. The method for adaptively acquiring DFE taps based on clock phase shift according to claim 1, wherein: The adjusting of the current TAP1 value adjustment range according to the comparison relationship between the number of the first mark and the number of the second mark within the preset time period includes: If it is determined that the number of the first marks within the preset time period is greater than the number of the second marks, the current TAP1 value adjustment range is adjusted based on a range between a middle value and a maximum value of the current TAP1 value adjustment range; If it is determined that the number of the first marks within the preset time period is not greater than the number of the second marks, the current TAP1 value adjustment range is adjusted based on a range between a middle value and a minimum value of the current TAP1 value adjustment range.

4. The method for adaptively acquiring DFE taps based on clock phase shift according to claim 1, wherein: The method of satisfying the preset conditions includes: The maximum number of adjustments corresponding to the initial TAP1 value adjustment range is determined based on the dichotomy method. If it is determined that the number of adjustments to the current TAP1 value adjustment range reaches the maximum number of adjustments, it is determined that the preset condition is met.

5. The method for adaptively acquiring DFE taps based on clock phase shift according to claim 4, wherein: The initial TAP1 value is adjusted from 0 to 0.

5.

6. The method for adaptively acquiring DFE taps based on clock phase shift according to claim 4, wherein: The initial TAP1 value adjustment range is divided into 256 TAP1 optional values; the maximum number of adjustments corresponding to the initial TAP1 value adjustment range is 8 times.

7. A DFE tap adaptive acquisition device based on clock phase shift, characterized in that: include: A TAP1 value selection module is used to select the current TAP1 value based on the current TAP1 value adjustment range; a determination line adding module, configured to output an eye diagram based on a currently selected TAP1 value, determine a vertex of the eye diagram, and add auxiliary determination lines to the eye diagram based on the vertex, wherein the module specifically includes: outputting an eye diagram based on the currently selected TAP1 value, determining a vertex of the eye diagram, and adding horizontal and vertical auxiliary determination lines with the vertex as an origin, so that the eye diagram is divided into four quadrants by the auxiliary determination lines; a data marking module, configured to sequentially sample data based on a sampling clock and output a first mark or a second mark based on the positional relationship between each sampled data and the auxiliary determination line, wherein the module specifically includes: sequentially sampling data based on the sampling clock, outputting a first mark if the sampled data falls in the third quadrant corresponding to the auxiliary determination line, and outputting a second mark if the sampled data falls in the first quadrant corresponding to the auxiliary determination line; A range adjustment module, configured to adjust the current TAP1 value adjustment range according to a comparison relationship between the number of the first mark and the second mark within a preset time period; The loop control module is used to return to loop and execute the steps corresponding to the TAP1 value selection module, the determination line adding module, the data marking module and the range adjustment module until a preset condition is met to obtain a final TAP1 value.

8. A terminal device comprising a processor and a memory storing a computer program, characterized in that: When the processor executes the computer program, the DFE tap adaptive acquisition method based on clock phase shift according to any one of claims 1 to 6 is implemented.

9. A non-transitory computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the method for adaptively acquiring DFE taps based on clock phase shift according to any one of claims 1 to 6 is implemented.

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