A pixel-level focal plane readout circuit and its random window implementation circuit and method

Abstract

The application discloses a pixel-level focal plane readout circuit and a random window implementation circuit and method thereof, and belongs to the technical field of microelectronics and optoelectronics.The random window implementation circuit comprises a row selection signal generator, a column selection signal generator and a plurality of pixel control circuits.The random window implementation circuit has simple structure, can realize random window of the pixel-level focal plane readout circuit, and can be used only once after being configured once after starting, so that the power consumption and error code rate of the circuit can be greatly reduced.In addition, the application sets the pixel control circuit for each pixel of the pixel-level focal plane array, prevents selecting unnecessary windows when realizing multi-window selection output, and improves the working efficiency of the readout circuit and the detection efficiency of the detector.

Description

A pixel-level focal plane readout circuit and its random window implementation circuit and method Technical Field

[0001] This invention belongs to the fields of microelectronics and optoelectronics, specifically relating to a pixel-level focal plane readout circuit and its random window implementation circuit and method. Background Technology

[0002] The infrared readout circuit is an important component of the infrared detector. It provides bias voltage to the infrared detection pixels and outputs the conversion results in a certain order, which is the basis for the detector to realize various functions.

[0003] Pixel-level readout circuitry refers to a circuit where each pixel module integrates an analog-to-digital converter (ADC), and all ADCs operate in parallel to convert all pixel data in one operation. Column-level readout circuitry refers to a circuit where one or more columns of pixels share a single ADC, and all ADCs operate in parallel to convert one or more columns of pixel data in one operation.

[0004] Windowing refers to selecting a region of interest within a large-scale infrared focal plane array for output, instead of outputting the entire array's data. Windowing is generally divided into fixed windowing and random windowing. Fixed windowing refers to a window of fixed size and area; random windowing refers to a window whose position and size can be changed as needed. Multiple random windows allow for simultaneous readout of multiple windows, significantly improving detector efficiency when detecting multiple targets simultaneously.

[0005] With the continuous development of infrared detector technology, infrared focal plane arrays have evolved from the initial 320×240 to the commonly seen 1024×1024, and even ultra-large-scale detector arrays can reach 2048×2048. Simultaneously, the output frame rate has increased from the initial 25 frames per second to 60 frames per second. However, as the array size and output frame rate increase, the clock frequency required for the readout circuit increases significantly. Meanwhile, the progress in integrated circuit manufacturing technology is not significant, making the design of the readout circuit increasingly difficult. The substantial increase in clock frequency also brings problems related to power consumption and area. Therefore, windowing functionality can be used to control a portion of the output area, thereby increasing the frame rate and resolving the contradiction between frame rate and array size to some extent.

[0006] However, traditional column-level windowing readout circuits require shifting through a shift register to select pixels each time a window is opened, resulting in high power consumption and a high bit error rate. In addition, traditional column-level windowing readout circuits are complex to implement when opening multiple windows simultaneously, and usually require the introduction of a state machine. Summary of the Invention

[0007] To address the problems of high power consumption, high bit error rate, and complex implementation of traditional windowed readout circuits, this invention provides a pixel-level focal plane readout circuit and its random window implementation circuit and method.

[0008] This invention is achieved through the following technical solution:

[0009] A random window implementation circuit for a pixel-level focal plane readout circuit includes a row selection signal generator, a column selection signal generator, and several pixel control circuits.

[0010] The row selection signal generator is used to generate row selection signals, and the column selection signal generator is used to generate column selection signals;

[0011] Both the row selection signal generator and the column selection signal generator include a counter, a comparator, a selector, and a shift register;

[0012] The counter is used to count the cell addresses;

[0013] The comparator is used to determine whether the cell address output by the counter is within the windowed area, and inputs the determination result into the selector;

[0014] The selector is used to receive the judgment result of the comparator. If the cell address is within the window area, it outputs a high level; otherwise, it outputs a low level and inputs the result to the shift register.

[0015] The shift register is used to receive the output data of the selector and perform serial-to-parallel conversion to obtain a series of row / column selection signals;

[0016] Furthermore, the counter and shift register operate synchronously;

[0017] Each pixel is provided with a pixel control circuit, which controls the on / off state of the pixel signal by adding a transmission gate to the corresponding pixel to prevent the selection of unselected pixels.

[0018] The random window implementation circuit structure used in this invention is simple and can realize random windows in the pixel-level focal plane readout circuit. It only needs to be configured once after power-on to obtain the corresponding row and column selection signals, and then it can be discarded, significantly reducing circuit power consumption and bit error rate. Furthermore, this invention also prevents the selection of unwanted windows when implementing multi-window selection output by setting a pixel control circuit for each pixel of the pixel-level focal plane array, thereby improving the working efficiency of the readout circuit and the detection efficiency of the detector.

[0019] In a preferred embodiment, the pixel control circuit of the present invention includes a three-input AND gate, a selector A, a selector B, a latch, a transmission gate, and an inverter.

[0020] The input terminals of the three-input AND gate are the row selection signal, column selection signal, and multi-window configuration signal of a single pixel, and the output terminal of the three-input AND gate is connected to the data selection terminal of the selector A.

[0021] The two input terminals of selector A are connected to a low level and a high level, respectively, and the output terminal of selector A is connected to a data input terminal of selector B.

[0022] The two data input terminals of selector B are respectively connected to the output terminal and the high level of selector A. The output terminal of selector B is connected to the data input terminal of the latch. The data selection terminal of selector B receives the window opening signal.

[0023] The data input terminal of the latch is connected to the output terminal of the selector B, the enable input terminal of the latch is connected to the multi-window configuration signal, and the output terminal of the latch is connected to the positive phase control terminal of the transmission gate and the input terminal of the inverter.

[0024] The input terminal of the transmission gate is connected to the pixel signal, the output terminal of the transmission gate is connected to the pixel signal, the positive phase control terminal of the transmission gate is connected to the output terminal of the latch, and the negative phase control terminal of the transmission gate is connected to the output terminal of the inverter.

[0025] The input terminal of the inverter is connected to the output terminal of the latch, and the output terminal of the inverter is connected to the inversion control terminal of the transmission gate.

[0026] In a preferred embodiment, the counter of the present invention is a modulo-N binary counter, where N is the number of rows or columns of the readout circuit.

[0027] In a preferred embodiment, the comparator of the present invention outputs a high level when the window opening start coordinate is less than or equal to the address and the window opening end coordinate is greater than the address; otherwise, it outputs a low level.

[0028] In a preferred embodiment, the comparator of the present invention employs a three-input comparator, which is implemented by cascading multiple two-input comparators with an adder.

[0029] In a preferred embodiment, the counter and the shift register of the present invention are both controlled by the master clock of the readout circuit and the reset signal to achieve synchronous operation. When the row / column selection signal for windowing begins to be generated, the reset signal is valid, and the counter and the shift register are reset to the initial state. A data change occurs once after each clock trigger.

[0030] In a preferred embodiment, the depth of the shift register of the present invention is N, where N is the number of rows or columns of the readout circuit.

[0031] Secondly, the present invention proposes a pixel-level focal plane readout circuit, which uses the above-mentioned random window implementation circuit to realize random window output.

[0032] Thirdly, this invention proposes a method for generating row / column selection signals based on the above-mentioned random window implementation circuit, the method comprising:

[0033] initialization;

[0034] Input window configuration signals, including window size and coordinates;

[0035] The input signal of the shift register is changed by comparing the address signal with the position of the window using a comparator until the address signal reaches the upper limit.

[0036] Fourthly, this invention proposes a multi-window implementation method based on the above-mentioned random window implementation circuit, the method comprising:

[0037] initialization;

[0038] The window opening signal is set to low level;

[0039] Input the size and coordinates of N windows, where N is an integer greater than or equal to 2;

[0040] The multi-window configuration signal is set to high level. The row and column addresses of window 1 are used to generate the corresponding row and column selection signals and close the transmission gate corresponding to window 1. Then, the row and column addresses of window 2 are used to generate the corresponding row and column selection signals and close the transmission gate corresponding to window 2. This process continues until the transmission gates corresponding to N windows are closed.

[0041] When the multi-window configuration signal is set to low, the corresponding row and column selection signals are generated using the row and column addresses of the N windows respectively. At this time, only the pixels with closed transmission gates will be selected.

[0042] Compared with the prior art, the present invention has the following advantages and beneficial effects:

[0043] 1. The random window implementation circuit proposed in this invention can realize the random window of the pixel-level focal plane readout circuit. It only needs to be configured once after power-on to generate the corresponding row and column selection signals, and then it can be discarded. This can greatly reduce the power consumption and bit error rate of the circuit and improve the working efficiency and reliability of the readout circuit.

[0044] 2. The random window implementation circuit proposed in this invention can realize the simultaneous opening of multiple windows. By setting a pixel control circuit on the pixel, it prevents the selection of unwanted windows, effectively improving the working efficiency of the readout circuit and the detection efficiency of the detector.

[0045] 3. The random window implementation circuit proposed in this invention only requires the configuration of the switch signal once during operation. It is configured once during power-on initialization. As long as the subsequent window information remains unchanged, the required window can be selected by using the row and column selection signals of the second stage of multi-window operation. The implementation method is simple. Attached Figure Description

[0046] The accompanying drawings, which are included to provide a further understanding of embodiments of the invention and form part of this application, do not constitute a limitation thereof. In the drawings:

[0047] Figure 1 is a schematic diagram of the overall structure of the random window implementation circuit according to an embodiment of the present invention.

[0048] Figure 2 is a schematic diagram of the pixel control circuit structure according to an embodiment of the present invention.

[0049] Figure 3 is a timing diagram of the row and column selection signals in an embodiment of the present invention.

[0050] Figure 4 is a flowchart of the process for generating row and column selection signals according to an embodiment of the present invention.

[0051] Figure 5 is a schematic diagram of row and column selection of multiple windows according to an embodiment of the present invention.

[0052] Figure 6 is a flowchart of the process of opening multiple windows according to an embodiment of the present invention.

[0053] Figure reference numerals and corresponding component names:

[0054] 10 - Counter, 20 - Comparator, 30 - Selector, 40 - Shift register, 50 - Pixel control circuit, 501 - Three-input AND gate, 502 - Selector A, 503 - Selector B, 504 - Transmission gate, 505 - Inverter, 506 - Latch. Detailed Implementation

[0055] In the following, the terms “comprising” or “may include” as used in various embodiments of the invention indicate the presence of an inventive function, operation, or element, and do not limit the addition of one or more functions, operations, or elements. Furthermore, as used in various embodiments of the invention, the terms “comprising,” “having,” and their cognates are intended only to indicate a specific feature, number, step, operation, element, component, or combination of the foregoing, and should not be construed as primarily excluding the presence of one or more other features, numbers, steps, operations, elements, components, or combinations of the foregoing, or adding one or more combinations of the foregoing.

[0056] In various embodiments of the invention, the expression "or" or "at least one of A and / or B" includes any combination or all combinations of the words listed simultaneously. For example, the expression "A or B" or "at least one of A and / or B" may include A, may include B, or may include both A and B.

[0057] The expressions used in the various embodiments of the present invention (such as "first," "second," etc.) may modify various constituent elements in the various embodiments, but do not limit the corresponding constituent elements. For example, the above expressions do not limit the order and / or importance of the elements. The above expressions are only used for the purpose of distinguishing one element from other elements. For example, a first user device and a second user device refer to different user devices, although both are user devices. For example, a first element may be referred to as a second element without departing from the scope of the various embodiments of the present invention, and similarly, a second element may also be referred to as a first element.

[0058] It should be noted that if a description is made of "connecting" one component to another, then the first component can be directly connected to the second component, and a third component can be "connected" between the first and second components. Conversely, when a component is "directly connected" to another component, it can be understood that there is no third component between the first and second components.

[0059] The terminology used in the various embodiments of the invention is for the purpose of describing particular embodiments only and is not intended to limit the various embodiments of the invention. As used herein, the singular form is intended to include the plural form as well, unless the context clearly indicates otherwise. Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art to which the various embodiments of the invention pertain. The terms (such as those defined in a generally used dictionary) are to be interpreted as having the same meaning as in the context of the relevant technical field and are not to be interpreted as having an idealized or overly formal meaning, unless clearly defined in the various embodiments of the invention.

[0060] To make the objectives, technical solutions, and advantages of the present invention clearer, the present invention will be further described in detail below with reference to the embodiments and accompanying drawings. The illustrative embodiments and descriptions of the present invention are only used to explain the present invention and are not intended to limit the present invention.

[0061] Example:

[0062] Traditional column-level windowing readout circuits typically include a counter, adder, selector, decoder, and shift register. The operation is as follows: after receiving the windowing configuration information, the counter and adder obtain the corresponding row and column selection coordinates. The coordinates of the starting point are decoded by the decoder to obtain the row and column selection signal of the starting point coordinates. Then, the shift register is used to shift the value to select the windowed pixel. It can be seen that traditional column-level windowing readout circuits require shifting the value through the shift register each time a window is opened, resulting in high power consumption and bit error rate. Based on this, this embodiment proposes a random window implementation circuit for pixel-level focal plane readout circuits. This random window implementation circuit receives the configuration signals for the window position and size, outputs the row and column selection signals and pixel control signals, and can realize random windows in the pixel-level focal plane readout circuit. After configuration only once after power-on to obtain the corresponding row and column selection signals, it can be discontinued, significantly reducing power consumption and bit error rate.

[0063] As shown in Figure 1, the random window implementation circuit proposed in this embodiment includes a row selection signal generator, a column selection signal generator, and several pixel control circuits 50; wherein, both the row selection signal generator and the column selection signal generator include a counter 10, a comparator 20, a selector 30, and a shift register 40.

[0064] The counter 10 is used to count the row and column addresses of the pixels, and the row and column pixels are counted separately. The counter 10 includes a reset terminal, a clock input terminal and a counting signal output terminal. The reset terminal and the clock input terminal are respectively connected to the reset terminal and the clock terminal of the readout circuit, and the counting signal output terminal is connected to the input terminal of the comparator 20.

[0065] Counter 10 uses binary counting to count the current row and column coordinate positions. Its working principle is as follows: when the row and column selection signals for windowing are generated, the reset signal is valid and the counter is reset to the initial state. After the clock signal arrives, the clock signal controls the address counter to increment by 1. When the row and column addresses are calculated to the maximum value, they remain unchanged.

[0066] The counter 10 in this embodiment can be, but is not limited to, a modulo-N binary counter. Here, N is the number of rows or columns of the readout circuit. A binary counter means that the counter's output is in binary form, and the data changes once after each clock trigger. It should be noted that the counter 10 can also be other counters commonly used in the art; their specific structures will not be detailed here.

[0067] Comparator 20 is used to determine whether the cell row and column address is within the windowed area and inputs the determination result to selector 30. Comparator 20 includes two input terminals and one output terminal. The two input terminals are respectively input to window configuration information and output information of counter 10 output terminal. The output terminal is connected to the data selection port of selector 30.

[0068] Comparator 20 compares whether the row address or column address is within the window area. If the starting coordinate of the window opening is less than or equal to the address (i.e., the row address or column address) and the ending coordinate of the window opening is greater than the address, the comparator outputs a high level; otherwise, it outputs a low level. In this embodiment, comparator 20 is a three-input comparator, implemented by cascading multiple two-input comparators with an adder, used to determine whether window opening is necessary.

[0069] Selector 30 receives the judgment result of comparator 20. If the output of comparator 20 is high, selector 30 outputs a high level; otherwise, it outputs a low level and outputs the result to the input of shift register 40. Selector 30 includes a data selection port, two data inputs, and a selection result output. The data selection port is connected to the output of comparator 20, and the two data inputs are connected to high and low levels respectively. The selection result output is connected to the data input of shift register 40. Selector 30 in this embodiment can be a commonly used selector in the art, and its specific structure will not be described in detail here.

[0070] The shift register 40 is used to receive the output data of the selector 30 and complete the serial-to-parallel conversion to obtain a series of row and column selection signals. The shift register 40 includes a reset terminal, a clock input terminal, a data input terminal, and a row / column selection signal output terminal. The reset terminal and the clock input terminal are respectively connected to the reset terminal and the clock terminal of the readout circuit. That is, when the windowed row and column selection signals are generated, the reset signal is valid and the shift register 40 is reset to the initial state. The data input terminal of the shift register 40 is connected to the output terminal of the selector 30, and the output terminal outputs the row / column selection signals.

[0071] In this embodiment, the shift register 40 has a depth of N, where N is the number of rows or columns of the readout circuit. It operates synchronously with the counter 10, and a data change occurs once after each clock trigger. The shift register 40 can be a commonly used shift register in the art, and its specific structure will not be described in detail here.

[0072] Each pixel is equipped with a pixel control circuit 50. When multiple windows are used, the pixel control circuit 50 controls the pixel signal by controlling the on / off state of the pixel signal through a transmission gate. The pixel control circuit 50 includes a row selection signal input terminal, a column selection signal input terminal, a multiple window configuration information input terminal, a windowing signal input terminal, a pixel signal input terminal, and a pixel signal output terminal. The row / column selection signal input terminal is used to input row / column selection signals (i.e., the row / column selection signal input terminal is connected to the output terminal of the shift register 40).

[0073] In one alternative implementation, the pixel control circuit 50 includes a three-input AND gate 501, a selector A 502, a selector B 503, a transmission gate 504, an inverter 505, and a latch 506, as shown in Figure 2.

[0074] In the pixel control circuit, the input terminals of the three-input AND gate 501 receive the row and column selection signals for a single pixel and the multi-window configuration signal `mult`. The output terminal of the three-input AND gate 501 is connected to the data selection terminal of selector A502. The two data input terminals of selector A502 are connected to low and high levels, respectively. The output terminal of selector A502 is connected to one data input terminal of selector B503. The two data input terminals of selector B503 are connected to the output terminal of selector A502 and the high level, respectively. The output terminal of selector B503 is connected to the data input terminal of latch 506. The data selection terminal of selector B503 is connected to the windowing signal `sign`. The input terminal A of gate 504 is connected to the pixel signal, the output terminal B of transmission gate 504 is connected to the pixel signal, the control terminal C of transmission gate 504 is connected to the output terminal of latch 506, and the inverting control terminal CB of transmission gate 504 is connected to the output terminal of inverter 505; the input terminal of inverter 505 is connected to the output terminal of latch 506, and the output terminal of inverter 505 is connected to the inverting control terminal CB of transmission gate 504; the data input terminal of latch 506 is connected to the output terminal of selector B503, the enable input terminal of latch 506 is connected to the multi-window configuration signal mult, and the output terminal of latch 506 is connected to the control terminal C of transmission gate 504 and the input terminal of inverter 505.

[0075] In transmission gate 504, the control terminal C and the inverting control terminal CB are opposite level configuration terminals connected by an inverter.

[0076] The row and column selection signals of the input pixel control circuit are D0 and D0 respectively. <n> 、D1 <m>.

[0077] The working principle of the random window implementation circuit proposed in this embodiment is as follows: If the starting coordinate of a row of the window is M, the size of the row window is N, and M+N does not exceed the address limit, then the random windowing circuit will generate the row selection signal shown in Figure 3. The selection of the windowing part is achieved by setting the corresponding row selection signal to "1". The column address is similar, and will not be elaborated further here. The workflow of generating the row and column selection signals is shown in Figure 4. After the power-on configuration signal is input, the comparator compares the address signal with the position of the window to change the input signal of the shift register until the address signal reaches the upper limit. Since the address counter and the shift register are both controlled by the main clock and reset signal of the read circuit, the counter and the shift register can work completely synchronously. The pixel control circuit is used to prevent the selection of unnecessary pixels. This problem is avoided by adding a transmission gate switch on the pixel, as shown in Figure 5. If you want to select window 1 and window 2, you need to input row address 1, column address 1, row address 2, and column address 2 respectively. The resulting row and column selection signals will select unnecessary windows 3 and 4, thus reducing the windowing efficiency. The multi-window operation process is shown in Figure 6. In the first stage of multi-windowing, row address 1 and column address 1 are used to generate corresponding row and column selection signals, closing the transmission gate 504 corresponding to window 1. Then, row address 2 and column address 2 are used to generate corresponding row and column selection signals, closing the transmission gate 504 corresponding to window 2, and so on, until all transmission gates 504 corresponding to all windows are closed. After completion, the multi-windowing configuration signal mult is pulled low, and the latch circuit latches and holds the output signal at this time, which remains unchanged. In the second stage, row address 1, column address 1, row address 2, column address 2, etc., are used again to generate corresponding row and column selection signals. At this time, only the cells with closed transmission gates are selected. The windowing signal sign is low only in multi-windowing mode and high when outputting to the entire array, ensuring that all cell switches are closed when no windows are opened. The multi-windowing configuration signal mult is high in the first stage of multi-windowing and low in the second stage of multi-windowing.

[0078] Compared to traditional column-level windowed readout circuits, which require a shift register to select pixels each time a window is opened, the random window implementation circuit proposed in this embodiment only needs to generate the corresponding row and column selection signals during power-on configuration. After that, the shift register is no longer needed, which can reduce the power consumption and bit error rate of the circuit.

[0079] Furthermore, traditional column-level windowing readout circuits are quite complex to implement when opening multiple windows simultaneously, and usually require the introduction of a state machine. However, this embodiment greatly simplifies the process, and the configuration of the switch signals only needs to be done once, once during power-on initialization. As long as the subsequent window information remains unchanged, the required window can be selected simply by using the row and column selection signals in the second stage of multi-windowing.

[0080] The specific embodiments described above further illustrate the purpose, technical solution, and beneficial effects of the present invention. It should be understood that the above description is only a specific embodiment of the present invention and is not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.< / m> < / n>

Claims

1. A random window implementation circuit for a pixel-level focal plane readout circuit, characterized in that, It includes a row selection signal generator, a column selection signal generator, and several cell control circuits. The row selection signal generator generates row selection signals, and the column selection signal generator generates column selection signals. Both the row and column selection signal generators include a counter, a comparator, a selector, and a shift register. The counter counts cell addresses. The comparator determines whether the cell address output by the counter is within the windowed area and inputs the result to the selector. The selector receives the result from the comparator; if the cell address is within the windowed area... Within the specified range, a high level is output; otherwise, a low level is output, and the result is input to the shift register. The shift register receives the output data of the selector and performs serial-to-parallel conversion to obtain a series of row / column selection signals. The counter and shift register operate synchronously. Each pixel is equipped with a pixel control circuit, which controls the on / off state of the pixel signal by adding a transmission gate to the corresponding pixel to prevent the selection of unselected pixels. The pixel control circuit includes a three-input AND gate, selector A, selector B, latch, transmission gate, and inverter. The input terminals of the three-input AND gate receive the row selection signal, column selection signal, and multi-window configuration signal for a single pixel. The output terminal of the three-input AND gate is connected to the data selection terminal of selector A. The two input terminals of selector A are connected to a low-level and a high-level signal, respectively. The output terminal of selector A is connected to one data input terminal of selector B. The two data input terminals of selector B are connected to the output terminal of selector A and a high-level signal, respectively. The output terminal of selector B is connected to the data input terminal of the latch, and the data selection terminal of selector B receives the windowing signal. The latch... The data input terminal is connected to the output terminal of the selector B; the enable input terminal of the latch is connected to the multi-window configuration signal; the output terminal of the latch is connected to the positive phase control terminal of the transmission gate and the input terminal of the inverter; the input terminal of the transmission gate is connected to the pixel signal; the output terminal of the transmission gate is connected to the pixel signal; the positive phase control terminal of the transmission gate is connected to the output terminal of the latch; the negative phase control terminal of the transmission gate is connected to the output terminal of the inverter; the input terminal of the inverter is connected to the output terminal of the latch; and the output terminal of the inverter is connected to the negative phase control terminal of the transmission gate.

2. The random window implementation circuit for a pixel-level focal plane readout circuit according to claim 1, characterized in that, The counter is a modulo-N binary counter, where N is the number of rows or columns of the readout circuit.

3. The random window implementation circuit for a pixel-level focal plane readout circuit according to claim 1, characterized in that, The comparator outputs a high level when the starting coordinate of the window opening is less than or equal to the address and the ending coordinate of the window opening is greater than the address; otherwise, it outputs a low level.

4. The random window implementation circuit for a pixel-level focal plane readout circuit according to claim 1, characterized in that, The comparator is a three-input comparator, which is implemented by cascading multiple two-input comparators with an adder.

5. The random window implementation circuit for a pixel-level focal plane readout circuit according to claim 1, characterized in that, Both the counter and the shift register are controlled by the master clock and reset signal of the readout circuit to achieve synchronous operation. When the row / column selection signal for windowing begins to be generated, the reset signal is valid, and the counter and shift register are reset to their initial state. A data change occurs once after each clock trigger.

6. The random window implementation circuit for a pixel-level focal plane readout circuit according to claim 1, characterized in that, The depth of the shift register is N, where N is the number of rows or columns of the readout circuit.

7. A pixel-level focal plane readout circuit, characterized in that, Random window output is achieved using the random window implementation circuit described in any one of claims 1-6.

8. A method for generating row / column selection signals based on the random window implementation circuit according to any one of claims 1-6, characterized in that, The method includes: initialization; input window configuration signals, including window size and coordinates; and changing the input signal of the shift register by comparing the address signal with the position of the window through a comparator until the address signal reaches the upper limit.

9. A multi-window implementation method based on the random window implementation circuit according to any one of claims 1-6, characterized in that, The method includes: initialization; setting the windowing signal to low level; inputting the size and coordinates of N windows, where N is an integer greater than or equal to 2; setting the multi-window configuration signal to high level, generating corresponding row and column selection signals using the row and column addresses of window 1, and closing the transmission gate corresponding to window 1; then generating corresponding row and column selection signals using the row and column addresses of window 2, and closing the transmission gate corresponding to window 2, and so on, until the transmission gates corresponding to N windows are closed; setting the multi-window configuration signal to low level, generating corresponding row and column selection signals using the row and column addresses of the N windows respectively, at which point only the cells with closed transmission gates will be selected.

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