Analog-digital hybrid computing method and neuromorphic system using the same

Abstract

The present disclosure provides an analog-digital hybrid computing method and a neuromorphic system using the same. The neuromorphic system includes: an input signal section that generates an input signal; a synapse section that includes synapse units that receive the input signal and flow a current according to a set weight, each synapse unit including a storage unit that is provided in a memory array including an input electrode line and an output electrode line and generates an output signal; a digital computing section that digitizes and sums the output signals; and a control section that specifies a digitization bit number for each output electrode line and stores a logic state in the storage unit; causes the input signal to be applied to each storage unit of each synapse unit through each input electrode line; generates, for each output electrode line, a sum of the currents flowing from the storage units of each synapse unit by the input signal as an output signal; and causes the digital computing section to digitize the output signals according to the bit number and calculate a sum of the digitized output signals.

Description

Technical Field

[0001] This invention relates to the use of memory devices capable of controlling gradual resistance changes in the realization of neuromorphic systems. More specifically, this invention relates to neuromorphic systems and methods of operation thereof, which detect current flowing from multiple memory cells using a hybrid analog-digital computing approach, while allowing multiple selected memory cells to be identified and operated as a single synaptic unit. Background Technology

[0002] The artificial intelligence semiconductor industry is currently in its early stages. Recently, semiconductor design and manufacturing companies have begun to release prototypes or early products. These prototypes and initial products are first-generation AI semiconductor products based on CMOS, and from a memory perspective, they are indistinguishable from existing semiconductor products, with the expectation of introducing and using new memory in second-generation AI semiconductors.

[0003] For second-generation artificial intelligence semiconductors with an integration level similar to that of biological neural networks, artificial synapses possessing all the key characteristics of biological synapses should be implemented as a single element. In processing signals transmitted from neurons, synapses in biological systems undergo changes in synaptic weights, thereby enabling learning and memory functions. Therefore, artificial synaptic elements aim to simulate this, such that changes in synaptic weights can be represented as current (or resistance), thus achieving learning and memory functions. Therefore, to achieve this, it is crucial to develop elements in which controllable and distinguishable gradual changes in current (or resistance) can be made. For the most ideal artificial synaptic element, the gradual change in current (or resistance) is one in which the change in current (or resistance) occurs precisely proportional to the number of applied pulses.

[0004] To achieve this goal, various artificial synaptic elements have been proposed and fabricated. Among the technologies already studied in the semiconductor field for synaptic elements, research has been conducted in the direction of implementing a high resistance variation method for switching digital methods. This method distinguishes between low-resistance and high-resistance states in a memory array by using elements such as RRAM, PRAM, or MRAM that can change resistance, and reads the logic state of the cells in the memory array based on the resistance variation, thereby storing information in each cell.

[0005] However, for artificial synaptic elements, not only does a single element need to have a wide variety of resistance states, but these resistance states also need to be controlled. Although a great deal of research and development has been carried out on these elements using RRAM elements, PRAM elements, etc., there are still many asymmetries or a lack of repeatability, and therefore it is still insufficient to achieve the level of simultaneous control while generating distinctive resistance states. Summary of the Invention

[0006] The present invention solves the above and other problems associated with conventional methods and apparatus.

[0007] The purpose of this invention is to provide a neuromorphic system and its operation method for digitizing analog output signals in a synaptic unit comprising multiple storage units.

[0008] According to an embodiment of the present invention, a neuromorphic system is provided, the neuromorphic system comprising: an input signal unit that generates an input signal; a synapse unit comprising a plurality of synaptic units that receive the input signal and cause current to flow according to a set weight, each of the plurality of synaptic units comprising a plurality of non-volatile memory units capable of selectively storing logic states, the non-volatile memory units being disposed in a memory array comprising intersecting input electrode lines and output electrode lines, and generating an output signal for each output electrode line according to the input signal; a digital computing unit that digitizes the output signals generated for each output electrode line and calculates the sum of the digitized output signals; and a control unit that controls the input signal. The control unit comprises: a control unit, a synaptic unit, and a digital computing unit; wherein the control unit: assigns a digitization bit depth to each output electrode line, stores the logic state in the plurality of non-volatile memory cells according to a predetermined weight in each of the plurality of synaptic units, applies the input signal generated by the input signal unit to each of the plurality of non-volatile memory cells of each of the plurality of synaptic units through the input electrode line, generates, for each output electrode line, the sum of the currents flowing from the plurality of non-volatile memory cells of each of the plurality of synaptic units through the applied input signal as the output signal, and causes the digital computing unit to digitize the output signal generated for each output electrode line according to the bit depth, and calculates the sum of the digitized output signals.

[0009] Furthermore, in the neuromorphic system according to an embodiment of the present invention, the control unit: can make the input signal generated from the input signal unit into one or more pulses having the same width and height, such that the one or more pulses are sequentially applied to the synapse according to the generation order, and such that the different digitization bits in the pulses are assigned to the one or more pulses according to the generation order, such that the output signal is sequentially generated for each of the sequentially applied pulses, and such that the digital calculation unit digitizes the output signal generated by each pulse for each output electrode line according to the number of bits in the pulse according to the generation order of the pulses and the number of bits of the output electrode line, and calculates the sum of the digitized output signals.

[0010] According to another embodiment of the present invention, a method for operating a neuromorphic system is provided, the neuromorphic system comprising: an input signal unit that generates an input signal; a synapse unit comprising a plurality of synaptic units that receive the input signal and cause current to flow according to a set weight, each of the plurality of synaptic units comprising a plurality of non-volatile memory units capable of selectively storing logical states, the non-volatile memory units being disposed in a memory array comprising intersecting input electrode lines and output electrode lines, and generating an output signal for each output electrode line according to the input signal; a digital computing unit that digitizes the output signals generated for each output electrode line and calculates the sum of the digitized output signals; and a control unit that controls the input signal unit, the synapse unit, and the synapse unit. The method includes the following steps: (a) assigning a digitization bit depth to each output electrode line and storing the logic state in the plurality of non-volatile memory cells according to a predetermined weight in each of the plurality of synaptic units; (b) generating an input signal by the input signal unit and applying the input signal through the input electrode line to each of the plurality of non-volatile memory cells of each of the plurality of synaptic units; (c) generating a sum of currents as an output signal for each output electrode line, the current flowing from the plurality of non-volatile memory cells through the input signal applied to each output electrode line; (d) digitizing the output signal according to the bit depth of each output electrode line; and (e) calculating the sum of the digitized output signals.

[0011] Furthermore, in a method for operating a neuromorphic system according to another embodiment of the present invention, in step (b), the input signal is one or more pulses having the same width and height, and specifying different digitization bits in the pulses according to the generation order, such that the one or more pulses are sequentially applied to the plurality of non-volatile memory cells according to the generation order; in step (c), an output signal is sequentially generated for each sequentially applied pulse; and in step (d), the output signal is digitized according to the number of bits in the pulses according to the generation order of the pulses and the number of bits in the output electrode lines.

[0012] This invention enables the realization of novel neuromorphic systems with high precision, small size, and low power consumption. Attached Figure Description

[0013] Figure 1 This is a conceptual diagram illustrating vector-matrix multiplication used for image recognition;

[0014] Figure 2 This is a conceptual diagram illustrating vector-matrix multiplication using a memory array;

[0015] Figure 3 This is a graph illustrating the change in the conductance of a cell based on the write pulse;

[0016] Figure 4 This is a diagram illustrating how the conductance changes with the number of connected cells when a synapse is represented by multiple memory cells;

[0017] Figure 5 This is a diagram illustrating the structure of a neuromorphic system according to the present invention;

[0018] Figure 6 This is a diagram illustrating an embodiment of the present invention in which multiple storage cells form a synapse;

[0019] Figure 7 This is a graph illustrating the change in conductance according to the present invention through a combination of multiple storage cells forming a synapse;

[0020] Figure 8 This is a diagram illustrating the performance of vector-matrix multiplication according to an embodiment of the present invention;

[0021] Figure 9 This is a diagram illustrating the performance of vector-matrix multiplication according to an embodiment of the present invention;

[0022] Figure 10 This is a diagram illustrating the performance of vector-matrix multiplication according to an embodiment of the present invention;

[0023] Figure 11 This is a diagram illustrating the setting of synaptic weights according to the storage cells forming synapses in an embodiment of the present invention;

[0024] Figure 12 This is a diagram illustrating the setting of synaptic weights according to the storage cells forming synapses in an embodiment of the present invention;

[0025] Figure 13 This is a diagram illustrating the performance of vector-matrix multiplication according to an embodiment of the present invention;

[0026] Figure 14 This is a diagram illustrating the performance of vector-matrix multiplication according to an embodiment of the present invention;

[0027] Figure 15 This is a graph illustrating the current flowing in the memory cell when a transistor is used as a selection element in an embodiment according to the invention;

[0028] Figure 16This is a diagram illustrating a method of applying a read voltage in the prior art when a two-terminal switching element or a selective storage element is used as a selection element;

[0029] Figure 17 This is a diagram illustrating a method of applying a read voltage when a two-terminal switching element or a selective memory element is used as a selection element in an embodiment according to the invention; and

[0030] Figure 18 This is a diagram illustrating that, in an embodiment of the invention, multiple storage units belonging to a synaptic unit are arranged in multiple memory arrays. Detailed Implementation

[0031] In the following description, the configuration and operation of embodiments of the present invention will be described with reference to the accompanying drawings. In the following description of the invention, detailed descriptions of relevant well-known functions or configurations will be omitted where it is determined that such detailed descriptions may unnecessarily obscure the gist of the invention. Furthermore, when a portion “comprises” a component, this means that other components may be further included, rather than excluded, unless otherwise stated.

[0032] In this invention, a novel neuromorphic system and its operation method will be described.

[0033] In deep learning algorithms, vector-matrix multiplication (VMM) is a key computational operation for learning and inference.

[0034] When reference Figure 1 When describing the VMM method for image recognition, the image is divided into n×n regions, weights are assigned to each region, and information such as brightness and darkness is used as various input signals. When expressed using a neuromorphic system, the input signal X... i It is a signal from the preneuron, with an output current I. tot It is the output signal to the postneuron, and W i It is the weighted multiplication of the input signal by the synapse. Thus, by multiplying I... tot (It is the current that appears as the sum of the product of the input signal and the weight) compared with a reference value and the synapse with the closest weight is found to identify the image.

[0035] However, there are many problems in implementing this operation in existing computing systems, such as power consumption and device size issues.

[0036] To address this issue, recent research is actively exploring novel memory technologies, such as resistive random access memory (RRAM), phase-change random access memory (PRAM), magnetic random access memory (MRAM), and ferroelectric random access memory (FeRAM), which are non-volatile memories.

[0037] Typically, memory arrays using new memory have a structure in which input electrode lines and output electrode lines cross each other, and the input electrode lines and output electrode lines are connected to each other at the intersection points via memory cells.

[0038] Reference Figure 2 A VMM using this memory array is described. Figure 2 In the above, when X can be represented as a vector X i When the input signal is applied to the row metal line 122 while the column metal line 121 is kept in a grounded state, the current flowing through each memory cell at the intersection (i, j) becomes X. i W ij (X i It is the applied voltage, and W ij (This refers to the conductance of the memory cell). Because the current flowing through these column lines 121 becomes the sum of the currents flowing through the memory located in the same column lines 121, therefore I j =X1*W 1j +X2*W 2j +X3*W 3j +..+X n *W nj (exist Figure 2 In this context, j ranges from 1 to m.

[0039] Thus, by outputting m currents I1 to I from column line 121 m Each of the values ​​is compared to a baseline value to perform inference processing.

[0040] Here, the input signal X i It is an analog signal, and can be a pulse with a constant width and different heights, a pulse with a constant height and different widths, or a pulse with a constant width and height but different durations. W is used as the weight. ij It can be represented by the conductance of the memory cells at each point in the memory array.

[0041] Additionally, the weight W here ij The conductance corresponds to the storage cell. To increase the accuracy of the inference, various values ​​(i.e., various conductances) should be stored in the storage cell in steps. Since the accuracy of the inference increases with the increase of diversity, it is feasible to develop a new memory capable of storing conductances of different steps for this purpose, but satisfactory results have not yet been obtained.

[0042] This is Figure 3 As shown in the diagram. In memory cells such as RRAM, if the conductance is measured while a write pulse is applied to change the conductance corresponding to the synaptic weight, the conductance of the memory cell is changed, but it does not change to an ideal straight line. Figure 3Instead of drawing dashed lines, draw curves. Figure 3 (The solid lines in the diagram). Furthermore, these curves do not repeatedly show the same curve but rather change continuously. That is, in the case of synaptic cells using memory cells such as an RRAM, not only does the conductance of the memory cell corresponding to the weight increase or decrease nonlinearly, but the change in conductance varies with each measurement, making it practically impossible to increase the accuracy of the inference.

[0043] To overcome this phenomenon, attempts have been made to control the conductance changes of memory cells in a manner that is easily inferred through peripheral circuits, etc. However, such attempts complicate neuromorphic systems and reduce operating speed, and the conductance changes of memory cells have not been controlled to a satisfactory level.

[0044] To address the problems of existing technologies, a novel neuromorphic system and an operational method using this system have been proposed. This system is capable of representing various changes in conductance by using multiple storage units instead of a single storage unit as synaptic units. In the novel neuromorphic system and its operational method, by utilizing multiple units instead of a single unit as synaptic units, the weights of synaptic units can be represented in various ways through linear and predictable resistance changes (see...). Figure 4 ).

[0045] Synaptic units comprising multiple memory cells can gradually change their conductance based on the increase or decrease in the number of switched-on cells (i.e., memory cells in a low-resistance state) among the multiple memory cells, and this change becomes linear and predictable.

[0046] On the other hand, by using multiple memory cells as a single synaptic unit in this way, the weight of the synaptic unit can be represented in various ways by the sum of the currents flowing through the multiple memory cells, but there is a problem of increasing the number of memory cells used.

[0047] In order for synaptic units to represent weights in the range of 1 to 256, 256 storage units are needed if one storage unit can store 1 bit of logical state.

[0048] If multiple memory cells are used for synaptic units in this way, linear and predictable resistance changes are possible. However, as the number of memory cells used increases, the problem arises in the increased size and manufacturing cost of the device.

[0049] Therefore, it is necessary to reduce the number of storage cells used to an appropriate level. To this end, in this invention, when multiple storage cells are used as synaptic units, the number of storage cells used can be reduced by outputting the sum of the analog currents flowing from the multiple storage cells as a digital signal.

[0050] Specifically, this invention provides a neuromorphic system comprising: an input signal unit that generates an input signal; a synapse unit comprising a plurality of synaptic units that receive the input signal and cause current to flow according to a set weight, each of the plurality of synaptic units comprising a plurality of non-volatile memory units capable of selectively storing logical states, the non-volatile memory units being disposed in a memory array comprising intersecting input electrode lines and output electrode lines, and generating output signals for each output electrode line according to the input signal; a digital computing unit that digitizes the output signals generated for each output electrode line and calculates the sum of the digitized output signals; and a control unit that controls the input signal unit, the synapse unit, and the digital computing unit. The control unit: specifies the number of digits for each output electrode line and stores the logic state in the plurality of non-volatile memory cells according to a predetermined weight in each of the plurality of synaptic units; applies the input signal generated by the input signal unit to each of the plurality of non-volatile memory cells of each of the plurality of synaptic units through the input electrode line; specifies the number of digits for each output electrode line in the synaptic unit; generates the sum of the currents flowing from the plurality of non-volatile memory cells of each of the plurality of synaptic units through the applied input signal as the output signal for each output electrode line, and causes the digital calculation unit to digitize the output signal generated for each output electrode line according to the number of digits, and calculates the sum of the digitized output signals.

[0051] The neuromorphic system according to the present invention includes a plurality of synaptic units capable of having various weights, and each of these synaptic units includes a plurality of non-volatile memory units capable of storing logical states. These non-volatile memory units are disposed at the intersections of output electrode lines and input electrode lines to form a memory array. First, a digitization bit depth is assigned to each of these output electrode lines, and according to the predetermined weights of each synaptic unit, the logical states, based on the number of digits for each electrode line stored in the plurality of non-volatile memories disposed in the memory array, are stored in the plurality of non-volatile memories in the memory array.

[0052] Each synaptic unit includes multiple storage units, each storing a logic state. When an input signal is applied to the synapse comprising multiple synaptic units, the synapse converts the applied input signal into an output signal according to the stored weights, generating an output signal. In this case, an output signal is generated for each output electrode line equipped with a non-volatile storage unit.

[0053] Therefore, the output signal generated on one output electrode line becomes the sum of the currents flowing through the non-volatile memory cells on that output electrode line. Thus, the output signal generated for each output electrode line becomes the sum of the currents flowing from each memory cell and appears in analog form. Furthermore, the number of digits for each output electrode line is determined. Based on the number of digits corresponding to the output electrode line of the generated output signal, the analog output signal is converted into a digital signal in a digital calculator. In this way, the data required for artificial intelligence inference can be obtained by summing and calculating the output signals generated for each output electrode line and converted into digital signals.

[0054] Reference Figures 5 to 7 The neuromorphic system and its computational steps are described in more detail.

[0055] The neuromorphic system according to the present invention includes an input signal unit 200 that generates an input signal 210, a synaptic unit 300 that receives the input signal 210 from the input signal unit 200 and generates an output signal 310 for each output electrode line according to a set weight, a digital calculation unit 400 that digitizes the output signal 310 generated for each output electrode line and transmits a digital signal 410, and a control unit 100 that controls the entire system.

[0056] Figure 6 This is a diagram illustrating the number of bits assigned to each output electrode line, thus indicating synaptic weights through gradual changes in resistance.

[0057] The synapse includes one or more memory arrays. The memory arrays include input electrode lines 301 and output electrode lines 302 that intersect each other, and memory cells 303 formed at the intersections of these electrode lines and connected to each other.

[0058] Synaptic units 320 and 330 included in the synapse include a plurality of memory cells 303 disposed in a memory array of this cross-point structure. Figure 6 The diagram illustrates a case 320 where N memory cells in a single synaptic unit are arranged in a row on one input line, and a case 330 where 2N memory cells are arranged on two input electrode lines. However, these cases are merely one embodiment, and the memory cells can be arranged on the memory array in various ways, such as 3N memory cells 303 arranged on three input electrode lines or N memory cells 303 arranged on N input electrode lines in one output electrode line.

[0059] In the case where the synaptic unit 320 includes N storage units 303 in one input line, by setting the number of digits for each configured output electrode line 302, for each output electrode line 302, the N storage units C0 to C10 are configured. N-1Having different digits 2 0 to 2 N-1 These storage units C0 to C... N-1 The weights of synaptic cells can be represented by their high and low resistance states. These memory cells are in the same on-state (i.e., low-resistance state), therefore, even if the current flowing along the output electrode lines is the same, when these currents are received as output signals and calculated by the digital computing unit, they are weighted according to the digitization bit depth. 0 Up to 2 N-1 The values ​​are calculated as different values. That is, when only the first digital storage unit C0 is in the ON state, and the current flowing through it is a single current i, this single current i is sent as an output signal to the digital computing unit, and the digital computing unit recognizes this output signal as 2. 0 ×i and digitize it. However, when only the second digital storage unit C1 is turned on, even if the current flowing through the storage unit is the same as the single current i, when the single current i is sent to the digital computing unit, the digital computing unit will recognize the output signal as 2. 1 ×i and digitize it. The same applies when the third storage cell C3 is active, and when the third storage cell is active, the digital computing unit will identify the output signal generated by the flowing current as 2. 2 ×i and digitize it.

[0060] In this way, the weights of synaptic units 320 can be represented in steps, and finally, as... Figure 7 As shown, synaptic unit 320 can even be represented by N units, 2 N Each weight.

[0061] Conversely, even if a synaptic unit has multiple storage units, if each storage unit does not have a number of bits, then 2 N One storage unit and one synaptic unit represent 2. N Each weight.

[0062] Reference Figure 8 An example of calculating the VMM when multiple synaptic units are present in the neuromorphic system according to the invention is described in more detail.

[0063] Figure 8 The example illustrates the case where signals 1, 3, and 6 are input signals and the synaptic weights are 2, 5, and 1, respectively. The VMM is calculated by multiplying the input signals by the weights of the synaptic units. When performing the calculation, the final signal 23 should be calculated.

[0064] Figure 8 Three synaptic units W, each with four memory cells, are illustrated. 11 W21 W 31 It is configured in a memory array with a cross-point structure. Here, the output electrode lines have digitization bits, and according to the binary number system, L0 has 2 bits. 0 L1 has 2 bits. 1 L2 has 2 bits. 2 And L3 has 2 bits. 3 .

[0065] An example is shown in the synaptic unit W. 11 In, set with 2 bits 1 The storage unit C on the output electrode line 13 In the activated unit state, in the synaptic unit W 21 In, set with 2 bits 0 The storage unit C on the output electrode line 22 and has 2 bits 2 The storage unit C on the output electrode line 24 In the connected unit state, and in the synaptic unit W 31 In, set with 2 bits 0 The storage unit C on the output electrode line 34 The cell is in the ON state. When the cell is ON, the conductance of each memory cell is the same, while when the cell is OFF, no current flows.

[0066] Here, it means that the magnitudes of the input signals X1, X2, and X3 are 1, 3, and 6, respectively. Figure 8 The example illustrates the case where the magnitude of each input signal is represented by the number of pulses with the same height and width. However, various input signals can be represented not only by the number of pulses, but also by differences in pulse width or pulse height.

[0067] Input signal X1 is applied to synaptic unit W 11 This causes the current X1*C 13 From the connection unit C 13 The current flows through the output electrode line L1. Here, since each memory cell in the ON state has the same conductivity level, if the output signal has multiple pulses, the same current flows for one of the pulses. Therefore, if the current flowing through the memory cell when a pulse is applied to the ON cell is i, then the current flows from memory cell C... 13 Outflowing current X1*C 13 It has a size of 1*i.

[0068] Similarly, when an input signal X2 with three pulses is applied to the synaptic unit W... 21At that time, a current of magnitude 3*i flows through the output electrode line L2, and a current of magnitude 3*i flows through the output electrode line L0. Finally, when an input signal X3 with six pulses is applied to the synaptic unit W... 31 At that time, a current of magnitude 6*i flows through the output electrode line L0.

[0069] Thus, for each output electrode line, the summation of the current flowing through each synaptic unit caused by the input signal can be expressed as follows.

[0070] L0:X2*C 24 +X3*C 34 =3*i + 6*i = 9*i

[0071] L1:X1*C 13 =1*i

[0072] L2:X2*C 22 =3*i

[0073] As described above, the current in each output electrode line is transmitted as an output signal to the digital computing unit, which then evaluates and calculates the output signal based on the number of bits specified for each output electrode line. The current flowing through output electrode line L0 is multiplied by 2. 0 The current flowing through the output electrode line L1 is multiplied by 2. 1 The current flowing through the output electrode line L2 is multiplied by 2. 2 This is used to sum these digitized signals. Therefore, the sum of all digitized output signals becomes (9*2). 0 +1*2 1 +3*2 2 =23.

[0074] Thus, in the neuromorphic system according to the invention, the output signal, which is an analog representation of the sum of currents through the individual output electrode lines of the synapse, is digitized according to the digitization bits of each line. With this analog-digital hybrid computing system, linear and predictable changes in synaptic weights can be represented using a small number of storage units.

[0075] Furthermore, in embodiments of the present invention, the non-volatile memory cell can be a multi-bit memory cell capable of storing two or more bits of information. In this specification, a multi-bit memory cell refers to a cell capable of storing two or more bits of information through multiple resistance states. Therefore, multi-bit memory cells typically include 3-bit TLC, 4-bit QLC, and MLC capable of storing 2 bits of information in flash memory. Additionally, a multi-bit memory cell also includes resistive random access memory (RRAM), phase-change random access memory (PRAM), magnetic random access memory (MRAM), and ferroelectric random access memory (FeRAM), which can store two or more bits of information through multiple resistance states.

[0076] By using such multi-bit storage cells, the number of storage cells used can be reduced, and thus the size of the memory array can be reduced, thereby reducing the area of ​​the entire system and the amount of power consumed during operation.

[0077] Figure 9 An implementation method is illustrated in the case where the non-volatile memory cell is a flash memory and a single-level cell (SLC) is used to store 1 bit of information. Figure 10 An example is given of an implementation where the non-volatile storage cell is a flash memory and it is capable of storing 2 bits of information in a multilevel cell (MLC).

[0078] exist Figure 9 In, such as Figure 8 The input signals X1, X2, and X3 are respectively applied to the synaptic unit W. 11 W 21 and W 31 And current flows from the turn-on unit through the output electrode line. Here, since each memory cell in the turn-on state has the same conductivity level, if the output signal has multiple pulses, the same current flows for one of the pulses. Therefore, when a pulse is applied to a memory cell that is the turn-on unit, if the current flowing through the memory cell is i, then the magnitude of the current flowing out of a memory cell due to a single input pulse becomes 1*i.

[0079] Therefore, in order to Figure 8 The same method is used to generate output signals for each output electrode line based on the input signal, and outputs digital signals according to the number of bits specified for each output electrode line. The calculated digital signal value becomes 89.

[0080] In comparison, Figure 10Each memory cell can represent three levels of resistance states R1, R2, and R3. Therefore, for a pulse of the input signals X1, X2, and X3, the currents i1, i2, and i3 flowing through the memory cells are different in each resistance state R1, R2, and R3. Because the three different resistance states can be represented in this way, the number of bits for each output electrode line can be represented according to the quaternion system. According to the quaternion system, L0 represents 4 bits. 0 L1 indicates a 4-bit number. 1 L2 indicates 4 bits. 2 L3 indicates a 4-bit number. 3 .

[0081] exist Figure 10 In the middle, synaptic unit W 11 In setting with 4 bits 0 The storage unit C on the output electrode line 14 When the synaptic unit W is in the ON state and has resistance R2, the synaptic unit W... 21 In setting with 4 bits 1 The storage unit C on the output electrode line 23 and set with 4 bits 0 The storage unit C on the output electrode line 24 When the synaptic unit W is in the ON state and has resistance states R1 and R3 respectively, 31 In setting with 4 bits 1 The storage unit C on the output electrode line 33 and set with 4 bits 0 The storage unit C on the output electrode line 34 When the unit is in the ON state and has resistors R2 and R3 respectively.

[0082] Here, as Figure 9 As shown, when the input signals X1, X2, and X3 represent the number of pulses with the same height and width, and are input in magnitudes of 1, 3, and 6, current flows from the switching units with various resistances in the respective output electrode lines.

[0083] First, when an input signal X1 with a pulse is applied to the synaptic unit W... 11 At that time, current 1*i2 flows from storage cell C, which has a resistive state R2. 14 Flow. Furthermore, when an input signal X2 with three pulses is applied to the synaptic unit W... 21 At that time, current 3*i1 flows from storage cell C, which has a resistive state R1. 23 The current flows, and the current 3*i3 flows from the storage cell C with resistance state R3. 24Flow. Furthermore, when an input signal X3 with six pulses is applied to the synaptic unit W... 31 At that time, current 6*i2 flows from storage cell C, which has a resistive state R2. 33 The current flows, and a current of 6*i3 flows from the storage cell C with resistance state R3. 34 flow.

[0084] Therefore, current (3*i1 + 6*i2) flows from output electrode line L1, while current (1*i2 + 9*i3) flows from output electrode line L0. When these currents are converted into digital signals, digital signal i1 is identified as 1, digital signal i2 as 2, digital signal i3 as 3, and output electrode line L1 as 4. 1 , output electrode line L 0 Recognized as 4 0 To perform the calculation.

[0085] The calculated digital signal output value is 89, such as... Figure 9 As shown. In Figure 9 In the process, seven memory units from four output electrode lines L0, L1, L2, and L3 are used to perform calculations, while... Figure 10 In this process, four memory cells in two output electrode lines L0 and L1 can be used to perform calculations.

[0086] By using multi-bit storage cells in this way, the area of ​​the memory array can be reduced, thereby reducing the area of ​​the entire neuromorphic system and also reducing power consumption.

[0087] Reference Figure 11 To further describe the reduction in memory array area as a result of using multi-bit storage cells, let's consider setting a synaptic weight. If the synaptic weight of synapse Ws is 137 and the synaptic storage cell is a single-level cell (SLC), where each cell can store 1 bit of information, then according to the binary digital system (… Figure 11 (a)), consisting of 8 output electrode lines 2 0 to 2 7 This represents a value of 10001001. In contrast, if the same synaptic weight is represented by a synapse Wm composed of MLCs, each MLC can represent 2 bits of information. Therefore, according to the quaternion system, this is achieved through four output electrode lines 4... 0 up to 4 3 Synaptic weights can be represented by the value 2021. Figure 11 (b)). Furthermore, in order to represent the same synaptic weight 137 in a synapse Wt composed of TLCs, each TLC can represent 3 bits of information, and the synaptic weight can be represented by three output electrode lines 8. 0 up to 8 2 ( Figure 11 The value of (c) is represented as 211.

[0088] Furthermore, in this invention, the control unit can set the bit level of a multi-bit storage cell for each output electrode line. For example, a TLC capable of storing 3 bits of information can be used to represent a lower-order output electrode line, while an SLC capable of storing 1 bit of information or an MLC capable of storing 2 bits of information can be used to represent a higher-order output electrode line. This bit level setting is determined by the control unit when storing the logic state.

[0089] In this method, if an error occurs in the higher bits, the VMM operation is greatly affected. Therefore, storage cells with high precision that store low information (e.g., 1 bit or 2 bits) are used in the higher bits, while multi-bit storage cells that can store more information (e.g., 3 bits or 4 bits) are used in the lower bits, thereby reducing the area of ​​the entire memory array.

[0090] Therefore, it is preferable that the bit level determined by the controller for each output electrode line depends on whether the output electrode line becomes the same or lower as the number of bits increases.

[0091] Reference Figure 12 This describes an implementation method for determining synaptic weights, wherein different levels of bits are assigned to each output electrode line. Figure 12 In (a), if the first output electrode line L of synapse Wh1 is set 10 Second output electrode line L 11 The storage cells on the device are configured to store 3 bits of information and are each assigned a bit depth of 8. 0 and 8 1 And set on the third output electrode line L of synapse Wh1 12 The storage unit on the device is configured to store 2 bits of information and is specified to have a bit depth of 4. 3 Then, the weights from 137 to 211 can be expressed as a combination of these.

[0092] In addition, such as Figure 12 As shown in (b), if the first output electrode line L of synapse Wh2 is set 20 Second output electrode line L 21 The storage cells on the device are configured to store 3 bits of information and are each assigned a bit depth of 8. 0 and 8 1 And it is set on the third output electrode line L of synapse Wh2. 22 and the fourth output electrode line L 23 The storage cells on the device are configured to store 1 bit of information and are each assigned a bit depth of 2. 6 and 2 7 Then, it can express weights from 137 to 1011, which are also combinations of these.

[0093] exist Figure 12 In (c), if the first, second, and third output electrode lines L of synapse Wh3 are set 30 L 31 and L 32 The storage cells on the device are configured to store 2 bits of information and are each assigned a bit depth of 4. 0 4 1 and 4 2 And set on the fourth and fifth output electrode lines L of synapse Wh3 33 and L 34 The storage cells on the device are configured to store 1 bit of information and are each assigned a bit depth of 2. 6 and 2 7 Then, weights from 137 to 10021 can be expressed, which are combinations of these.

[0094] In this way, even if multi-bit storage units are used, the impact of errors in the output is not significant at the lower bits. Therefore, using high-level multi-bit storage units at the lower bits and high-accuracy low-level multi-bit storage units at the higher bits can effectively reduce the area of ​​the entire neuromorphic system while maintaining computational accuracy.

[0095] Furthermore, in embodiments of the present invention, the positive output electrode line and the negative output electrode line can be designated as a pair for each digit in the digitization bits.

[0096] When synaptic weights can represent both positive and negative integers, accuracy in the learning and inference processes can be improved. To this end, negative synaptic weights can be represented by pairing two output electrode lines of the same bit length, with one line representing a positive value and the other a negative value.

[0097] Its in Figure 13 Example shown in the text. Although there are two representations of 2 1 The output electrode lines are configured such that one line represents a positive value and the other a negative value. Therefore, to represent the negative value -2, at the synapse W... 11 Middle indicator digit 2 1 In the output electrode lines, the unit -C represents the output electrode line with a negative value. 13 It is placed in the ON unit state to represent a negative value of -2.

[0098] In the process of converting the current flowing through each output electrode line into a digital signal, the current in the negative output electrode line is converted to a negative value, and the sum of these converted signals is calculated. Therefore, in Figure 13 In the -L1 line, the current flows at a magnitude of 1*i, but when converted to a secondary output signal, it is calculated as -1*2. 1On the other hand, the current 6*i flows in the +L1 line, which has the same number of bits but represents a positive value, and when converted to a secondary output signal, this current is calculated as 6*2. 1 If the current flowing in each line is summed, the current 5*i flowing is calculated, and when converted into a final digital signal, it can be represented in a 2-bit format. 1 Calculate 5*2 at the output electrode line 1 The digital signal. Finally, when the signals of each line are summed, the output value is 31.

[0099] Its advantage lies in reducing the actual calculation error caused by parasitic currents. Throughout the memory array, parasitic currents flow minutely through even the off-grid cells. The problem arises when accumulated parasitic currents increase, potentially leading to errors in estimating the number of on-grid cells. Figure 13 The implementation method described herein is a way to effectively control minute parasitic currents flowing through or even shutting down the unit. For parasitic currents flowing through the shut-down unit, when the currents flowing in the positive output electrode line and the currents flowing in the negative output electrode line are identified as positive and negative, respectively, and summed, the currents cancel each other out to reduce their magnitude.

[0100] For example, in Figure 13 Only turn-off units are provided in the +L3 and -L3 of the output electrode lines, but parasitic currents even flow slightly to these turn-off units. However, if the current flowing into +L3 is made positive and the current flowing into -L3 is made negative and their sum is calculated, then theoretically 0 is calculated, eliminating the possibility of error.

[0101] In addition to determining the number of digits only in the synaptic unit, the VMM can be performed more efficiently by setting the number of digits in the output signal.

[0102] Therefore, in one embodiment of the neuromorphic system provided by the present invention, the input signal generated from the input signal unit can be one or more pulses with the same width and height. One or more pulses can be applied to the synapse in sequence according to the generation order. Different digitization bits can be assigned to the one or more pulses in sequence according to the generation order. Output signals can be generated sequentially for each sequentially applied pulse. The digital calculation unit can digitize the output signals generated for each output electrode line for each pulse according to the number of bits in the pulse generation order and the number of bits of the output electrode line, and calculate the sum of the digitized output signals.

[0103] Multiple storage units within the synaptic unit have digitized bits for each output electrode line configured as in the example above. Furthermore, the input signal is one or more pulses with the same width and height, such that the input signal has digitized bits according to the order in which the pulses are generated. Therefore, the digital computing unit digitizes the output signal through this combination and calculates the sum of the output signals to perform the VMM.

[0104] This will Figure 14 A more detailed description is available in the text. For example... Figure 8 As shown, three synaptic units W, each with four memory cells, are arranged in the memory array. 11 W 21 and W 31 Here, the output electrode line L0 has 2 bits. 0 Output electrode line L1 has 21 bits, and output electrode line L2 has 2 bits. 2 The output electrode line L3 has a bit depth of 2. 3 The on / off units of the configured storage units are also related to... Figure 8 The situation is the same.

[0105] Depending on the generation order of the pulses, the input signals to the storage unit have different numbers of digits within each pulse. The first pulse P0 generated has 2 digits. 0 The second pulse P1 has a bit depth of 2. 1 The third pulse P 2具 With 2 bits 2 The fourth pulse P3 has a bit depth of 2. 3 Therefore, if as Figure 8 If input signals 1, 3, and 6 are input as described above, then input signal X1 uses only the first pulse, represented as 0001 in the binary number system, to input 1. Input signal X2 generates the first and second pulses, represented as 0011 in the binary number system, to input 3. Input signal X3 generates the second and third pulses, represented as 0110 in the binary number system, to input 6.

[0106] Therefore, based on the input signals applied in the order of pulse generation and the output electrode lines that generate the output signals, the output signals are digitized, and the sum of these digitized output signals is calculated.

[0107] If the value of the current applied to the memory cell by a pulse is χ and the current flowing when a pulse is applied to the turn-on cell is i, then firstly, by the first pulse (P0), the current flows from the memory cell C by the input signal X2 for the output electrode line L0. 24 The flowing current 1*i is generated by the input signal X1 for the output electrode line L1 from the storage unit C. 13The current flowing is 1*i, and is generated by the input signal X2 for the output electrode line L2 from the storage cell C. 22 The current flowing is 1*i.

[0108] Figure 14 An example is given for the generation sequence of each pulse and the output signals generated for each output electrode line. In output electrode line L0, a current 1*i is generated as an output signal by the first pulse P0, a current 2*i is generated as an output signal by the second pulse P1, and a current 1*i is generated as an output signal by the third pulse P2. These currents are then used as output signals. When these output signals are sent to the digital computing unit, the digital computing unit identifies the number of bits 2 in the output signal for the first pulse. 0 The number of bits in the output signal of the second pulse is 2. 1 And the number of bits 2 for the output signal of the third pulse. 2 And by using digit 2 0 The calculation is performed on L0, which is the output electrode line. The output signal from output electrode line L0 is calculated as an output signal digitized from each pulse, and has a value of 9 (4+4+1=9).

[0109] When the output signals from the other output electrode lines are converted into digitized output signals in this way, digitized output signal 2 is calculated for output electrode line L1, and digitized output signal 12 is calculated for output electrode line L2. For example... Figure 8 As shown, the sum of these digitized output signals from each output electrode line becomes 23.

[0110] By specifying the number of digits according to the pulse generation sequence, input signals of various sizes can be expressed using a finite number of pulses, pulse widths, pulse heights, or combinations thereof. As a result, the energy consumption for generating input signals in neuromorphic systems can be significantly reduced.

[0111] The storage unit in this invention is a non-volatile storage unit capable of storing logical states. The non-volatile storage unit may include non-volatile storage elements and selection elements, and the non-volatile storage elements may be any of the following: flash memory elements, resistive random access memory (RRAM) elements, phase-change random access memory (PRAM) elements, magnetic random access memory (MRAM) elements, ferroelectric random access memory (FeRAM) elements, and selective storage elements.

[0112] Alternatively, the selection element can be a transistor or a diode. When a transistor or diode is connected to the selected cell, current flows through the memory cell according to the resistance state of the non-volatile memory element when an input signal is applied, and current flow is blocked in the case of unselected cells. Thus, by allowing current to flow only through the selected memory cell, that is, the memory cell corresponding to the synaptic element to be calculated by the VMM, unnecessary current flow can be prevented. Conversely, if a two-terminal element or the like is used as the selection element, the device has the advantage of miniaturization compared to using a transistor or the like. However, even in a memory array, it is not possible to prevent even a small amount of current from flowing to memory cells that are not needed for calculation, resulting in power consumption.

[0113] On the other hand, when a transistor or diode is connected as a selection element, the current flowing from the selected memory cell of the synaptic unit by the input signal can be controlled to a predetermined current magnitude, while allowing the input signal to flow only to the memory array to calculate the required selected memory cell. When the non-volatile memory element of the selected cell is in the ON state, the resistance of each memory element may have a certain local deviation, and the error caused by this deviation is unavoidable. By controlling the current flowing from the memory element by the input signal to a predetermined magnitude to minimize this deviation, the error range of the output signal due to the deviation between memory elements can be minimized. In particular, when the number of digits of the memory cell is large, for example, when it is 2... 7 At that time, even a tiny error was magnified to 2. 7 And therefore it is very important that the current flowing in the switching unit is precisely controlled to a constant level.

[0114] Furthermore, when the unit is turned on, the current flowing appears to be very large, so power consumption can be reduced by limiting it to a certain range or making it smaller.

[0115] This is Figure 15 The example illustrates this. When an input voltage V1 is applied to a memory cell without a transistor acting as a selection element, the current through the memory cell changes according to the state of the cell being turned on or off. on or I off Specifically, I on (The current in the on-state of the cell) has a very large magnitude and an error dependent on the memory cell. This error needs to be kept constant because it can lead to large errors when the memory cell is located in an electrode line with a large number of bits.

[0116] Therefore, if transistors are included as selection elements to limit the current to a certain range, then no current flows in the unselected cells of the memory array, and even in the selected cells, the current is limited to a value of I.off The current still flows in the memory cells that are in the off state, but it is possible to limit the current in the on state to I. TR ,like Figure 15 exemplified in .

[0117] If transistors are used as selection elements in this way, there are advantages such as current flowing only through the selected synaptic elements required for calculation, power consumption being greatly reduced by limiting the magnitude of the current through the switching unit, and error factors being minimized by controlling the current flowing through the switching unit to a certain extent.

[0118] Furthermore, the selection element can be a two-terminal switching element. Using two-terminal switching elements as selection elements for memory cells in this way increases integration density and reduces power consumption. Two-terminal switching elements can be elements such as bidirectional threshold switches, transition metal oxide switches, mixed ion-electron conductor (MIEC) switches, complementary resistor switches, doped amorphous silicon, etc. Such two-terminal switching elements exhibit a large resistance change based on a fixed voltage (i.e., threshold voltage), and this characteristic allows selection of cells in the memory array.

[0119] Furthermore, in this invention, the multiple storage units of the synaptic unit may include selective storage elements capable of simultaneously storing logical states and performing the functions of the selection unit.

[0120] Selective memory elements are elements that possess both the characteristics of non-volatile memory and selectable elements. A selective memory element is one that can store its logic state through changes in resistance, and simultaneously function as a selectable element by causing a change in resistance based on a fixed voltage (i.e., a threshold voltage).

[0121] For example, in the case of a bidirectional threshold switch made of chalcogenide material, different resistance states can be created by applying write voltages of different polarities, and the logic state used therein can be stored and read. Therefore, even chalcogenide materials without phase transitions can be variable resistance elements, and can simultaneously possess the characteristic that the resistance changes constantly before and after the threshold voltage based on unique switching characteristics (i.e., threshold voltage).

[0122] Thus, when using a variable resistance element (such as a conventional bidirectional threshold switch element) containing chalcogenide material without phase change, one or more memory cells can be selected by switching characteristics, and logic states can be stored in each memory cell of multiple memory cells by variable resistance characteristics.

[0123] This type of element can be represented as a selective storage element. In this case, since no additional storage or selection element is required, the density of the memory device can be increased and its power consumption reduced. Chalcogenide materials such as In-Ge-As-Se alloy, Te-Se alloy, As-Se alloy, Ge-Te alloy, Ge-Se alloy, As-Se-Te alloy, Ge-As-Se alloy, Ge-As-Sb alloy, Ge-Sb-Te alloy, Ge-Sb-Se alloy, Ge-As-Te alloy, Si-Ge-As-Se alloy, Si-Te-As-Ge alloy, In-Sb-Te alloy, In-Sb-Se alloy, In-Ge-As alloy, In-Ge-Te alloy, and In-Te alloy can be used. However, there are no particular limitations other than the materials mentioned above, as long as they are materials capable of storing logic states through changes in resistance and simultaneously performing switching functions.

[0124] Furthermore, in this invention, when a non-volatile memory cell uses a two-terminal switching element as a selective memory element that can realize both the storage logic state and the memory cell selection function, or as a selection element for the cell selection function, the voltage of the input signal can be within a range that makes all non-volatile memory cells in the plurality of non-volatile memory cells unconnected, and simultaneously within a range that can distinguish the resistance states of the plurality of non-volatile memory cells.

[0125] The general cell selection process using the switching function in the memory array of this invention is performed by using the characteristics of the switching element to allow only very low current to flow in the unselected cells and applying a voltage that can distinguish the logic state of the cell to the selected cell.

[0126] Reference Figure 16 This describes a general method for reading the current of memory cells disposed in a memory array, which includes two-terminal switching elements or selective storage elements. To determine the logic state of a non-volatile memory cell disposed in the memory array, i.e., whether the cell is on or off, the current of the read voltage V is... read1 Apply to the memory location whose logical state is known. V read1 Located at threshold voltage V th_A With threshold voltage V th_B Between (V) th_A <V read1 <V th_B ), at the threshold voltage V th_A At this point, a sharp resistance change occurs in a cell with low resistance, at the threshold voltage V. th_BAt this point, a sharp change in resistance occurs in a cell with high resistance. In other words, by allowing cells with low resistance (turn-on cells) to turn on due to a sudden change in resistance, and by disallowing sudden changes in resistance in cells with high resistance (turn-off cells), the logic state can be distinguished from the current flowing through the selected cell. Figure 16 In the middle, when V is applied read1 When, current I target,off A current I flows in a cell with high resistance. target,on The current flows in cells with low resistance. In this method, only one cell can be selected from the memory array for read-only digital on and off states. The reason is that the current flowing in the on state is so large that once a read voltage is applied to a single cell in the on state, the current flowing is so large that it is difficult to measure the current in other cells in the same memory array. For this reason, conventional read methods may not be suitable for the operation of the neuromorphic system of the present invention, where it is necessary to simultaneously measure the current of two or more selected memory cells constituting the memory array.

[0127] When operating the neuromorphic system of the present invention, reference will be made to Figure 17 A method suitable for reading current from a synaptic unit is described, the synaptic unit comprising a plurality of memory cells in a memory array having a crosspoint structure and including a two-terminal switching element or a selective memory element.

[0128] like Figure 17 The "V" in read2 The voltage of the input signal applied to the multiple storage cells included in the synaptic unit, as indicated, is within the subthreshold voltage range (less than V). th1 ) and the range of resistance states that can distinguish multiple non-volatile memory cells (exceeding V) sep Within the range of () and (), in the subthreshold voltage range, all multiple non-volatile memory cells, including those in the synaptic unit, are not turned on. That is, in Figure 17 In the middle, V is used as the reading voltage. read2 In a state greater than V sep And less than V th1 Within this range, it is the threshold voltage of the cell in the lowest resistance state among the selected cells, and within this range, like I target That way, the high-resistance state and low-resistance state of the storage element can be distinguished. This range is within... Figure 17 V in Chinese input express.

[0129] In this way, multiple cells can be read simultaneously when the voltage of the input signal is applied in the subthreshold region. This is because, unlike the general method described above, even when the input signal is applied to the turn-on cell, the current flowing through the turn-on cell is not large, so the sum of the currents flowing through multiple non-volatile memory cells can be easily measured.

[0130] In this invention, the multiple non-volatile memory cells of the synaptic unit can be disposed on different output electrode lines, so that each memory cell among the multiple memory cells can have a different number of bits. Figures 8 to 14 An example of this is shown in the figure.

[0131] Furthermore, in embodiments of the present invention, the plurality of non-volatile storage cells of the synaptic unit can be disposed in a plurality of memory arrays. Here, the memory array may refer to a memory array having a cross-point structure.

[0132] For example, such as Figure 18 As shown, synaptic unit W 11 Multiple storage units can be arranged one after another in k memory arrays.

[0133] In this invention, the digital computing unit may include an analog-to-digital converter (ADC) connected to each output electrode line. As described above, current, which is an analog signal, flows in each output electrode line. In order to digitize each output electrode line and each pulse of the input signal, it is necessary to connect the ADC to the individual output electrode line.

[0134] Furthermore, the digital computing unit may include a current path converter connected sequentially to each output electrode line, a capacitor with a digitized bit depth, and an analog-to-digital converter. When the bit depth is specified according to the pulse generation order, the current path converter stores each output signal generated sequentially by each pulse applied to each output electrode line according to the bit depth specified in the pulse generation order in the capacitor with the digitized bit depth. The sum of the output signals stored in the capacitor can be converted into a digital signal by the analog-to-digital converter.

[0135] As another example of the present invention, when the number of bits is specified according to the generation order of the pulses, the digital calculation unit may include an analog-to-digital converter, a digital shifter, and a digital calculator connected sequentially to the respective output electrode lines.

[0136] An analog-to-digital converter converts the sequentially applied pulses, which generate analog output signals for each output electrode line, into a first digital signal. This first digital signal is then converted into a second digital signal by a digital shifter, according to the number of bits in the pulse generation order. A digital calculator then calculates the sum of the converted second digital signals.

Claims

1. A neuromorphic system comprising: an input signal section that generates an input signal; a synapse section that includes a plurality of synapse units that receive the input signal and cause a current to flow in accordance with a set weight, each of the plurality of synapse units including a plurality of nonvolatile storage units capable of selectively storing a logic state, the nonvolatile storage units being arranged in a memory array including input electrode lines and output electrode lines that cross each other, and generating an analog output signal for each output electrode line in accordance with the input signal; a digital calculation section that converts the analog output signal generated for each output electrode line into a digital output signal and calculates a sum of the digital output signals; and a control section that controls the input signal section, the synapse section, and the digital calculation section; wherein the control section: specifies a number of digitization bits for each output electrode line, and stores the logic state in the plurality of nonvolatile storage units in accordance with a predetermined weight in each of the plurality of synapse units; causes the input signal generated by the input signal section to be applied through each input electrode line to each of the plurality of nonvolatile storage units of each of the plurality of synapse units; generates, for each output electrode line, a sum of the currents flowing from the plurality of nonvolatile storage units of each of the plurality of synapse units by the applied input signal as the analog output signal; and causes the digital calculation section to convert the analog output signal generated for each output electrode line into the digital output signal in accordance with the number of bits, and calculate a sum of the digital output signals.

2. The neuromorphic system according to claim 1, the nonvolatile storage unit includes a nonvolatile storage element and a selection element, and the nonvolatile storage element is any one of a flash memory element, a resistive random access memory (RRAM) element, a phase change random access memory (PRAM) element, a magnetic random access memory (MRAM) element, a ferroelectric random access memory (FeRAM) element, and a selective storage element. wherein 3. The neuromorphic system according to claim 1, the nonvolatile storage unit includes a multi-bit storage unit capable of storing two or more bits of information. wherein 4. The neuromorphic system according to claim 3, a bit level of the multi-bit storage unit is determined for each output electrode line by the control section, and the determined bit levels are two or more bit levels that are different from each other. wherein 5. The neuromorphic system according to claim 4, the bit levels become equal or lower as the number of bits increases. wherein 6. The neuromorphic system according to claim 1, the nonvolatile storage unit includes a selective storage element and does not include a selection element. wherein 7. The neuromorphic system according to claim 2, the selection element is a two-terminal element. wherein 8. The neuromorphic system according to claim 2, the selection element is a transistor or a diode. wherein, ​ 9. The neuromorphic system according to claim 6 or claim 7, wherein, a voltage of the input signal is in a range in which all of the plurality of nonvolatile memory cells are not turned on, and is in a range in which resistance states of the plurality of nonvolatile memory cells can be distinguished.

10. The neuromorphic system according to claim 8, wherein the control section controls, by controlling the transistor or diode in each nonvolatile memory cell of the plurality of nonvolatile memory cells in the synapse cell, a current flowing from each selected memory cell of the synapse cell caused by the input signal to be a predetermined current size while allowing the input signal to flow only through the selected memory cell of the synapse cell.

11. The neuromorphic system according to claim 1, wherein, the plurality of nonvolatile memory cells of the synapse cell are provided on different output electrode lines such that each nonvolatile memory cell of the plurality of nonvolatile memory cells has a different bit number.

12. The neuromorphic system according to claim 1, wherein the plurality of nonvolatile memory cells of the synapse cell are provided in two or more memory arrays.

13. The neuromorphic system according to claim 1, wherein the input signal is in the form of a pulse, and the input signal is represented by a frequency, a number, a height, a width, or a combination thereof of the pulse.

14. The neuromorphic system according to claim 1, wherein the digital computation section includes an analog-digital converter (ADC) connected to each of the output electrode lines.

15. The neuromorphic system according to claim 1, wherein for each of the digitized bit numbers, a pair of a positive output electrode line and a negative output electrode line is specified.

16. The neuromorphic system according to claim 1, wherein the control section: causes an input signal generated from the input signal section to be one or more pulses having the same width and height, causes the one or more pulses to be sequentially applied to the synapse section according to a generation order, and causes different digitized bit numbers in the pulses to be assigned to the one or more pulses according to the generation order, causes the analog output signal to be sequentially generated for each of the sequentially applied pulses, and causes the digital computation section to convert the analog output signal generated for each output electrode line for each pulse to the digital output signal in accordance with the bit number in the pulse according to the generation order of the pulse and the bit number of the output electrode line, and to calculate a sum of the digital output signals.

17. The neuromorphic system according to claim 16, wherein the digital computation section includes an analog-digital converter, a digital shifter, and a digital calculator sequentially connected to each of the output electrode lines, the analog-digital converter converts each of the analog output signals sequentially generated for each output electrode line by each of the sequentially applied pulses to a first digital signal, and the digital shifter converts the converted first digital signal to a second digital signal in accordance with the bit number in the pulse according to the generation order of the pulse, the digital calculator calculates a sum of the second digital signals generated for the respective output electrode lines by the one or more pulses, and calculates a value of the digital output signal.

18. The neuromorphic system according to claim 16, wherein, the digital calculation section includes a current path converter, a capacitor, and an analog-digital converter connected in series to each of the output electrode lines, each of the analog output signals sequentially generated for each of the output electrode lines by each of the sequentially applied pulses is stored in the capacitor by the current path converter in accordance with the number of bits in the pulse according to the generation order of the pulse, and a sum of the analog output signals stored in the capacitor is converted into the digital output signal by the analog-digital converter, and calculates a value of the digital output signal.

19. A method for operating a neuromorphic system, the neuromorphic system comprising: an input signal section that generates an input signal; a synapse section that includes a plurality of synapse cells that receive the input signal and flow a current according to a set weight, each of the plurality of synapse cells including a plurality of nonvolatile storage units capable of selectively storing a logic state, the nonvolatile storage units being arranged in a memory array including input electrode lines and output electrode lines that cross each other, and generating an analog output signal for each of the output electrode lines according to the input signal; a digital calculation section that converts the analog output signals generated for each of the output electrode lines into a digital output signal and calculates a sum of the digital output signals; and a control section that controls the input signal section, the synapse section, and the digital calculation section; the method including the steps of: (a) specifying a number of digitized bits for each of the output electrode lines, and storing the logic state in the plurality of nonvolatile storage units according to a predetermined weight in each of the plurality of synapse cells; (b) generating an input signal by the input signal section, and applying the input signal through the input electrode lines to each of the nonvolatile storage units in each of the plurality of synapse cells; (c) generating a sum of currents as the analog output signal for each of the output electrode lines, the currents flowing from the plurality of nonvolatile storage units through the applied input signal for each of the output electrode lines; (d) converting the analog output signal into the digital output signal according to the number of bits for each of the output electrode lines; and (e) calculating a sum of the digital output signals.

20. The method according to claim 19, in the step (b), the input signal is one or more pulses having the same width and height, and the number of digitized bits different from each other is specified in the pulses according to a generation order, so that the one or more pulses are sequentially applied to the plurality of nonvolatile storage units according to the generation order, wherein ​ In the step (c), the analog output signal is generated for each of the sequentially applied pulses, and In the step (d), the analog output signal is converted into the digital output signal in accordance with the number of bits in the pulse and the number of bits of the output electrode line according to the generation order of the pulses.

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