A soft start circuit, a controller and a switching power supply

Abstract

The present invention discloses a soft start circuit, a controller and a switching power supply. The soft start circuit includes a soft start preprocessing circuit, a boost following comparison circuit and a logic circuit. A first output terminal of the soft start preprocessing circuit outputs a first voltage signal to an input terminal of the boost following comparison circuit. The boost following comparison circuit raises the first voltage signal to a second voltage signal, and a feedback voltage signal output from its voltage following terminal follows the second voltage signal. A comparison output terminal of the boost following comparison circuit outputs a third voltage signal to an input terminal of the logic circuit. The logic circuit is configured such that when the feedback voltage signal is lower than the second voltage signal, or when the feedback voltage signal and the second voltage signal are higher than a set voltage range, the third voltage signal flips to a high level. At this time, the logic circuit outputs a signal indicating that the soft start of the switching power supply is completed. The soft start circuit of the present invention can provide soft start protection in various situations where the output voltage climbs or recovers to a set value.

Description

Technical Field

[0001] The present invention relates to the field of integrated circuits, and particularly to an internal soft-start control circuit and method. Background Art

[0002] For a switching power supply controller, in a conventional voltage regulation circuit design, the output voltage of the converter is generally maintained stable through a negative feedback control loop. During the circuit startup phase, since the output voltage has not been established and is far lower than the set value, in order to quickly increase the output voltage, it will cause an input surge current. On the other hand, due to the delay in the loop control, at the moment when the output is established, the frequency cannot be reduced quickly in time, resulting in an overshoot of the output voltage during startup, especially serious in the no-load case. At the same time, when the capacitor of the soft-start circuit is set outside the controller, the peripheral circuit of the controller is not simple enough, bringing inconvenience in use. Therefore, an internal soft-start circuit can well solve such problems. Summary of the Invention

[0003] In view of this, the technical problem to be solved by the present invention is to provide a soft-start circuit, a controller and a switching power supply, which can solve the above-mentioned deficiencies of the prior art to a certain extent.

[0004] As the first aspect of the present invention, the technical solution of the soft-start control circuit embodiment is as follows:

[0005] A soft-start circuit is applied to a switching power supply. The switching power supply includes a PWM controller. The feedback pin of the PWM controller is used to receive a feedback voltage signal VFB and control the operating frequency of the switching power supply accordingly. The soft-start circuit includes:

[0006] A soft-start preprocessing circuit, a boost following comparison circuit and a logic circuit;

[0007] The power supply terminal of the soft-start preprocessing circuit and the power supply terminal of the boost following comparison circuit are connected together, and the grounding terminals are connected together; the first output terminal of the soft-start preprocessing circuit outputs a first voltage signal Vsoft to the input terminal of the boost following comparison circuit; the boost following comparison circuit will raise the first voltage signal Vsoft to a second voltage signal VN, the voltage following terminal of the boost following comparison circuit outputs the feedback voltage signal VFB, and the feedback voltage signal VFB follows the second voltage signal VN; the comparison output terminal of the boost following comparison circuit outputs a third voltage signal S_flag to the input terminal of the logic circuit. The logic circuit is configured to control the signals output by the soft-start preprocessing circuit and the boost following comparison circuit as follows:

[0008] Before the soft start of the switching power supply, the first voltage signal Vsoft is clamped to a first set voltage, and the third voltage signal S_flag is at a high level;

[0009] At the soft start moment of the switching power supply, after a delay time, the third voltage signal S_flag flips to a low level;

[0010] During the soft start process of the switching power supply, the first voltage signal Vsoft gradually rises, and the feedback voltage signal VFB rises with the rise of the first voltage signal Vsoft until the feedback voltage signal VFB is pulled down to be lower than the second voltage signal VN, or when the feedback voltage signal VFB and the second voltage signal VN are higher than a set voltage range, the third voltage signal S_flag flips to a high level, and at this time the logic circuit outputs a signal indicating the completion of the soft start of the switching power supply.

[0011] Further, before the soft start of the switching power supply, the logic circuit shields the rising edge signal of the high level output by the flip of the third voltage signal S_flag.

[0012] Preferably, the soft start preprocessing circuit includes a resistor R1, a switching tube K1, a resistor R2, a capacitor C1, a clamping circuit, and a soft start capacitor C2; one end of the resistor R1 is the power supply terminal of the soft start preprocessing circuit, the other end of the resistor R1 is connected to one end of the capacitor C1 and one end of the switching tube K1 at the same time, the other end of the switching tube K1 is connected to one end of the resistor R2, the other end of the resistor R2 is connected to one end of the clamping circuit, the other end of the clamping circuit and one end of the soft start capacitor C2 are connected together to output the first voltage signal Vsoft, the other end of the capacitor C1 and the other end of the soft start capacitor C2 are connected and then connected to the ground terminal of the soft start preprocessing circuit, the switching tube K1 is controlled by a first control signal provided by the logic circuit, and the clamping circuit is controlled by a second control signal provided by the logic circuit.

[0013] Further, the first control signal is a narrow pulse signal.

[0014] Preferably, the boost follower comparison circuit includes: PMOS transistor MP1, PMOS transistor MP2, tail current source I3, current source I2, current source I1, NMOS transistor MN1, NMOS transistor MN2, NMOS transistor MN3, NMOS transistor MN4, NMOS transistor MN5, NMOS transistor MN6, NMOS transistor MN7, resistor R3, capacitor C3, and capacitor C4; the input terminals of the tail current source I3, the current source I2, and the current source I1 are connected together to be the power supply terminal of the boost follower comparison circuit, the output terminal of the tail current source I3 is simultaneously connected to the source electrodes of the PMOS transistor MP1 and the PMOS transistor MP2, the drain electrode of the PMOS transistor MP1 is simultaneously connected to the drain electrode of the NMOS transistor MN1, the gate electrode of the NMOS transistor MN1, and the gate electrode of the NMOS transistor MN2, the drain electrode of the PMOS transistor MP2 is simultaneously connected to the drain electrode of the NMOS transistor MN2, the gate electrode of the NMOS transistor MN3, the drain electrode of the NMOS transistor MN7, and the gate electrode of the NMOS transistor MN4, the gate electrode of the PMOS transistor MP1, the drain electrode of the NMOS transistor MN5, and the drain electrode of the NMOS transistor MN3 are connected together to be the voltage follower terminal of the boost follower comparison circuit, the voltage follower terminal of the boost follower comparison circuit is coupled to the power supply terminal of the boost follower comparison circuit, one end of the resistor R3 is the input terminal of the boost follower comparison circuit, the other end of the resistor R3 is simultaneously connected to the output terminal of the current source I2, the gate electrode of the PMOS transistor MP2, the drain electrode of the NMOS transistor MN6, and one end of the capacitor C4 for outputting the second voltage signal VN, the output terminal of the current source I1, the drain electrode of the NMOS transistor MN4, and the capacitor C3 are connected together to output the third voltage signal S_flag, the source electrodes of the NMOS transistor MN1, the NMOS transistor MN2, the NMOS transistor MN3, the NMOS transistor MN4, the NMOS transistor MN5, the NMOS transistor MN6, the NMOS transistor MN7, the capacitor C3, and the other end of the capacitor C4 are connected together to be the ground terminal of the boost follower comparison circuit, the NMOS transistor MN6 is controlled by the third control signal provided by the logic circuit, the NMOS transistor MN5 is controlled by the fourth control signal provided by the logic circuit, and the NMOS transistor MN7 is controlled by the fifth control signal provided by the logic circuit.

[0015] Preferably, for the soft start circuit, where:

[0016] The soft start preprocessing circuit includes: a resistor R1, a switching transistor K1, a resistor R2, a capacitor C1, a clamping circuit, and a soft start capacitor C2; one end of the resistor R1 is the power supply terminal of the soft start preprocessing circuit, the other end of the resistor R1 is connected to one end of the capacitor C1 and one end of the switching transistor K1 at the same time, the other end of the switching transistor K1 is connected to one end of the resistor R2, the other end of the resistor R2 is connected to one end of the clamping circuit, the other end of the clamping circuit and one end of the soft start capacitor C2 are connected together to output the first voltage signal Vsoft, the other end of the capacitor C1 and the other end of the soft start capacitor C2 are connected to each other and then connected to the ground terminal of the soft start preprocessing circuit, the switching transistor K1 is controlled by the first control signal provided by the logic circuit, and the clamping circuit is controlled by the second control signal provided by the logic circuit;

[0017] The boost follower comparison circuit includes: PMOS transistor MP1, PMOS transistor MP2, tail current source I3, current source I2, current source I1, NMOS transistors MN1, MN2, MN3, MN4, MN5, MN6, MN7, resistor R3, capacitor C3, and capacitor C4; the input terminals of the tail current source I3, the current source I2, and the current source I1 are connected together to be the power supply terminal of the boost follower comparison circuit, the output terminal of the tail current source I3 is simultaneously connected to the source electrodes of the PMOS transistor MP1 and the PMOS transistor MP2, the drain electrode of the PMOS transistor MP1 is simultaneously connected to the drain electrode of the NMOS transistor MN1, the gate electrode of the NMOS transistor MN1, and the gate electrode of the NMOS transistor MN2, the drain electrode of the PMOS transistor MP2 is simultaneously connected to the drain electrode of the NMOS transistor MN2, the gate electrode of the NMOS transistor MN3, the drain electrode of the NMOS transistor MN7, and the gate electrode of the NMOS transistor MN4, the gate electrode of the PMOS transistor MP1, the drain electrode of the NMOS transistor MN5, and the drain electrode of the NMOS transistor MN3 are connected together to be the voltage follower terminal of the boost follower comparison circuit, the voltage follower terminal of the boost follower comparison circuit is coupled to the power supply terminal of the boost follower comparison circuit, one end of the resistor R3 is the input terminal of the boost follower comparison circuit, the other end of the resistor R3 is simultaneously connected to the output terminal of the current source I2, the gate electrode of the PMOS transistor MP2, the drain electrode of the NMOS transistor MN6, and one end of the capacitor C4, and is used to output the second voltage signal VN, the output terminal of the current source I1, the drain electrode of the NMOS transistor MN4, and the capacitor C3 are connected together to output the third voltage signal S_flag, the source electrodes of the NMOS transistors MN1, MN2, MN3, MN4, MN5, MN6, MN7, the capacitor C3, and the other end of the capacitor C4 are connected together to be the ground terminal of the boost follower comparison circuit, the NMOS transistor MN6 is controlled by the third control signal provided by the logic circuit, the NMOS transistor MN5 is controlled by the fourth control signal provided by the logic circuit, and the NMOS transistor MN7 is controlled by the fifth control signal provided by the logic circuit.

[0018] Preferably, the clamping circuit includes a PMOS transistor PM1, a resistor R4, an inverter, an NMOS transistor NM1, and an NMOS transistor NM2; the source of the PMOS transistor PM1 is connected to the power supply terminal of the soft start preprocessing circuit, the drain of the PMOS transistor PM1 and one end of the resistor R4 are connected together as one end of the clamping circuit, the gate of the PMOS transistor PM1 and the input terminal of the inverter are connected together and input the second control signal, the other end of the resistor R4, the drain of the NMOS transistor NM1, and the gate of the NMOS transistor NM1 are connected together as the other end of the clamping circuit, the source of the NMOS transistor NM1 is connected to the drain of the NMOS transistor NM2, the output terminal of the inverter is connected to the gate of the NMOS transistor NM2, and the source of the NMOS transistor NM2 is connected to the ground terminal of the soft start preprocessing circuit.

[0019] Preferably, the clamping circuit includes an NMOS transistor NM3 and a resistor R5; the drain of the NMOS transistor NM3 is used to input a reference voltage, the gate of the NMOS transistor NM3 is used to input the second control signal, the source of the NMOS transistor NM3 and one end of the resistor R5 are connected together as one end of the clamping circuit, and the other end of the resistor R5 is used as the other end of the clamping circuit.

[0020] As a second aspect of the present invention, the technical solution of the controller embodiment is as follows:

[0021] A controller includes the soft start circuit according to any one of the first aspects above.

[0022] As a third aspect of the present invention, the technical solution of the switching power supply embodiment is as follows:

[0023] A switching power supply includes a PWM controller. The feedback pin of the PWM controller is used to receive a feedback voltage signal VFB and control the operating frequency of the switching power supply accordingly. The operating frequency increases as the feedback voltage signal VFB increases. When the feedback voltage signal VFB rises to a first set value, the operating frequency is the set maximum frequency. When the feedback voltage signal VFB drops to a second set value, the operating frequency is the set minimum frequency. The switching power supply further includes the soft start circuit according to any one of the first aspects above.

[0024] The embodiments of the present invention at least include the following beneficial effects:

[0025] (1) The soft start circuit provided by the embodiment of the present invention can control the rising speed of the first voltage signal through the logic control circuit. Under the boosting and following effects of the boosting and following comparison circuit, the second input voltage and the feedback voltage signal rise slowly, thereby controlling the rising speed of the frequency of the PWM controller, that is, enabling the energy transferred from the primary side to the secondary side of the switching power supply to linearly increase at a certain speed. Thus, it can not only avoid excessive inrush current during startup, but also eliminate the overshoot of the output voltage during startup.

[0026] (2) The soft start circuit provided by the embodiment of the present invention controls the magnitude of the initial voltage of the feedback voltage signal by controlling the first voltage signal to rise to the magnitude of the second voltage signal, thereby realizing the setting of the initial frequency of the controller when the switching power supply starts soft start, avoiding the controller from working in the intermittent mode for a long time, and shortening the startup delay of the switching power supply.

[0027] (3) The soft start circuit in the embodiment of the present invention outputs the first voltage signal specifically by charging the soft start capacitor. The soft start capacitor can be integrated with the soft start circuit inside the controller, which can make the periphery of the controller more concise and convenient to use.

[0028] Other features and advantages of the present invention will be described in the subsequent specification, and, in part, will become apparent from the specification or will be understood by implementing the present invention. The objectives and other advantages of the present invention can be achieved and obtained through the structures specifically pointed out in the specification, claims, and drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1 is the principle block diagram of the soft start circuit according to the first embodiment of the present invention;

[0030] Figure 2 is a specific circuit diagram of the soft start circuit according to the first embodiment of the present invention;

[0031] Figure 3 is the startup timing diagram of the soft start circuit according to the first embodiment of the present invention applied to a switching power supply;

[0032] Figure 4 is Figure 2 an implementation circuit diagram of the clamping circuit diagram in

[0033] Figure 5 is Figure 2 another implementation circuit diagram of the clamping circuit diagram in

[0034] Figure 6 is a schematic diagram of a switching power supply applying the soft start circuit of the present invention.

[0035] SPECIFIC EMBODIMENT CASES

[0036] Next, the technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments in this disclosure without making creative efforts belong to the scope of protection of this disclosure.

[0037] It should be noted that the terms "first", "second", etc. in the specification, claims and the above-mentioned drawings of this application are used to distinguish similar objects, and do not necessarily need to describe a specific order or sequence. It should be understood that such data can be interchanged under appropriate circumstances so as to describe the embodiments of this application here. In addition, the terms "comprising" and "having" and any variations thereof are intended to cover non-exclusive inclusion. For example, a process, method, system, product or device that includes a series of steps or units does not necessarily have to be limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or are inherent to these processes, methods, products or devices.

[0038] It should be understood that in the specification, claims and the drawings of the specification, when it is described that one step is consecutive to another step, this step can be directly consecutive to the other step, or consecutive to the other step through a third step; when it is described that an element / unit is "consecutive" to another element / unit, this element / unit can be "directly connected" to the other element / unit, or "connected" to the other element / unit through a third element / unit.

[0039] In addition, the drawings of this disclosure are only schematic diagrams of this disclosure and are not necessarily drawn to scale. The same reference numerals in the drawings represent the same or similar parts, and thus repeated descriptions thereof will be omitted. Some of the block diagrams shown in the drawings are functional entities and do not necessarily correspond to physically or logically independent entities. These functional entities can be implemented by software, or implemented in one or more hardware modules or integrated circuits, or implemented in different networks and / or processor devices and / or microcontroller devices.

[0040] First Embodiment

[0041] This embodiment provides a soft start circuit applied to a switching power supply. The switching power supply includes a PWM controller. The feedback pin of the PWM controller is used to receive the feedback voltage signal VFB and accordingly control the operating frequency of the switching power supply. Specifically, the operating frequency increases as the feedback voltage signal VFB increases. When the feedback voltage signal VFB increases to a first set value, the operating frequency is the set highest frequency. When the feedback voltage signal VFB decreases to a second set value, the operating frequency is the set lowest frequency. Figure 1The following is a schematic diagram of the soft start circuit according to the first embodiment of the present invention. Please refer to Figure 1 , where the soft start circuit includes:

[0042] A soft start preprocessing circuit 101, a boost following comparison circuit 102, and a logic circuit 103;

[0043] The power supply terminals of the soft start preprocessing circuit 101 and the boost following comparison circuit 102 are connected together, and the ground terminals are connected together; the first output terminal of the soft start preprocessing circuit 101 outputs a first voltage signal Vsoft to the input terminal of the boost following comparison circuit 102; the boost following comparison circuit 102 will raise the first voltage signal Vsoft to a second voltage signal VN, and the voltage following terminal of the boost following comparison circuit 102 outputs a feedback voltage signal VFB, and the feedback voltage signal VFB follows the second voltage signal VN; the comparison output terminal of the boost following comparison circuit 102 outputs a third voltage signal S_flag to the input terminal of the logic circuit. The logic circuit 103 is configured to control the signals output by the soft start preprocessing circuit 101 and the boost following comparison circuit 102 as follows:

[0044] Before the soft start of the switching power supply, the first voltage signal Vsoft is clamped to a first set voltage, and the third voltage signal S_flag is at a high level;

[0045] At the moment of the soft start of the switching power supply, after a delay time, the third voltage signal S_flag flips to a low level;

[0046] During the soft start of the switching power supply, the first voltage signal Vsoft gradually rises, and the feedback voltage signal VFB rises as the first voltage signal Vsoft rises until the feedback voltage signal VFB is pulled down to be lower than the second voltage signal VN, or when the feedback voltage signal VFB and the second voltage signal VN are higher than the set voltage range, the third voltage signal S_flag flips to a high level. At this time, the logic circuit 103 outputs a signal L6 indicating that the soft start of the switching power supply is completed.

[0047] Among them, before the soft start of the switching power supply, the logic circuit 103 controls the third voltage signal S_flag output by the boost following comparison circuit 102 to be at a high level. The purpose is to prevent the third voltage signal S_flag from being at an intermediate potential, which may cause the circuits in the logic circuit 103 to be common, increasing the power consumption of the chip before the soft start and even making the chip unable to work properly.

[0048] Further, before the soft start of the switching power supply, the logic circuit 103 will shield the rising edge signal of the high level output by the flip of the third voltage signal S_flag, aiming to ensure that the soft start circuit can normally enter the subsequent soft start process.

[0049] Figure 2 For a specific circuit diagram of the first embodiment of the present invention, please refer to Figure 2 :

[0050] Among them, the soft start preprocessing circuit 101 includes a resistor R1, a switching transistor K1, a resistor R2, a capacitor C1, a clamping circuit, and a soft start capacitor C2; one end of the resistor R1 is the power supply terminal of the soft start preprocessing circuit 101, and the other end of the resistor R1 is connected to one end of the capacitor C1 and one end of the switching transistor K1 at the same time. The other end of the switching transistor K1 is connected to one end of the resistor R2. The other end of the resistor R2 is connected to one end of the clamping circuit. The other end of the clamping circuit and one end of the soft start capacitor C2 are connected together to output a first voltage signal Vsoft. The other end of the capacitor C1 and the other end of the soft start capacitor C2 are connected together and then connected to the ground terminal of the soft start preprocessing circuit 101. The switching transistor K1 is controlled by a first control signal provided by the logic circuit 103, and the clamping circuit is controlled by a second control signal provided by the logic circuit 103.

[0051] Among them, the boost follower comparison circuit 102 includes: PMOS transistor MP1, PMOS transistor MP2, tail current source I3, current source I2, current source I1, NMOS transistor MN1, NMOS transistor MN2, NMOS transistor MN3, NMOS transistor MN4, NMOS transistor MN5, NMOS transistor MN6, NMOS transistor MN7, resistor R3, capacitor C3 and capacitor C4; the input ends of the tail current source I3, the current source I2 and the current source I1 are connected together to be the power supply end of the boost follower comparison circuit 102, the output end of the tail current source I3 is simultaneously connected to the source electrodes of the PMOS transistor MP1 and the PMOS transistor MP2, the drain electrode of the PMOS transistor MP1 is simultaneously connected to the drain electrode of the NMOS transistor MN1, the gate electrode of the NMOS transistor MN1 and the gate electrode of the NMOS transistor MN2, the drain electrode of the PMOS transistor MP2 is simultaneously connected to the drain electrode of the NMOS transistor MN2, the gate electrode of the NMOS transistor MN3, the drain electrode of the NMOS transistor MN7 and the gate electrode of the NMOS transistor MN4, the gate electrode of the PMOS transistor MP1, the drain electrode of the NMOS transistor MN5 and the drain electrode of the NMOS transistor MN3 are connected together to be the voltage follower end of the boost follower comparison circuit 102, the voltage follower end of the boost follower comparison circuit 102 is coupled to the power supply end of the boost follower comparison circuit 102, one end of the resistor R3 is the input end of the boost follower comparison circuit 102, the other end of the resistor R3 is simultaneously connected to the output end of the current source I2, the gate electrode of the PMOS transistor MP2, the drain electrode of the NMOS transistor MN6 and one end of the capacitor C4, and is used to output the second voltage signal VN, the output end of the current source I1, the drain electrode of the NMOS transistor MN4 and the capacitor C3 are connected together to output the third voltage signal S_flag, the source electrodes of the NMOS transistor MN1, the NMOS transistor MN2, the NMOS transistor MN3, the NMOS transistor MN4, the NMOS transistor MN5, the NMOS transistor MN6, the NMOS transistor MN7, the capacitor C3 and the other end of the capacitor C4 are connected together to be the ground end of the boost follower comparison circuit 102, the NMOS transistor MN6 is controlled by the third control signal provided by the logic circuit 103, the NMOS transistor MN5 is controlled by the fourth control signal provided by the logic circuit 103, and the NMOS transistor MN7 is controlled by the fifth control signal provided by the logic circuit 103.

[0052] Among them, the voltage follower end of the boost follower comparison circuit 102 is coupled to the power supply end of the boost follower comparison circuit 102, which means that it is indirectly connected to the power supply end of the boost follower comparison circuit 102 through the resistor R1 in the soft start preprocessing circuit 101.

[0053] Among them, the input end of the boost follower comparison circuit 102 inputs the first voltage signal Vsoft. After being boosted by the resistor R3, at the connection point of the other end of the resistor R3, the output end of the current source I2, the gate of the PMOS transistor MP2, the drain of the NMOS transistor MN6, and one end of the capacitor C4, the second voltage signal VN is obtained.

[0054] Among them, the PMOS transistor MP1, the PMOS transistor MP2, the NMOS transistor MN1, the NMOS transistor MN2, the NMOS transistor MN2, the tail current source I3 in the boost follower comparison circuit 102 and the resistor R1 in the soft start preprocessing circuit 101 form a follower. The gate of the PMOS transistor MP2 serves as the non-inverting input end of the follower, and the input signal is the second voltage signal VN. The gate of the PMOS transistor MP1 serves as the inverting input end of the follower, and at the same time serves as the voltage follower end of the boost follower comparison circuit 102. The output signal is the feedback voltage signal VFB. When the follower functions as a follower, the feedback voltage signal VFB follows the second voltage signal VN.

[0055] Among them, the charging and discharging process of the capacitor C3 can characterize the potential change of the third voltage signal S_flag.

[0056] Figure 3 This is the soft start circuit startup timing diagram of the first embodiment of the present invention. Next, with the Figure 3 timing, combined with the Figure 2 circuit, the working principle of this embodiment is described:

[0057] (1) Before the soft start of the switching power supply, that is, during the time period from t0 to t2 in Figure 3 , the first control signal output by the logic circuit 103 controls L1 to configure the switching transistor K1 to be turned off, and the second control signal controls L2 to configure the clamping circuit to be turned on to discharge the capacitor C2. The voltage across the capacitor C2 rapidly drops to the clamping voltage, that is, the first voltage signal Vsoft is clamped to the first set voltage by the clamping circuit; at the same time, the third control signal output by the logic circuit 103 controls L3 to configure the NMOS transistor MN6 to be turned on to discharge the capacitor C4, the fourth control signal controls L4 to configure the NMOS transistor MN5 to be turned on to discharge the capacitor C1, and the fifth control signal controls L5 to configure the NMOS transistor MN7 to be turned on. Under the action of the current source I1 charging the capacitor C3, the initial output level of the third voltage signal S_flag is high, preventing the third voltage signal S_flag from being at an intermediate potential. During this time period, to ensure that the soft start circuit can normally enter the subsequent soft start process, the logic circuit 103 will mask the rising edge signal of the high level of the third voltage signal S_flag's flipped output;

[0058] (2) At the soft start moment of the switching power supply, that is, Figure 3At time t2, the first control signal output by the logic circuit 103 controls L1 to configure the switching transistor K1 to conduct, the second control signal controls L2 to configure the clamping circuit to turn off, the third control signal controls L3 to configure the NMOS transistor MN6 to turn off, the fourth control signal controls L4 to configure the NMOS transistor MN5 to turn off, and the fifth control signal controls L5 to configure the NMOS transistor MN7 to turn off. After a delay time (which is extremely short) at this moment, at the instant when the boost following comparison circuit 102 starts to work normally, the MNOS transistor MN4 conducts. Under the pull-down action of the NMOS transistor MN4, the third output signal S_flag is pulled to a low level, and the third voltage signal S_flag is inverted to a low level;

[0059] (3) During the soft start process of the switching power supply, that is Figure 3 In the time period from t2 to t3 in, the first control signal output by the logic circuit 103 controls L1 to continue to be configured to control the switching transistor K1 to conduct, the second control signal controls L2 to continue to be configured to control the clamping circuit to turn off. The soft start capacitor C2 is charged by the VCC voltage at the power supply end of the soft start preprocessing circuit 101 through the first switching transistor and the clamping circuit, so that the first voltage signal Vsoft gradually rises starting from the preset initial value (i.e., the clamping voltage of the clamping circuit). The magnitude of the charging current determines the rising speed of the first voltage signal Vsoft; the third control signal output by the logic circuit 103 controls L3 to continue to be configured to control the NMOS transistor MN6 to turn off, the fourth control signal controls L4 to continue to be configured to control the NMOS transistor MN5 to turn off, and the fifth control signal controls L5 to continue to be configured to control the NMOS transistor MN7 to turn off. The first voltage signal Vsoft is boosted to the second voltage signal VN through the resistor R3, and the feedback voltage signal VFB follows the second voltage signal VN, so that the feedback voltage signal VFB rises as the first voltage signal Vsoft rises, and the feedback voltage signal VFB quickly rises to the preset soft start initial value. At this moment, the feedback voltage signal VFB can be expressed as:

[0060] VFB = Vsoft + I2 * R3

[0061] Where, I2 is the output current value of the constant current source I2, and R3 is the resistance value of the resistor R3.

[0062] It can be seen from the above formula that by adjusting the resistance value of the circuit R3, the magnitude of the initial voltage of the feedback voltage signal VFB can be controlled, thereby realizing the setting of the initial frequency of the PWM controller when the switching power supply starts soft start, avoiding the controller from working in the intermittent mode for a long time, and shortening the start-up delay of the switching power supply; by controlling the rising speed of the first voltage signal Vsoft, the rising speed of the frequency of the PWM controller in the soft start stage can be controlled, which can not only avoid excessive inrush current during startup, but also eliminate the overshoot of the output voltage during startup.

[0063] During the time period from t2 to t3, the third voltage signal S_flag remains at a low level continuously until the feedback voltage signal VFB is pulled down to be lower than the second voltage signal VN, or when the feedback voltage signal VFB and the second voltage signal VN are higher than the set voltage range, the third voltage signal S_flag flips to a high level. At this time, the logic circuit 103 outputs the signal L6 indicating the completion of the soft start of the switching power supply.

[0064] After the moment t3, that is, after a delay time (which is extremely short) at this moment, the fifth control signal controls L5 to configure and control the NMOS transistor MN7 to conduct, so that the boost following comparison circuit 102 loses its following function. The feedback voltage signal VFB is pulled to a low level due to the establishment of the switching power supply system loop, and the switching power supply system starts to switch from open-loop control to closed-loop control. The voltage of the feedback voltage signal VFB gradually rises. When the switching power supply enters the steady-state operation, the final steady-state voltage of the feedback voltage signal VFB is controlled by the feedback loop of the switching power supply system. The first control signal output by the logic circuit 103 controls L1 to configure and control the switch tube K1 to conduct, the second control signal controls L2 to configure and control the clamping circuit to turn off, the third control signal controls L3 to configure and control the NMOS transistor MN6 to turn off, and the fourth control signal controls L4 to configure and control the NMOS transistor MN5 to turn off.

[0065] Further, the second control signal is a narrow pulse signal so that the first voltage signal Vsoft can rise slowly.

[0066] Figure 4 For Figure 2 an implementation circuit diagram of the clamping circuit diagram, please refer to Figure 4 , where the clamping circuit includes a PMOS transistor PM1, a resistor R4, an inverter 1, an NMOS transistor NM1, and an NMOS transistor NM2; the source of the PMOS transistor PM1 is connected to the power supply terminal of the soft start preprocessing circuit 101. The drain of the PMOS transistor PM1 and one end of the resistor R4 are connected together as one end VIN of the clamping circuit. The gate of the PMOS transistor PM1 and the input terminal of the inverter are connected together and then input the second control signal L2. The other end of the resistor R4, the drain of the NMOS transistor NM1, and the gate of the NMOS transistor NM1 are connected together as the other end V0 of the clamping circuit. The source of the NMOS transistor NM1 is connected to the drain of the NMOS transistor NM2. The output terminal of the inverter is connected to the gate of the NMOS transistor NM2. The sources of the NMOS transistors NM2 are connected together and then connected to the ground terminal of the soft start preprocessing circuit 101.

[0067] During the time period from t0 to t2 of the switching power supply, the second control signal L2 output by the logic circuit 103 will keep the control signal of the PMOS transistor PM1 at a low level. The PMOS transistor PM1 and the NMOS transistor NM1 are both turned on. At this time, the clamping voltage V0 at the other end of the clamping circuit can be expressed as:

[0068] V0 = V GS(NM1) + V DS(NM2)

[0069] Among them, V GS(NM1) is the gate-source voltage difference of the NMOS transistor NM1, and V DS(NM2) is the drain-source voltage difference of the NMOS transistor NM2.

[0070] The V O calculated by the above formula is the preset initial value of the first voltage signal Vsoft.

[0071] Among them, the resistor R4 plays a current-limiting role. At the same time, the resistor R4 and the soft-start capacitor C2 form a filter circuit, which can prevent the overshoot phenomenon of the output voltage V0 signal of the clamping circuit.

[0072] When entering the time period from t2 to t3, the second control signal L2 output by the logic circuit 103 will invert the control signal of the PMOS transistor PM1 to a high level. The PMOS transistor PM1 and the NMOS transistor NM1 are both turned off, and the soft-start circuit starts soft-starting. The clamping circuit is equivalent to a resistor. Under the action of the charging current flowing in from one end VIN of the clamping circuit, the soft-start capacitor C2 is charged, and the output voltage V0 will continuously increase with the clamping voltage as the initial value.

[0073] Figure 5 For Figure 2 another implementation circuit diagram of the clamping circuit diagram in, please refer to Figure 5 , where the clamping circuit includes the NMOS transistor NM3 and the resistor R5; the drain of the NMOS transistor NM3 is used to input a reference voltage, the gate of the NMOS transistor NM3 is used to input the second control signal, the source of the NMOS transistor NM3 is connected to one end of the resistor R5 and then used as one end VIN of the clamping circuit, and the other end of the resistor R5 is used as the other end V0 of the clamping circuit.

[0074] During the time period from t0 to t2 of the switching power supply, the second control signal L2 output by the logic circuit 103 will make the control signal of the PMOS transistor PM1 at a high level, and the NMOS transistor NM1 is turned on. At this time, the clamping voltage V0 at the other end of the clamping circuit is equal to the reference voltage VREF, that is, the preset initial value of the first voltage signal Vsoft is the reference voltage VREF.

[0075] When entering the time period from t2 to t3, the second control signal L2 output by the logic circuit 103 will invert the control signal of the PMOS transistor PM1 to a low level, turning off the NMOS transistor NM1. The soft-start circuit starts soft-starting. The clamping circuit is equivalent to a resistor. Under the action of the charging current flowing in from one end VIN of the clamping circuit, the soft-start capacitor C2 is charged, and the output voltage V0 will continuously increase with the clamping voltage as the initial value.

[0076] Second Embodiment

[0077] The controller provided in this embodiment is a kind of controller, including any one of the soft-start circuits in the first embodiment. Since the soft-start circuit of the first embodiment and the soft-start capacitor that needs to be externally placed in the prior art are integrated inside the controller of this embodiment, the periphery of the controller can be made more concise and convenient to use.

[0078] Third Embodiment

[0079] The switch power supply provided in this embodiment includes a PWM controller. The feedback pin of the PWM controller is used to receive the feedback voltage signal VFB and control the operating frequency of the switch power supply accordingly. The operating frequency increases as the feedback voltage signal VFB increases. When the feedback voltage signal VFB rises to the first set value, the operating frequency is the set highest frequency. When the feedback voltage signal VFB drops to the second set value, the operating frequency is the set lowest frequency. The switch power supply of this embodiment also includes any one of the soft-start circuits in the first embodiment. Figure 6 It is the schematic diagram of a switch power supply applying any one of the soft-start circuits in the first embodiment of the present invention. The controller of this switch power supply is a PWM controller, and the primary side feedback technology is adopted. The soft-start circuit of the first embodiment of the present invention is integrated in the PWM controller.

[0080] Please refer to Figure 6 , where the positive pole of the input voltage V of the switch power supply IN is connected to the drain of the main power switch tube SW through the primary winding NP of the transformer. The source of the main power switch tube SW is connected to the negative pole of the input voltage VIN (also known as "ground") through the resistor R CS . The source of the main power switch tube SW is also connected to the current sensing pin of the PWM controller. The gate of the main power switch tube SW is connected to the drive signal output by the controller 100. The secondary winding NS of the transformer is connected in parallel across the two ends of the output capacitor C OUT in sequence through the anode and cathode of the rectifier diode D. The output voltage is the voltage across the two ends of the output capacitor C OUT . The positive port of the output voltage V OUT is connected to one end of the resistor RS1 and one end of the resistor RS3. The V OUTThe negative port is grounded. The resistor RS3 is connected to the 1st terminal of the optocoupler. The 2nd port of the optocoupler is connected to the 1st port of the voltage regulator controller TL431 and one end of the capacitor CS1. The 2nd port of the voltage regulator controller TL431 is connected to one end of the resistor RS1, one end of the resistor RS2, and one end of the capacitor CS1. The 3rd port of the voltage regulator controller TL431 is connected to the other end of the resistor RS2 and then grounded. The 3rd port of the optocoupler is connected to the input feedback pin FB of the PWM controller 100, and the 4th port of the optocoupler is grounded. Figure 3 Some circuits irrelevant to loop control are omitted. The input voltage V IN is the rectified and filtered DC input voltage.

[0081] It should be noted that the soft-start circuit of the present invention is universal. The specific topology of the switching power supply and the primary-side feedback control method in this embodiment are only illustrative and should not be regarded as a limitation to the application scope of the soft-start circuit of the present invention and the switching power supply of the present invention.

[0082] In the time period from t0 to t2 of the switching power supply in this embodiment, the voltage value of the internal auxiliary power supply of the PWM controller rises from 0V to the stable operating voltage value. During this stage, the power-on and initialization are completed inside the PWM controller. During this stage Figure 3 no drive pulse is input to the gate of the primary main power switch tube SW. No energy is transferred from the primary side NP to the secondary side NS of the transformer in the switching power supply. The output voltage V OUT of the switching power supply is at a low level. At this time, the secondary-side circuit cannot be established, that is, no current flows through the optocoupler ports 1 and 2 on the secondary side, and no current flows through the optocoupler ports 3 and 4 on the primary side. The feedback voltage signal VFB is not controlled by the switching power supply system loop.

[0083] In the time period from t2 to t3 of the switching power supply in this embodiment, when the following working conditions occur, the third voltage signal S_flag of the boost following comparison circuit 102 will flip to a high level, output a rising edge signal to the logic circuit 103, and the soft-start circuit inputs the soft-start completion signal L6, and the soft-start process ends.

[0084] After the switching power supply in this embodiment reaches the t3 moment, the switching power supply starts to switch from switch control to closed-loop control. After a period of time, the switching power supply enters the steady-state operation, and the voltage value of the feedback pin VFB is controlled by the feedback voltage loop of the switching power supply.

[0085] (1) During the start-up process of the switching power supply, after the power-on and initialization of the PWM controller are completed, the soft start begins. The PWM controller starts to output a periodic signal with a certain duty cycle at the initial operating frequency to drive the main power transistor M1. The switching power supply starts to output from the primary side to the secondary side output terminal V OUTTransfer energy, during which the voltage value of the feedback voltage signal VFB is equal to the second input voltage VN and rises slowly. As the voltage of the feedback voltage signal VFB rises slowly, the switching frequency of the PWM controller increases, and the energy transferred from the primary side to the secondary side of the switching power supply increases, and the output voltage V of the secondary side OUT begins to rise slowly. When the output voltage V OUT begins to rise to the set value, the switching power supply system begins to switch from open-loop control to closed-loop control. At this moment, current flows into the switching power supply from port 1 of the optocoupler and flows out from port 2 of the optocoupler. The current flowing through the secondary-side optocoupler is amplified according to a certain ratio, so that the current flowing into port 3 of the optocoupler increases instantaneously, causing the voltage of the feedback pin of the control controller to be pulled down instantaneously, so that the voltage of the feedback voltage signal VFB is lower than the second voltage signal VN within a certain period of time. The third voltage signal S_flag will flip to a high level and output a rising-edge signal to the logic circuit 103. The logic circuit 103 will judge that the soft-start circuit has completed soft start.

[0086] (2) If during the startup process of the switching power supply, due to reasons such as output overload, the feedback voltage loop of the switching power supply cannot be fully established during the soft-start process of the switching power supply, and the output voltage V OUT has been unable to rise to the set value, the voltage values of the feedback voltage signal VFB and the second voltage signal VN will continue to rise. When the voltage values of the feedback voltage signal VFB and the second voltage signal VN are higher than the set voltage value range, the third voltage signal S_flag automatically flips to a high level. This rising-edge signal is output to the logic circuit 103, and the logic circuit 103 will judge that the soft-start circuit has completed soft start.

[0087] (3) During the normal operation of the switching power supply, the output voltage V OUT has a short circuit, that is, the output voltage V OUT is 0, and the switching power supply will have a secondary startup phenomenon. During the startup process, the soft-start circuit will start soft start. When the feedback voltage signal VFB rises from the initial voltage value, if the switching power supply is still in a short-circuit state at this time, similarly, the voltage values of the feedback voltage signal VFB and the second voltage signal VN will continue to rise. When the voltage values of the feedback voltage signal VFB and the second voltage signal VN are higher than the set voltage value range, the third voltage signal S_flag automatically flips to a high level. This rising-edge signal is output to the logic circuit 103, and the logic circuit 103 will judge that the soft-start circuit has completed soft start.

[0088] From the above description, it can be seen that the above embodiments of the present application achieve the following technical effects:

[0089] (1) After the PWM controller completes power-on and initialization, after the soft-start preprocessing circuit 101 in the soft-start circuit enables soft start, the feedback voltage VFB quickly rises to a preset value, that is, the PWM controller quickly rises to the initial operating frequency, avoiding the controller from working in the intermittent mode for a long time and shortening the start-up delay of the switching power supply.

[0090] (2) The first control signal output by the logic circuit 103 can control the supply voltage VCC to generate a very small average current to charge the soft-start capacitor C2, so that the first voltage signal Vsoft rises slowly. Under the boosting and following effects of the boosting following comparison circuit 102, the second input voltage VN and the feedback voltage signal VFB rise slowly, thereby controlling the frequency rising speed of the PWM controller, that is, enabling the energy transferred from the primary side to the secondary side of the switching power supply to increase linearly at a certain speed, so as to avoid excessive inrush current during startup and prevent overshoot of the output voltage of the switching power supply.

[0091] The above are specific embodiments of the present invention. It should be noted that for those of ordinary skill in the art, without departing from the principle of the present invention, several improvements and refinements made should also be regarded as the protection scope of the present invention.

Claims

1. A soft start circuit is applied to a switching power supply. The switching power supply includes a PWM controller. The feedback pin of the PWM controller is used to receive a feedback voltage signal VFB and control the operating frequency of the switching power supply accordingly. It is characterized in that, The soft start circuit includes: A soft start preprocessing circuit (101), a boost following comparison circuit (102), and a logic circuit (103); The power supply terminals of the soft start preprocessing circuit (101) and the power supply terminals of the boost following comparison circuit (102) are connected together, and the ground terminals are connected together; the first output terminal of the soft start preprocessing circuit (101) outputs a first voltage signal Vsoft to the input terminal of the boost following comparison circuit (102); the boost following comparison circuit (102) will raise the first voltage signal Vsoft to a second voltage signal VN, the voltage following terminal of the boost following comparison circuit (102) outputs the feedback voltage signal VFB, and the feedback voltage signal VFB follows the second voltage signal VN; the comparison output terminal of the boost following comparison circuit (102) outputs a third voltage signal S_flag to the input terminal of the logic circuit, and the logic circuit (103) is configured to control the signals output by the soft start preprocessing circuit (101) and the boost following comparison circuit (102) as follows: Before the soft start of the switching power supply, the first voltage signal Vsoft is clamped to a first set voltage, and the third voltage signal S_flag is at a high level; At the moment of the soft start of the switching power supply, after a delay time, the third voltage signal S_flag flips to a low level; During the soft start process of the switching power supply, the first voltage signal Vsoft gradually rises, and the feedback voltage signal VFB rises as the first voltage signal Vsoft rises. Until the feedback voltage signal VFB is pulled down to be lower than the second voltage signal VN, or when the feedback voltage signal VFB and the second voltage signal VN are higher than the set voltage range, the third voltage signal S_flag flips to a high level. At this time, the logic circuit (103) outputs the soft start completion signal of the switching power supply.

2. The soft start circuit according to claim 1, wherein: Before the soft start of the switching power supply, the logic circuit (103) will shield the rising edge signal of the high level output by the flip of the third voltage signal S_flag.

3. The soft start circuit according to claim 1, wherein: The soft start preprocessing circuit (101) includes a resistor R1, a switch tube K1, a resistor R2, a capacitor C1, a clamping circuit, and a soft start capacitor C2; one end of the resistor R1 is the power supply terminal of the soft start preprocessing circuit (101), the other end of the resistor R1 is simultaneously connected to one end of the capacitor C1 and one end of the switch tube K1, the other end of the switch tube K1 is connected to one end of the resistor R2, the other end of the resistor R2 is connected to one end of the clamping circuit, the other end of the clamping circuit and one end of the soft start capacitor C2 are connected together to output the first voltage signal Vsoft, the other end of the capacitor C1 and the other end of the soft start capacitor C2 are connected together and then connected to the ground terminal of the soft start preprocessing circuit (101), the switch tube K1 is controlled by a first control signal provided by the logic circuit (103), and the clamping circuit is controlled by a second control signal provided by the logic circuit (103).

4. The soft start circuit according to claim 3, wherein: The first control signal is a narrow pulse signal.

5. The soft start circuit according to claim 1, wherein The boost follower comparison circuit (102) includes: PMOS transistor MP1, PMOS transistor MP2, tail current source I3, current source I2, current source I1, NMOS transistor MN1, NMOS transistor MN2, NMOS transistor MN3, NMOS transistor MN4, NMOS transistor MN5, NMOS transistor MN6, NMOS transistor MN7, resistor R3, capacitor C3, and capacitor C4; the input ends of the tail current source I3, the current source I2, and the current source I1 are connected together to be the power supply end of the boost follower comparison circuit (102), the output end of the tail current source I3 is simultaneously connected to the source electrodes of the PMOS transistor MP1 and the PMOS transistor MP2, the drain electrode of the PMOS transistor MP1 is simultaneously connected to the drain electrode of the NMOS transistor MN1, the gate electrode of the NMOS transistor MN1, and the gate electrode of the NMOS transistor MN2, the drain electrode of the PMOS transistor MP2 is simultaneously connected to the drain electrode of the NMOS transistor MN2, the gate electrode of the NMOS transistor MN3, the drain electrode of the NMOS transistor MN7, and the gate electrode of the NMOS transistor MN4, the gate electrode of the PMOS transistor MP1, the drain electrode of the NMOS transistor MN5, and the drain electrode of the NMOS transistor MN3 are connected together to be the voltage follower end of the boost follower comparison circuit (102), the voltage follower end of the boost follower comparison circuit (102) is coupled to the power supply end of the boost follower comparison circuit (102), one end of the resistor R3 is the input end of the boost follower comparison circuit (102), the other end of the resistor R3 is simultaneously connected to the output end of the current source I2, the gate electrode of the PMOS transistor MP2, the drain electrode of the NMOS transistor MN6, and one end of the capacitor C4, for outputting the second voltage signal VN, the output end of the current source I1, the drain electrode of the NMOS transistor MN4, and the capacitor C3 are connected together to output the third voltage signal S_flag, the source electrodes of the NMOS transistor MN1, the NMOS transistor MN2, the NMOS transistor MN3, the NMOS transistor MN4, the NMOS transistor MN5, the NMOS transistor MN6, the NMOS transistor MN7, the capacitor C3, and the other end of the capacitor C4 are connected together to be the ground end of the boost follower comparison circuit (102), the NMOS transistor MN6 is controlled by the third control signal provided by the logic circuit (103), the NMOS transistor MN5 is controlled by the fourth control signal provided by the logic circuit (103), and the NMOS transistor MN7 is controlled by the fifth control signal provided by the logic circuit (103).

6. The soft start circuit according to claim 1, wherein: The soft start preprocessing circuit (101) includes: a resistor R1, a switching transistor K1, a resistor R2, a capacitor C1, a clamping circuit, and a soft start capacitor C2; one end of the resistor R1 is the power supply terminal of the soft start preprocessing circuit (101), the other end of the resistor R1 is connected to one end of the capacitor C1 and one end of the switching transistor K1 at the same time, the other end of the switching transistor K1 is connected to one end of the resistor R2, the other end of the resistor R2 is connected to one end of the clamping circuit, the other end of the clamping circuit and one end of the soft start capacitor C2 are connected together to output the first voltage signal Vsoft, the other end of the capacitor C1 and the other end of the soft start capacitor C2 are connected together and then connected to the ground terminal of the soft start preprocessing circuit (101), the switching transistor K1 is controlled by a first control signal provided by the logic circuit (103), and the clamping circuit is controlled by a second control signal provided by the logic circuit (103); The boost follower comparison circuit (102) includes: PMOS transistor MP1, PMOS transistor MP2, tail current source I3, current source I2, current source I1, NMOS transistor MN1, NMOS transistor MN2, NMOS transistor MN3, NMOS transistor MN4, NMOS transistor MN5, NMOS transistor MN6, NMOS transistor MN7, resistor R3, capacitor C3, and capacitor C4; the input ends of the tail current source I3, the current source I2, and the current source I1 are connected together to be the power supply end of the boost follower comparison circuit (102), the output end of the tail current source I3 is simultaneously connected to the source electrodes of the PMOS transistor MP1 and the PMOS transistor MP2, the drain electrode of the PMOS transistor MP1 is simultaneously connected to the drain electrode of the NMOS transistor MN1, the gate electrode of the NMOS transistor MN1, and the gate electrode of the NMOS transistor MN2, the drain electrode of the PMOS transistor MP2 is simultaneously connected to the drain electrode of the NMOS transistor MN2, the gate electrode of the NMOS transistor MN3, the drain electrode of the NMOS transistor MN7, and the gate electrode of the NMOS transistor MN4, the gate electrode of the PMOS transistor MP1, the drain electrode of the NMOS transistor MN5, and the drain electrode of the NMOS transistor MN3 are connected together to be the voltage follower end of the boost follower comparison circuit (102), the voltage follower end of the boost follower comparison circuit (102) is coupled to the power supply end of the boost follower comparison circuit (102), one end of the resistor R3 is the input end of the boost follower comparison circuit (102), the other end of the resistor R3 is simultaneously connected to the output end of the current source I2, the gate electrode of the PMOS transistor MP2, the drain electrode of the NMOS transistor MN6, and one end of the capacitor C4, and is used to output the second voltage signal VN, the output end of the current source I1, the drain electrode of the NMOS transistor MN4, and the capacitor C3 are connected together to output the third voltage signal S_flag, the source electrodes of the NMOS transistor MN1, the NMOS transistor MN2, the NMOS transistor MN3, the NMOS transistor MN4, the NMOS transistor MN5, the NMOS transistor MN6, the NMOS transistor MN7, the capacitor C3, and the other end of the capacitor C4 are connected together to be the ground end of the boost follower comparison circuit (102), the NMOS transistor MN6 is controlled by the third control signal provided by the logic circuit (103), the NMOS transistor MN5 is controlled by the fourth control signal provided by the logic circuit (103), and the NMOS transistor MN7 is controlled by the fifth control signal provided by the logic circuit (103).

7. The soft start circuit according to claim 3 or 6, characterized in that: The clamping circuit includes a PMOS transistor PM1, a resistor R4, an inverter, an NMOS transistor NM1, and an NMOS transistor NM2; the source of the PMOS transistor PM1 is connected to the power supply terminal of the soft start preprocessing circuit (101), the drain of the PMOS transistor PM1 and one end of the resistor R4 are connected together and used as one end of the clamping circuit, the gate of the PMOS transistor PM1 and the input terminal of the inverter are connected together and input the second control signal, the other end of the resistor R4, the drain of the NMOS transistor NM1, and the gate of the NMOS transistor NM1 are connected together and used as the other end of the clamping circuit, the source of the NMOS transistor NM1 is connected to the drain of the NMOS transistor NM2, the output terminal of the inverter is connected to the gate of the NMOS transistor NM2, and the source of the NMOS transistor NM2 is connected to the ground terminal of the soft start preprocessing circuit (101).

8. The soft start circuit according to claim 3 or 6, characterized in that: The clamping circuit includes an NMOS transistor NM3 and a resistor R5; the drain of the NMOS transistor NM3 is used to input a reference voltage, the gate of the NMOS transistor NM3 is used to input the second control signal, the source of the NMOS transistor NM3 and one end of the resistor R5 are connected together and used as one end of the clamping circuit, and the other end of the resistor R5 is used as the other end of the clamping circuit.

9. A controller, characterized in that: It includes the soft start circuit according to any one of claims 1 to 8.

10. A switching power supply, the switching power supply includes a PWM controller, a feedback pin of the PWM controller is used to receive a feedback voltage signal VFB, and accordingly control the operating frequency of the switching power supply, the operating frequency increases as the feedback voltage signal VFB increases, when the feedback voltage signal VFB increases to a first set value, the operating frequency is the set highest frequency, when the feedback voltage signal VFB decreases to a second set value, the operating frequency is the set lowest frequency, and it is characterized in that: The switching power supply further includes the soft start circuit according to any one of claims 1 to 8.

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