Electronic device and updating method

Abstract

The electronic device with a connector supporting a multi-connection standard includes a connector, a processor, a controller, an extended display identification read-only memory, a first multi-tasking circuit, and a second multi-tasking circuit. The first multi-tasking circuit is coupled to at least one signal pin of the connector, the processor, and the controller. The second multi-tasking circuit is coupled to the extended display identification read-only memory, the first multi-tasking circuit, the processor, and the controller. In an update state, the controller is electrically connected to the extended display identification read-only memory via the second multi-tasking circuit, and updates extended display identification data in the extended display identification read-only memory with update data.

Description

Technical Field

[0001] This invention relates to an electronic device having a connector that supports multiple connection standards, and more particularly to an electronic device and a method for updating it. Background Technology

[0002] Traditionally, standard display devices have an Extended Display Identification Read-Only Memory (EDID) that stores Extended Display Identification Data (EDID). When an image source device is connected to a standard display device, the image source device reads the EDID from the standard display device to obtain the display information of the standard display device, and then provides a matching image to the standard display device accordingly.

[0003] However, in specialized display devices, extended display capability identification read-only memory is not present; instead, it is located in the image source device. In this case, if the extended display capability identification data for the specialized display device is to be updated, it must be done through the image source device.

[0004] Furthermore, traditionally, image source devices need to have separate connectors for each connection standard to support multiple connection standards. However, the more connectors required, the larger and more expensive the image source device becomes.

[0005] Furthermore, while image source devices can use DisplayPort connectors with custom pin configurations to connect to specialized display devices, these connectors occupy a large area on the input / output panel. Moreover, due to pin limitations, these connectors forgo the standard High Resolution Multimedia Interface – Display Data Channel Bus (HDMI-DDC Bus), making them unsuitable for connection to standard display devices using standard DisplayPort connectors or standard High Resolution Multimedia Interface (HDMI) connectors. This significantly reduces the flexibility of applications for end-users. Summary of the Invention

[0006] The present invention provides an electronic device and an update method that enables the controller to update data in an update state to update the extended display capability identification read-only memory built into the electronic device with a connector that supports multiple connection standards.

[0007] In a first aspect, embodiments of the present invention provide an electronic device having a connector supporting multiple connection standards. The electronic device having a connector supporting multiple connection standards includes a connector, a processor, a controller, an extended display capability identification read-only memory (EPI), a first multitasking circuit, and a second multitasking circuit. The connector includes at least one signal pin. The controller is coupled to the processor. The EPI is used to store EPI identification data. The first multitasking circuit is coupled to at least one signal pin, the processor, and the controller. The second multitasking circuit is coupled to the EPI, the first multitasking circuit, the processor, and the controller. In an update state, the controller is electrically connected to the EPI via the second multitasking circuit and updates the EPI identification data in the EPI with update data.

[0008] Secondly, embodiments of the present invention provide a method for updating an electronic device having a connector supporting multiple connection standards. The updating method includes: in an updating state, updating an Extended Display Capability Identification Read-Only Memory (EPI) with update data via a second multitasking circuit using a controller.

[0009] In summary, the electronic device and its update method with a connector supporting multiple connection standards provided in this invention can establish a link path between the controller and the Extended Display Capability Identification Read-Only Memory (EPIROM) through the switching of a multi-tasking circuit. This allows the controller to update data in the EPIROM built into the electronic device with the connector supporting multiple connection standards during the update process. Furthermore, in the electronic device and its update method with a connector supporting multiple connection standards provided in this invention, in addition to manually causing the processor to send update data to the controller to enter the update state, the controller can also automatically determine whether to enter the update state based on the EPIROM identification data after receiving a device signal. Specifically, after the controller enters the update state based on the determination result, it can also obtain the corresponding update data based on the device signal and perform automatic updates accordingly. Furthermore, the electronic device and its updating method with a connector supporting multiple connection standards provided in the embodiments of the present invention switch the transmission path of at least one signal pin of the connector according to whether a device signal is received, so that a single connector can support multiple connection standards, thereby enabling the electronic device to transmit with standard devices or special devices through this single connector, and to select one of the multiple connection standards for application.

[0010] The following detailed description of the features and advantages of the present invention is sufficient to enable anyone skilled in the art to understand the technical content of the present invention and implement it accordingly. Based on the content disclosed in this specification, the scope of the patent application, and the drawings, anyone skilled in the art can easily understand the related objectives and advantages of the present invention. Attached Figure Description

[0011] Figure 1 This is a schematic diagram of the connection between an electronic device and an external device provided in an embodiment of the present invention;

[0012] Figure 2 This is a schematic diagram of the structure of an electronic device provided in an embodiment of the present invention;

[0013] Figure 3 A flowchart illustrating the update method provided in an embodiment of the present invention;

[0014] Figure 4 A flowchart illustrating another update method provided in an embodiment of the present invention;

[0015] Figure 5 A flowchart illustrating another updating method provided in an embodiment of the present invention;

[0016] Figure 6 A flowchart illustrating step S06 of the update method provided in an embodiment of the present invention;

[0017] Figure 7 A flowchart illustrating another update method provided in an embodiment of the present invention;

[0018] Figure 8 A schematic diagram of the execution flow of the update method provided in the embodiment of the present invention after determining that it does not meet the specifications in step S10;

[0019] Figure 9 A flowchart illustrating the update method provided in this embodiment of the invention after step S22;

[0020] Figure 10 A schematic diagram of the execution flow of the update method provided in the embodiment of the present invention after determining that it does not meet the specifications in step S10;

[0021] Figure 11 A schematic diagram of the execution flow of the update method provided in this embodiment of the invention after step S31;

[0022] Figure 12 This is a schematic diagram of the power supply circuit provided in an embodiment of the present invention;

[0023] Figure 13 This is a schematic diagram of another power supply circuit provided in an embodiment of the present invention. Detailed Implementation

[0024] The present invention will now be described in further detail with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and not intended to limit it. Furthermore, it should be noted that, for ease of description, the accompanying drawings show only the parts relevant to the invention, not the entire structure.

[0025] Figure 1 This is a schematic diagram illustrating the connection between an electronic device and an external device according to an embodiment of the present invention. This embodiment is applicable to situations where an extended display capability identification read-only memory needs to be updated. Please refer to... Figure 1 An electronic device 100 having a connector supporting multiple connection standards includes a connector 101, a processor 102, a controller 103, an extended display capability identification read-only memory 104, and at least two multitasking circuits (hereinafter referred to as a first multitasking circuit 105 and a second multitasking circuit 106, respectively). The controller 103 is coupled to the processor 102. The first multitasking circuit 105 is coupled to the connector 101, the processor 102, and the controller 103. The second multitasking circuit 106 is coupled to the extended display capability identification read-only memory 104, the first multitasking circuit 105, the processor 102, and the controller 103.

[0026] Connector 101 is disposed in the housing of electronic device 100 and can be connected to an external device having a corresponding connector, thereby enabling transmission between electronic device 100 and the external device. In some embodiments, the external device may be another electronic device having a corresponding connector, and is connected to or disconnected from connector 101 of electronic device 100 by plugging and unplugging, but the present invention is not limited thereto. In other embodiments, the external device may be an external device 300, which is connected to one end of transmission line 200 and is connected to or disconnected from electronic device 100 by plugging and unplugging the other end of transmission line 200 through connector 101. The following description uses external device 300 as an example of connecting or disconnecting from electronic device 100 through transmission line 200, but this is not intended to limit the present invention.

[0027] Connector 101 includes at least one signal pin P1. Processor 102 may include a first interface CPU_I1 and a second interface CPU_I2 using different connection standards. Furthermore, controller 103 includes a first interface MCU_I1 and a second interface MCU_I2 using different connection standards.

[0028] Here, the first multitasking circuit 105 is coupled to the signal pin P1 of the connector 101, the first interface CPU_I1 of the processor 102, the first interface MCU_I1 of the controller 103, the second interface MCU_I2 of the controller 103, and the second multitasking circuit 106. The first multitasking circuit 105 can selectively connect the signal pin P1 to the first interface CPU_I1 of the processor 102, the first interface MCU_I1 of the controller 103, the second interface MCU_I2 of the controller 103, or the second multitasking circuit 106 according to the selection signal SEL1 from the controller 103. Furthermore, the second multitasking circuit 106 is coupled to the second interface CPU_I2 of the processor 102, the first interface MCU_I1 of the controller 103, the extended display capability identification read-only memory 104, and the first multitasking circuit 105. The second multitasking circuit 106 can selectively connect the second interface CPU_I2 of the processor 102 to the extended display capability identification read-only memory 104 or the first multitasking circuit 105, or selectively connect the first interface MCU_I1 of the controller 103 to the extended display capability identification read-only memory 104.

[0029] Figure 2 This is a schematic diagram of the structure of an electronic device provided in an embodiment of the present invention. Please refer to [link / reference]. Figure 2 In some embodiments, the second multitasking circuit 106 may include at least two multiplexers (hereinafter referred to as the first multiplexer 106A and the second multiplexer 106B, respectively). The first multiplexer 106A is coupled to the first multitasking circuit 105, the Extended Display Capability Identification Read-Only Memory 104, and the controller 103, and the second multiplexer 106B is coupled to the first multiplexer 106A, the second interface CPU_I2 of the processor 102, and the first interface MCU_I1 of the controller 103. The first multiplexer 106A may selectively electrically connect the second multiplexer 106B to the Extended Display Capability Identification Read-Only Memory 104 or the first multitasking circuit 105 according to the selection signal SEL2 from the controller 103, and the second multiplexer 106B may selectively electrically connect the second interface CPU_I2 of the processor 102 or the first interface MCU_I1 of the controller 103 to the first multiplexer 106A according to the selection signal SEL3 from the controller 103.

[0030] In the initial state of the electronic device 100, the controller 103 can normally generate a selection signal SEL1 with a first set value to the first multitasking circuit 105, so as to control the first multitasking circuit 105 to normally control the first multitasking circuit 105 to electrically connect the signal pin P1 to the first interface MCU_I1 of the controller 103. Furthermore, the controller 103 can normally generate a selection signal SEL2 with a first selection value to the first multiplexer 106A of the second multiplexing circuit 106 to control the first multiplexer 106A to electrically connect the second multiplexer 106B to the extended display capability identification read-only memory 104. It can also normally generate a selection signal SEL3 with a second selection value to the second multiplexer 106B of the second multiplexing circuit 106 to control the second multiplexer 106B to electrically connect the processor 102 to the first multiplexer 106A. This causes the second interface CPU_I2 of the processor 102 to be electrically connected to the extended display capability identification read-only memory 104 in sequence via the second multiplexer 106B and the first multiplexer 106A.

[0031] In some implementations, the first selection value can be logic "0" and the second selection value can be logic "1", but the present invention is not limited thereto, and the first selection value and the second selection value can be designed according to the usage requirements.

[0032] In some embodiments, the electronic device 100 may further include a voltage level shifter 107, which is coupled between the second interface CPU_I2 of the processor 102 and the second multiplexer 106B of the second multiplexing circuit 106. In other words, the second multiplexer 106B of the second multiplexing circuit 106 may also be coupled to the second interface CPU_I2 of the processor 102 via the voltage level shifter 107.

[0033] In some embodiments, the voltage level converter 107 can be used to convert voltage levels. For example, when the second interface CPU_I2 of the processor 102 is used as a display data channel via the connection path between the voltage level converter 107 and the second multitasking circuit 106 electrically connected to the signal pin P1, and an external device 300 can transmit extended display capability identification data to the processor 102 through this connection path, the voltage level converter 107 can convert the voltage level (e.g., from 5 volts to 3 volts) after receiving the extended display capability identification data, and then transmit the converted extended display capability identification data to the processor 102.

[0034] In some embodiments, connector 101 may further include image pin P5, and voltage level converter 107 may be coupled to image pin P5 and controller 103. Here, voltage level converter 107 can be used as a repeater. Voltage level converter 107 can receive a selection signal SEL3 from controller 103 and selectively generate a notification signal HDMI_HPD to processor 102 according to selection signal SEL3. Specifically, when selection signal SEL3 has a first selection value, voltage level converter 107 does not output notification signal HDMI_HPD, while when selection signal SEL3 has a second selection value, voltage level converter 107 outputs notification signal HDMI_HPD to processor 102. Upon receiving the HDMI_HPD notification signal, the processor 102 outputs image data D2 to the voltage level converter 107, which then amplifies the image data D2 and outputs the amplified image data D2 to the external device 300 via the image pin P5 of the connector 101, enabling the external device 300 to display the corresponding image and audio. However, this invention is not limited to this; in other embodiments, the processor 102 may also directly output image data D2 to the image pin P5 of the connector 101 according to the instructions of the controller 103.

[0035] In some embodiments, the electronic device 100 may be a digital video recorder or a computer, and the external device 300 may be various screens, such as touch screens, display screens, etc. The connector 101 may be a standard high-definition multimedia interface (HDMI A Type) port, the signal pin P1 may be pins 15 and 16 of the standard high-definition multimedia interface port as the display data channel (DDC), and the image pin P5 may be pins 1 to 12 of the standard high-definition multimedia interface port used for transmitting time-minimized differential signal (TMDS). Processor 102 may be implemented using a system-on-a-chip (SoC), a central processing unit (CPU), a microprocessor, an application processor (AP), a digital signal processor (DSP), an application-specific integrated circuit (ASIC), or a combination thereof. However, the present invention is not limited thereto, and processor 102 may be any core circuit in electronic device 100 suitable for performing various operations. Controller 103 may be implemented using a microcontroller (MCU), a keyboard controller (KBC), or an embedded controller (EC). However, the present invention is not limited thereto, and controller 103 may be any control circuit suitable for performing a specific task. Furthermore, voltage level converter 107 may be implemented using an integrated chip to simultaneously perform voltage level conversion and signal enhancement functions.

[0036] In some embodiments, the first interface MCU_I1 of the controller 103 may be a standard transmission interface connected via an Inter-Integrated Circuit (I2C) bus, and the second interface MCU_I2 of the controller 103 may be a standard transmission interface connected via a Universal Asynchronous Receiver / Transmitter (UART). Furthermore, the first interface CPU_I1 of the processor 102 may be a standard transmission interface connected via a Universal Serial Bus (USB) 2.0, but the present invention is not limited thereto.

[0037] Extended display capability identification read-only memory 104 is used to store extended display capability identification data. In some embodiments, when the external device 300 connected to the electronic device 100 does not have extended display capability identification data, the processor 102 of the electronic device 100 can read the extended display capability identification read-only memory 104 to generate image data D2 with corresponding display specifications according to the extended display capability identification data and display it to the external device 300.

[0038] In some embodiments, the electronic device 100 may perform an update method according to any embodiment to update the extended display capability identification data in the extended display capability identification read-only memory 104. In one embodiment, the update may be to update an older version of the extended display capability identification data stored in the extended display capability identification read-only memory 104 to a newer version of the extended display capability identification data. In another embodiment, the update may be to change extended display capability identification data that does not conform to the specifications of the external device 300 to extended display capability identification data that conforms to the specifications of the external device 300.

[0039] Figure 3 This is a schematic flowchart illustrating the update method provided in an embodiment of the present invention. Please refer to [link / reference]. Figures 1 to 3 In some embodiments, in step S31, the electronic device 100 may, in an update state, use the controller 103 via the second multitasking circuit 106 to update the extended display capability identification data in the extended display capability identification read-only memory 104 with update data D1. The update data D1 may be a new version of the extended display capability identification data or extended display capability identification data conforming to the specifications of the external device 300.

[0040] Figure 4 This is a flowchart illustrating another update method provided in an embodiment of the present invention. Please refer to [link / reference]. Figures 1 to 4In some embodiments, in step S22, the electronic device 100 can obtain update data D1 using the processor 102, and the processor 102 can transmit the update data D1 to the controller 103 via bus B1, so that the controller 103 can update the Extended Display Capability Identification Read-Only Memory 104. In step S23, when the controller 103 receives the update data D1 from the processor 102, the controller 103 can control the second multitasking circuit 106 to electrically connect the controller 103's first interface MCU_I1 to the Extended Display Capability Identification Read-Only Memory 104, and then continue to execute step S31, so that the controller 103 updates the Extended Display Capability Identification Read-Only Memory 104 with the update data D1. Therefore, in some embodiments, when the controller 103 receives the update data D1 from the processor 102, the electronic device 100 will enter the update state. Here, the controller 103 in the update state controls the second multitasking circuit 106 to electrically connect the controller 103 to the extended display capability identification read-only memory 104, and updates the extended display capability identification read-only memory 104 with update data D1.

[0041] In one embodiment of step S22, the processor 102 may obtain updated data D1 upon receiving an update instruction. The update instruction may be generated by a user manually updating via an input device. In some embodiments, the updated data D1 may be stored in a storage device, and the processor 102 may access this storage device to obtain the updated data D1 according to the update instruction. In some embodiments, the storage device may be a hard disk or a flash drive, etc. Furthermore, the bus B1 may be an integrated circuit bus, but the present invention is not limited thereto.

[0042] In one embodiment of step S23, the controller 103 may generate a selection signal SEL2 having a first selection value and a selection signal SEL3 having a first selection value to the second multitasking circuit 106. Specifically, the first multiplexer 106A of the second multitasking circuit 106 electrically connects the Extended Display Capability Identifier Read-Only Memory 104 to the second multiplexer 106B of the second multitasking circuit 106 according to the selection signal SEL2 having the first selection value, and the second multiplexer 106B electrically connects the controller 103 to the first multiplexer 106A according to the selection signal SEL3 having the first selection value, so that the controller 103 can be electrically connected to the Extended Display Capability Identifier Read-Only Memory 104 sequentially via the second multiplexer 106B and the first multiplexer 106A.

[0043] In some embodiments, such as Figure 1As shown, connector 101 may also include a detection pin P2. Controller 103 is coupled to the detection pin P2 of connector 101. Here, controller 103 can monitor the detection pin P2 and determine whether an external device 300 is connected to connector 101 via transmission line 200 based on whether a hot-plug signal HPD appears on the detection pin P2. In some embodiments, detection pin P2 may be pin 19 of a standard high-resolution multimedia interface port used for hot-plug detection.

[0044] Figure 5 This is a flowchart illustrating another updating method provided in an embodiment of the present invention. Please refer to [link / reference]. Figures 1 to 5 as well as Figure 7 In some embodiments, before steps S04 and S22, the electronic device 100 can use the controller 103 to monitor the detection pin P2 to confirm whether an external device 300 is connected to the connector 101. In step S05, when the controller 103 detects a hot-plug signal HPD on the detection pin P2, it indicates that an external device 300 is connected to the connector 101 via the transmission line 200. At this time, the controller 103 can issue an acknowledgment command C1 through its first interface MCU_I1, and transmit it through the first multitasking circuit 105 and the signal pin P1 to request the external device 300 to respond with a device signal DEV. In this way, the controller 103 can determine whether the external device 300 is a standard device or a special device based on whether it receives the device signal DEV.

[0045] In some embodiments, a special device refers to an electronic device with a controller, whose controller generates a device signal DEV with corresponding content based on the connection standard used for transmission, and replies to the electronic device 100 accordingly. A standard device refers to an electronic device without a controller, and does not generate a device signal DEV in response to the acknowledgment instruction C1. In some embodiments, the acknowledgment instruction C1 may be an instruction addressed using an integrated circuit bus connection standard. Furthermore, the special device may use an integrated circuit bus connection standard, a universal asynchronous transceiver connection standard, or a universal serial bus 2.0 connection standard for transmission, but the present invention is not limited thereto.

[0046] In some embodiments, after executing step S05, if the controller 103 receives a device signal DEV from the external device 300 via the first multitasking circuit 105 and signal pin P1 at its first interface MCU_I1, it indicates that the external device 300 connected to the connector 101 is a special device. Conversely, if the controller 103 does not receive a device signal DEV from the external device 300 at its first interface MCU_I1 after executing step S05, it indicates that the external device 300 connected to the connector 101 is a standard device. In some embodiments, the controller 103 may wait for a predetermined time after executing step S05, and determine that the external device 300 is a standard device if it does not receive the device signal DEV before the end of this predetermined time. In other embodiments, the controller 103 may repeat step S05 and wait for a predetermined time, and determine that the external device 300 is a standard device only after a predetermined number of times. In some embodiments, the predetermined number of times may be between 3 and 10 times, but the present invention is not limited thereto, and the predetermined number of times may be any applicable value.

[0047] In some embodiments, such as Figure 5 As shown, the aforementioned steps S04 and S05 can be executed before step S22. In this embodiment, in step S06, when the controller 103 determines that the external device 300 is a special device after step S05 is executed, the controller 103 can know the connection standard adopted by the external device 300 according to the content of the device signal DEV, and then selectively control the first multitasking circuit 105 to electrically connect the signal pin P1 of the connector 101 to the first interface MCU_I1 of the controller 103, the second interface MCU_I2 of the controller 103, or the first interface CPU_I1 of the processor 102, and control the second multitasking circuit 106 to electrically connect the processor 102 to the extended display capability identification read-only memory 104. Step S07: When the controller 103 determines that the external device 300 is a standard device after executing step S05, the controller 103 can control the first multitasking circuit 105 to electrically connect the signal pin P1 of the connector 101 to the second multitasking circuit 106, and control the second multitasking circuit 106 to electrically connect the processor 102 to the first multitasking circuit 105, so that the signal pin P1 of the connector 101 can be electrically connected to the processor 102 in sequence via the first multitasking circuit 105 and the second multitasking circuit 106.

[0048] Figure 6 This is a flowchart illustrating step S06 of the update method provided in an embodiment of the present invention. Please refer to... Figures 1 to 6In one embodiment of step S06, in step S061, the controller 103 can identify the device signal DEV. In step S062, when the controller 103 identifies the device signal DEV as the first content, the controller 103 can maintain the generation of a selection signal SEL1 with a first set value to the first multitasking circuit 105 to control the first multitasking circuit 105 to electrically connect the signal pin P1 to the first interface MCU_I1 of the controller 103, and generate a selection signal SEL2 with a first selection value to the first multitasking unit 106A and a selection signal SEL3 with a second selection value to the second multitasking unit 106B to control the second multitasking circuit 106 to electrically connect the extended display capability identification read-only memory 104 to the processor 102. Step S063: When the controller 103 identifies the device signal DEV as the second content, the controller 103 can generate a selection signal SEL1 with a second set value to the first multitasking circuit 105 to control the first multitasking circuit 105 to electrically connect the signal pin P1 to the first interface CPU_I1 of the processor 102, and generate a selection signal SEL2 with a first selection value to the first multitasking unit 106A and a selection signal SEL3 with a second selection value to the second multitasking unit 106B to control the second multitasking circuit 106 to electrically connect the extended display capability identification read-only memory 104 to the processor 102. Step S064: When the controller 103 identifies the device signal DEV as the third content, the controller 103 can generate a selection signal SEL1 with a third set value to the first multitasking circuit 105 to control the first multitasking circuit 105 to electrically connect the signal pin P1 to the second interface MCU_I2 of the controller 103, and generate a selection signal SEL2 with a first selection value to the first multitasking unit 106A and a selection signal SEL3 with a second selection value to the second multitasking unit 106B to control the second multitasking circuit 106 to electrically connect the extended display capability identification read-only memory 104 to the processor 102.

[0049] In one embodiment of step S07, the controller 103 may generate a selection signal SEL1 with a fourth set value to the first multitasking circuit 105 to control the first multitasking circuit 105 to electrically connect the signal pin P1 to the second multitasking circuit 106, and the controller 103 may generate a selection signal SEL2 with a second selection value and a selection signal SEL3 with a second selection value to the second multitasking circuit 106 to control the second multitasking circuit 106 to electrically connect the first multitasking circuit 105 to the processor 102.

[0050] In some embodiments, the first content of the device signal DEV may be an integrated circuit bus connection standard, the second content of the device signal DEV may be a Universal Serial Bus 2.0 connection standard, and the third content of the device signal DEV may be a Universal Asynchronous Receiver / Transmitter (UART) connection standard, but the present invention is not limited thereto. Furthermore, the processor 102 may also have a transmission interface CPU_I3 employing the UART connection standard. Therefore, in step S064, the controller 103 may also control the first multitasking circuit 105 to electrically connect the signal pin P1 of the connector 101 to the UART connection interface CPU_I3 in the processor 102.

[0051] In some embodiments, the second interface MCU_I2 of the controller 103 and the transmission interface CPU_I3 of the processor 102 may coexist. In other embodiments, only one of the second interface MCU_I2 of the controller 103 and the transmission interface CPU_I3 of the processor 102 may coexist.

[0052] Figure 7 This is a flowchart illustrating another update method provided in an embodiment of the present invention. Please refer to [link / reference]. Figures 1 to 7 In some embodiments, the electronic device 100 may first execute the aforementioned steps S04 and S05 sequentially. Here, in step S08, when the controller 103 determines that the external device 300 is a special device after executing step S05, the controller 103 may first control the second multitasking circuit 106 to electrically connect the controller 103 to the extended display capability identification read-only memory 104. In step S09, the controller 103 can read the extended display capability identification data in the extended display capability identification read-only memory 104 via the second multitasking circuit 106. In one embodiment of step S08, the controller 103 may generate a selection signal SEL2 with a first selection value and a selection signal SEL3 with a first selection value to the second multiplexer 106B and the first multiplexer 106A of the second multitasking circuit 106, so that the controller 103 can be electrically connected to the extended display capability identification read-only memory 104 sequentially via the second multiplexer 106B and the first multiplexer 106A.

[0053] Following step S09, in step S10, the controller 103 determines whether the extended display capability identification data conforms to the specifications of the external device 300 based on the extended display capability identification data and the device signal DEV. In one embodiment of step S10, the controller 103 determines whether the extended display capability identification data is applicable to the external device 300 based on whether the identity (ID) information carried in the extended display capability identification data matches the identity information carried in the device signal DEV; however, this invention is not limited thereto. In another embodiment of step S10, the controller 103 may also determine whether the extended display capability identification data is applicable to the external device 300 based on the version information in the extended display capability identification data and the device signal DEV.

[0054] When the controller 103 determines in step S10 that the extended display capability identification data does not conform to the specifications of the external device 300, it indicates that the extended display capability identification data is not applicable to the external device 300 and should be updated. At this time, the controller 103 executes step S31 to update the extended display capability identification read-only memory 104 using update data D1. Therefore, in some embodiments, the electronic device 100 can enter an update state when the controller 103 determines that the extended display capability identification data does not conform to the specifications of the external device 300. Here, the controller 103 in the update state can directly update the extended display capability identification read-only memory 104 with update data D1 via the second multitasking circuit 106.

[0055] Figure 8 This is a schematic diagram of the execution flow of the update method provided in this embodiment of the invention after determining that the specification is not met in step S10. Please refer to... Figures 1 to 8 In some embodiments, after determining that the extended display capability identification data does not conform to the specifications of the external device 300 in step S11, the controller 103 may request the processor 102 to transmit corresponding update data D1 to the controller 103 according to the device signal DEV. Furthermore, the controller 103 will only proceed to step S31 after obtaining the update data D1 from the processor 102. However, the present invention is not limited thereto. In other embodiments, after determining that the extended display capability identification data does not conform to the specifications of the external device 300 in step S12, the controller 103 may also obtain the corresponding update data D1 from its internal storage unit according to the device signal DEV, and proceed to step S31 with the update data D1 obtained from the internal storage unit. In one embodiment of step S12, the controller 103 may obtain update data D1 with matching identity information from its internal storage unit according to the identity information in the device signal DEV. In some embodiments, the internal storage unit may be, but is not limited to, a cache of the controller 103.

[0056] In some embodiments, such as Figure 7As shown, when the controller 103 determines in step S10 that the extended display capability identification data conforms to the specifications of the external device 300, it indicates that no update is required. At this time, the controller 103 can execute step S06 to control the first multitasking circuit 105 and the second multitasking circuit 106 to switch out the corresponding connection path according to the content of the device signal DEV.

[0057] In some embodiments, when the controller 103 determines that the external device 300 is a standard device after executing step S05, the controller 103 may execute step S07 and subsequent steps (such as...). Figure 5 and Figure 4 (As shown).

[0058] Figure 9 This is a flowchart illustrating the update method provided in an embodiment of the present invention after step S22. Figure 10 This is a schematic diagram of the execution flow of the update method provided in this embodiment of the invention after determining that the specification is not met in step S10. Please refer to... Figures 1 to 10 In some embodiments, before the execution of steps S24 and S31, the controller 103 may generate a selection signal SEL1 with a fourth set value to the first multitasking circuit 105, such that the first multitasking circuit 105 electrically connects at least one signal pin P1 of the connector 101 to the second multitasking circuit 106. In some embodiments, Figure 9 Steps S23 and S24 can be executed sequentially, in reverse order, or simultaneously. Furthermore, Figure 10 Step S14 can be executed before or simultaneously with step S12 or step S13.

[0059] Figure 11 This is a schematic diagram of the execution flow of the update method provided in this embodiment of the invention after step S31. Please refer to... Figures 1 to 11 ,

[0060] In some embodiments, after the controller 103 completes updating the Extended Display Capability Identification Read-Only Memory 104 with update data D1 in step S32, the controller 103 will sequentially execute a pull-out control procedure and an insertion control procedure. In some embodiments, the controller 103 will execute step S32 after step S31 only if the external device 300 has been determined to be a special device.

[0061] In some embodiments of step S32, the controller 103 may control the first multitasking circuit 105 to electrically connect the signal pin P1 to the first interface MCU_I1 of the controller 103 during the unplug control program, and control the second multitasking circuit 106 to electrically connect the processor 102 to the extended display capability identification read-only memory 104 to restore the electronic device 100 to its initial state.

[0062] In some embodiments, such as Figure 2 As shown, the electronic device 100 further includes a power supply circuit 108, and the connector 101 further includes a power pin P3. The power supply circuit 108 is coupled to the power pin P3 and the controller 103. The power supply circuit 108 can be used to provide a first voltage V1 or a second voltage V2 to the power pin P3 according to the control of the controller 103.

[0063] In some embodiments, when the controller 103 outputs a first enable signal EN1 to the power supply circuit 108, the power supply circuit 108 can output a first voltage V1 to the power supply pin P3. When the controller 103 outputs a second enable signal EN2 to the power supply circuit 108, the power supply circuit 108 outputs a second voltage V2 to the power supply pin P3. The second voltage V2 is higher than the first voltage V1.

[0064] In some embodiments, the power pin P3 of connector 101 may be pin 18 of a standard high-resolution multimedia interface port used for providing power. The first voltage V1 may be, but is not limited to, 5 volts (V), and the second voltage V2 may be, but is not limited to, 12 volts, 14 volts, 18 volts, 24 volts, or 48 volts. The values ​​of the first voltage V1 and the second voltage V2 may be set according to the needs of the external device 300.

[0065] In some embodiments, in the initial state of the electronic device 100, the controller 103 may normally output a first enable signal EN1 to the power supply circuit 108, so that the power supply circuit 108 normally provides a first voltage V1 to the power supply pin P3 according to the first enable signal EN1.

[0066] Figure 12 This is a schematic diagram of the power supply circuit provided in an embodiment of the present invention. Please refer to [link / reference]. Figures 1 to 12 In some embodiments, the power supply circuit 108 may include a power conversion circuit 108A and a power load switch 108B. The power conversion circuit 108A is coupled to the controller 103 and the power supply pin P3, and the power load switch 108B is coupled to the controller 103 and the power supply pin P3. The power conversion circuit 108A is used to convert a second voltage V2 into a first voltage V1, and when it receives a first enable signal EN1 generated by the controller 103, it outputs the converted first voltage V1 to the power supply pin P3. The power load switch 108B is used to receive the second voltage V2, and when it receives a second enable signal EN2 generated by the controller 103, it outputs the second voltage V2 to the power supply pin P3.

[0067] In some embodiments, the power conversion circuit 108A may be implemented using, but is not limited to, a low dropout linear regulator (LDO). Furthermore, the power load switch 108B may be implemented using, but is not limited to, a metal-oxide-semiconductor field-effect transistor (MOSFET), a bipolar junction transistor (BJT), a gallium nitride field-effect transistor (GaN FET), or an insulated-gate bipolar transistor (IGBT).

[0068] Figure 13 This is a schematic diagram of another power supply circuit provided in an embodiment of the present invention. Please refer to [link / reference]. Figures 1 to 13 In other embodiments, the power supply circuit 108 may include a power conversion circuit 108C and a power load switch 108B. The power conversion circuit 108C is coupled to the controller 103 and the power supply pin P3, and the power load switch 108B is coupled to the controller 103 and the power supply pin P3. The power conversion circuit 108C is used to convert a first voltage V1 into a second voltage V2, and when it receives a second enable signal EN2 generated by the controller 103, it outputs the converted second voltage V2 to the power supply pin P3. The power load switch 108B is used to receive the first voltage V1, and when it receives a first enable signal EN1 generated by the controller 103, it outputs the first voltage V1 to the power supply pin P3. In some embodiments, the power conversion circuit 108C may be implemented using, but is not limited to, a buck converter.

[0069] In some embodiments, the electronic device 100 further includes a discharge circuit 109, which is coupled to a power supply pin P3. The discharge circuit 109 can discharge or stop discharging the power supply pin P3 according to a discharge signal DG1 from the controller 103. In some embodiments, when the discharge signal DG1 is high, the discharge circuit 109 can discharge the power supply pin P3. When the discharge signal DG1 is low, the discharge circuit 109 does not discharge or stops discharging the power supply pin P3. However, this invention is not limited thereto, and the discharge circuit 109 can also be modified to discharge the power supply pin P3 when the discharge signal DG1 is low, and not discharge or stop discharging the power supply pin P3 when the discharge signal DG1 is high.

[0070] In some embodiments of step S32, during the unplugging control procedure, the controller 103 may not output the first enable signal EN1 and the second enable signal EN2, causing the power supply circuit 108 to stop supplying power to the power pin P3. The controller 103 may also output a discharge signal DG1, causing the discharge circuit 109 to discharge the power pin P3. After a preset discharge time, the controller 103 stops outputting the discharge signal DG1, causing the discharge circuit 109 to stop discharging the power pin P3, and outputs the first enable signal EN1 to control the power supply circuit 108 to resume providing the first voltage V1 to the power pin P3. In some embodiments, the preset time may be several hundred milliseconds, but the present invention is not limited thereto.

[0071] In some embodiments of step S32, during the insertion control procedure, the controller 103 can monitor the detection pin P2, and when a hot-insertion signal HPD is detected on the detection pin P2, it sends an acknowledgment command C1 via the first multitasking circuit 105 and the signal pin P1 to request a response to the device signal DEV. Upon receiving the device signal DEV, the controller 103 can selectively control the first multitasking circuit 105 to electrically connect the signal pin P1 of the connector 101 to the first interface MCU_I1, the second interface MCU_I2 of the controller 103, or the first interface CPU_I1 of the processor 102, based on the content of the device signal DEV. It also controls the second multitasking circuit 106 to electrically connect the processor 102 to the Extended Display Capability Identification Read-Only Memory 104. When no device signal DEV is received, the controller 103 can control the first multitasking circuit 105 to electrically connect the signal pin P1 of the connector 101 to the second multitasking circuit 106, and control the second multitasking circuit 106 to electrically connect the processor 102 to the first multitasking circuit 105, so that the signal pin P1 of the connector 101 can be electrically connected to the processor 102 in sequence via the first multitasking circuit 105 and the second multitasking circuit 106.

[0072] In some embodiments, where the external device 300 is a special device, after the controller 103 completes the update of the extended display capability identification read-only memory 104, it can, through the sequential execution of the pull-out control program and the insertion control program, cause the first multitasking circuit 105 and the second multitasking circuit 106 to switch to the correct link path (because the controller 103 can perform corresponding control according to the device signal DEV in the insertion control program). Furthermore, the controller 103 can, through the selection signal SEL3 with a second selection value, cause the processor 102 to output image data D2 to the image pin P5, thereby causing the electronic device 100 to enter the display state. With the external device 300 as a standard device, after the controller 103 completes the update of the extended display capability identification read-only memory 104, it can switch the selection signal SEL3 from the first selection value to the second selection value and switch the selection signal SEL2 from the first selection value to the second selection value, so that the second multitasking circuit 106 electrically connects the processor 102 to the first multitasking circuit 105 (at this time, the first multitasking circuit 105 electrically connects the signal pin P1 to the second multitasking circuit 106), and causes the processor 102 to output image data D2 to the image pin P5, so that the electronic device 100 enters the display state.

[0073] In some embodiments, such as Figure 2 As shown, the electronic device 100 further includes a third multitasking circuit 110, and the connector 101 further includes a control pin P4. The third multitasking circuit 110 is coupled to the control pin P4, the processor 102, and the controller 103. The third multitasking circuit 110 is used to selectively connect the control pin P4 of the connector 101 to the processor 102 or the controller 103 according to the selection signal SEL2. Here, when the selection signal SEL2 has a first selection value, the third multitasking circuit 110 electrically connects the control pin P4 to the controller 103. When the selection signal SEL2 has a second selection value, the third multitasking circuit 110 electrically connects the control pin P4 to the processor 102.

[0074] In some embodiments, when the external device 300 is a special device, the external device 300 may output a start signal to the control pin P4 of the connector 101. In some embodiments, the start signal may be generated using a power button. However, the invention is not limited thereto; in other embodiments, the start signal may also be generated when the external device 300 is started. In other embodiments, when the external device 300 is a standard device, standard consumer electronic control signals may be transmitted between the electronic device 100 and the external device 300 via the control pin P4 of the connector 101.

[0075] In some embodiments, the control pin P4 of connector 101 may be pin 13 of a standard high-resolution multimedia interface port for Consumer Electronics Control (CEC).

[0076] In summary, the electronic device 100 and its update method with a connector 101 supporting multiple connection standards provided in this embodiment of the invention can establish a link path between the controller 103 and the extended display capability identification read-only memory 104 by switching the second multitasking circuit 106 in the update state. This allows the controller 103 to update the extended display capability identification read-only memory 104 built into the electronic device 100 with the connector 101 supporting multiple connection standards by updating data D1. Furthermore, in the electronic device 100 and its update method with a connector 101 supporting multiple connection standards provided in this embodiment of the invention, in addition to manually causing the processor 102 to send update data D1 to the controller 103 to enter the update state, the controller 103 can also automatically determine whether to enter the update state based on the extended display capability identification data after receiving the device signal DEV. In particular, after the controller 103 enters the update state due to the determination result, the controller 103 can obtain the corresponding update data D1 based on the device signal DEV and perform automatic updates accordingly. Furthermore, the electronic device 100 and its updating method with a connector 101 supporting multiple connection standards provided in the embodiments of the present invention switch the transmission path of at least one signal pin P1 of the connector according to whether a device signal DEV is received, so that a single connector 101 can support multiple connection standards, thereby enabling the electronic device 100 to transmit with standard devices or special devices through this single connector 101, and to select one of the multiple connection standards for application.

[0077] Note that the above description is merely a preferred embodiment of the present invention and the technical principles employed. Those skilled in the art will understand that the present invention is not limited to the specific embodiments described herein, and various obvious changes, readjustments, and substitutions can be made without departing from the scope of protection of the present invention. Therefore, although the present invention has been described in detail through the above embodiments, the present invention is not limited to the above embodiments, and may include many other equivalent embodiments without departing from the concept of the present invention, the scope of which is determined by the scope of the appended claims.

Claims

1. An electronic device having a connector supporting multiple connection standards, characterized in that, include: A connector, including at least one signal pin; processor; Controller, coupled to the processor; Extended display capability identification read-only memory is used to store extended display capability identification data; A first multitasking circuit is coupled to the at least one signal pin, the processor, and the controller; as well as The second multitasking circuit is coupled to the extended display capability identification read-only memory, the first multitasking circuit, the processor, and the controller; In the update state, the controller is electrically connected to the Extended Display Capability Identification Read-Only Memory via the second multitasking circuit, and updates the Extended Display Capability Identification Data in the Extended Display Capability Identification Read-Only Memory with update data.

2. The electronic device according to claim 1, characterized in that, The controller also receives device signals from external devices via the first multitasking circuit and the at least one signal pin; When the controller receives the device signal, the controller controls the second multitasking circuit to electrically connect the controller to the Extended Display Capability Identification Read-Only Memory, so that the controller reads the Extended Display Capability Identification Data in the Extended Display Capability Identification Read-Only Memory via the second multitasking circuit, and determines whether the Extended Display Capability Identification Data conforms to the specifications of the external device based on the Extended Display Capability Identification Data and the device signal. as well as When it is determined that the extended display capability identification data does not conform to the specifications of the external device, the controller updates the extended display capability identification read-only memory with the updated data via the second multitasking circuit.

3. The electronic device according to claim 2, characterized in that, The controller requests the processor to transmit the updated data to the controller based on the device signal, or the controller obtains the updated data from its internal storage unit based on the device signal.

4. The electronic device according to claim 2, characterized in that, The connector also includes a detection pin, which the controller monitors. When a hot-insertion signal is detected at the detection pin, the controller sends an acknowledgment command via the first multitasking circuit and the at least one signal pin to request the external device to respond with a device signal.

5. The electronic device according to claim 4, characterized in that, When the controller issues the confirmation command but does not receive the device signal, when the controller receives the update data from the processor, the controller controls the second multitasking circuit to electrically connect the controller to the Extended Display Capability Identification Read-Only Memory, so that the controller updates the Extended Display Capability Identification Read-Only Memory with the update data via the second multitasking circuit.

6. The electronic device according to claim 1, characterized in that, When the controller receives the updated data from the processor, the controller controls the second multitasking circuit to electrically connect the controller to the Extended Display Capability Identification Read-Only Memory, so that the controller updates the Extended Display Capability Identification Read-Only Memory with the updated data via the second multitasking circuit.

7. The electronic device according to claim 1, characterized in that, The controller also controls the first multitasking circuit to electrically connect the at least one signal pin to the second multitasking circuit.

8. The electronic device according to claim 1, characterized in that, The second multitasking circuit includes: A first multitasking unit, coupled to the first multitasking circuit and the extended display capability identification read-only memory; and The second multitasking unit is coupled to the first multitasking unit, the processor, and the controller; In the display state, the second multiplexer electrically connects the processor to the first multiplexer, and the first multiplexer electrically connects the second multiplexer to the first multiplexing circuit or the Extended Display Capability Identification Read-Only Memory (EPIROM), such that the processor is electrically connected to the first multiplexing circuit or the EPIROM via the second multiplexer and the first multiplexer; and In the updated state, the second multiplexer electrically connects the controller to the first multiplexer, and the first multiplexer electrically connects the second multiplexer to the Extended Display Capability Identification Read-Only Memory, such that the controller is electrically connected to the Extended Display Capability Identification Read-Only Memory via the second multiplexer and the first multiplexer.

9. The electronic device according to claim 8, characterized in that, Also includes: A voltage level converter, wherein the second multiplexer is coupled to the processor via the voltage level converter.

10. The electronic device according to claim 1, characterized in that, Also includes: A voltage level converter, wherein the second multitasking circuit is coupled to the processor via the voltage level converter.

11. The electronic device according to claim 1, characterized in that, In the display state, the controller controls the first multitasking circuit to electrically connect the at least one signal pin to the controller, the processor, or the second multitasking circuit, and controls the second multitasking circuit to electrically connect the processor to the Extended Display Capability Identification Read-Only Memory or the first multitasking circuit.

12. The electronic device according to claim 2, characterized in that, After the controller completes updating the extended display capability identification read-only memory with the updated data, the controller sequentially executes the pull-out control procedure and the insertion control procedure.

13. The electronic device according to claim 12, characterized in that, In the unplug control program, the controller controls the first multitasking circuit to electrically connect the at least one signal pin to the controller, and controls the second multitasking circuit to electrically connect the processor to the Extended Display Capability Identification Read-Only Memory.

14. The electronic device according to claim 12, characterized in that, The connector also includes a power pin, and the electronic device further includes: A power supply circuit, coupled to the power supply pin, provides a first voltage to the power supply pin; and Discharge circuit, coupled to the power supply pin; When the device signal is received, the controller controls the power supply circuit to provide a second voltage higher than the first voltage to the power supply pin; and During the unplugging control program, the controller controls the power supply circuit to stop supplying power and controls the discharge circuit to discharge the power pin. After the discharge has been performed for a preset time, the controller controls the discharge circuit to stop discharging and controls the power supply circuit to provide the first voltage to the power pin.

15. The electronic device according to claim 12, characterized in that, The connector also includes a detection pin, and in the insertion control program, the controller monitors the detection pin and, upon detecting a hot-insertion signal on the detection pin, issues an acknowledgment command via the first multitasking circuit and the at least one signal pin to request a response to the device signal. Upon receiving the device signal, the controller controls the first multitasking circuit to electrically connect the at least one signal pin to the controller or the processor, and controls the second multitasking circuit to electrically connect the processor to the Extended Display Capability Identification Read-Only Memory.

16. A method for updating an electronic device having a connector supporting multiple connection standards, characterized in that, include: In update mode, the extended display capability identification read-only memory is updated using update data via the controller through the second multitasking circuit. The electronic device is an image source device. The second multitasking circuit is coupled to the extended display capability identification read-only memory, the first multitasking circuit, the processor, and the controller. The first multitasking circuit coupling connector includes at least one signal pin, the processor, and the controller.

17. The method according to claim 16, characterized in that, Also includes: When a device signal from an external device is received via at least one signal pin of the first multitasking circuit and the connector, the controller is electrically connected to the Extended Display Capability Identification Read-Only Memory using the second multitasking circuit. The controller reads the extended display capability identification data from the extended display capability identification read-only memory via the second multitasking circuit. The controller uses the extended display capability identification data and the device signal to determine whether the extended display capability identification data conforms to the specifications of the external device. as well as When it is determined that the extended display capability identification data does not conform to the specifications of the external device, an operation is performed to update the extended display capability identification read-only memory with the updated data using the controller via the second multitasking circuit.

18. The method according to claim 17, characterized in that, Also includes: The controller requests the processor to transmit the updated data to the controller based on the device signal.

19. The method according to claim 17, characterized in that, Also includes: In the updated state, the controller retrieves the updated data from its internal storage unit based on the device signal.

20. The method according to claim 17, characterized in that, Also includes: The controller is used to monitor the detection pins of the connector; as well as When a hot-insertion signal is detected at the detection pin, the controller sends an acknowledgment command via the first multitasking circuit and the at least one signal pin to request the external device to respond with the device signal.

21. The method according to claim 20, characterized in that, Also includes: If the controller issues the confirmation command but does not receive the device signal, when the controller receives the update data from the processor, the controller controls the second multitasking circuit to electrically connect the controller to the Extended Display Capability Identification Read-Only Memory, and performs the operation of updating the Extended Display Capability Identification Read-Only Memory with the update data via the second multitasking circuit.

22. The method according to claim 16, characterized in that, Also includes: The processor transmits the updated data to the controller. as well as When the controller receives the updated data, it uses the controller to control the second multitasking circuit to electrically connect the controller to the Extended Display Capability Identification Read-Only Memory, and performs the operation of updating the Extended Display Capability Identification Read-Only Memory with the updated data via the second multitasking circuit.

23. The method according to claim 16, characterized in that, Also includes: The first multitasking circuit electrically connects at least one signal pin of the connector to the second multitasking circuit.

24. The method according to claim 16, characterized in that, In the display state, the first multiplexer of the second multiplexing circuit electrically connects the Extended Display Capability Identification Read-Only Memory to the second multiplexer of the second multiplexing circuit, and the second multiplexer electrically connects the first multiplexer to the processor. In the update state, the first multiplexer electrically connects the Extended Display Capability Identification Read-Only Memory to the second multiplexer, and the second multiplexer electrically connects the first multiplexer to the controller.

25. The method according to claim 24, characterized in that, The second multiplexer is coupled to the processor via a voltage level converter.

26. The method according to claim 16, characterized in that, Also includes: In the display state, at least one signal pin of the connector is electrically connected to the controller, the processor, or the second multitasking circuit using the first multitasking circuit; as well as In the display state, the processor is electrically connected to the Extended Display Capability Identification Read-Only Memory or the first multitasking circuit using the second multitasking circuit.

27. The method according to claim 17, characterized in that, Also includes: After updating the extended display capability identification read-only memory with the updated data, the controller sequentially executes the pull-out control program and the insertion control program.

28. The method according to claim 27, characterized in that, The pull-out control procedure includes: The at least one signal pin is electrically connected to the controller using the first multitasking circuit; and The processor is electrically connected to the extended display capability identification read-only memory using the second multitasking circuit.

29. The method according to claim 27, characterized in that, Also includes: A first voltage is provided to the power pins of the connector using a power supply circuit; as well as When the device signal is received, the power supply circuit is used to provide a second voltage higher than the first voltage to the power supply pin. The pull-out control program includes: Control the power supply circuit to stop supplying power; The control discharge circuit discharges the power supply pin; and After a preset period of discharge, the discharge circuit is controlled to stop discharging and the power supply circuit is controlled to provide the first voltage to the power supply pin.

30. The method according to claim 27, characterized in that, The insertion control program includes: The controller is used to monitor the detection pins of the connector; When a hot-insertion signal is detected on the detection pin, the controller sends an acknowledgment command via the first multitasking circuit and the at least one signal pin to request a response from the device; and When the device signal is received, the controller controls the first multitasking circuit to electrically connect the at least one signal pin to the controller or the processor, and controls the second multitasking circuit to electrically connect the processor to the Extended Display Capability Identification Read-Only Memory.

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