Failure location method and electronic equipment

Abstract

The present invention provides a failure location method and electronic device. Specifically, the method utilizes the principle that when a polysilicon gate terminal is grounded, a first conductive plug in the active region shorted to the polysilicon gate terminal remains conductive regardless of whether the voltage applied by the probe is positive or negative. In other words, only the electrical signal of the first conductive plug shorted to the polysilicon gate terminal is visible on the generated PicoCurrent image. The method then performs FIB circuit modification on an area of ​​a measurement sample consisting of a located hotspot polysilicon circuit and multiple adjacent polysilicon circuits surrounding the hotspot. This area is then grounded. A picoampere-level current map of the measurement sample is then generated using an atomic force microscope. Based on the bright spots in the picoampere-level current map, the method can quickly and accurately locate the defect location in the test structure of the measurement sample where leakage occurs due to a short circuit between the polysilicon gate in the active region and the conductive plugs located on both sides of the hotspot.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuit manufacturing, and in particular to a failure location method and electronic equipment. Background Art

[0002] In semiconductor technology, it is usually necessary to design various test structures to monitor various semiconductor process problems on the production line. If an electrical failure event occurs during the monitoring of the test structures, the causes of the failure of these test structures can be analyzed to help solve the problems in the process online, thereby promoting the research and development of semiconductor technology.

[0003] Typically, the conventional failure analysis process for a test structure includes: electrical confirmation, failure location location, physical property analysis to find the root cause of the failure; among them, failure location location is a very critical step. Currently, the commonly used failure location location methods in the semiconductor industry can be roughly divided into: thermal emission microscopy (Thermal), photon emission microscopy (EMMI), photoresistance change microscopy (OBIRCH), electron beam resistance change microscopy (EBIRCH), etc.

[0004] However, as semiconductor process technology becomes increasingly advanced, the test structures used for testing are not only larger in area and higher in density, but also more complex. As a result, the leakage caused by failure in many test structures has become very small, and the defects that cause the failure have also become very small. In other words, the conventional failure location analysis methods used in the existing technology cannot accurately determine the failure location on the test structure, or the location is difficult and the positioning accuracy is insufficient.

[0005] Therefore, it is necessary to propose a new failure analysis method that can accurately locate the failure position in large-area, high-density and complex test structures, so that the failure cause can be found through subsequent further failure analysis and the failed product can be improved. Summary of the Invention

[0006] The purpose of the present invention is to provide a failure location method and electronic equipment to solve the technical problems in the prior art that it is impossible to accurately locate the leakage failure position between the gate in the active area of ​​the semiconductor structure or its corresponding test structure and the conductive plugs located on both sides of the gate for electrically connecting its source and drain, as well as the difficulty of positioning and the insufficient positioning accuracy.

[0007] In a first aspect, to solve the above technical problems, the present invention provides a failure location method, which may include at least the following steps:

[0008] A test structure is provided, the test structure comprising an active area, a gate area, and a plurality of polysilicon lines arranged at intervals and passing through the active area and the gate area, wherein a plurality of first conductive plugs are further provided on both sides of each polysilicon line corresponding to the active area;

[0009] performing electrical failure analysis on the test structure to determine a leakage failure path in the test structure;

[0010] performing hotspot capture on the determined leakage failure path to locate the hotspot, and performing FIB circuit repair on a measurement sample of a test structure including a polysilicon circuit including the located hotspot in the gate region and a plurality of adjacent polysilicon circuits therearound, so that the polysilicon circuit including the located hotspot and first conductive plugs located in the active region on both sides thereof are in a conductive state;

[0011] An atomic force microscope is used to obtain a picoampere current diagram of the measurement sample of the polysilicon circuit containing the hotspot, and the leakage failure position contained in the test structure corresponding to the measurement sample is located based on the picoampere current diagram.

[0012] Furthermore, the test structure may further include a plurality of second conductive plugs located in the gate region and covering the polysilicon line.

[0013] Furthermore, the test structure may further include a first metal layer covering the first conductive plug and the second conductive plug and used for externally connecting the test pad.

[0014] Furthermore, a photoresistance change microscope and an electron beam resistance change mode are used to capture hot spots of the identified leakage failure path.

[0015] Furthermore, after the step of locating the hotspot and before the step of performing FIB circuit repair on the measurement sample, the failure location method provided by the present invention may also include: removing the first metal layer to expose the top surfaces of the first conductive plug distributed in the active area and the second metal plug distributed in the gate area.

[0016] Furthermore, the step of performing FIB circuit repair on the measurement sample of the test structure including the polysilicon circuit including the located hotspot in the gate region and a plurality of adjacent polysilicon circuits therearound may specifically include:

[0017] The polysilicon circuit including the located hotspot is set as a target polysilicon circuit, and with the target polysilicon circuit as the center, the target polysilicon circuit in the gate area and multiple polysilicon circuits around it are grounded along a direction crossing the target polysilicon circuit.

[0018] Furthermore, the step of obtaining a picoampere-level current diagram of the measurement sample of the polysilicon circuit containing the hotspot using an atomic force microscope may specifically include:

[0019] Applying a reverse voltage to the first conductive plug in the active area to reverse bias a PN junction formed by a polysilicon circuit corresponding to a non-leakage failure path in a test structure included in the measurement sample and the active area;

[0020] The picoampere current diagram is formed by using an atomic force microscope, wherein the highlighted areas in the picoampere current diagram correspond one-to-one to the electrical signals of the first conductive plugs connected to the leakage failure locations.

[0021] Furthermore, after the step of locating the leakage failure position contained in the test structure corresponding to the measurement sample according to the picoampere current diagram, the failure analysis method provided by the present invention may also include: performing further physical failure analysis on the test structure contained in the measurement sample to determine the failure cause of the leakage failure position.

[0022] Furthermore, the step of performing electrical failure analysis on the test structure to determine a leakage failure path in the test structure may specifically include:

[0023] A voltage is provided to the first conductive pad and the second conductive pad through the test pad to determine an area where a short circuit failure problem occurs on the test structure, and the area where the short circuit failure problem occurs is defined as the leakage failure path.

[0024] In a second aspect, based on the same inventive concept as the failure localization method described above, the present invention further provides an electronic device, which may include a processor, a communication interface, a memory, and a communication bus, wherein the processor, the communication interface, and the memory communicate with each other via the communication bus;

[0025] Memory for storing computer programs;

[0026] The processor is configured to implement any of the steps of the failure location method described in the first aspect when executing a program stored in the memory.

[0027] In a third aspect, based on the same inventive concept as the failure localization method described above in the present invention, the present invention also provides a computer-readable storage medium, in which a computer program is stored. When the computer program is executed by a processor, the method steps of any failure localization method described in the first aspect are implemented.

[0028] In a fourth aspect, based on the same inventive concept as the failure localization method described above in the present invention, the present invention also provides a computer program product comprising instructions, which, when running on a computer, enables the computer to execute the method steps of any of the failure localization methods described in the first aspect above.

[0029] Compared with the prior art, the technical solution of the present invention has at least one of the following beneficial effects:

[0030] In a failure location method proposed in the present invention, it utilizes the principle that when the polysilicon gate terminal is grounded, the first conductive plug in the active area short-circuited with the polysilicon gate terminal can always remain in a conductive state regardless of whether the voltage applied by the probe is positive or negative. In other words, only the electrical signal of the first conductive plug short-circuited with the polysilicon gate can always be seen in the formed picoampere-level current diagram (PicoCurrent image). The area consisting of the polysilicon circuit containing the located hotspot and multiple adjacent polysilicon circuits in the measurement sample is modified by FIB circuit modification, that is, the formed area is grounded. Then, an atomic force microscope is used to form a picoampere-level current diagram of the measurement sample. Based on the bright spots in the picoampere-level current diagram, the defect location where the polysilicon gate in the active area of ​​the test structure in the measurement sample and the conductive plugs located on both sides thereof are short-circuited and cause leakage can be quickly and accurately located.

[0031] Obviously, in the failure localization method provided by the present invention, it is only necessary to first remove the first metal layer covering the surfaces of the first conductive plug and the second conductive plug for the external power supply in the test structure to expose the conductive plugs. Then, the FIB circuit modification function of the FIB device is used to ground a portion of the second conductive plug on the surface of the polysilicon circuit that is suspended and exposed in the gate area (to achieve the purpose of grounding the polysilicon circuit). The atomic force microscope can then be used to quickly and accurately determine the leakage failure location, thereby improving the failure analysis efficiency and reducing the failure analysis cost, while providing strong support for further physical failure analysis to find the root cause of the leakage failure location, and for the development of new processes and improvement of yield. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] Figure 1A schematic diagram of a layout of a test structure for determining whether a polysilicon gate and metal plugs in active areas on both sides thereof have leakage defects caused by shorting between the two in the prior art;

[0033] Figure 2 This is a heat map of hotspots located using OBIRCH;

[0034] Figure 3 SEM plan view of the abnormal first metal plug located for VC;

[0035] Figure 4 This is a SEM plan view of the verification result of the electrical test of the first metal plug with VC abnormality;

[0036] Figure 5 This is a flow chart of a failure location method provided in one embodiment of the present invention;

[0037] Figure 6 A schematic diagram of the layout of a final test structure obtained by using a failure localization method provided in an embodiment of the present invention;

[0038] Figure 7 This is a plan view obtained after a partial area P including a target polysilicon circuit is grounded after the gate area 2 is repaired by FIB circuit repair using the failure localization method provided by the present invention in one embodiment of the present invention;

[0039] Figure 8 In one embodiment of the present invention Figure 7 The cross-sectional image obtained after the corresponding planar TEM sample is converted into a cross-sectional TEM sample. DETAILED DESCRIPTION

[0040] As described in the background technology, at present, as semiconductor process technology becomes more and more advanced, the test structures used for testing are not only larger in area and higher in density but also more complex. Therefore, the leakage caused by failure of many test structures becomes very small, and the defects that cause failures also become very small. That is, the conventional failure position location analysis methods used in the existing technology cannot accurately determine the failure position on the test structure, or the positioning is difficult and the positioning accuracy is insufficient.

[0041] Figure 1This is a schematic diagram of a test structure used in the prior art to determine whether a polysilicon gate and the metal plugs located in the active area on either side of it have leakage defects caused by shorting. Reference numeral 100 represents a polysilicon gate strip, 120 represents a first metal plug located in the active area and electrically connected to the active area, 130 represents a second metal plug located in the non-active area and electrically connected to the polysilicon gate strip 100, and 140a and 140b represent metal layers used to electrically connect the first metal plug 120 and the second metal plug 130, respectively. Furthermore, metal layers 140a and 140b are connected to external pads (not shown).

[0042] Currently, for Figure 1 The layout of the test structure shown in the figure shows that the second metal plug 130 of the polysilicon gate strip 100 is connected to the test pad through the metal layer 140b, and the two first metal plugs 120 located in the active area are also connected to different test pads through the metal layer 140a, which is used to monitor the leakage problem between the polysilicon gate strip 100 and the first metal plug 120. The conventional analysis process is to first use OBIRCH / EBIRCH to capture the point, but the hot spot can only be roughly located, for example Figure 1 The test structure layout shown corresponds to a test structure size of approximately 60um by 120um. The corresponding test structure contains tens of thousands of polysilicon gate strips 100 and metal plugs. This hotspot is insufficient to locate the leakage failure location. The measurement sample needs to be further processed to the CT layer (metal plug layer). Using a nanoprober, a probe is inserted into the first metal plugs of dozens or even tens of polysilicon gate strips near the hotspot. An appropriate voltage is applied to the probe, and the secondary electron image is viewed using SEM mode. Based on the principle of AVC, the first metal plug leaking from the polysilicon gate strip will show a different voltage contrast than the other first metal plugs in the SEM image, highlighting the first metal plug leaking from the polysilicon gate strip, thereby accurately locating the defect. However, this method is labor-intensive and has a low success rate. First, the hotspot location is imprecise, requiring multiple tests. Second, the contrast difference caused by VC is not obvious, requiring extensive engineer experience.

[0043] Taking a real case as an example, Figure 2 This is a plan view of the hotspot located using OBIRCH. In a test structure measuring 60um*120um, the distance from the hotspot to the edge of the structure was roughly measured, and the measurement sample was ground to the metal plug layer. A NanoProber needle was then inserted into the second metal plug of the polysilicon gate strip. Using the AVC principle, with the hotspot as the center, combined with SEM observation, repeated attempts were made until the first metal plug with VC anomaly was found. Figure 3This is the SEM plan view of the VC positioning of the abnormal first metal plug. It can be seen that the VC difference is very slight. This step requires very high standards from engineers. Figure 4 This is a SEM plan view of the results of a second electrical test on the first metal plug with VC anomaly. It shows that the first metal plug with VC anomaly is indeed short-circuited with the polysilicon gate strip, effectively pinpointing the exact location of the leakage failure. TEM analysis was then performed. Clearly, the failure analysis methods used in existing technologies, such as those described above, present technical challenges such as difficulty, time consumption, high cost, and difficulty in ensuring accurate analysis.

[0044] In response to this problem, the inventors of the present invention discovered through analysis that: when the polysilicon gate terminal is grounded, regardless of whether the voltage applied by the probe is positive or negative, the first conductive plug in the active area short-circuited with the polysilicon gate terminal can always remain in a conductive state. In other words, only the electrical signal of the first conductive plug short-circuited with the polysilicon gate can always be seen on the formed picoampere current diagram (PicoCurrent image). Therefore, as long as a reverse voltage is applied to the probe so that the first conductive plug in the active area that is not short-circuited with the polysilicon gate terminal and the PN junction it forms are reverse biased, it cannot be seen on the picoampere current diagram (PicoCurrent image). That is, the brightly marked area in the picoampere current diagram (Pico Current image) corresponds one-to-one with the electrical signal of the first conductive plug connected to the leakage failure position, thereby achieving the purpose of accurately locating the leakage failure position.

[0045] To this end, the present invention provides a failure location method and electronic equipment to solve the technical problems in the prior art of being unable to accurately locate the leakage failure position between the gate in the active area of ​​the semiconductor structure or its corresponding test structure and the conductive plugs located on both sides thereof for electrically connecting its source and drain, as well as the difficulty of positioning and insufficient positioning accuracy.

[0046] The failure location method and electronic device proposed in the present invention are further described in detail below with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become clearer based on the following description. It should be noted that the drawings are all in a very simplified form and are not in precise proportions, and are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention. In the following description, many specific details are set forth to facilitate a full understanding of the present invention, but the present invention can also be implemented in other ways different from those described herein, so the present invention is not limited to the specific embodiments disclosed below.

[0047] As shown in this application and the claims, unless the context clearly indicates an exception, the words "a", "an", "a kind" and / or "the" do not specifically refer to the singular and may also include the plural. Generally speaking, the terms "include" and "comprise" only indicate the inclusion of clearly identified steps and elements, and these steps and elements do not constitute an exclusive list. The method or device may also include other steps or elements. When describing the embodiments of the present invention in detail, for the sake of convenience, the cross-sectional views showing the device structure will not be partially enlarged according to the general proportion, and the schematic views are only examples, which should not limit the scope of protection of the present invention. In addition, in actual production, the three-dimensional spatial dimensions of length, width and depth should be included.

[0048] See Figure 5 , Figure 5 This is a flow chart of a failure location method provided in one embodiment of the present invention. Figure 5 As shown, the failure location method provided by the present invention may include at least the following steps:

[0049] Step S501, providing a test structure, the test structure comprising an active area, a gate area, and a plurality of polysilicon lines spaced apart and extending through the active area and the gate area, wherein a plurality of first conductive plugs are disposed on both sides of each polysilicon line corresponding to the active area;

[0050] Step S502, performing electrical failure analysis on the test structure to determine a leakage failure path in the test structure;

[0051] Step S503: performing hotspot capture on the determined leakage failure path to locate the hotspot, and performing FIB circuit repair on a measurement sample of a test structure including a polysilicon circuit including the located hotspot in the gate region and a plurality of adjacent polysilicon circuits therearound, so that the polysilicon circuit including the located hotspot and the first conductive plugs located in the active region on both sides thereof are in a conductive state;

[0052] In step S504 , an atomic force microscope is used to obtain a picoampere current diagram of the measurement sample including the polysilicon circuit of the hotspot, and a leakage failure position in the test structure corresponding to the measurement sample is located according to the picoampere current diagram.

[0053] In the above step S501, a test structure is first provided, wherein the test structure is used to test whether there is a short circuit between the polysilicon gate and the metal plug (named as the first conductive plug CT1 in the present invention) in the active region, thereby causing a leakage defect. Therefore, in this embodiment, the test structure can be as follows: Figure 1The test structure corresponding to the layout shown in the figure is only adjusted by the failure analysis method used in the present invention, so as to obtain the test structure finally used in the present invention. Figure 6 The test structure layout shown corresponds to the test structure.

[0054] Specific, combined Figure 6 In step S501, the test structure used may include an active area 1, a gate area 2, and a plurality of polysilicon lines P1 to Pn arranged at intervals and passing through the active area 1 and the gate area 2, and a plurality of first conductive plugs CT1 are also arranged on both sides of each polysilicon line corresponding to the active area 1.

[0055] In addition, the test structure used in this step also includes a plurality of second conductive plugs CT2 located in the gate region 2 and covering the polysilicon line, and a first metal layer (not shown) covering the first conductive plugs CT1 and the second conductive plugs CT2 and used for external test pads.

[0056] It is understandable that the test structure including the above components can be formed using conventional semiconductor manufacturing processes. For example, the active area and the gate area can be divided on a material such as silicon, germanium, silicon germanium, carbon silicon, carbon germanium silicon, indium arsenide, gallium arsenide, indium phosphide or other III / V compound semiconductors, or a material such as silicon on insulator, stacked silicon on insulator, stacked silicon germanium on insulator, silicon germanium on insulator and germanium on insulator, and then a plurality of polysilicon lines are formed on the surface of the entire material, which are spaced apart and pass through the active area and the gate area. Then, CT1 for connecting the active area and CT2 for connecting the polysilicon line on the gate area are formed on both sides of each polysilicon line in the active area. The steps will not be repeated here.

[0057] In step S502, the test structure described in step S501 (also known as Figure 1 An electrical failure analysis is performed on the test structure corresponding to the test structure layout shown in the figure to determine the leakage failure path in the test structure.

[0058] As a preferred example, the step of performing electrical failure analysis on the test structure to determine a leakage failure path in the test structure may include:

[0059] In step S502.1, a voltage is applied to the first conductive pad and the second conductive pad via the test pad to determine an area on the test structure where a short circuit failure occurs, and the area where the short circuit failure occurs is defined as the leakage failure path. Then, in step S503, a hotspot is captured for the leakage failure path.

[0060] In step S503, a photoresistance change microscope and an electron beam induced resistance change mode (OBIRCH / EBIRCH) can be used to capture the hotspot of the determined leakage failure path to locate the hotspot. Then, the sample preparation function of the FIB device is used to prepare the test structure to obtain a measurement sample (not shown). After that, the FIB circuit repair is performed on the measurement sample of the test structure including the polysilicon circuit located in the gate region 2 and the located hotspot and multiple adjacent polysilicon circuits therearound, that is, the following is obtained. Figure 6 The layout corresponding to the final test structure after modification according to the present invention is shown, so that the polysilicon circuit including the located hotspot and the first conductive plugs located in the active area on both sides thereof are in a conductive state.

[0061] After locating the hotspot in step S503 and before performing FIB circuit repair on the measurement sample, the failure localization method further needs to perform the following steps:

[0062] Step S503.1, remove the same Figure 1 The test structure corresponding to the test layout shown includes the first metal layer (not shown) for electrically connecting the first conductive plug CT1 and the second conductive plug CT2, so as to expose the top surfaces of the first conductive plug CT1 distributed in the active area 1 and the second metal plug CT2 distributed in the gate area 2.

[0063] Obviously, in this embodiment, the purpose of removing the first metal layer covering the surfaces of the first conductive plug and the second conductive plug for external power supply in the test structure is to expose the conductive plugs, namely, the second conductive plug CT2 and the first conductive plug CT1 for electrically connecting to the polysilicon circuit, respectively. Due to the doping process, these two will form a PN junction with the active region. Therefore, the step S503 of performing FIB circuit repair on the measurement sample of the test structure including the located hotspot polysilicon circuit and multiple adjacent polysilicon circuits therearound is to ground a portion of the second conductive plug CT2 on the surface of the polysilicon circuit that is suspended and exposed in the gate region, that is, to achieve the purpose of grounding the polysilicon circuit.

[0064] Then, by utilizing the principle that when the polysilicon gate terminal is grounded, the first conductive plug CT1 in the active area 1 short-circuited with the polysilicon gate terminal can always remain in a conductive state regardless of whether the voltage applied by the probe is positive or negative, that is, only the electrical signal of the first conductive plug CT1 short-circuited with the polysilicon gate terminal can always be seen on the formed PicoCurrent image (picoampere current diagram), thereby achieving the purpose of the present invention.

[0065] As a preferred example, the present invention provides a specific step of performing FIB circuit repair on a measurement sample of a test structure including a polysilicon circuit located in the gate region 2 and including the located hotspot and a plurality of adjacent polysilicon circuits therearound, comprising:

[0066] Step S503.2: The polysilicon circuit including the located hot spot is set as a target polysilicon circuit, and the target polysilicon circuit in the gate region and the surrounding polysilicon circuits (such as Figure 6 The areas shown in the figure (Mark) are all grounded.

[0067] In this embodiment, after the first metal layer of the measurement sample is removed and processed to the conductive plug layer, it can be transferred to the FIB device and the original Figure 6 The multiple polysilicon lines corresponding to the area Mark shown in are grounded. Specifically, the target polysilicon line containing the located hotspot can be used as the center and extended left and right along the X direction (along the direction across the target polysilicon line) in the gate area 2 to ensure that the polysilicon lines near the hotspot (i.e., the gate Poly) are included; then, a grounding Mark that meets the requirements is designed, and the relative angle between the measurement sample and the I-beam can be selected between 0-52 degrees. Here, an angle of 52 degrees is taken as an example, the ion beam action mode selects "Cleaning regular section", the etching depth is required to reach the substrate, and the scanning direction is arbitrary.

[0068] In step S504, refer to Figure 7 , using an atomic force microscope, obtaining a picoampere current diagram of the measurement sample of the polysilicon circuit containing the hot spot, and locating the leakage failure position contained in the test structure corresponding to the measurement sample according to the picoampere current diagram, such as Figure 8 The bridge location shown in .

[0069] In this embodiment, the measurement sample prepared in the above steps is transferred to the AFMbase Nano Prober for PicoCurrent testing, and finally a picoampere current graph is obtained.

[0070] As a preferred example, the step of obtaining a picoampere current diagram of the measurement sample of the polysilicon circuit containing the hotspot using an atomic force microscope includes:

[0071] Step S504.1, applying a reverse voltage to the first conductive plug in the active region to reverse bias a PN junction formed by the polysilicon circuit corresponding to the non-leakage failure path in the test structure included in the measurement sample and the active region;

[0072] Step S504.2: Using an atomic force microscope, form the picoampere current map, wherein the highlighted areas in the picoampere current map correspond one-to-one to the electrical signals of the first conductive plugs connected to the leakage failure locations.

[0073] Furthermore, after locating the leakage failure position contained in the test structure corresponding to the measurement sample according to the picoampere current diagram in step S504, the failure analysis method further includes:

[0074] Step S505 : performing further physical failure analysis on the test structure included in the measurement sample to determine the failure cause of the leakage failure location.

[0075] In summary, in a failure location method proposed in the present invention, it utilizes the principle that when the polysilicon gate terminal is grounded, the first conductive plug in the active area short-circuited with the polysilicon gate terminal can always remain in a conductive state regardless of whether the voltage applied by the probe is positive or negative. That is, only the electrical signal of the first conductive plug short-circuited with the polysilicon gate can always be seen on the formed picoampere current diagram (PicoCurrent image). The area consisting of the polysilicon circuit containing the located hotspot and multiple adjacent polysilicon circuits around it in the measurement sample is modified by the FIB circuit, that is, the formed area is grounded, and then the picoampere current diagram of the measurement sample is formed in combination with an atomic force microscope. Based on the bright spots in the picoampere current diagram, the defect position of the polysilicon gate in the active area of ​​the test structure in the measurement sample and the conductive plugs located on both sides thereof causing leakage due to the short circuit can be quickly and accurately located.

[0076] Obviously, in the failure localization method provided by the present invention, it is only necessary to first remove the first metal layer covering the surfaces of the first conductive plug and the second conductive plug for the external power supply in the test structure to expose the conductive plugs. Then, the FIB circuit modification function of the FIB device is used to ground a portion of the second conductive plug on the surface of the polysilicon circuit that is suspended and exposed in the gate area (to achieve the purpose of grounding the polysilicon circuit). The atomic force microscope can then be used to quickly and accurately determine the leakage failure location, thereby improving the failure analysis efficiency and reducing the failure analysis cost, while providing strong support for further physical failure analysis to find the root cause of the leakage failure location, and for the development of new processes and improvement of yield.

[0077] In addition, an embodiment of the present invention further provides an electronic device, including a processor, a communication interface, a memory, and a communication bus, wherein the processor, the communication interface, and the memory communicate with each other via the communication bus.

[0078] Memory for storing computer programs;

[0079] The processor is used to implement the method and steps described in the above failure location method when executing the program stored in the memory.

[0080] For the specific implementation of each step of this method and related explanations, please refer to the above Figure 6 The method embodiment shown is not described in detail here.

[0081] In addition, other implementations of the application setting method implemented by the processor executing the program stored in the memory are the same as the implementations mentioned in the aforementioned method embodiment part and will not be repeated here.

[0082] In another embodiment of the present invention, a computer-readable storage medium is provided. The computer-readable storage medium stores a computer program. When the computer program is executed by a processor, the steps of the above-mentioned failure location method are implemented.

[0083] In another embodiment of the present invention, the present invention further provides a computer program product comprising instructions, which, when executed on a computer, enables the computer to execute the above-mentioned failure localization method.

[0084] In the above embodiments, all or part of the embodiments can be implemented using software, hardware, firmware, or any combination thereof. When implemented using software, all or part of the embodiments can be implemented in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, the processes or functions described in accordance with the embodiments of the present invention are generated in whole or in part. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, the computer instructions can be transmitted from one website, computer, server, or data center to another website, computer, server, or data center via a wired (e.g., coaxial cable, optical fiber, digital subscriber line) or wireless (e.g., infrared, wireless, microwave, etc.) method. The computer-readable storage medium can be any available medium that can be accessed by a computer or a data storage device such as a server or data center that includes one or more available media. The available medium can be a magnetic medium (e.g., a floppy disk, a hard disk, a tape), an optical medium (e.g., ), or a semiconductor medium (e.g., a solid-state drive (SSD)).

[0085] It should be noted that, in this document, relational terms such as first and second, etc., are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply the existence of any such actual relationship or order between these entities or operations. Moreover, the terms "comprises," "comprising," or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article, or device comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or device. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of other identical elements in the process, method, article, or device comprising the element.

[0086] Each embodiment in this specification is described in a related manner. Similar portions between the various embodiments can be referenced to each other. Each embodiment focuses on the differences between the other embodiments. In particular, the device, user terminal, computer-readable storage medium, and computer program product embodiments are generally similar to the method embodiments, so their descriptions are relatively simple. For related portions, reference can be made to the descriptions of the method embodiments.

[0087] The above description is only a preferred embodiment of the present invention and is not intended to limit the scope of protection of the present invention. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present invention are included in the scope of protection of the present invention.

Claims

1. A failure location method, characterized in that: At least the following steps are included: A test structure is provided, the test structure comprising an active area, a gate area, and a plurality of polysilicon lines arranged at intervals and passing through the active area and the gate area, wherein a plurality of first conductive plugs are further provided on both sides of each polysilicon line corresponding to the active area; performing electrical failure analysis on the test structure to determine a leakage failure path in the test structure; performing hotspot capture on the determined leakage failure path to locate the hotspot, and performing FIB circuit repair on a measurement sample of a test structure including a polysilicon circuit including the located hotspot in the gate region and a plurality of adjacent polysilicon circuits therearound, so that the polysilicon circuit including the located hotspot and first conductive plugs located in the active region on both sides thereof are in a conductive state; Using an atomic force microscope, obtaining a picoampere-level current diagram of the measurement sample of the polysilicon circuit containing the hotspot, and locating a leakage failure position contained in the test structure corresponding to the measurement sample based on the picoampere-level current diagram; The step of obtaining a picoampere-level current diagram of the measurement sample of the polysilicon circuit containing the hotspot using an atomic force microscope comprises: Applying a reverse voltage to the first conductive plug in the active area to reverse bias a PN junction formed by a polysilicon circuit corresponding to a non-leakage failure path in a test structure included in the measurement sample and the active area; The picoampere current diagram is formed by using an atomic force microscope, wherein the highlighted areas in the picoampere current diagram correspond one-to-one to the electrical signals of the first conductive plugs connected to the leakage failure locations.

2. The failure location method according to claim 1, wherein: The test structure further includes a plurality of second conductive plugs located in the gate region and covering the polysilicon line.

3. The failure location method according to claim 2, wherein: The test structure further includes a first metal layer covering the first conductive plug and the second conductive plug and used for externally connecting a test pad.

4. The failure location method according to claim 1, wherein: The photoresistance change microscope and electron beam induced resistance change mode are used to capture the hot spots of the identified leakage failure path.

5. The failure location method according to claim 3, wherein: After the step of locating the hotspot and before the step of performing FIB circuit repair on the measurement sample, the failure locating method further includes: removing the first metal layer to expose the top surfaces of the first conductive plug distributed in the active area and the second metal plug distributed in the gate area.

6. The failure location method according to claim 5, wherein: The step of performing FIB circuit repair on a measurement sample of a test structure including a polysilicon circuit located in the gate region and including the located hotspot and a plurality of adjacent polysilicon circuits therearound comprises: The polysilicon circuit including the located hotspot is set as a target polysilicon circuit, and with the target polysilicon circuit as the center, the target polysilicon circuit in the gate area and multiple polysilicon circuits around it are grounded along a direction crossing the target polysilicon circuit.

7. The failure location method according to claim 1, wherein: After the step of locating the leakage failure position contained in the test structure corresponding to the measurement sample according to the picoampere current diagram, the failure analysis method also includes: performing further physical failure analysis on the test structure contained in the measurement sample to determine the failure cause of the leakage failure position.

8. The failure location method according to claim 3, wherein: The step of performing electrical failure analysis on the test structure to determine a leakage failure path in the test structure includes: A voltage is provided to the first conductive pad and the second conductive pad through the test pad to determine an area where a short circuit failure problem occurs on the test structure, and the area where the short circuit failure problem occurs is defined as the leakage failure path.

9. An electronic device, characterized in that: It includes a processor, a communication interface, a memory and a communication bus, wherein the processor, the communication interface and the memory communicate with each other via the communication bus; Memory for storing computer programs; A processor is configured to implement the method steps of the failure localization method according to any one of claims 1 to 8 when executing a program stored in a memory.

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