Wiring substrate

Abstract

The present application provides a wiring substrate, which is excellent in flatness and has fine wiring. The wiring substrate of the embodiment has a first conductor layer (11), a first interlayer insulating layer (13) covering the first conductor layer (11), a second conductor layer (21), and a first via conductor (14) penetrating the first interlayer insulating layer (13) and connecting the first conductor layer (11) and the second conductor layer (21), the first interlayer insulating layer (13) includes a first insulating layer (101) and a second insulating layer (102), the first insulating layer (101) includes a wiring portion (110) formed locally on a side opposite to the second insulating layer (102), and the wiring portion (110) includes a buried wiring layer filling a groove (101b) formed in the first insulating layer (101).

Description

TECHNICAL FIELD

[0001] The present application relates to a wiring substrate. BACKGROUND

[0002] A multilayer substrate disclosed in Patent Literature 1 includes: an insulating layer in which a fine pattern layer is formed on an upper surface; and an insulating layer in which a circuit pattern layer is formed on an upper surface, the circuit pattern layer having a larger pattern pitch than the fine pattern layer. The insulating layer in which the circuit pattern layer is formed on the upper surface is formed of a material having a higher rigidity than the insulating layer in which the fine pattern layer is formed on the upper surface.

[0003] Patent Literature 1: Japanese Patent Application Publication No. 2014-131017

[0004] In the multilayer substrate disclosed in Patent Literature 1, the insulating layer in which the circuit pattern layer is formed on the upper surface is formed of a material having a higher rigidity, and the insulating layer in which the fine pattern layer is formed on the upper surface is formed of a material having a smaller surface roughness in order to be able to form the fine pattern. Sometimes, the fine pattern layer and the insulating layer in which the fine pattern layer is formed on the upper surface are insufficient in planarity. Sometimes, problems such as connection failure within a circuit occur. SUMMARY

[0005] The wiring substrate of the present application has: a first conductor layer; a first interlayer insulating layer covering the first conductor layer; a second conductor layer formed on the first interlayer insulating layer; and a first via conductor penetrating the first interlayer insulating layer and connecting the first conductor layer and the second conductor layer. Further, the first interlayer insulating layer includes a first insulating layer and a second insulating layer stacked in a thickness direction thereof, the first insulating layer includes a wiring portion partially formed on a side of a surface opposite to the second insulating layer, the second insulating layer is located on a side opposite to a side of the first insulating layer in contact with a lower surface of the first conductor layer, and the wiring portion includes a buried wiring layer filling a groove formed in the first insulating layer.

[0006] According to the embodiment of the present application, it is possible to provide a wiring substrate having a wiring portion including a form buried in an insulating layer only in a necessary portion. BRIEF DESCRIPTION OF DRAWINGS

[0007] Figure 1 is a cross-sectional view showing an example of a wiring substrate of one embodiment of the present application.

[0008] Figure 2A is a cross-sectional view showing a manufacturing method of a wiring substrate of one embodiment.

[0009] Figure 2B is a cross-sectional view showing a manufacturing method of a wiring substrate of one embodiment.

[0010] Figure 2C FIG. 1 is a cross-sectional view showing a manufacturing method of a wiring substrate according to one embodiment.

[0011] Figure 2D FIG. 1 is a cross-sectional view showing a manufacturing method of a wiring substrate according to one embodiment.

[0012] Figure 2E FIG. 1 is a cross-sectional view showing a manufacturing method of a wiring substrate according to one embodiment.

[0013] Figure 2F FIG. 1 is a cross-sectional view showing a manufacturing method of a wiring substrate according to one embodiment.

[0014] Figure 2G FIG. 1 is a cross-sectional view showing a manufacturing method of a wiring substrate according to one embodiment.

[0015] Figure 2H FIG. 1 is a cross-sectional view showing a manufacturing method of a wiring substrate according to one embodiment.

[0016] Figure 2I FIG. 1 is a cross-sectional view showing a manufacturing method of a wiring substrate according to one embodiment.

[0017] Explanation of Reference Numerals

[0018] 1: wiring substrate; 2: core insulating layer; 2a: through-hole of core insulating layer; 2c: metal foil; 2e: first electroplated film; 2f: second electroplated film; 3: via conductor; 3a: void; 4: resin; 5: conductor pad; 10: core substrate; 11: first conductor layer; 13: first interlayer insulating layer; 14: first via conductor; 21: second conductor layer; 21p: connection pad; 23: second interlayer insulating layer; 24: second via conductor; 31: third conductor layer; 34: third via conductor; 40: interlayer insulating layer; 42: conductor layer; 42p: connection pad; 43: via conductor; 44: fourth via conductor; 101: first insulating layer; 102: second insulating layer; 110: wiring portion; A: component mounting region; FW: fine wiring. DETAILED DESCRIPTION

[0019] A manufacturing method of a wiring substrate according to one embodiment will be described with reference to the drawings. Furthermore, in the drawings to be referred to below, the accurate ratios of the respective structural elements are not indicated, but the drawings are drawn in a manner that makes it easy to understand the features of the present application. In the drawings, the same reference numerals are used for the same components. Figure 1 In FIG. 1, as one example of the configuration that the wiring substrate according to one embodiment can have, a cross-sectional view of a wiring substrate 1 is shown.

[0020] As shown in FIG. 1, the wiring substrate 1 includes a core substrate 10, a first conductor layer 11, a first interlayer insulating layer 13, a first via conductor 14, a second conductor layer 21, a second interlayer insulating layer 23, a second via conductor 24, a third conductor layer 31, a third via conductor 34, an interlayer insulating layer 40, a conductor layer 42, a connection pad 42p, a via conductor 43, a fourth via conductor 44, a first insulating layer 101, and a second insulating layer 102. Figure 1As shown, the wiring substrate 1 includes an insulating layer (core insulating layer) 2 and two conductor layers (a third conductor layer 31 and a fourth conductor layer 41) formed on two main surfaces (a first surface 2F and a second surface 2B) of the core insulating layer 2, respectively, which are opposed in the thickness direction of the core insulating layer 2. The core substrate 10 of the wiring substrate 1 is composed of the core insulating layer 2, the third conductor layer 31, and the fourth conductor layer 41. The third conductor layer 31 is formed on the first surface 2F of the core insulating layer 2, and the fourth conductor layer 41 is formed on the second surface 2B. The core insulating layer 2 includes a via conductor 3 that penetrates the core insulating layer 2 and connects the third conductor layer 31 and the fourth conductor layer 41.

[0021] On the first surface 2F of the core substrate 10, the second interlayer insulating layer 23, the first conductor layer 11, the first interlayer insulating layer 13, and the second conductor layer 21 are stacked in this order from the first surface 2F side. On the other hand, on the second surface 2B of the core substrate 10, each of two interlayer insulating layers 40 and each of two conductor layers 42 are alternately stacked. In the illustrated example, a surface composed of the first interlayer insulating layer 13 and the second conductor layer 21 forms the first surface 1F of the wiring substrate 1. In addition, a surface composed of the outermost interlayer insulating layer 40 and the conductor layer 42 forms the second surface 1B of the wiring substrate 1.

[0022] Further, in the description of the embodiments, the side away from the core insulating layer 2 in the thickness direction of the wiring substrate 1 is also referred to as the "upper side" or the "outer side", the "upper portion", or simply the "upper", and the side close to the core insulating layer 2 is also referred to as the "lower side" or the "inner side", the "lower portion", or simply the "lower". Also, in each of the conductor layers and each of the interlayer insulating layers, the surface toward the side opposite to the core insulating layer 2 is also referred to as the "upper surface", and the surface toward the side of the core insulating layer 2 is also referred to as the "lower surface".

[0023] In each of the interlayer insulating layers 13, 23, and 40, a connection conductor (a via conductor) that penetrates each of the interlayer insulating layers and connects conductor layers adjacent to each other through each of the interlayer insulating layers is formed. In the second interlayer insulating layer 23, a fourth via conductor 44 that connects the third conductor layer 31 and the first conductor layer 11 is formed. In the first interlayer insulating layer 13, a first via conductor 14 that connects the first conductor layer 11 and the second conductor layer 21 is formed. In the present embodiment, the length of the first via conductor 14 is substantially equal to the length of the fourth via conductor 44. That is, the thickness of the first interlayer insulating layer 13 is substantially equal to the thickness of the second interlayer insulating layer 23. In the interlayer insulating layer 40, a via conductor 43 that connects the conductor layers 42 to each other or the fourth conductor layer 41 and the conductor layers 42 is formed.

[0024] The through-hole conductor 3 is formed within the through-hole 2a of the core insulating layer 2 in such a way that it does not completely fill the interior of the through-hole 2a, but has a predetermined thickness on the inner wall of the through-hole 2a. That is, the through-hole conductor 3 has a cavity 3a extending through the core insulating layer 2 in the thickness direction, and as a whole has a cylindrical shape along the inner wall of the through-hole 2a. The through-hole conductor 3 can be, for example, made of a metal film.

[0025] The void 3a is preferably substantially completely filled by the resin 4. The material of the resin 4 is not particularly limited, as long as it can fill the void 3a. The resin 4 can be non-conductive or conductive. For example, the resin 4 can be an insulating resin such as epoxy resin, acrylic resin, or phenolic resin, or a conductive paste or conductive ink containing conductive particles such as silver particles and epoxy resin. As the resin 4, a resin having a thermal expansion coefficient close to that of the core insulating layer 2 can also be selected. This can sometimes reduce the thermal stress generated within the core insulating layer 2.

[0026] The first conductor layer 11, the second conductor layer 21, the third conductor layer 31, the fourth conductor layer 41, and the conductor layer 42, as well as the first via conductor 14, the fourth via conductor 44, the via conductor 43, and the through-hole conductor 3, can be formed using any metal such as copper or nickel. The first conductor layer 11, the second conductor layer 21, the conductor layer 42, the first via conductor 14, the fourth via conductor 44, and the via conductor 43... Figure 1 The example has a 2-layer structure, but it can have a single-layer structure or a stacked structure with any number of layers. Figure 1 In the example, conductor layers 11, 21, 42 and via conductors 14, 44, 43 respectively comprise, for example, a metal film formed by electroless electroplating or sputtering, and an electroplated film formed on the metal film by electrolytic electroplating using the metal film as a power supply layer. The first via conductor 14 is integrally formed with the second conductor layer 21. The fourth via conductor 44 is integrally formed with the first conductor layer 11. Furthermore, the via conductor 43 is integrally formed with the conductor layer 42.

[0027] exist Figure 1 In the example, the through-hole conductor 3 is formed on the inner wall of the through-hole 2a by a first electroplated film 2e, in a manner that covers the inner wall. That is, the first electroplated film 2e is formed in a cylindrical shape with the thickness direction of the core insulating layer 2 as the axial direction. The first electroplated film 2e can be formed, for example, by an electroless electroplated film formed on the inner wall of the through-hole 2a, and an electrolytic electroplated film formed inside the electroless electroplated film in the through-hole 2a, using the electroless electroplated film as a power supply layer, in a manner that covers the electroless electroplated film. However, the through-hole conductor 3 can be formed by one or more electroplated films of any number of layers. In addition, in Figure 1 In the figure, the first electroplated film 2e is represented as a single layer as a metal film.

[0028] The third conductor layer 31 and the fourth conductor layer 41 each comprise a stacked structure having three or fewer layers. Figure 1 In the example, the third conductor layer 31 and the fourth conductor layer 41 each have a three-layer structure. The three-layer structure includes, for example, a metal foil 2c, a first electroplated film 2e on the metal foil 2c, and a second electroplated film 2f on the first electroplated film 2e, respectively, stacked on the first surface 2F and the second surface 2B of the core insulating layer 2. The second electroplated film 2f... Figure 1 The metal film is represented as a single layer with a one-layer structure, but it can be formed, similar to the first electroplating film 2e, from an electroless electroplating film and an electrolytic electroplating film formed on the electroless electroplating film by using the electroless electroplating film as a power supply layer.

[0029] The metal foil 2c can be formed of any metal, such as copper foil, nickel foil, etc. For example, the metal foil 2c is a copper foil bonded to the core insulating layer 2 by hot pressing. The first electroplated film 2e and the second electroplated film 2f are formed, for example, using any metal such as copper or nickel. The first electroplated film 2e and the second electroplated film 2f may also include a sputtered film or other metal film formed by sputtering instead of an electroless electroplated film.

[0030] However, the third conductor layer 31 and the fourth conductor layer 41 may also be formed, for example, by a two-layer structure comprising a metal foil 2c and a thick first electroplated film 2e formed on the metal foil 2c, instead of a three-layer structure.

[0031] Each conductor layer 11, 21, 31, 41, and 42 can contain any conductor pattern. Figure 1 In the example, the third conductor layer 31 and the fourth conductor layer 41 include conductor pads 5 disposed at positions overlapping with the through-hole conductor 3 when viewed from above. It should be noted that "viewed from above" means viewing the wiring substrate with a line of sight along the thickness direction of the wiring substrate in the embodiment.

[0032] That is, the conductor pad 5 functions as a so-called through-hole pad for the through-hole conductor 3. Furthermore, the conductor pad 5 is positioned to overlap with the through-hole 2a and the cavity 3a when viewed from above. The conductor pad 5 blocks the through-hole 2a and the cavity 3a. Therefore, the conductor pad 5 is also a so-called cover pad for the through-hole conductor 3. The through-hole 2a and the cavity 3a are sandwiched between the conductor pad 5 of the third conductor layer 31 and the conductor pad 5 of the fourth conductor layer 41. If a conductor pad 5 is provided as such a cover pad, then... Figure 1 As shown, the fourth via conductor 44 and via conductor 43 of the wiring substrate 1 can be disposed directly above the via conductor 3.

[0033] In this embodiment, the first interlayer insulating layer 13 has a two-layer structure. The two-layer structure includes a first insulating layer 101 stacked on the second interlayer insulating layer 23 and the first conductor layer 11, and a second insulating layer 102 on the first insulating layer 101. The first insulating layer 101 includes wiring portions 110 partially formed on the side facing the second insulating layer 102. That is, the wiring portions 110 are formed as buried wiring layers having a shape that is buried from the outer surface of the first insulating layer 101 toward the inner side, and are formed as fine wiring FWs with relatively fine patterns. Furthermore, in Figure 1 The diagram shows an example where the outer interlayer insulating layer 40 of the two interlayer insulating layers 40 has a two-layer structure consisting of insulating layer 401 and insulating layer 402, but the interlayer insulating layer 40 can also be a single-layer structure. In the case where the interlayer insulating layer 40 has a two-layer structure, such as... Figure 1 As shown, the via conductor 43 that connects the conductor layers 42 to each other is formed in a manner that simultaneously penetrates two layers.

[0034] The core insulating layer 2, the second interlayer insulating layer 23, the interlayer insulating layer 40, and the first interlayer insulating layer 13, i.e., the first insulating layer 101 and the second insulating layer 102, are formed of any insulating resin. Examples of insulating resins include thermosetting resins such as epoxy resin, bismaleimide triazine resin (BT resin), or phenolic resin. Each insulating layer may also contain inorganic fillers (not shown) composed of particles such as silica (SiO2), alumina, or mullite. Figure 1 In the example, the core insulation layer 2 includes a core material (reinforcing material) 2d formed of glass fiber, aramid fiber, etc.

[0035] exist Figure 1 In this example, the wiring section 110 is constructed of two layers: a metal film layer (non-electrolytic plating film layer) 111 and an electrolytic plating film layer 112. The inner surface of the groove 101b formed in the first insulating layer 101 is covered by the metal film layer 111. The inner side of the metal film layer 111 in the groove 101b is filled with the electrolytic plating film layer 112.

[0036] The fine wiring fabrication layer (FW) is formed with a wiring pattern having a relatively small line width and inter-wire spacing. For example, in the fine wiring FW, the minimum line width and inter-wire spacing are approximately 0.5 μm to 3.0 μm. Preferably, the minimum line width of the fine wiring FW included in the embedded wiring layer is formed to be smaller than the minimum line width of the wiring included in the first conductor layer 11 and the second conductor layer 21. In addition, the fine wiring FW included in the embedded wiring layer can be formed such that the inter-wire spacing between the closest wirings is smaller than the inter-wire spacing between the closest wirings in the first conductor layer 11 and the second conductor layer 21.

[0037] The aspect ratio of the fine wiring FW is greater than that of the wiring contained in the first conductor layer 11 and the second conductor layer 21. For example, the aspect ratio of the fine wiring FW can be 2.0 or more and 6.0 or less. On the other hand, the aspect ratio of the wiring contained in the first conductor layer 11 and the second conductor layer 21 can be 1.0 or more and 2.0 or less.

[0038] The buried wiring layer of the wiring section 110 is connected to the first conductor layer 11 via a second via conductor 24. That is, a second via conductor 24 connecting the buried wiring layer to the first conductor layer 11 is formed in the first insulating layer 101. Furthermore, the buried wiring layer of the wiring section 110 is connected to the second conductor layer 21 via a third via conductor 34. That is, a third via conductor 34 connecting the buried wiring layer to the second conductor layer 21 is formed in the second insulating layer 102.

[0039] The conductor pattern of the second conductor layer 21 includes connecting pads 21p. The connecting pads 21p are formed to support components (not shown) mounted on the wiring substrate 1 when it is used. That is, the connecting pads 21p are component mounting pads used as connection portions when mounting external components on the wiring substrate 1, and the first surface 1F of the wiring substrate 1 can be a component mounting surface having at least one component mounting area A capable of mounting components. Electrodes of electronic components can be electrically and mechanically connected to the component mounting pads (connecting pads) 21p, for example, via bonding materials (not shown) such as solder. Examples of components that can be mounted on the wiring substrate 1 include, for example, active components such as semiconductor integrated circuit devices and transistors.

[0040] The second surface 1B of the wiring substrate 1 can be a connection surface that connects to an external element, such as a wiring substrate or the motherboard of any electrical device, when the wiring substrate 1 itself is mounted on an external element. Additionally, like the first surface 1F, the second surface 1B can also be a component mounting surface for mounting electronic components such as semiconductor integrated circuit devices. The connection pads 42p constituting the second surface 1B can connect to any substrate, electrical component, or mechanical component, not limited to these.

[0041] exist Figure 1In the example shown, the wiring portion (buried wiring layer) 110 is connected to the component mounting pad (connecting pad) 21p of the second conductor layer 21 via the third via conductor 34. The wiring portion (buried wiring layer) 110 may be formed only on the component mounting surface side of the wiring substrate 1. Moreover, the wiring portion (buried wiring layer) 110 may be formed only partially below the component mounting region A of the wiring substrate 1. For example, the wiring portion (buried wiring layer) 110 may be formed in such a way that it at least partially overlaps with the component mounting region A when viewed from above. That is, in this embodiment, the buried wiring layer is formed only in a specified area, not on the entire surface of the first insulating layer 101. In areas where the buried wiring layer is not formed, such as Figure 2A - Figure 2I As shown, the first via conductor 14 connecting the first conductor layer 11 and the second conductor layer 21 is formed in a manner that penetrates both the first insulating layer 101 and the second insulating layer 102. By forming the buried wiring layer only at specified locations, the flatness of the surface of the buried wiring layer containing the micro-wiring FW and the first insulating layer 101 can be well maintained. Defects such as short circuits between micro-wiring FWs and poor connection between the buried wiring layer and the conductor layer are avoided. It is believed that the manufacturing yield of the wiring substrate 1 is improved.

[0042] The second via conductor 24 and the third via conductor 34 can be formed from the same material and with the same structure as the first via conductor 14, the fourth via conductor 44, and the via conductor 43. That is, the second via conductor 24 and the third via conductor 34 can be formed from any metal such as copper or nickel. The second via conductor 24 and the third via conductor 34 can be formed, for example, from a metal film formed by electroless electroplating or sputtering, and an electroplated film formed by electrolytic electroplating using the metal film as a power supply layer, respectively. The second via conductor 24 is integrally formed with the wiring portion (embedded wiring layer) 110. The third via conductor 34 is integrally formed with the second conductor layer 21.

[0043] The via diameters of the second via conductor 24 and the third via conductor 34 are smaller than the via diameters of the first via conductor 14, the fourth via conductor 44, and the via conductor 43. That is, the first interlayer insulating layer 13 contains via conductors having at least two different via diameters. Furthermore, here, "via diameter" refers to the top diameter of each via conductor (the diameter of the end face of the wiring substrate 1 on the surface side of the via conductor), which is the maximum value of the distance between two points on the outer periphery of that end face.

[0044] Fine wiring (FW) is sometimes used for signal transmission, and the signal can be a high-frequency signal. Therefore, the first insulating layer 101 with the embedded wiring portion (embedded wiring layer) 110 preferably has excellent high-frequency characteristics. When the insulating layer in contact with the wiring has a relatively high dielectric constant and dielectric loss tangent, the dielectric loss (transmission loss) of the high-frequency signal transmitted by the wiring is relatively large. There is a tendency for the dielectric loss to increase as the signal frequency increases, especially when transmitting high-frequency signals in the microwave and millimeter-wave regions, where the dielectric loss may become significant. Therefore, the first insulating layer 101 with the embedded wiring portion (embedded wiring layer) 110 is preferably made of a material with a small dielectric constant and dielectric loss tangent, for example, preferably a relative dielectric constant of 3.3 or less at a frequency of 1 GHz and a dielectric loss tangent of 0.03 or less.

[0045] Regarding the relative permittivity and dielectric loss tangent of the aforementioned insulating layers, the second insulating layer 102 directly above the wiring portion (embedded wiring layer) 110 is also preferably configured to have a relative permittivity of 3.3 or less and a dielectric loss tangent of 0.03 or less at a frequency of 1 GHz. Since all insulating layers in contact with the wiring portion (embedded wiring layer) 110 possess excellent high-frequency characteristics, the wiring portion (embedded wiring layer) 110 can have superior signal transmission quality.

[0046] Reference Figure 1 To manufacture Figure 1 Taking the wiring substrate 1 shown as an example, the manufacturing method will be explained. Furthermore, the structural elements formed in the manufacturing method described below can be used in [various applications] unless otherwise specified. Figure 2A The material used as the material of the corresponding structural element in the description of the wiring substrate 1 is formed.

[0047] First, a substrate (starting substrate) is prepared having a core insulating layer 2 and metal foils 2c stacked on both sides of the core insulating layer 2. The core insulating layer 2 is formed of any insulating resin, such as epoxy resin, BT resin, or phenolic resin. Figure 2B As shown, the core insulating layer 2 includes a core material 2d. However, the core insulating layer 2 may also not include a core material 2d. The metal foil 2c is formed of any metal, such as copper or nickel. The metal foil 2c is bonded to both sides of the core insulating layer 2 by any method, such as hot pressing. For example, a double-sided copper-clad laminate may also be prepared as the starting substrate.

[0048] Next, a through-hole 2a is formed, penetrating the core insulating layer 2 and the metal foil 2c. The through-hole 2a can be formed, for example, by irradiating the core insulating layer 2 from the first surface 2F side and / or the second surface 2B side with a laser such as a carbon dioxide laser. The through-hole 2a can also be formed by drilling. The through-hole 2a can be formed using any forming method.

[0049] Next, a first electroplated film 2e is formed on the entire surface of the metal foil 2c on the side opposite to the core insulating layer 2, the end face exposed towards the through hole 2a, and the inner wall of the through hole 2a. The first electroplated film 2e is formed, for example, from an electroless electroplated film and an electrolytic electroplated film. After forming an electroless electroplated film made of any metal such as copper or nickel by electroless electroplating, an electrolytic electroplated film is formed on the electroless electroplated film by electrolytic electroplating, using the electroless electroplated film as a power supply layer. Alternatively, a metal film such as a sputtered film formed by sputtering can be formed instead of the electroless electroplated film. The first electroplated film 2e can also be formed from a single layer of electroplated film. A first electroplated film 2e with a desired thickness is formed.

[0050] A first electroplated film 2e is formed on the end face of the metal foil 2c exposed in the through hole 2a and on the inner wall of the through hole 2a. A through-hole conductor 3, composed of the first electroplated film 2e and having a cavity 3a in the center, is formed in the through hole 2a. The metal foil 2c and the first electroplated film 2e are sequentially stacked on the first surface 2F and the second surface 2B of the core insulating layer 2, respectively. After the resin 4 is filled into the cavity 3a and cured, a second electroplated film 2f is formed on the entire surface of the core insulating layer 2 on the first surface 2F side and the second surface 2B side. The second electroplated film 2f, like the first electroplated film 2e, can be formed from an electroless electroplated film and an electroplated film. For example, an electroless electroplating film can be formed on the entire surface of the first side 2F and the second side 2B of the core insulating layer 2. Using the electroless electroplating film as a power supply layer, an electrolytic electroplating film is formed on the electroless electroplating film, and these two layers constitute the second electroplating film 2f.

[0051] As a result, a third conductor layer 31 and a fourth conductor layer 41, composed of a metal foil 2c, a first electroplated film 2e, and a second electroplated film 2f, are formed on the first surface 2F side and the second surface 2B side of the core insulating layer 2, respectively. The third conductor layer 31 and the fourth conductor layer 41 are patterned using a subtractive method, thereby obtaining a core substrate 10 with a predetermined conductor pattern. The third conductor layer 31 and the fourth conductor layer 41 include conductor pads 5 that block through-holes 2a and voids 3a.

[0052] like Figure 2CAs shown, a second interlayer insulating layer 23 and a first conductor layer 11 are formed on the first surface 2F side of the core insulating layer 2, and an interlayer insulating layer 40 and a conductor layer 42 are formed on the second surface 2B side of the core insulating layer 2. In the formation of the second interlayer insulating layer 23 and the interlayer insulating layer 40, a film-like epoxy resin is laminated on the first surface 2F and the third conductor layer 31 of the core insulating layer 2, and on the second surface 2B and the fourth conductor layer 41 of the core insulating layer 2, and then heated and pressurized. As a result, the second interlayer insulating layer 23 and the interlayer insulating layer 40 are formed. Through-holes 23a for forming the fourth via conductor 44 are formed on the second interlayer insulating layer 23 by, for example, irradiation with a carbon dioxide laser, and through-holes 40a for forming the via conductor 43 are formed on the interlayer insulating layer 40 by, for example, irradiation with a carbon dioxide laser.

[0053] The first conductor layer 11 and conductor layer 42 are formed, for example, by a semi-additive process. That is, a metal film is formed on the surface of the second interlayer insulating layer 23 and the interlayer insulating layer 40, and within the through holes 23a and 40a, by electroless electroplating and sputtering. An electroplated film is formed by patterning electroplating that includes using the metal film as a power supply layer. Then, unwanted portions of the metal film are removed, for example, by etching. As a result, the first conductor layer 11 and conductor layer 42 containing a defined conductor pattern are formed. A fourth via conductor 44 is formed within the through hole 23a, and a via conductor 43 is formed within the through hole 40a.

[0054] Next, as Figure 2B As shown, using and referencing Figure 2D The same method is used to describe this process, in which a first insulating layer 101 is formed on the first surface 2F side of the core insulating layer 2, and an insulating layer 401 is formed on the second surface 2B side of the core insulating layer 2.

[0055] Next, as Figure 1 As shown, a through hole 101a is formed in the first insulating layer 101 by laser processing. The through hole 101a is formed in a second via conductor 24 (see reference) that should penetrate the first insulating layer 101. Figure 2E The location of the through-hole 101a. A carbon dioxide laser with a relatively long wavelength of about 10 μm can be used in the formation of the through-hole 101a. Alternatively, a groove 101b can be formed using an excimer laser or similar process with a relatively short wavelength, which has excellent linearity in the processing of the insulating layer. However, the through-hole 101a and the groove 101b can also be formed together by an excimer laser. The groove 101b is formed according to the wiring pattern that the wiring portion 110, which is embedded in the first insulating layer 101, should have.

[0056] Next, as Figure 2FAs shown, a metal film layer 111 is formed to cover the entire upper surface of the first insulating layer 101 (the interior of the through hole 101a, the interior of the groove 101b, and the upper surface of the first insulating layer 101). For example, the metal film layer 111 is formed on the entire upper surface of the first insulating layer 101 by electroless electroplating or sputtering. The metal film layer 111 covers the entire area of ​​the inner surfaces of the through hole 101a and the groove 101b, as well as the upper surface of the first insulating layer 101.

[0057] Next, as Figure 2G As shown, the metal film layer 111 is used as a seed layer to perform electrolytic plating to form an electroplated film layer 112. The electroplated film layer 112 fills the inner side of the metal film layer 111 through holes 101a and grooves 101b, and covers the entire area of ​​the upper surface of the first insulating layer 101.

[0058] Next, as Figure 2H As shown, the portions of the metal film layer 111 and the electroplated film layer 112 that are above the upper surface of the first insulating layer 101 are removed by grinding. This exposes the upper surface of the first insulating layer 101, completing the integral formation of the wiring portion 110 with the second via conductor 24, which has micro-wiring FW. The grinding of the metal film layer 111 and the electroplated film layer 112 can be performed, for example, by chemical mechanical polishing (CMP).

[0059] Next, as Figure 2B As shown, using and referencing Figure 2I The same method is used to describe this process, in which a second insulating layer 102 is formed on the first surface 2F side of the core insulating layer 2, and an insulating layer 402 is formed on the second surface 2B side of the core insulating layer 2.

[0060] Then, as Figure 2B As shown, a through-hole 102a for forming the third via conductor 34 is formed in the second insulating layer 102 by means of, for example, irradiation with a carbon dioxide laser. Furthermore, a through-hole 13a for forming the first via conductor 14 is formed in the first interlayer insulating layer 13 by means of, for example, irradiation with a carbon dioxide laser. Additionally, a through-hole 40a for forming the via conductor 43 is formed in the interlayer insulating layer 40 by means of, for example, irradiation with a carbon dioxide laser. Next, using the reference... Figure 1Using the same method described above, on the first surface 2F side of the core insulating layer 2, the second conductor layer 21 is integrally formed with the first via conductor 14 and the third via conductor 34; on the second surface 2B side of the core insulating layer 2, the conductor layer 42 is integrally formed with the via conductor 43. The second conductor layer 21 is formed with a conductor pattern including a connecting pad 21p for component mounting. The conductor layer 42 is formed with a pattern including a connecting pad 42p for connection with external elements. After the above processes, the core insulating layer 2 is complete. ​ Example of a wiring substrate 1.

[0061] The wiring substrate of the embodiments is not limited to the structure illustrated in the accompanying drawings and the structure, shape, and material illustrated in this specification. For example, wiring portions with fine wiring may be partially formed in any single or multiple conductor layers constituting the wiring substrate. The wiring substrate may have any number of insulating and conductor layers on both sides of the core substrate. In addition, solder resist may be formed on the outermost conductor and insulating layers of the wiring substrate. A protective film (not shown) may also be formed on the exposed surfaces of the connection pads 21p and 42p on the outermost insulating layer of the wiring substrate. For example, a protective film composed of Ni / Au, Ni / Pd / Au, or Sn may be formed by electroplating. An OSP film may also be formed by spraying an organic material.

[0062] The method for manufacturing the wiring substrate in this embodiment is not limited to the method described with reference to the accompanying drawings, and the conditions, sequence, etc., can be appropriately modified. Depending on the structure of the wiring substrate being manufactured, some processes may be omitted, or other processes may be added.

Claims

1. A wiring substrate, comprising: First conductor layer; A first interlayer insulating layer that covers the first conductor layer; A second conductor layer, which is formed on the first interlayer insulating layer; and A first via conductor, which penetrates the first interlayer insulation layer and connects the first conductor layer to the second conductor layer. in, The first interlayer insulation layer comprises a first insulation layer and a second insulation layer stacked in its thickness direction. The first insulating layer includes a wiring portion partially formed on a surface opposite to the second insulating layer, the second insulating layer being located on the opposite side of the surface of the first insulating layer that contacts the lower surface of the first conductor layer. The wiring section includes an embedded wiring layer that fills the grooves formed in the first insulating layer. The minimum linewidth of the wiring contained in the embedded wiring layer is less than the minimum linewidth of the wiring contained in the first conductor layer and the second conductor layer. The aspect ratio of the wiring included in the embedded wiring layer is above 2.0 and below 6.

0. The aspect ratio of the wiring contained in the first conductor layer and the second conductor layer is 1.0 or higher and 2.0 or lower.

2. The wiring substrate according to claim 1, wherein, The embedded wiring layer includes wiring for signal transmission.

3. The wiring substrate according to claim 1, wherein, The first insulating layer includes a second via conductor connecting the first conductor layer to the embedded wiring layer. The second insulating layer includes a third via conductor that connects the second conductor layer to the embedded wiring layer.

4. The wiring substrate according to claim 1, wherein, The distance between the closest wirings in the embedded wiring layer is less than the distance between the closest wirings in the first conductor layer and the second conductor layer.

5. The wiring substrate according to claim 1, wherein, The surface formed by the first interlayer insulating layer and the second conductor layer is a component mounting surface of the wiring substrate having at least one component mounting area.

6. The wiring substrate according to claim 5, wherein, The wiring portion overlaps at least partially with the component mounting area when viewed from above.

7. The wiring substrate according to claim 5, wherein, The second conductor layer includes a connection pad disposed within the component mounting area. The second insulating layer includes a third via conductor that connects the second conductor layer to the embedded wiring layer. The embedded wiring layer is connected to the connection pad via the third via conductor.

8. The wiring substrate according to claim 1, wherein, The first conductor layer is formed on the second interlayer insulating layer. The second interlayer insulating layer is formed on the third conductor layer and includes a fourth via conductor connecting the third conductor layer to the first conductor layer. The length of the first via conductor is approximately equal to the length of the fourth via conductor.

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